Pattern recognition system and method

Abstract

To provide systems and methods that enable pattern recognition with less energy consumption and without external computational power.SOLUTION: A pattern recognition system 100 is provided, comprising: one or more pairs of memristor arrays configured to receive a first set of voltage input values corresponding to a pattern on a first memristor array 102 of a pair 131 of memristor arrays, and a second set of voltage input values corresponding to a negative of the pattern on a second memristor array 103 of the pair of memristor arrays; and an artificial neuron 141 connected to each pair of memristor arrays and configured to be triggered when the pattern is recognized by a corresponding pair of memristor arrays.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on U.S. Patent Application No. 18 / 323,637, filed May 25, 2023, and has the benefit of its filing date. This application is related to U.S. Patent No. 10,902,914, entitled "Programmable resistive memory element and a method of making the same," filed June 4, 2019, and issued January 26, 2021, which is incorporated herein by reference in its entirety. This application is also related to U.S. Patent No. 11,183,240, entitled "Programmable resistive memory element and a method of making the same," filed January 26, 2021, and issued November 23, 2021, which is also incorporated herein by reference in its entirety. [Background technology]

[0002]

[0002] Pattern recognition is fundamental in developing artificial intelligence. Typically, pattern recognition is performed using software-based artificial neural networks. However, software-based artificial neural networks require a lot of computing power and also consume a lot of energy. Therefore, systems and methods that would achieve pattern recognition using much less energy consumption and that can perform local processing of data without a lot of external computing power are highly desirable. Summary of the Invention

[0003] A pattern recognition system and method for training and deploying the pattern recognition system are disclosed. The pattern recognition system is based on a memristor array and an artificial neuron constructed with electronic components. A pattern and its negative are used for training a pair of memristor arrays. Multiple patterns can be trained on the memristor crossbar. Pattern recognition is performed with the trained memristor array connected with the artificial neuron. The artificial neuron has an excitatory component and an inhibitory component. The excitatory component determines the triggering of the artificial neuron when the current output of one memristor array of the pair has a minimum value established during training. The inhibitory component stops the triggering of the artificial neuron when the current output of the other memristor array of the pair has a maximum value established during training.

[0004] In one embodiment, a pattern recognition system may be provided. The system may include one or more pairs of memristor arrays configured to receive (i) a first set of voltage input values ​​corresponding to a pattern on a first one of the pair of memristor arrays, and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second one of the pair of memristor arrays. The system may further include an artificial neuron connected to each pair of memristor arrays and configured to be triggered when the pattern is recognized by the corresponding pair of memristor arrays.

[0005] In another embodiment, a method of pattern recognition may be provided. The method may include receiving, by a pair of memristor arrays of a pattern recognition system, (i) a first set of voltage input values ​​corresponding to a pattern on a first memristor array of the pair of memristor arrays and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second memristor array of the pair of memristor arrays. The method may also include triggering an artificial neuron connected to the pair of memristor arrays in response to the pair of memristor arrays recognizing the pattern.

[0006] In yet another embodiment, a method for training a pattern recognition system may be provided. The method may include inputting to a pair of memristor arrays of the pattern recognition system: (i) a first set of voltage input values ​​corresponding to a pattern on a first memristor array of the pair of memristor arrays, the first set of voltage input values ​​causing corresponding resistances of memristors in the first memristor array to be altered; and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second memristor array of the pair of memristor arrays, the second set of voltage input values ​​causing corresponding resistances of memristors in the second memristor array to be altered. The method may also include configuring an artificial neuron connected to the pair of memristor arrays in response to inputting the pattern to the pair of memristor arrays. [Brief description of the drawings]

[0007] [Figure 1]

[0007] FIG. 1 illustrates an exemplary pattern recognition system based on memristors and artificial neurons constructed using electronic components in accordance with the principles disclosed herein. [Figure 2A]

[0008] FIG. 2 illustrates example patterns and corresponding negative patterns that may be used to train a pattern recognition system (such as the pattern recognition system shown in FIG. 1) based on principles disclosed herein. [Figure 2B]

[0009] FIG. 2B illustrates an exemplary process for training a pattern recognition system using the patterns shown in FIG. 2A according to principles disclosed herein. [Figure 2C] FIG. 2B illustrates an exemplary process for training a pattern recognition system using the patterns shown in FIG. 2A according to principles disclosed herein. [Figure 3A]

[0010] 1 illustrates example patterns and corresponding negative patterns that may be used to train a pattern recognition system (e.g., a pattern recognition system) based on principles disclosed herein. [Figure 3B]

[0011] FIG. 3B illustrates an exemplary process for training a pattern recognition system using the patterns shown in FIG. 3A according to principles disclosed herein. [Figure 3C] FIG. 3B illustrates an exemplary process for training a pattern recognition system using the patterns shown in FIG. 3A according to principles disclosed herein. [Figure 4]

[0012] FIG. 1 illustrates an exemplary process for deploying a trained pattern recognition system based on principles disclosed herein. [Diagram 5]

[0013] FIG. 1 illustrates an exemplary process for deploying a trained pattern recognition system based on principles disclosed herein. [Figure 6] FIG. 1 illustrates an exemplary process for deploying a trained pattern recognition system based on principles disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008]

[0014] 1 shows an exemplary pattern recognition system 100 based on memristors and artificial neurons constructed with electronic components according to the principles disclosed herein. The use of electronic components is merely an exemplary use case and should not be considered limiting. Various types of components should also be considered within the scope of this disclosure, based on any type of technology, such as chemical, electrical, electrochemical, mechanical, electromechanical, etc.

[0009]

[0015] The memristor 101 used in system 100 can be different types of memristors. For example, indium gallium zinc oxide (IGZO) memristors with coplanar electrodes such as those described in U.S. Pat. Nos. 10,902,914 and 11,183,240, both of which are incorporated by reference in their entireties, may be used.

[0010]

[0016] Memristors 101 are connected in memristor arrays 102, 103, 104, 105. Memristor arrays 102, 103, 104, 105 can be used as separate arrays or configured as memristor columns in a memristor crossbar. Memristor arrays 102, 103, 104, 105 can be organized and configured in pairs to be connected to corresponding artificial neurons. For example, memristor arrays 102, 103 can form a pair of memristor arrays 131 that can be connected to an artificial neuron 141. Similarly, memristor arrays 104, 105 can form another pair of memristor arrays 132 that can be connected to another artificial neuron 142.

[0011]

[0017] 1 has two pairs of memristor arrays 131, 132 and two artificial neurons 141, 142, with each memristor array 102, 103, 104, 105 including four individual memristors 101, it should be understood that this is for illustrative purposes only, and systems with a much larger number of memristors, memristor array pairs, and artificial neurons can be similarly constructed and operated. That is, the particular number of memristors 101 for different levels of abstraction and organization (e.g., several memristors 101 connected to an artificial neuron) is for ease of explanation only and should not be considered limiting.

[0012]

[0018] The memristor array 102 of the pair 131 may be connected to an inhibitory component of the artificial neuron 141 via a switch 106. The inhibitory component of the artificial neuron 141 may be formed by resistors 110, 113 and a transistor 112. The inhibitory component of the artificial neuron 141 may be configured to stop triggering the artificial neuron 141 when the output current of the memristor array 102 of the pair 131 reaches a certain maximum value established during the training process. Furthermore, the memristor array 103 of the pair 131 may be connected to an excitatory component of the artificial neuron 141 via a switch 107. The excitatory component of the artificial neuron 141 may be formed by resistor 111 and transistors 114, 115. The excitatory component of the artificial neuron 141 may be configured to trigger the artificial neuron 141 when the output current of the memristor array 103 of the pair 131 reaches a certain minimum value established during the training process. Triggering of artificial neuron 141 means that transistor 115 is open and therefore current is flowing through indicator 116, thereby turning it on. Also, note that indicator 116 may be replaced by a connection (e.g., for sending a trigger indication) to the next layer of a hardware-based neural network in pattern recognition system 100, which may be a layer for feature recognition.

[0013]

[0019] Similarly, switch 108 can connect the inhibitory component of artificial neuron 142 to memristor array 104, and switch 109 can connect the excitatory component of neuron 142 to memristor array 105. The inhibitory and excitatory components of artificial neuron 142 can be similar to the corresponding components in artificial neuron 141.

[0014]

[0020] Also, each of the memristor arrays 102, 103, 104, 105 may be separately connected directly to ground via a corresponding switch 117, 118, 119, 120.

[0015]

[0021] The first memristor 101 of each array 102, 103, 104, 105 may form a first line of a crossbar that is connected to a power supply V1 via a diode 121. Similarly, the second, third, and fourth memristors of each array may be connected to corresponding power supplies V2, V3, V4 via diodes 122, 123, 124.

[0016]

[0022] As explained above, it should be noted that the manner in which both the excitatory and inhibitory parts of the neuron shown here are constructed is for illustrative purposes only, and other components (e.g., potentiometers instead of fixed resistors or various types of transistors, etc.) can also be used to obtain the excitatory and inhibitory functions described herein. Also, instead of switches, other types of control units that can cause the respective connections to be interrupted can be used (e.g., transistors, etc.).

[0017]

[0023] A pattern recognition system can be trained to recognize different patterns. In some exemplary embodiments, training can include inputting an exemplary pattern and the negative of the exemplary pattern. For example, FIG. 2A shows an exemplary pattern 250 and a corresponding negative pattern 252 that can be used to train a pattern recognition system (e.g., pattern recognition system 100) based on the principles disclosed herein.

[0018]

[0024] To train the pattern recognition system, the pattern 250 and the corresponding negative pattern 252 may be divided into portions or pixels, which may then be converted into voltage input vectors 260, 262, respectively.

[0019]

[0025] In one or more embodiments, the voltage input vectors 260, 262 may be scaled up to obtain voltage values ​​high enough to alter the resistance of a memristor (e.g., memristor 101). For example, when the voltage input vectors 260, 262 are applied to a pair of memristor arrays (e.g., pair 131), the pattern recognition system will be trained to recognize the respective pattern 250.

[0020]

[0026] 2B-2C illustrate an exemplary process for training a pattern recognition system using the pattern 250 shown in FIG. 2A based on the principles disclosed herein. As shown, the pattern 250 may be divided into pixels, which are then converted into a voltage input vector 260. In some cases, the application of high voltages may increase the resistance of the memristor. In these cases, high voltage values ​​(V1, V3) corresponding to the pattern 250 are applied to the memristor array 202 associated with the inhibitory component of the artificial neuron 241, as shown in FIG. 2B. Additionally, high voltage values ​​(V2, V4) corresponding to the negative pattern 252 of the pattern 250 are applied to the memristor array 203 associated with the excitatory component of the artificial neuron 241, as shown in FIG. 2C.

[0021]

[0027] Conversely, in some cases, application of high voltage values ​​can decrease the resistance of a memristor. In these cases, high voltage values ​​(V1, V3) corresponding to pattern 250 are applied to memristor array 202 associated with the excitatory component of artificial neuron 241, and high voltage values ​​(V2, V4) corresponding to the negative 252 of pattern 250 are applied to memristor array 203 associated with the inhibitory component of artificial neuron 241. While the resistance of a memristor may increase or decrease in response to application of high voltage values, the following example describes a use case in which the resistance of a memristor increases in response to application of high voltage values, for simplicity and ease of explanation.

[0022]

[0028] As shown in FIG. 2B, by applying a high voltage value corresponding to pattern 250 to memristor array 202 and closing switch 217, current will flow through the first and third memristors (counting from ground) of memristor array 202, increasing their corresponding resistances.

[0023]

[0029] As shown in FIG. 2C, by applying a high voltage value corresponding to negative 252 of pattern 250 to memristor array 203 and closing switch 218, current will flow through the second and fourth memristors (counting from ground) of memristor array 203, increasing their corresponding resistances.

[0024]

[0030] In this manner, one pair of the memristor array (in this case the first pair, e.g., pair 131 shown in FIG. 1) may be trained to recognize pattern 250. Pattern 250 is merely an example, and depending on the crossbar configuration of memristor pairs, different types of patterns may be learned; i.e., additional patterns may be learned using additional memristor pairs on the same crossbar.

[0025]

[0031] For example, FIG. 3A shows an example pattern 350 and a corresponding negative pattern 352 that can be used to train a pattern recognition system (e.g., pattern recognition system 100) based on the principles disclosed herein. Training can be performed using a second pair of memristor arrays (e.g., pair 132 shown in FIG. 1). For this, the same procedure as for learning pattern 250 (shown in FIG. 2A) can be used. Pattern 350 and negative 352 of pattern 350 can be divided into portions or pixels, which are then converted into voltage input vectors 360, 362, respectively. Voltage input vectors 360, 362 can be scaled up to obtain voltage values ​​high enough to change the memristor resistance and applied to the second pair of memristor arrays (e.g., pair 132 shown in FIG. 1), which can be trained to recognize pattern 350.

[0026]

[0032] 3B-3C illustrate an exemplary process for training a pattern recognition system using the pattern 350 shown in FIG 3A according to principles disclosed herein. For example, as shown in FIG 3B, by applying high voltage values ​​(V1, V2) corresponding to the pattern 350 to the memristor array 304 and closing switch 319, current will flow through the first and second memristors (counting from ground) of the memristor array 304, increasing their corresponding resistances.

[0027]

[0033] As shown in FIG. 3C, by applying high voltage values ​​(V3, V4) corresponding to negative 352 of pattern 350 to memristor array 305 and closing switch 320, current will flow through the third and fourth memristors (counting from ground) of memristor array 305, increasing their corresponding resistances.

[0028]

[0034] Thus, using the principles disclosed herein, a pattern recognition system can be trained to recognize different patterns using a pair of memristor arrays and their associated neurons for each pattern.

[0029]

[0035] After the pattern recognition system is trained, the trained system can be deployed to recognize patterns. To recognize a pattern, each pattern is divided into parts or pixels, which are then converted into a voltage input vector similar to the voltage input vector used during the training process, but this time the voltage input vector is scaled down to obtain a voltage value low enough to not change the memristor resistance. The voltage input vector corresponding to each pattern is then applied to all memristor array pairs, and each pair is connected with its associated neuron. If the respective pattern corresponds to one that the memristor array pair was trained to recognize, its associated neuron will be triggered and its indicator (e.g., indicator 116 shown in FIG. 1) will be turned on.

[0030]

[0036] FIG. 4 illustrates an exemplary process for deploying a trained pattern recognition system based on the principles disclosed herein. As shown, the trained pattern recognition system can recognize a pattern 450 (similar to pattern 250 shown in FIGS. 2A-2C). In particular, a voltage input vector 460 can be generated from pattern 450. Voltage input vector 460 can include voltages V1 (high), V2 (low), V3 (high), V4 (low), which are lower than the corresponding training vectors to not change the resistance of the trained memristors. As shown in FIG. 4, an artificial neuron 441 associated with a first pair of memristor arrays trained to recognize pattern 250 is triggered and turns on its indicator.

[0031]

[0037] 5 illustrates an exemplary process for deploying a trained pattern recognition system based on the principles disclosed herein. As shown, the trained pattern recognition system is capable of recognizing pattern 550 (similar to pattern 350 shown in FIGS. 3A-3C). Thus, artificial neuron 542 associated with the second pair of memristor arrays trained to recognize 552 (or 352) is triggered and turns on its indicator.

[0032]

[0038] In some cases, the trained pattern recognition system may receive a pattern that the system is not trained to recognize. In such a case, the artificial neuron will not be triggered and all indicators will be turned off. For example, FIG. 6 illustrates an exemplary process of deploying a trained pattern recognition system based on the principles disclosed herein. In particular, a pattern 680 that the pattern recognition is not trained for is used to generate a voltage input vector 682 with voltages V1 (high), V2 (high), V3 (high), V4 (low). However, the pattern 680 is different from the pattern 250, 350 that the pattern recognition system is trained to recognize. Thus, the pattern recognition system may not be able to recognize the pattern 680, the artificial neuron will not be activated, and the signal will not be turned on.

[0033]

[0039] Also, it should be noted that while the described patterns 250, 350 are only black and white pixels and therefore the corresponding voltage vector inputs have only two values, the disclosed systems and methods of operation may also be used with patterns having grayscale pixels (or multi-level pixels in general), in which case the voltage vector values ​​will have many different voltage values. For example, memristors with multiple states, preferably analog states, may be used.

[0034]

[0040] Additional examples of the presently described method and device embodiments are suggested in accordance with the structures and techniques described herein. Other non-limiting examples may be configured to operate separately or may be combined in any permutation or combination with any one or more of the other examples provided above or throughout this disclosure.

[0035]

[0041] Those skilled in the art will understand that the present disclosure may be embodied in other specific forms without departing from the spirit or main characteristics thereof.The present disclosure is therefore considered in all respects to be illustrative and not restrictive.The scope of the present disclosure is indicated by the appended claims, rather than the above description, and all changes that come within the meaning and scope and equivalents thereof are intended to be embraced therein.

[0036]

[0042] It should be noted that the terms "including" and "comprising" should be interpreted as meaning "including, but not limited to." Unless already expressly recited in the claims, the term "a" should be interpreted as "at least one," and "the," "said," etc. should be interpreted as "the at least one," "said at least one," etc. Furthermore, it is Applicant's intent that only claims that include the expression language "means for" or "steps for" be interpreted under 35 U.S.C. 112(f). Any claim that does not expressly include the phrase "means for" or "steps for" should not be interpreted under 35 U.S.C. 112(f).

Claims

1. 1. A pattern recognition system comprising: one or more pairs of memristor arrays configured to receive (i) a first set of voltage input values ​​corresponding to a pattern on a first one of a pair of memristor arrays, and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second one of the pair of memristor arrays; an artificial neuron coupled to each pair of the memristor arrays and configured to be triggered when the pattern is recognized by a corresponding pair of the memristor arrays; A pattern recognition system comprising:

2. 2. The system of claim 1 , wherein the memristor array is organized as memristor columns in a memristor crossbar.

3. The artificial neuron is an excitation component configured to determine the triggering of the artificial neuron when a current output of one of the memristor arrays of the pair has a minimum value established during training; an inhibitory component configured to stop the triggering of the artificial neuron when the current output of the other memristor array of the pair has a maximum value established during the training; The system of claim 2 , comprising:

4. 10. The system of claim 1, wherein the memristor comprises an indium gallium zinc oxide (IGZO) based memristor.

5. The system of claim 1 , wherein the memristors have electrodes on the same plane.

6. The trigger of the artificial neuron may include turning on an indicator on the artificial neuron The system of claim 1 , comprising:

7. The trigger of the artificial neuron may include Sending an indication of said trigger to a next layer of said pattern recognition system. The system of claim 1 , comprising:

8. The system of claim 1 , wherein the pattern comprises pixels, each voltage input value corresponding to a state of the pixel.

9. 9. The system of claim 8, wherein the pixels are binary and each voltage input value is either a high voltage input value or a low voltage input value.

10. 9. The system of claim 8, wherein the pixels are multi-level, each voltage input value corresponding to a level of the corresponding pixel.

11. 1. A pattern recognition method comprising: receiving, by a pair of memristor arrays of a pattern recognition system, (i) a first set of voltage input values ​​corresponding to a pattern on a first memristor array of the pair of memristor arrays, and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second memristor array of the pair of memristor arrays; triggering an artificial neuron connected to the pair of memristor arrays in response to the pair of memristor arrays recognizing the pattern; and A pattern recognition method comprising:

12. 12. The method of claim 11, wherein the first memristor array and the second memristor array are arranged as memristor columns in corresponding memristor crossbars.

13. triggering an artificial neuron when a current output of one of the memristor arrays of the pair has a minimum value established during training, by an excitatory component of the artificial neuron; and stopping the triggering of the artificial neuron when the current output of the other memristor array of the pair has a maximum value established during the training, by an inhibitory component of the artificial neuron. The method of claim 11 further comprising:

14. The method of claim 11 , wherein the memristor comprises an indium gallium zinc oxide (IGZO) based memristor.

15. The method of claim 11 , wherein the memristors have electrodes that lie on the same plane.

16. 1. A method for training a pattern recognition system, comprising: inputting to a pair of memristor arrays of the pattern recognition system: (i) a first set of voltage input values ​​corresponding to a pattern on a first memristor array of a pair of memristor arrays, where the first set of voltage input values ​​changes corresponding resistances of the memristors in the first memristor array; and (ii) a second set of voltage input values ​​corresponding to a negative of the pattern on a second memristor array of the pair of memristor arrays, where the second set of voltage input values ​​changes corresponding resistances of the memristors in the second memristor array; configuring an artificial neuron connected to the pair of memristor arrays in response to inputting the pattern to the pair of memristor arrays; A method comprising:

17. 17. The method of claim 16, wherein the first memristor array and the second memristor array are arranged as memristor columns in corresponding memristor crossbars.

18. The configuring of the artificial neuron comprises: configuring an excitatory component of the artificial neuron to trigger the artificial neuron when a current output of one of the memristor arrays of the pair has a minimum value; configuring an inhibitory component of the artificial neuron to cease the triggering of the artificial neuron when the current output of the other memristor array of the pair has a maximum value; 20. The method of claim 16 comprising:

19. 17. The method of claim 16, wherein the memristor comprises an indium gallium zinc oxide (IGZO) based memristor.

20. 17. The method of claim 16, wherein the memristors have electrodes that lie on the same plane.

Images