Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of reducing seams in a trench.SOLUTION: A semiconductor device 100 includes: a semiconductor substrate 1 including a trench 200 surrounding a device; an insulating film 2 covering an inner surface of the trench 200; and a conductive region provided in the trench 200. The trench 200 includes: a first trench 201 located on a bottom surface side of the trench 200; and a second trench 202 located on a front surface side of the trench 200, formed to be continuous with the first trench 201, and having a width that is narrowed along a depth direction. An amount of reduction in width per unit depth of the second trench 202 is greater than an amount of reduction in width per unit depth of the first trench 201.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-32332 A Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the semiconductor device that can reduce seams in a trench. [Means for solving the problem]

[0005] One embodiment of the present disclosure provides a semiconductor device comprising: a semiconductor substrate including a trench surrounding a device; an insulating film covering an inner surface of the trench; and a conductive region disposed within the trench, the trench comprising: a first trench located on the bottom side of the trench; and a second trench located on the surface side of the trench, continuous with the first trench, and narrowing in width along the depth direction, wherein a reduction in width of the second trench per unit depth is greater than a reduction in width of the first trench per unit depth.

[0006] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: etching a semiconductor substrate through an opening in a mask provided on the semiconductor substrate to form a space directly below the opening and directly below a region outside both ends of the opening in a width direction; dry etching the semiconductor substrate through the opening to form a trench continuous with the space; forming an insulating film on an exposed surface of the space and the trench; supplying a first conductive material into the trench through the opening to form a first conductive region, and supplying the first conductive material into the space to form a second conductive region having a seam, and forming a first material region including the first conductive region and a second conductive region; etching the second conductive region through the opening until a seam in the second conductive region is reached; and supplying a second conductive material into the seam through the opening to form a second material region in the seam. Effect of the Invention

[0007] An embodiment of the present disclosure can provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce seams in a trench. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of the semiconductor device. [Diagram 2] FIG. 2 is an enlarged view of the device area including the trench structure shown in FIG. [Diagram 3] FIG. 3 is a vertical cross-sectional view of the device region shown in FIG. 2 taken along line III-III. [Figure 4] FIG. 4 is a vertical cross-sectional view of a first semiconductor device including a trench structure. [Diagram 5] FIG. 5 is an enlarged view of the first region S1 shown in FIG. [Figure 6] Figure 6 is a diagram for explaining the manufacturing method of the first semiconductor device (Figure 6(A), Figure 6(B), Figure 6(C), Figure 6(D), Figure 6(E), Figure 6(F), Figure 6(G), Figure 6(H)). [Figure 7]7A to 7G are diagrams for explaining the manufacturing method of the first semiconductor device (FIGS. 7A, 7B, 7C, 7D, 7E, 7F, and 7G). [Figure 8] Figure 8 is a diagram for explaining the manufacturing method of the first semiconductor device (Figure 8(A), Figure 8(B), Figure 8(C), Figure 8(D), Figure 8(E), Figure 8(F), Figure 8(G), Figure 8(H)). [Figure 9] FIG. 9 is a diagram for explaining the method for manufacturing the first semiconductor device (FIG. 9(A) and FIG. 9(B)). [Figure 10] FIG. 10 is a vertical cross-sectional view of a first semiconductor device including a trench structure without an STI structure. [Figure 11] FIG. 11 is a vertical cross-sectional view of a second semiconductor device including a trench structure. [Figure 12] FIG. 12 is an enlarged view of the second region S2 shown in FIG. [Figure 13] Figure 13 is a diagram for explaining the manufacturing method of the second semiconductor device (Figure 13(A), Figure 13(B), Figure 13(C), Figure 13(D), Figure 13(E), Figure 13(F), Figure 13(G), Figure 13(H)). [Figure 14] Figure 14 is a diagram for explaining the manufacturing method of the second semiconductor device (Figure 14(A), Figure 14(B), Figure 14(C), Figure 14(D), Figure 14(E), Figure 14(F), Figure 14(G)). [Figure 15] Figure 15 is a diagram for explaining the manufacturing method of the second semiconductor device (Figure 15(A), Figure 15(B), Figure 15(C), Figure 15(D), Figure 15(E), Figure 15(F), Figure 15(G), Figure 15(H)). [Figure 16] FIG. 16 is a diagram for explaining the method for manufacturing the second semiconductor device (FIG. 16(A) and FIG. 16(B)). [Figure 17] FIG. 17 is a vertical cross-sectional view of a second semiconductor device including a trench structure without an STI structure. [Figure 18] FIG. 18 is a vertical cross-sectional view of a third semiconductor device including a trench structure. [Figure 19] FIG. 19 is an enlarged view of the third region S3 shown in FIG. [Figure 20] Figure 20 is a diagram for explaining the manufacturing method of the third semiconductor device (Figure 20(A), Figure 20(B), Figure 20(C), Figure 20(D), Figure 20(E), Figure 20(F), Figure 20(G), Figure 20(H)). [Figure 21] FIG. 21 is a diagram for explaining the third semiconductor device manufacturing method (FIG. 21(A), FIG. 21(B), FIG. 21(C), FIG. 21(D), FIG. 21(E), FIG. 21(F)). [Figure 22] Figure 22 is a diagram for explaining the manufacturing method of the third semiconductor device (Figure 22(A), Figure 22(B), Figure 22(C), Figure 22(D), Figure 22(E), Figure 22(F), Figure 22(G), Figure 22(H)). [Diagram 23] FIG. 23 is a diagram for explaining the third semiconductor device manufacturing method (FIG. 23(A) and FIG. 23(B)). [Figure 24] FIG. 24 is a vertical cross-sectional view of a third semiconductor device including a trench structure without an STI structure. [Diagram 25] FIG. 25 is a vertical cross-sectional view of a fourth semiconductor device including a trench structure. [Figure 26] FIG. 26 is an enlarged view of the fourth region S4 shown in FIG. [Figure 27] Figure 27 is a diagram for explaining the manufacturing method of the fourth semiconductor device (Figure 27(A), Figure 27(B), Figure 27(C), Figure 27(D), Figure 27(E), Figure 27(F), Figure 27(G), Figure 27(H)). [Figure 28] 28A to 28F are diagrams for explaining the fourth semiconductor device manufacturing method (FIGS. 28A, 28B, 28C, 28D, 28E, and 28F). [Figure 29] Figure 29 is a diagram for explaining the manufacturing method of the fourth semiconductor device (Figure 29(A), Figure 29(B), Figure 29(C), Figure 29(D), Figure 29(E), Figure 29(F), Figure 29(G), Figure 29(H)). [Diagram 30] 30A to 30E are diagrams for explaining the fourth semiconductor device manufacturing method (FIG. 30A, FIG. 30B, FIG. 30C, FIG. 30D, FIG. 30E). [Diagram 31] FIG. 31 is a vertical cross-sectional view of a fourth semiconductor device including a trench structure without an STI structure. [Diagram 32] FIG. 32 is a vertical cross-sectional view of a fifth semiconductor device including a trench structure. [Diagram 33] FIG. 33 is an enlarged view of the fifth region S5 shown in FIG. [Diagram 34] Figure 34 is a diagram for explaining the manufacturing method of the fifth semiconductor device (Figure 34(A), Figure 34(B), Figure 34(C), Figure 34(D), Figure 34(E), Figure 34(F), Figure 34(G), Figure 34(H)). [Diagram 35] FIG. 35 is a diagram for explaining the fifth semiconductor device manufacturing method (FIG. 35(A), FIG. 35(B), FIG. 35(C), FIG. 35(D), FIG. 35(E), FIG. 35(F)). [Diagram 36] Figure 36 is a diagram for explaining the manufacturing method of the fifth semiconductor device (Figure 36(A), Figure 36(B), Figure 36(C), Figure 36(D), Figure 36(E), Figure 36(F), Figure 36(G), Figure 36(H)). [Figure 37] FIG. 37 is a diagram for explaining the fifth semiconductor device manufacturing method (FIG. 37(A) and FIG. 37(B)). [Figure 38] FIG. 38 is a vertical cross-sectional view of a fifth semiconductor device including a trench structure without an STI structure. [Figure 39] FIG. 39 is a vertical cross-sectional view of a sixth semiconductor device including a trench structure. [Diagram 40] FIG. 40 is an enlarged view of the sixth region S6 shown in FIG. [Diagram 41] Figure 41 is a diagram for explaining the sixth semiconductor device manufacturing method (Figure 41(A), Figure 41(B), Figure 41(C), Figure 41(D), Figure 41(E), Figure 41(F), Figure 41(G), Figure 41(H)). [Diagram 42] 42A to 42F are views for explaining the sixth semiconductor device manufacturing method (FIG. 42A, FIG. 42B, FIG. 42C, FIG. 42D, FIG. 42E, FIG. 42F). [Diagram 43]Figure 43 is a diagram for explaining the sixth semiconductor device manufacturing method (Figure 43(A), Figure 43(B), Figure 43(C), Figure 43(D), Figure 43(E), Figure 43(F), Figure 43(G), Figure 43(H)). [Diagram 44] FIG. 44 is a diagram for explaining the sixth method for manufacturing a semiconductor device (FIG. 44(A) and FIG. 44(B)). [Diagram 45] FIG. 45 is a vertical cross-sectional view of a sixth semiconductor device including a trench structure without an STI structure. [Figure 46] FIG. 46 is an enlarged view of the first end region R1 and the second end region R2 shown in FIG. 3 (FIG. 46(A), FIG. 46(B), FIG. 46(C)). [Figure 47] FIG. 47 is an enlarged view of the interface region R3 shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0010] First, the basic structure of the semiconductor device will be described.

[0011] FIG. 1 is a plan view of the semiconductor device.

[0012] The semiconductor device 100 includes a chip 101 (semiconductor chip) having a rectangular parallelepiped shape. The chip 101 has a first main surface 3 on one side and a second main surface 4 (see FIG. 3) on the other side. The chip 101 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. The thickness direction of the chip 101 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. Note that the depth direction of the chip 101 (depth direction of a trench formed in a substrate) is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the second main surface 4 (rear surface) of the semiconductor substrate toward the first main surface 3 (upper surface).

[0013] The first main surface 3 and the second main surface 4 are each perpendicular to the Z-axis. The planar shape (shape in plan view) of the first main surface 3 as viewed from the normal direction (Z-axis direction) of the first main surface 3 is a rectangle (quadrilateral). The shape of the second main surface 4 in plan view is a rectangle (quadrilateral). The first side surface 5A and the second side surface 5B constituting two opposing sides of the rectangle in plan view each extend along the X-axis direction. The third side surface 5C and the fourth side surface 5D constituting the other two opposing sides of the rectangle in plan view each extend along the Y-axis direction. These adjacent side surfaces are perpendicular to each other in plan view, but may also intersect at an angle other than perpendicular.

[0014] The semiconductor device 100 includes a plurality of device regions 10 provided on the first main surface 3. There is a gap between each of the device regions 10 and each of the side surfaces (first side surface 5A to fourth side surface 5D) of the chip 101. The number, arrangement and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement and shape.

[0015] Various devices are formed in each device region 10. At least one device region 10 includes a trench surrounding a device 50. The number of trenches may be one or more. An exemplary device region 10 includes a first trench structure TR1 and a second trench structure TR2.

[0016] The devices 50 formed in each device region 10 may each include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0017] A metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as the MISFET. The device 50 can also be a power transistor. A double-diffused MOSFET (DMOS) can be used as the power MOSFET, and a vertical type (VDMOS) or a horizontal type (LDMOS) can be used. As the drain-source voltage of the MISFET, high voltage HV (high voltage: for example, 100 V or more and 1000 V or less), middle voltage MV (middle voltage: for example, 30 V or more and 100 V or less), and low voltage LV (low voltage: for example, 1 V or more and 30 V or less) are also known. In addition, an optical device such as a light-emitting element or a light-receiving element can be used as the device 50 formed in the device region 10.

[0018] The semiconductor material constituting the chip 101 in this example is silicon (Si). As the semiconductor material constituting the chip 101, compound semiconductors can also be used. Examples of compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and mixed crystal semiconductors using these semiconductors. As III-V compound semiconductors, Ga-containing semiconductors such as GaAs and GaN can be used. As IV-IV compound semiconductors, Si-containing semiconductors such as SiC and SiGe can be used.

[0019] Figure 2 is an enlarged view of the device region including the trench structure shown in Figure 1.

[0020] The device region 10 includes a first trench structure TR1 and a second trench structure TR2. The first trench structure TR1 surrounds the second trench structure TR2 and is located outside thereof. The second trench structure TR2 surrounds the device 50.

[0021] The planar shape of the first trench structure TR1 is annular. The first width W1 of the first trench structure TR1 may be 0.5 μm or more and 10 μm or less. The first width W1 may be 2 μm or more and 4 μm or less. The planar shape of the second trench structure TR2 is annular. The second width W2 of the second trench structure TR2 may be 0.5 μm or more and 10 μm or less. The second width W2 may be 1.5 μm or more and 3.5 μm or less. The second width W2 may be smaller than the first width W1 (W2 < W1).

[0022] The distance between the first trench structure TR1 and the second trench structure TR2 in plan view is given by a third width W3. The semiconductor region providing the third width W3 in plan view has a wider width along the depth direction (+Z direction). The third width W3 may be 0.5 μm or more and 10 μm or less. The third width W3 may be 1 μm or more and 3 μm or less. The third width W3 may be less than the first width W1 (W3 < W1). The third width W3 can be less than the second width W2 (W3 < W2). The third width W3 may be greater than or equal to the second width W2 (W2 ≤ W3), and may also be greater than or equal to the first width W1 (W1 ≤ W3).

[0023] FIG. 3 is a vertical cross-sectional view of the device region shown in FIG. 2 taken along line III-III.

[0024] The device region 10 constituting the semiconductor device includes a semiconductor substrate 1 and a protective film 14 provided on the semiconductor substrate 1. The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B (epitaxial layer) formed on the underlying substrate 1A. The epitaxial crystal region 1B includes a first epitaxial layer 1B1 on the underlying substrate 1A side and a second epitaxial layer 1B2 formed thereon. The first trench structure TR1 extends from the surface of the semiconductor substrate 1 so as to taper toward the depth. The first trench structure TR1 (first trench) penetrates the interface (second position Z2) between the underlying substrate 1A and the epitaxial crystal region 1B. The second trench structure TR2 extends from the surface of the semiconductor substrate 1 so as to taper toward the depth. The second trench structure TR2 (second trench) penetrates the interface (second position Z2) between the underlying substrate 1A and the epitaxial crystal region.

[0025] The device 50 is surrounded by the second trench structure TR2 around the Z axis in a plan view. The first trench structure TR1 is located outside the second trench structure TR2. The second trench structure TR2 is surrounded by the first trench structure TR1 around the Z axis in a plan view. The structure of the device 50 is not particularly limited, but an example will be described.

[0026] The exemplary device 50 is a type of transistor using a high voltage HV (HV-MISFET cell). The device 50 includes a first well region 51 and a plurality of second well regions 52 in the epitaxial crystal region 1B. A drain region 53 is formed in the first well region 51. A source region 54 and a contact region 56 are formed in each of the second well regions 52. A gate insulating film 58 is provided on a surface region of the semiconductor substrate 1 between the drain region 53 and the source region 54. A gate electrode 59 is disposed on the gate insulating film 58. A planar gate structure 57 is formed by the gate insulating film 58 and the gate electrode 59.

[0027] A plurality of insulating portions 60 are arranged at intervals on the front surface side of the semiconductor substrate 1. The insulating portions 60 are arranged at the boundary between the second trench structure TR2 and the second well region 52. The insulating portions 60 are arranged in a region between the drain region 53 and the source region 54, adjacent to the drain region 53. Each insulating portion 60 can be formed of shallow trench isolation (STI), and includes an insulator 62 embedded in a shallow trench 61.

[0028] A drain potential VD is applied to the drain region 53 via a drain contact electrode 63. A source potential VS is applied to the source region 54 via a source contact electrode 64 and a contact region 56. A gate potential VG is applied to the gate electrode 59 via a gate contact electrode 65. When a gate potential VG that turns the switch ON is applied, a channel 55 is formed in the surface layer of the semiconductor substrate 1 directly below the gate electrode 59. Charges flowing through the channel 55 drift in the region below the insulating portion 60 adjacent to the drain region 53, and can electrically connect the source region 54 and the drain region 53.

[0029] A first potential V1 is applied to the first trench structure TR1 via a first contact electrode 71. A second potential V2 is applied to the second trench structure TR2 via a second contact electrode 72. A region between the first trench structure TR1 and the second trench structure TR2 constitutes a mesa portion 27. A third potential V3 is applied to the mesa portion 27 via a third contact electrode 73. The third potential V3 can be a potential equal to or lower than (preferably less than) the drain potential VD. In other words, the third potential V3 can be less than the maximum device potential. The third potential V3 can be equal to or higher than the first potential V1 (V1≦V3). The third potential V3 can exceed the first potential V1 (V1<V3). The third potential V3 can be equal to or lower than the second potential V2 (V3≦V2). The third potential V3 can be less than the second potential V2 (V3<V2). In this case, each potential can be set to gradually decrease in a direction away from the device 50 (in the order of VD>V2>V3>V1).

[0030] In this example, each semiconductor region constituting the semiconductor device has an n-type as the first conductivity type and a p-type as the second conductivity type, but these conductivity types can be mutually replaced. An exemplary p-type impurity (trivalent element) is boron (B). Exemplary n-type impurities (pentavalent elements) are phosphorus (P) or arsenic (As). Phosphorus (P) may be preferred as the n-type impurity in some cases.

[0031] The material of the semiconductor substrate 1 in this example is Si. The underlying substrate 1A is made of p-type Si. The first epitaxial layer 1B1 is made of p-type Si. The second epitaxial layer 1B2 is made of n-type Si. The first well region 51 is made of n-type Si. The second well region 52 is made of p-type Si. The drain region 53 is made of n-type Si. The source region 54 is made of n-type Si. The contact region 56 is made of p-type Si.

[0032] The impurity concentration of the underlying substrate 1A is 1×10 17 cm -3 or more and 1×10 20 cm -3The thickness of the base substrate 1A may be 50 μm or more and 500 μm or less. The material of the base substrate 1A may be an insulator such as Al2O3 depending on the type of device. The impurity concentration of the first epitaxial layer 1B1 is lower than the impurity concentration of the base substrate 1A, and is 1×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the first epitaxial layer 1B1 may be 1 μm or more and 20 μm or less. The impurity concentration of the second epitaxial layer 1B2 may be 1×10 14 cm -3 More than 1×10 17 cm -3 The second epitaxial layer 1B2 may have a thickness of 5 μm or more and 40 μm or less, or may have a thickness of 5 μm or more and 30 μm or less.

[0033] The impurity concentrations and thicknesses of the first well region 51, the second well region 52, the drain region 53, the source region 54, and the contact region 56 can be set to typical values.

[0034] The insulator 62 embedded in the insulating portion 60 is made of an insulator (inorganic insulator) such as silicon oxide (SiO2) or silicon nitride (Si3N4). The material of the protective film 14 is made of an insulator (inorganic insulator) such as silicon oxide or silicon nitride. The thickness of the protective film 14 is not particularly limited.

[0035] The position of the first main surface 3 of the semiconductor substrate 1 in the Z-axis direction is defined as the reference position Z0. The position of the depth of the first well region 51 or the second well region 52 in the Z-axis direction is defined as the first position Z1. The position of the depth of the epitaxial crystal region 1B in the Z-axis direction is defined as the second position Z2. The position of the bottom surface of the first trench structure TR1 or the second trench structure TR2 is defined as the third position Z3. The thickness (Z2-Z0) of the epitaxial crystal region 1B is greater than the thickness (Z1-Z0) of the first well region 51 or the second well region 52. The depth (Z3-Z0) of the first trench structure TR1 is greater than the thickness (Z2-Z0) of the epitaxial crystal region 1B.

[0036] If the interface position between the first epitaxial layer 1B1 and the second epitaxial layer 1B2 is the pn junction position ZJ, the distance (Z3-ZJ) from the pn junction position ZJ to the third position Z3 may be 1 μm or more and 30 μm or less. The distance (Z3-ZJ) can be 5 μm or more and 25 μm or less. The distance (Z3-ZJ) can be 10 μm or more and 20 μm or less. It is preferable that the distance (Z3-ZJ) is larger than the distance (ZJ-Z0) between the reference position Z0 and the pn junction position ZJ ((ZJ-Z0)<(Z3-ZJ)). When the trench is deep, the isolation function provided by the trench can be reliably achieved.

[0037] The depth of the first trench structure TR1 and the depth of the second trench structure TR2 may be the same. The position of the bottom surface of the first trench structure TR1 is the third position Z3(TR1), and the position of the bottom surface of the second trench structure TR2 is the third position Z3(TR2). The difference in distance between them (third position Z3(TR1)-Z3(TR2)) is preferably 5 μm or less, and more preferably 1 μm or less. When the depths of multiple trenches are close to each other, they can be manufactured using the same process.

[0038] The depth of the first trench structure TR1 and the depth of the second trench structure TR2 may be different. For example, the depth of the second trench structure TR2 may be set to be smaller (third position Z3(TR2)<third position Z3(TR1)).

[0039] A first end region R1 that electrically connects the trench inner region to the base substrate 1A may be formed near the bottom surface of the first trench structure TR1. A second end region R2 (diode) to which a reverse bias is applied may be formed in the region near the bottom surface of the second trench structure TR2 (see FIG. 46).

[0040] Hereinafter, a trench structure TR applicable as the first trench structure TR1 or the second trench structure TR2 in the above-mentioned semiconductor device will be described.

[0041] Next, the first semiconductor device will be described.

[0042] FIG. 4 is a vertical cross-sectional view (XZ cross-sectional view) of the first semiconductor device including the trench structure TR.

[0043] The semiconductor device 100 includes a trench structure TR. Known trench structures include a deep trench isolation structure (DTI structure) and a shallow trench isolation structure (STI structure). The trench structure TR of this example includes a DTI structure 20, a first STI structure 21, and a second STI structure 22. The DTI structure 20 is located between the first STI structure 21 and the second STI structure 22. The trench structure TR is annular in plan view, but the first STI structure 21 is located outside the second STI structure 22 in plan view.

[0044] The DTI structure 20 includes a trench 200 as a groove formed in a semiconductor substrate 1. In a plan view, the trench 200 surrounds a device 50 (see FIG. 3) provided in a region shallower than a first position Z1. The inner surface of the trench 200 is covered with an insulating film 2. The trench 200 includes a first trench 201 located on the bottom side of the trench 200 and a second trench 202 located on the surface side of the trench 200. The first trench 201 narrows in width along the depth direction (positive direction of the Z axis). The second trench 202 is continuous with the first trench 201 and narrows in width along the depth direction (positive direction of the Z axis). In other words, the first trench 201 and the second trench 202 each have a tapered shape. The amount of reduction in width per unit depth of the second trench 202 located on the surface side is greater than the amount of reduction in width per unit depth of the first trench 201 located on the bottom side.

[0045] A first material region 11 is provided in the trench 200. The first material region 11 is in contact with the insulating film 2 covering the trench 200. The first material region 11 includes a first conductive region 11A and a second conductive region 11B. The first conductive region 11A is located inside the first trench 201. The second conductive region 11B is located inside the second trench 202. The first conductive region 11A and the second conductive region 11B are made of the same material and are continuous. The first material region 11 includes the first conductive region 11A and the second conductive region 11B embedded in the first trench 201 and the second trench 202.

[0046] The second material region 12 is located above the second conductive region 11B via a boundary line BD2. Although the manufacturing process of the second conductive region 11B and the manufacturing process of the second material region 12 are different, if they are manufactured from the same main raw material, the boundary line BD2 may not be observable. The boundary line BD2 protrudes in the depth direction and has a pointed shape. The second material region 12 is embedded inside the second conductive region 11B (first material region 11) and has etching characteristics different from those of the second conductive region 11B. When the impurity concentrations added to the semiconductor region are different, the resistance to the etching solution or etching gas is different, resulting in different etching rates and different etching characteristics.

[0047] In this example, the first material region 11 includes polysilicon doped with an impurity, and the second material region 12 includes polysilicon having an impurity concentration lower than the impurity concentration of the first material region 11. When the impurity concentration (e.g., boron) of the first material region 11 is high, the first material region 11 is easy to etch, and when the second material region 12 is embedded in the first material region 11 after etching, the impurity concentration of the second material region 12 is relatively low, so that the resistance of the second material region 12 is high. The conductivity type of the first material region 11 can be either p-type or n-type.

[0048] From this viewpoint, the first impurity concentration C1 of the first material region 11 and the second impurity concentration C2 of the second material region 12 can satisfy the following relationship: 18 cm -3 ≦C1≦1×10 22 cm -3 、 1×10 15 cm -3 ≦C2≦1×10 18 cm -3 It is.

[0049] As the conductive material used for the first material region 11 and the second material region 12, it is also possible to use materials such as tungsten and copper instead of polysilicon.

[0050] The second material region 12 includes a region 12A having a width that narrows toward the bottom surface of the trench 200, as indicated by a boundary line BD2. As described above, the boundary line BD2 may not be observable. The second trench 202 has a shape that narrows toward the bottom surface. Therefore, in the process of filling the inside of the second trench 202 with a conductive material, the conductive material is not filled near the center of the second trench 202 in the width direction, and a seam (space) is formed there. The seam has a shape that traces the shape of the second trench 202, so the seam has a shape that protrudes downward. The second material region 12 is formed by filling this inside the seam, so the region 12A has a shape that protrudes toward the bottom surface.

[0051] The first trench 201 has a first outer inner surface 201A and a first inner inner surface 201B. The second trench 202 has a second outer inner surface 202A and a second inner inner surface 202B. The insulating film 2 has an outer insulating film 2A and an inner insulating film 2B. The outer insulating film 2A is in contact with the first outer inner surface 201A and the second outer inner surface 202A. The inner insulating film 2B is in contact with the first inner inner surface 201B and the second inner inner surface 202B.

[0052] Boundary position BD between first trench 201 and second trench 202 is located closer to the substrate surface than first position Z1. Second position Z2, which is the position of the interface between underlying substrate 1A and epitaxial crystal region 1B, is located deeper than first position Z1. First trench 201 penetrates the interface (second position Z2) between underlying substrate 1A and epitaxial crystal region 1B.

[0053] The first STI structure 21 includes a first recess DP1 formed on the surface of the semiconductor substrate 1 (epitaxial crystal region 1B) and a first insulating region 13 filled in the first recess DP1. OUT The second STI structure 22 includes a second recess DP2 formed in the surface of the semiconductor substrate 1 and a second insulating region 13 filled in the second recess DP2. IN The material of the protective film 14 is the first insulating region 13. OUT and the second insulating region 13 INIf the first and second STI structures 21 and 22 are made of the same material, they are integrated. The protective film 14 covers the second material region 12 located on the upper part of the DTI structure 20. The protective film 14 covers the first STI structure 21 and the second STI structure 22.

[0054] The position of the upper main surface of the second material region 12 embedded in the top of the DTI structure 20 is set as the reference position Z0. The position of the bottom surface of the first recess DP1 is set as the first bottom surface position ZS. The distance from the reference position Z0 to the first bottom surface position ZS is set as the depth ΔZ of the first recess DP1 or the second recess DP2. The STI structure has a function of suppressing leakage current between adjacent elements and ensuring a withstand voltage. From the viewpoint of such function, it is preferable that the recess depth ΔZ of the first recess DP1 and the second recess DP2 as viewed from the reference position Z0 has a depth of a certain value or more. The depth (recess depth ΔZ) of the first recess DP1 is preferably 100 nm or more. The depth (recess depth ΔZ) of the second recess DP2 is preferably 100 nm or more. In this example, since the DTI structure and the STI structure are combined, the STI structure does not need to be too deep. From this viewpoint, the recess depth ΔZ defining the STI structure can be set to 100 nm or more and 500 nm or less. Moreover, the recess depth ΔZ is smaller than the depth (Z1-Z0) of the first position Z1. The recess depth ΔZ is smaller than the depth of the epitaxial crystal region 1B (the depth (Z2-Z0) of the second position Z2). By combining with the DTI structure, a sufficient isolation function can be achieved even under such depth conditions. The depths of the first recess DP1 and the second recess DP2 are smaller than the depth of the epitaxial crystal region 1B (the second position Z2).

[0055] FIG. 5 is an enlarged view of the first region S1 shown in FIG.

[0056] A first STI structure 21 is disposed on the outside of the DTI structure 20, and a second STI structure 22 is disposed on the inside. Each STI structure is formed by embedding an insulator (insulating region) in a recess. The maximum width W DTBThe position of the outer end of the second trench 202 that provides the above-mentioned is defined as a first position (X1), and the position of the inner end is defined as a second position (X6). Above the first position (X1) on the bottom surface of the first recess DP1, the first insulating region 13 in the first recess DP1 is OUT The first insulating region 13 is located OUT This allows sufficient suppression of leakage current. Above the second position (X6) on the bottom surface of the second recess DP2, the second insulating region 13 in the second recess DP2 is IN The second insulating region 13 is located IN This makes it possible to sufficiently suppress the leakage current.

[0057] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The width direction distance W between the second bottom surface 142 (the bottom surface of the second recess DP2) DTC is the maximum width W of the second trench 202 DTB The width direction distance W is smaller than DTC is defined as the distance between the inner end position (X2) of the first bottom surface 141 and the outer end position (X5) of the second bottom surface 142.

[0058] In FIG. 5, the dimensions and angles in the XZ cross section are shown. DTC The first vicinity region 11 at the inner end position (X2) of the first bottom surface 141 has a notch shape in the XZ cross section. OUT In the second conductive region 11B, the insulating film 2 and the first insulating region 13 OUT The first vicinity region 11 is filled in the gap between the first bottom surface 141 and the first vicinity region 11. OUT In this case, the first angle θ141 between the inner surface of the insulating film 2 and the first bottom surface 141 is an acute angle. IN In the second conductive region 11B, the insulating film 2 and the second insulating region 13 IN The second vicinity region 11 is filled in the gap between the second bottom surface 142 and the second vicinity region 11. IN , a second angle θ142 formed between the inner surface of the insulating film 2 and the second bottom surface 142 is an acute angle.

[0059] In the manufacturing process, in order to form a seam (see seam 310 in FIG. 7(A)) with an openable top and then fill the seam with a conductive material (see FIG. 7(C)), it is preferable that the first angle θ141 is set to 30°≦first angle θ141≦60°. Similarly, it is preferable that the second angle θ142 is set to 30°≦second angle θ142≦60°. For the same reason, the widthwise distance W DTC 2μm ≦ Width direction distance W DTC For the same reason, it is preferable that the horizontal thickness of the insulating film 2 is ΔW and the maximum width W DTB is 1μm≦(W DTB It is preferable that the maximum width W DTB 1μm≦W DTB It may be set to ≦10 μm.

[0060] In this case, an exemplary preferred range of the thickness (ΔW) of the insulating film 2 is 100 nm≦ΔW≦1000 nm. When the horizontal thickness ΔW of the insulating film 2 is substantially constant in the depth direction, the thickness ΔW at the boundary position BD can be used as an example, but the thickness at the depth position that gives the maximum width of the trench may also be used. The boundary position width W of the trench 200 that gives the boundary position BD DTA is defined as the distance between the third position (X3) and the fourth position (X4) in the X-axis direction. DTA is the maximum width W DTB Less than.

[0061] The XZ cross section (cross section including the width direction and depth direction of the first trench 201) and the intersection line (first outer inner surface 201A, first inner inner surface 201B) formed by the intersection of the first trench 201 are each line segments and extend linearly. The XZ cross section (cross section including the width direction and depth direction of the second trench 202) and the intersection line (second outer inner surface 202A, second inner inner surface 202B) formed by the intersection of the second trench 202 are each line segments and extend linearly. Since they extend linearly, there is an advantage that the reproducibility of shape control is high.

[0062] The angle (θ1A) between the first outer inner surface 201A of the first trench 201 and the horizontal plane (XY plane) is an acute angle. The angle (θ2A) between the second outer inner surface 202A of the second trench 202 and the horizontal plane (XY plane) is an acute angle. Similarly, the angle (θ1B) between the first inner inner surface 201B of the first trench 201 and the horizontal plane (XY plane) is an acute angle. The angle (θ2B) between the second inner inner surface 202B of the second trench 202 and the horizontal plane (XY plane) is an acute angle. Note that these angles (θ1A, θ2A, θ1B, θ2B) are angles between the direction horizontally away from the trench central axis and the direction upward along each trench inner surface in the XZ plane. The angle (θ1A) of the first trench 201 is larger than the angle (θ2A) of the second trench 202 (θ2A<θ1A). The angle (θ1B) of the first trench 201 is larger than the angle (θ2B) of the second trench 202 (θ2B<θ1B).

[0063] Since the first trench 201 extends to a deep position, the angle (θ1A) and the angle (θ1B) are set to a reference angle (θ UNDER ) and smaller than 90° (θ UNDER <θ1A<90°, θ UNDER <θ1B<90°). UNDER ) is 89.0°. The angle (θ2A) and the angle (θ2B) of the second trench 202 can be set to 80°≦angle (θ2A)<90° and 80°≦angle (θ2B)<90° for reasons such as seam filling.

[0064] The width of second material region 12 is constant up to a position (ZR) that is slightly deeper than reference position Z0. The width of second material region 12 gradually increases from position (ZR) in the depth direction to the positions of first bottom surface 141 and second bottom surface 142. In the manufacturing process, a mask of the same width is placed on the top surface (reference position Z0) of second material region 12 (fifth insulating film 313 (mask) in FIG. 8(F)), and the semiconductor region below within the mask opening is etched through this mask, resulting in this shape. When the mask width is changed, the above-mentioned widthwise distance W DTCIn other words, the shape of this example changes the width direction distance W DTC This shows that the structure is controlled so that the difference falls within the above-mentioned preferred range.

[0065] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0066] 6 to 9 are diagrams for explaining the method for manufacturing the first semiconductor device, and the steps described below are carried out in order.

[0067] As shown in Fig. 6(A), a first insulating film 301, a second insulating film 302, and a third insulating film 303 are laminated on a semiconductor substrate 1. A first resist material 304 is formed on the third insulating film 303. The first resist material 304 is patterned to form a first opening 305. The material of the semiconductor substrate 1 is silicon (Si). The material of the first insulating film 301 is silicon dioxide (SiO2), the material of the second insulating film 302 is silicon nitride (Si3N4), and the material of the third insulating film 303 is silicon dioxide (SiO2).

[0068] When silicon dioxide is formed on an exposed silicon surface as in the first insulating film 301, thermal oxidation of silicon can be used. When silicon nitride is formed as in the second insulating film 302, a low pressure CVD (chemical vapor deposition) method for forming silicon nitride can be used. Examples of raw material gases for the CVD method for forming silicon nitride include a mixed gas of dichlorosilane gas (SiH2Cl2), ammonia gas (NH3), and nitrogen gas (N2). When a relatively thick silicon dioxide is formed as in the third insulating film 303, a CVD method can be used. Examples of the CVD method for forming silicon dioxide include a formation method using TEOS (Si(OC2H5)4).

[0069] As shown in FIG. 6(B), the third insulating film 303, the second insulating film 302, and the first insulating film 301 are sequentially etched using the patterned first resist material 304 as a mask, and are patterned into the same shape as the mask opening. Anisotropic dry etching for insulating films can be used as the etching method. A laminate consisting of the patterned third insulating film 303, the second insulating film 302, and the first insulating film 301 is used as a hard mask. When anisotropic dry etching for insulating films is performed, a fluorocarbon-based etching gas is exemplified.

[0070] 6(C), the first resist material 304 is removed. If the first resist material 304 is made of a resin, it can be removed using an organic solvent.

[0071] As shown in Fig. 6(D), the front side of the semiconductor substrate 1 is etched through the opening of the hard mask including the third insulating film 303 to form a front side recess 306. The front side recess 306 corresponds to the above-mentioned second trench 202 (see Fig. 4). As an etching method, wet etching for silicon can be used. The width of the upper part of the front side recess 306 expands to a position where the lower surface of the first insulating film 301 is exposed.

[0072] Examples of etching solutions used in wet etching methods for silicon include acidic etching solutions such as hydrofluoric acid and nitric acid, and alkaline etching solutions such as KOH and ammonia. When using these wet etching methods, isotropic etching is performed on the lower surface of the hard mask. It is also possible to use wet etching at the beginning of etching and then dry etching. Known dry etching methods include anisotropic etching such as reactive ion etching (RIE) and isotropic dry etching using active species. Therefore, it is also possible to use only isotropic dry etching in forming the front side recess 306. By changing the control parameters during etching (temperature, time, type of etching solution or etching gas, etc.), etching of a desired shape can be performed. Examples of anisotropic dry etching methods for silicon include a method using reactive ion etching (RIE). Examples of etching gases for dry etching include those using fluorine-containing gases such as CF4 and SF6.

[0073] In the process of FIG. 6(D), the semiconductor substrate 1 is etched through an opening in a mask (a hard mask including a third insulating film) provided on the semiconductor substrate 1, to form a space (a second trench 202 (see FIG. 4)) directly below the opening and directly below a region outside both ends of the opening in the width direction.

[0074] As shown in FIG. 6(E), the semiconductor substrate 1 is further etched through the opening of the hard mask including the third insulating film 303, that is, the bottom of the front surface side recess 306 is etched to form a trench consisting of a deep bottom recess 307. Dry etching for silicon can be used as the etching method. For example, anisotropic dry etching using RIE can be used. In this process, the semiconductor substrate 1 is dry etched through the opening of the hard mask to form a trench (first trench 201) that is continuous with the space (second trench 202).

[0075] 6(F), an insulating film 2 is formed on the exposed surface of the deep-bottom recess 307 (trench). Thermal oxidation of silicon can be used as a formation method, and silicon dioxide can be formed as the insulating film 2. In this process, the insulating film 2 is formed on the exposed surfaces of the space (second trench 202) and the trench (first trench 201).

[0076] 6(G), a portion of the insulating film 2 located on the bottom surface of the deep recess 307 (trench) is removed to expose the semiconductor substrate 1 located on the bottom surface of the deep recess 307. Anisotropic dry etching for insulating films can be used as the removal method.

[0077] As shown in FIG. 6(H), a first conductive material 309 is formed so as to cover the insulating film 2 inside the trench, the inner side surface of the opening of the hard mask including the third insulating film 303, and the upper surface of the hard mask. The first conductive material 309 is polysilicon to which an impurity is added, and a CVD method can be used as a method for forming the first conductive material 309. A forming method using silane (SiH4) is exemplified as a CVD method capable of forming polysilicon. In this process, the first conductive material 309 is supplied into the trench (first trench 201) through the opening of the hard mask to form the first conductive region 11A, and the first conductive material 309 is supplied into this space (second trench 202) to form the second conductive region 11B having the seam 310, thereby forming the first material region 11 including the first conductive region 11A and the second conductive region 11B.

[0078] As shown in FIG. 7(A), the exposed surface of the first conductive material 309 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the third insulating film 303.

[0079] As shown in FIG. 7B, the conductive material filled in the opening of the hard mask including the third insulating film 303 is etched to open and expose the upper part of the seam 310. This etching can be performed by anisotropic dry etching for silicon. The etching is performed to a position deeper than the lower surface position of the first insulating film 301. This etching forms the first material region 11 in the trench. In this process, the second conductive region 11B is etched through the opening of the hard mask until the seam 310 in the second conductive region 11B is reached.

[0080] As shown in FIG. 7C, an upper conductive material 311 is formed so as to fill the opening of the hard mask including the third insulating film 303. The inside of the seam 310 that existed on the upper part of the first material region 11 is filled with the upper conductive material 311. The upper conductive material 311 is also deposited on the surface of the third insulating film 303. The material of the upper conductive material 311 is undoped polysilicon, and can be formed by using a CVD method. An example of a CVD method capable of forming polysilicon is a formation method using silane (SiH4). In this process, the upper conductive material 311 is supplied into the seam 310 through the opening of the hard mask, and the second material region 12 is formed in the seam 310.

[0081] As shown in FIG. 7(D), the exposed surface of the upper conductive material 311 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the third insulating film 303.

[0082] 7(E), the exposed surface of the third insulating film 303 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the second insulating film 302. By this process, the upper conductive material 311 existing in the opening of the third insulating film 303 is also removed.

[0083] 7(F), the second insulating film 302 is removed. The second insulating film 302 made of silicon nitride can be removed by wet etching. Examples of the etching liquid include phosphoric acid (H3PO4).

[0084] 7(G), the first insulating film 301 is removed. The first insulating film 301 made of silicon dioxide can be removed by wet etching. An example of the etching liquid is hydrofluoric acid (HF).

[0085] 8(A), a fourth insulating film 312 is formed on the exposed surface of the semiconductor substrate 1. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the fourth insulating film 312.

[0086] 8(B), a fifth insulating film 313 is formed on the fourth insulating film 312. The fifth insulating film 313 is made of silicon nitride, and a low-pressure CVD method for forming silicon nitride can be used as a forming method.

[0087] 8(C), a second resist material 314 is formed on the fifth insulating film 313. The second resist material 314 is patterned so as to open a region where a recess for an STI structure is to be formed.

[0088] 8(D), the fifth insulating film 313 and the fourth insulating film 312 present in the openings of the mask made of the second resist material 314 are sequentially etched to form a hard mask including the fifth insulating film 313. For this etching, dry etching for insulating films can be used.

[0089] 8(E), the second resist material 314 is removed. If the second resist material 314 is made of a resin, it can be removed using an organic solvent.

[0090] 8(F), the semiconductor substrate 1 is etched through the openings in the hard mask including the fifth insulating film 313 to form the first recess DP1 and the second recess DP2. As the etching method, a wet etching method or a dry etching method for silicon can be used. In this etching step, the top of the insulating film 2 can be positioned higher than the bottom surfaces of the first recess DP1 and the second recess DP2.

[0091] 8(G), a sixth insulating film 315 is formed on the exposed surfaces of the first recess DP1 and the second recess DP2. As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the sixth insulating film 315.

[0092] 8(H), the seventh insulating film 316 is formed so as to fill the first recess DP1 and the second recess DP2. As a forming method, a CVD method for forming silicon dioxide can be used, and a forming method using TEOS is exemplified, and silicon dioxide can be formed as the seventh insulating film 316. The seventh insulating film 316 is also formed on the fifth insulating film 313.

[0093] As shown in FIG. 9(A), the exposed surface of the seventh insulating film 316 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the fifth insulating film 313.

[0094] As shown in FIG. 9(B), the fifth insulating film 313 is removed. Wet etching can be used as a method for removing the fifth insulating film 313 made of silicon nitride. Phosphoric acid (H3PO4) is an example of an etching solution. Finally, a protective film is formed to cover the substrate surface, completing the structure having the protective film 14 shown in FIG. 4. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0095] FIG. 10 is a vertical cross-sectional view of a first semiconductor device including a trench structure without an STI structure.

[0096] The semiconductor device of this example differs from the semiconductor device shown in Fig. 4 in that it does not have an STI structure, but the other configurations are the same. The upper part of the insulating film 2 is continuous with the protective film 14, and the shape of the upper end portion of the second trench 202 in which the insulating film 2 is formed differs from that of the semiconductor device shown in Fig. 4. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is defined as a first bottom surface 141, the bottom surface of the protective film 14 located inside the trench is defined as a second bottom surface 142, and the position of these bottom surfaces is defined as ZT.

[0097] First Neighborhood Region 11 OUT In the second vicinity region 11, a first angle θ141 formed between the inner surface of the insulating film 2 and the first bottom surface 141 is an acute angle. IN 8(A), a second angle θ142 formed between the inner surface of the insulating film 2 and the second bottom surface 142 is an acute angle. The preferred ranges of the first angle θ141 and the second angle θ142 are the same as the preferred ranges of the first angle θ141 and the second angle θ142 shown in FIG. 5. The boundary line BD2 expands in the depth direction from the bottom surface position ZT. This structure can be manufactured by forming a protective film 14 on the exposed surface of the substrate after the process of FIG. 8(A).

[0098] Next, the second semiconductor device will be described.

[0099] FIG. 11 is a vertical cross-sectional view (XZ cross-sectional view) of a second semiconductor device including a trench structure TR.

[0100] The only difference between the first semiconductor device (FIG. 4) and the second semiconductor device (FIG. 11) is the shape of the second trench 202, and the other structures are the same as those of the first semiconductor device. The differences will be described below.

[0101] The first trench 201 narrows in width along the depth direction (positive direction of the Z axis). The second trench 202 is continuous with the first trench 201, and narrows in width along the depth direction (positive direction of the Z axis). The amount of reduction in width per unit depth of the second trench 202 located on the surface side is larger than the amount of reduction in width per unit depth of the first trench 201 located on the bottom side, but the intersection lines of the trench inner surfaces constituting the XZ cross-sectional shape of the second trench 202 are each arc-shaped.

[0102] The second material region 12 is located above the second conductive region 11B with a boundary line BD2 in between. Although the manufacturing process of the second conductive region 11B and the manufacturing process of the second material region 12 are different, when they are manufactured from the same main raw material, the boundary line BD2 may not be observable. In this example, the boundary line BD2 has an arc shape that bulges in the depth direction.

[0103] The second material region 12 includes a region 12A having a width that narrows toward the bottom surface of the trench 200, as shown by a boundary line BD2. In the process of filling the inside of the second trench 202 with a conductive material, the conductive material is not filled near the center in the width direction of the second trench 202, and a seam (space) having an arc-shaped bottom surface is formed there. The seam has a shape that traces the shape of the second trench 202, so the seam has a shape that bulges downward. The second material region 12 is formed by filling this into the seam, so the region 12A has a shape that gently protrudes toward the bottom surface.

[0104] FIG. 12 is an enlarged view of the second region S2 shown in FIG.

[0105] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The width direction distance W between the second bottom surface 142 (the bottom surface of the second recess DP2) DTC is the maximum width W of the second trench 202 DTB The width direction distance W is smaller than DTC is defined as the distance between the inner end position (X2) of the first bottom surface 141 and the outer end position (X5) of the second bottom surface 142.

[0106] A first vicinity region 11 where the first bottom surface 141 and the insulating film 2 intersect OUT In the second conductive region 11B, the insulating film 2 and the first insulating region 13 OUT The first vicinity region 11 is filled in the gap between the first bottom surface 141 and the first vicinity region 11. OUT In the second vicinity region 11 where the second bottom surface 142 and the insulating film 2 intersect, a first angle θ141 formed by the inner surface of the insulating film 2 and the first bottom surface 141 is an acute angle. IN In the second conductive region 11B, the insulating film 2 and the second insulating region 13 IN The second vicinity region 11 is filled in the gap between the second bottom surface 142 and the second vicinity region 11. IN , a second angle θ142 formed between the inner surface of the insulating film 2 and the second bottom surface 142 is an acute angle.

[0107] In the manufacturing process, in order to form a seam (see seam 310 in FIG. 14(A)) with an openable top and then fill the seam with a conductive material (see FIG. 14(C)), the first angle θ141 can be set to 30°≦first angle θ141≦60°. Similarly, the second angle θ142 can be set to 30°≦second angle θ142≦60°. Note that the first angle θ141 and the second angle θ142 in FIG. 12 may be set to angles larger than the angles shown in FIG. 5 or larger than the above range.

[0108] For the same reason, the width direction distance W DTC 2μm ≦ Width direction distance W DTC For the same reason, it is preferable that the thickness of the insulating film 2 is ΔW and the maximum width W DTB is 1μm≦(W DTB It is preferable that the maximum width W DTB 1μm≦W DTB It may be set to ≦10 μm.

[0109] In this case, an exemplary preferred range of the thickness (ΔW) of the insulating film 2 is 100 nm (0.1 μm)≦ΔW≦1000 nm (1 μm). When the horizontal thickness ΔW of the insulating film 2 is substantially constant in the depth direction, the thickness ΔW at the boundary position BD can be used as an example, but the thickness at the depth position that gives the maximum width of the trench may also be used. The boundary position width W of the trench 200 that gives the boundary position BD DTA is defined as the distance between the third position (X3) and the fourth position (X4) in the X-axis direction. DTA is the maximum width W DTB Less than.

[0110] The XZ cross section (a cross section including the width direction and depth direction of the second trench 202) and the intersection lines (second outer inner surface 202A, second inner inner surface 202B) formed by the intersection of the second trench 202 each extend in an arc shape. These arc-shaped intersection lines are curved so as to bulge in the depth direction. In other words, the rate of decrease in the width of the second trench 202 per depth increases toward the depth direction, that is, toward the boundary position BD. When the first angle θ141 and the second angle θ142 are large, it becomes easier to fill this region with the second material region 12.

[0111] The inner surface angle of the first trench 201 is the same as that of the first semiconductor device. Since the inner surface of the second trench 202 is arc-shaped, the average angle is defined at a position that is 1 / 2 the Z-axis distance of the second trench 202. That is, the Z-axis distance between the boundary position BD between the first trench 201 and the second trench 202 and the first bottom surface 141 is set to ΔC, and the angle of the second trench 202 is defined at a position that is ΔC / 2 above the boundary position BD.

[0112] The angle (θ2A) between the second outer inner surface 202A of the second trench 202 and the horizontal plane (XY plane) is an acute angle. The angle (θ2B) between the second inner inner surface 202B of the second trench 202 and the horizontal plane (XY plane) is an acute angle. The angle (θ1A) of the first trench 201 is larger than the angle (θ2A) of the second trench 202 (θ2A<θ1A). The angle (θ1B) of the first trench 201 is larger than the angle (θ2B) of the second trench 202 (θ2B<θ1B).

[0113] The angle (θ2A) and the angle (θ2B) of the second trench 202 can be set to 80°≦angle (θ2A)<90° and 80°≦angle (θ2B)<90° for reasons such as filling the seam.

[0114] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0115] 13 to 16 are diagrams for explaining the second method for manufacturing a semiconductor device, and the steps described below are carried out in order.

[0116] The steps in FIG. 13(A) to FIG. 13(C) are the same as the steps in FIG. 6(A) to FIG. 6(C).

[0117] In the step of FIG. 13(D), the front side of the semiconductor substrate 1 is etched through the opening of the hard mask including the third insulating film 303 to form a front side recess 306. This is the same as the step of FIG. 6(D), but the isotropy of the etching is increased in the step of FIG. 13(D) compared to the step of FIG. 6(D). As the etching method, wet etching for silicon can be used. The width of the upper part of the front side recess 306 expands to the position where the lower surface of the first insulating film 301 is exposed. The vertical cross-sectional shape of the front side recess 306 is an arc shape.

[0118] In the process of FIG. 13(D), the semiconductor substrate 1 is etched through an opening in a mask (a hard mask including a third insulating film) provided on the semiconductor substrate 1, to form a space (a second trench 202 (see FIG. 11)) directly below the opening and directly below a region outside both ends of the opening in the width direction.

[0119] The steps in FIG. 13(E) to FIG. 13(H) are the same as the steps in FIG. 6(E) to FIG. 6(H).

[0120] The steps in FIG. 14(A) to FIG. 14(G) are the same as the steps in FIG. 7(A) to FIG. 7(G).

[0121] The steps in FIG. 15(A) to FIG. 15(H) are the same as the steps in FIG. 8(A) to FIG. 8(H).

[0122] The steps in Figures 16(A) and 16(B) are the same as those in Figures 9(A) and 9(B). Finally, a protective film is formed to cover the surface of the substrate, completing the structure having the protective film 14 shown in Figure 11. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0123] FIG. 17 is a vertical cross-sectional view of a second semiconductor device including a trench structure without an STI structure.

[0124] 11 in that it does not have an STI structure, but the other configurations are the same. The upper part of the insulating film 2 is continuous with the protective film 14, and the shape of the upper end portion of the second trench 202 in which the insulating film 2 is formed is different from that of the semiconductor device shown in Fig. 11. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is defined as a first bottom surface 141, the bottom surface of the protective film 14 located inside the trench is defined as a second bottom surface 142, and the position of these bottom surfaces is defined as ZT.

[0125] First Neighborhood Region 11 OUT In the second vicinity region 11, a first angle θ141 formed between the inner surface of the insulating film 2 and the first bottom surface 141 is an acute angle. IN 15(A), a second angle θ142 formed between the inner surface of the insulating film 2 and the second bottom surface 142 is an acute angle. The preferred ranges of the first angle θ141 and the second angle θ142 are the same as the preferred ranges of the first angle θ141 and the second angle θ142 shown in FIG. 12. The boundary line BD2 expands in the depth direction from the bottom surface position ZT. This structure can be manufactured by forming a protective film 14 on the exposed surface of the substrate after the process of FIG. 15(A).

[0126] Next, the third semiconductor device will be described.

[0127] FIG. 18 is a vertical cross-sectional view (XZ cross-sectional view) of a third semiconductor device including a trench structure TR.

[0128] The semiconductor device 100 includes a trench structure TR. The trench structure TR of this example includes a DTI structure 20, a first STI structure 21, and a second STI structure 22. The DTI structure 20 is located between the first STI structure 21 and the second STI structure 22. The trench structure TR is annular in plan view, but the first STI structure 21 is located outside the second STI structure 22 in plan view.

[0129] The DTI structure 20 includes a trench 200 as a groove formed in a semiconductor substrate 1. In a plan view, the trench 200 surrounds a device 50 (see FIG. 3) provided in a region shallower than a first position Z1. The inner surface of the trench 200 is covered with an insulating film 2. The trench 200 includes a first trench 201 similar to the first and second semiconductor devices, and the inclination angle of the inner surface of the first trench 201 can satisfy the above-mentioned range. The width of the first trench 201 narrows along the depth direction (positive direction of the Z axis). In other words, the first trench 201 has a tapered shape.

[0130] A first material region 11 is provided in the trench 200. The first material region 11 is in contact with the insulating film 2 covering the trench 200. A second material region 12 is located above the first material region 11 via a boundary line BD2. The first material region 11 and the second material region 12 form a conductive region. The first and second material regions are manufactured using different manufacturing processes, but when they are manufactured from the same main raw material, the boundary line BD2 may not be observable. The boundary line BD2 extends along a horizontal plane (XY plane). The second material region 12 has different etching characteristics from the first material region 11. When the impurity concentrations added to the semiconductor region are different, the resistance to the etching solution or etching gas is different, and therefore the etching speed is different and the etching characteristics are different.

[0131] In this example, the first material region 11 includes polysilicon doped with an impurity, and the second material region 12 includes polysilicon having an impurity concentration lower than the impurity concentration of the first material region 11. When the impurity concentration (e.g., boron) of the first material region 11 is high, the first material region 11 is easy to etch, and when the second material region 12 is formed on the first material region 11 after etching, the impurity concentration of the second material region 12 is relatively low, so that the resistance of the second material region 12 is high. The conductivity type of the first material region 11 can be either p-type or n-type.

[0132] From this perspective, the first impurity concentration C1 of the first material region 11 and the second impurity concentration C2 of the second material region 12 can be set to the same concentration range as in the above-mentioned first and second semiconductor devices.

[0133] The conductive material embedded in the trench 200 tends to trace the shape of the inner surface of the trench 200. If the opening width of the trench 200 is wide and the inclination of the inner surface is gentle, seams are unlikely to be formed in the embedded conductive material. Therefore, during manufacturing, if the trench opening width is wide and the surface inclination of the upper positions (first upper position 2AT, second upper position 2BT (see FIG. 20(F))) of the insulating film 2 is gentle, seams are unlikely to be formed. To form a gentle surface, the insulating film 2 is made thick. In this example, the opening width of the trench 200 is relatively wide, and the thickness ΔW of the insulating film 2 (thickness in the horizontal plane (width direction (X-axis direction))) is set large.

[0134] The direction perpendicular to the thickness direction of the semiconductor substrate 1 is taken as the horizontal direction, and the maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction within the trench 200 satisfies the following range: 0.1 μm≦ΔW≦1 μm.

[0135] If the maximum value of ΔW is below the lower limit, the effect of suppressing the occurrence of seams is reduced, and if it exceeds the upper limit, the trench dimensions become larger than necessary. Note that the depth at which the maximum value of the thickness ΔW is obtained is a position near the first bottom position ZS of the first recess DP1 in this example.

[0136] The first trench 201 has a first outer inner surface 201A and a first inner inner surface 201B. The insulating film 2 has an outer insulating film 2A and an inner insulating film 2B. The outer insulating film 2A is in contact with the first outer inner surface 201A. The inner insulating film 2B is in contact with the first inner inner surface 201B.

[0137] First trench 201 penetrates the interface (second position Z2) between underlying substrate 1A and epitaxial crystal region 1B.

[0138] The first STI structure 21 includes a first recess DP1 formed on the surface of the semiconductor substrate 1 (epitaxial crystal region 1B) and a first insulating region 13 filled in the first recess DP1. OUT The second STI structure 22 includes a second recess DP2 formed in the surface of the semiconductor substrate 1 and a second insulating region 13 filled in the second recess DP2. IN The material of the protective film 14 is the first insulating region 13. OUT and the second insulating region 13 IN If the first and second STI structures 21 and 22 are made of the same material, they are integrated. The protective film 14 covers the second material region 12 located on the upper part of the DTI structure 20. The protective film 14 covers the first STI structure 21 and the second STI structure 22.

[0139] The position of the upper main surface of the second material region 12 embedded in the uppermost portion of the DTI structure 20 is defined as the reference position Z0. The position of the bottom surface of the first recess DP1 is defined as the first bottom position ZS. The distance from the reference position Z0 to the first bottom position ZS is defined as the depth ΔZ of the first recess DP1 or the second recess DP2. The STI structure has the function of suppressing leakage current between adjacent elements and ensuring a withstand voltage. From the viewpoint of such function, it is preferable that the recess depth ΔZ of the first recess DP1 and the second recess DP2 as viewed from the reference position Z0 has a depth of a certain value or more. The depth of the first recess DP1 (recess depth ΔZ) and the depth of the second recess DP2 (recess depth ΔZ) can be set to the same range as that described in the first semiconductor device.

[0140] FIG. 19 is an enlarged view of the third region S3 shown in FIG.

[0141] A first STI structure 21 is disposed on the outside of the DTI structure 20, and a second STI structure 22 is disposed on the inside. Each STI structure is formed by embedding an insulator (insulating region) in a recess. The maximum width W DTB The position of the outer end of the trench 200 that provides this is defined as a first position (X1), and the position of the inner end is defined as a second position (X6).

[0142] The horizontal thickness of the insulating film 2 is ΔW, and the maximum width W DTB is 1μm≦(WDTB It is preferable that the maximum width W DTB 1μm≦W DTB The horizontal thickness ΔW of the insulating film 2 may be, for example, the thickness ΔW at the first bottom surface position ZS, but may also be the thickness at the depth position that gives the maximum width of the trench.

[0143] The first recess DP1 extends outward from the first position (X1). The second recess DP2 extends inward from the second position (X6). A first insulating region 13 is formed in the first recess DP1. OUT The first insulating region 13 is located OUT As a result, the leakage current can be sufficiently suppressed. IN The second insulating region 13 is located IN This makes it possible to sufficiently suppress the leakage current.

[0144] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The position in the depth direction of the second bottom surface 142 (the bottom surface of the second recess DP2) is the first bottom surface position ZS. The maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction in the above-mentioned trench 200 (first trench 201) is, for example, the value at the first bottom surface position ZS. OUT The first bottom surface 141 and the second insulating region 13 IN The distance (width direction distance) between the second bottom surface 142 and the maximum width W of the trench 200 DTB Greater than.

[0145] The XZ cross section (a cross section including the width direction and depth direction of the first trench 201) and the intersection lines (first outer inner surface 201A, first inner inner surface 201B) formed by the intersection of the first trench 201 are each line segments and extend linearly. Since they extend linearly, there is an advantage that the reproducibility of shape control is high.

[0146] The width of second material region 12 gradually increases from reference position Z0 along the depth direction. In the manufacturing process, a mask of the same width is placed on the top surface (reference position Z0) of second material region 12 (fifth insulating film 313 (mask) in FIG. 22(F)), and the semiconductor region below the mask opening is etched through this mask. The shape of the region below the top surface of second material region 12 can be controlled by the mask width and etching method.

[0147] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0148] 20 to 23 are diagrams for explaining the third method for manufacturing a semiconductor device, in which the steps described below are carried out in order.

[0149] The steps in FIG. 20(A) to FIG. 20(C) are the same as those in FIG. 6(A) to FIG. 6(C).

[0150] As shown in FIG. 20(D), the semiconductor substrate 1 is etched through the opening of the hard mask including the third insulating film 303 to form a trench 200 consisting of a deep bottom recess 307. Dry etching for silicon can be used as the etching method. For example, anisotropic dry etching using RIE can be used. The method of anisotropic dry etching is as described in the first and second semiconductor device manufacturing methods.

[0151] 20(E), an insulating film 2 is formed on the exposed surface of the deep bottom recess 307 (trench). As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the insulating film 2.

[0152] As shown in FIG. 20(F), a portion of the insulating film 2 located on the bottom surface of the deep recess 307 (trench) is removed to expose the semiconductor substrate 1 located on the bottom surface of the deep recess 307. Anisotropic dry etching for insulating films can be used as a removal method. By this etching, the shape of the upper end surface of the insulating film 2 becomes a gentle arc in the XZ cross section. The surfaces of the first upper position 2AT and the second upper position 2BT of the insulating film 2 are deformed by the anisotropic dry etching so as to gently drop inside the trench.

[0153] As shown in FIG. 20(G), a first conductive material 309 is formed so as to cover the insulating film 2 inside the trench, the inner side surface of the opening of the hard mask including the third insulating film 303, and the upper surface of the hard mask. The first conductive material 309 is polysilicon doped with impurities, and a CVD method can be used as a method for forming the first conductive material 309. For the reasons described above, the occurrence of regions inside the trench that are not filled with the first conductive material 309 is suppressed. An example of a CVD method capable of forming polysilicon is a formation method using silane (SiH4).

[0154] As shown in FIG. 20(H), the exposed surface of the first conductive material 309 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the third insulating film 303.

[0155] As shown in FIG. 21(A), the first conductive material 309 filled in the opening of the hard mask including the third insulating film 303 is etched to expose the above-mentioned first upper position 2AT and second upper position 2BT. The top surface position of the first conductive material 309 (first material region 11) is lowered to the inside of the trench 200. This etching can be performed by anisotropic dry etching for silicon. The etching is performed to a position deeper than the bottom surface position of the first insulating film 301. This etching leaves the first conductive material 309 (first material region 11) in the trench 200.

[0156] 21(B), an upper conductive material 311 is formed on the first conductive material 309 so as to fill the openings of the hard mask including the third insulating film 303. The upper conductive material 311 is also deposited on the surface of the third insulating film 303. The material of the upper conductive material 311 is undoped polysilicon, and can be formed by a CVD method using silane (SiH4) or the like.

[0157] As shown in FIG. 21(C), the exposed surface of the upper conductive material 311 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the third insulating film 303.

[0158] 21(D), the exposed surface of the third insulating film 303 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the second insulating film 302. By this process, the upper conductive material 311 existing in the opening of the third insulating film 303 is also removed.

[0159] 21(E), the second insulating film 302 is removed. The second insulating film 302 made of silicon nitride can be removed by wet etching. Examples of the etching liquid include phosphoric acid (H3PO4).

[0160] 21(F), the first insulating film 301 is removed. The first insulating film 301 made of silicon dioxide can be removed by wet etching. An example of the etching liquid is hydrofluoric acid (HF).

[0161] 22(A), a fourth insulating film 312 is formed on the exposed surface of the semiconductor substrate 1. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the fourth insulating film 312.

[0162] 22(B), a fifth insulating film 313 is formed on the fourth insulating film 312. The fifth insulating film 313 is made of silicon nitride, and a low-pressure CVD method for forming silicon nitride can be used as a forming method.

[0163] 22C, a second resist material 314 is formed on the fifth insulating film 313. The second resist material 314 is patterned so as to open a region where a recess for an STI structure is to be formed.

[0164] 22(D), the fifth insulating film 313 and the fourth insulating film 312 present in the openings of the mask made of the second resist material 314 are sequentially etched to form a hard mask including the fifth insulating film 313. For this etching, dry etching for insulating films can be used.

[0165] 22(E), the second resist material 314 is removed. If the second resist material 314 is made of a resin, it can be removed using an organic solvent.

[0166] 22(F), the semiconductor substrate 1 is etched through the openings in the hard mask including the fifth insulating film 313 to form the first recess DP1 and the second recess DP2. As the etching method, a wet etching method or a dry etching method for silicon can be used. In this etching step, the top of the insulating film 2 can be positioned higher than the bottom surfaces of the first recess DP1 and the second recess DP2.

[0167] 22(G), a sixth insulating film 315 is formed on the exposed surfaces of the first recess DP1 and the second recess DP2. As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the sixth insulating film 315.

[0168] 22(H), a seventh insulating film 316 is formed so as to fill the first recess DP1 and the second recess DP2. As a forming method, a CVD method for forming silicon dioxide can be used, and a forming method using TEOS is exemplified, and silicon dioxide can be formed as the seventh insulating film 316. The seventh insulating film 316 is also formed on the fifth insulating film 313.

[0169] As shown in FIG. 23(A), the exposed surface of the seventh insulating film 316 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the fifth insulating film 313.

[0170] As shown in FIG. 23(B), the fifth insulating film 313 is removed. Wet etching can be used as a method for removing the fifth insulating film 313 made of silicon nitride. Phosphoric acid (H3PO4) is an example of an etching solution. Finally, a protective film is formed to cover the substrate surface, completing the structure having the protective film 14 shown in FIG. 18. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0171] FIG. 24 is a vertical cross-sectional view of a third semiconductor device including a trench structure without an STI structure.

[0172] The semiconductor device of this example is different from the semiconductor device shown in FIG. 18 in that it does not have an STI structure, but the other configurations are the same. The upper part of the insulating film 2 is continuous with the protective film 14. In the XZ cross section, the first trench 201 extending linearly from the bottom side is continuous with the lower surface of the protective film 14. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is the first bottom surface 141, and the bottom surface of the protective film 14 located inside the trench is the second bottom surface 142, and the bottom surface position is ZT. The boundary line BD2 can be set at a position deeper than the bottom surface position ZT. The boundary line BD2 can be set so as to be in contact with the surfaces of the first upper position 2AT and the second upper position 2BT shown in FIG. 20(F). The depth that gives the maximum value of the horizontal thickness ΔW of the insulating film 2 can be set at a position directly below the first upper position 2AT and the second upper position 2BT. This structure can be manufactured by forming a protective film 14 on the exposed surface of the substrate after the step of FIG. 22(A).

[0173] Next, the fourth semiconductor device will be described.

[0174] FIG. 25 is a vertical cross-sectional view (XZ cross-sectional view) of a fourth semiconductor device including a trench structure TR.

[0175] The semiconductor device 100 includes a trench structure TR. The trench structure TR of this example includes a DTI structure 20, a first STI structure 21, and a second STI structure 22. The DTI structure 20 is located between the first STI structure 21 and the second STI structure 22. The trench structure TR is annular in plan view, but the first STI structure 21 is located outside the second STI structure 22 in plan view.

[0176] The DTI structure 20 includes a trench 200 as a groove formed in a semiconductor substrate 1. In a plan view, the trench 200 surrounds a device 50 (see FIG. 3) provided in a region shallower than a first position Z1. The inner surface of the trench 200 is covered with an insulating film 2. The trench 200 includes a first trench 201 similar to the first to third semiconductor devices, and the inclination angle of the inner surface of the first trench 201 can satisfy the above-mentioned range. The width of the first trench 201 narrows along the depth direction (positive direction of the Z axis). In other words, the first trench 201 has a tapered shape.

[0177] First trench 201 has first outer inner surface 201A and first inner inner surface 201B. Insulating film 2 has outer insulating film 2A and inner insulating film 2B. Outer insulating film 2A is in contact with first outer inner surface 201A. Inner insulating film 2B is in contact with first inner inner surface 201B. First trench 201 penetrates the interface (second position Z2) between base substrate 1A and epitaxial crystal region 1B.

[0178] The inner surface of the insulating film 2 has a first inner surface (first lower side surface 2AX, second lower side surface 2BX) located on the bottom side of the trench 200. The inner surface of the insulating film 2 has a second inner surface (curved surface 2AA, curved surface 2BB) located on the surface side (substrate surface side) of the trench 200, continuous with the first inner surface, and narrowing in width along the depth direction. In this example, the boundary position BD between these first and second inner surfaces is set above the first bottom surface position ZS in the depth direction, but it can also be set below it.

[0179] The first lower side surface 2AX of the insulating film 2 faces the first outer inner surface 201A of the first trench 201, and the second lower side surface 2BX faces the first inner inner surface 201B of the first trench 201. The curved surface 2AA located at the upper part of the insulating film 2 has an arc shape and has a shape that bulges in the depth direction. The curved surface 2BB located at the upper part of the insulating film 2 has an arc shape and has a shape that bulges in the depth direction. In other words, multiple intersection lines formed by the intersection of a cross section (XZ cross section) including the width direction and depth direction of the trench 200 and the second inner surface (curved surface 2AA, curved surface 2BB) each have an arc shape.

[0180] The conductive region (first material region 11) filled inside the trench 200 extends to a position deeper than the deepest position (third position Z3) of the insulating film 2. This is because, after the formation of the above-mentioned second inner surface (curved surface 2AA, curved surface 2BB), the filling material inside the trench is removed until the bottom of the insulating film 2 is removed (see FIG. 28(D)). The deepest position of the first material region 11 is deeper than the deepest position (third position Z3) of the insulating film 2 by a depth difference ΔZ3. This depth difference ΔZ3 can also be applied to trench structures in other semiconductor devices. In this example, it is preferable that the exemplary depth difference ΔZ3 satisfies the following range. That is, 0.1 μm≦ΔZ3≦1 μm.

[0181] The seam 310 (see Figure 28(C)) that occurred in the trench is removed by forming the second inner surface (curved surface 2AA, curved surface 2BB) (see Figure 28(C)) and etching to obtain the depth difference ΔZ3 (see Figure 28(D)).

[0182] The first material region 11 provided in the trench 200 is in contact with the insulating film 2 covering the trench 200. In this example, the first material region 11 includes polysilicon doped with an impurity. When the first material region 11 has a high impurity concentration (e.g., boron), the first material region 11 is easy to etch. The conductivity type of the first material region 11 can be either p-type or n-type. From this perspective, the first impurity concentration C1 of the first material region 11 can be set to the same concentration range as that in the above-mentioned first semiconductor device.

[0183] The direction perpendicular to the thickness direction of the semiconductor substrate 1 is taken as the horizontal direction, and the maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction in the trench 200 satisfies the following range: 0.1 μm≦ΔW(maximum value)≦1 μm. In order to obtain the effect of suppressing the occurrence of seams, the thick insulating film 2 may have a thickness of 0.3 μm≦ΔW(maximum value) or more, 0.5 μm≦ΔW(maximum value), or 0.7 μm≦ΔW(maximum value).

[0184] The depth at which the maximum thickness ΔW is obtained is the maximum width W of the trench. DTB (See Figure 26) is the position where this can be obtained.

[0185] The first STI structure 21 includes a first recess DP1 formed on the surface of the semiconductor substrate 1 (epitaxial crystal region 1B) and a first insulating region 13 filled in the first recess DP1. OUT The second STI structure 22 includes a second recess DP2 formed in the surface of the semiconductor substrate 1 and a second insulating region 13 filled in the second recess DP2. IN The material of the protective film 14 is the first insulating region 13. OUT and the second insulating region 13 IN If the protective film 14 and the second STI structure 22 are made of the same material, they are integrated. The protective film 14 covers the first material region 11 located on the upper part of the DTI structure 20. The protective film 14 covers the first STI structure 21 and the second STI structure 22.

[0186] The position of the upper main surface of the first material region 11 located at the top of the DTI structure 20 is defined as the reference position Z0. The position of the bottom surface of the first recess DP1 is defined as the first bottom position ZS. The distance from the reference position Z0 to the first bottom position ZS is defined as the depth ΔZ of the first recess DP1 or the second recess DP2. The STI structure has the function of suppressing leakage current between adjacent elements and ensuring a withstand voltage. From the viewpoint of such function, it is preferable that the recess depth ΔZ of the first recess DP1 and the second recess DP2 as viewed from the reference position Z0 has a depth of a certain value or more. The depth of the first recess DP1 (recess depth ΔZ) and the depth of the second recess DP2 (recess depth ΔZ) can be set to the same range as that described in the first semiconductor device.

[0187] The first material region 11 has a width that increases in the depth direction between the reference position Z0 and the third reference position BD3. The third reference position BD3 is defined by the upper end positions of the arc-shaped curved surfaces 2AA and 2BB, which have a width that decreases in the depth direction.

[0188] FIG. 26 is an enlarged view of the fourth region S4 shown in FIG.

[0189] A first STI structure 21 is disposed on the outside of the DTI structure 20, and a second STI structure 22 is disposed on the inside. Each STI structure is formed by embedding an insulator (insulating region) in a recess. The maximum width W DTB The position of the outer end of the first trench 201 that provides this is defined as a first position (X1), and the position of the inner end is defined as a second position (X6).

[0190] The horizontal thickness of the insulating film 2 is ΔW, and the maximum width W DTB is 1μm≦(W DTB It is preferable that the maximum width W DTB 1μm≦W DTB In this example, the thickness ΔW may be set to ≦10 μm. DTB is the thickness at the depth position that gives

[0191] The first recess DP1 extends outward from the first position (X1) (see FIG. 30(A)). The second recess DP2 extends inward from the second position (X6) (see FIG. 30(A)). Within the first recess DP1, a first insulating region 13 OUT The first insulating region 13 is located OUT As a result, the leakage current can be sufficiently suppressed. IN The second insulating region 13 is located IN This makes it possible to sufficiently suppress the leakage current.

[0192] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The position in the depth direction of the second bottom surface 142 (the bottom surface of the second recess DP2) is the first bottom surface position ZS. The maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction in the above-mentioned trench 200 (first trench 201) is, for example, the value at the first bottom surface position ZS.

[0193] The XZ cross section (a cross section including the width direction and depth direction of the first trench 201) and the intersection lines (first outer inner surface 201A, first inner inner surface 201B) formed by the intersection of the first trench 201 are each line segments and extend linearly. Since they extend linearly, there is an advantage that the reproducibility of shape control is high.

[0194] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0195] 27 to 30 are diagrams for explaining the fourth method for manufacturing a semiconductor device, in which the steps described below are carried out in order.

[0196] The steps in FIG. 27(A) to FIG. 27(D) are the same as the steps in FIG. 20(A) to FIG. 20(D).

[0197] As shown in FIG. 27(E), a first insulating material 317 is filled into the deep bottom recess 307 (trench 200). Silicon dioxide can be used as the first insulating material 317. The first insulating material 317 can be formed by a CVD method. An example of a CVD method for forming silicon dioxide is a formation method using TEOS (Si(OC2H5)4). The first insulating material 317 is formed not only inside the trench 200 but also on the top of the third insulating film 303 and is integrated therewith. Inside the trench 200, a space (seam 310) where no material is filled is formed inside the first insulating material 317.

[0198] As shown in FIG. 27(F), the exposed surface of the third insulating film 303 (the upper region of the first insulating material 317) is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the second insulating film 302.

[0199] 27(G), a mask conductive material 318 is formed on the exposed surface of the substrate including the surface of the second insulating film 302. The mask conductive material 318 in this example is undoped polysilicon, and can be formed by a CVD method using silane (SiH4) or the like.

[0200] 27(H), a third resist material 319 is formed on the mask conductive material 318. In the third resist material 319, a pattern having a second opening 320 above the trench 200 is formed.

[0201] 28(A), the mask conductive material 318 is etched through the second opening 320 of the third resist material 319. Anisotropic dry etching for silicon can be used for this etching. As a result, the second opening 320 is also formed in the mask conductive material 318.

[0202] 28(B), the third resist material 319 is removed. When the third resist material 319 is made of a resin, it can be removed using an organic solvent.

[0203] 28(C), the surface region of the first insulating material 317 is etched through the openings in the mask conductive material 318 to form shallow recesses 321. This etching can be isotropic etching, and in this example, wet etching using hydrofluoric acid is used. The bottom surface of the shallow recesses 321 is continuous with the seam 310, and the upper part of the seam 310 is opened.

[0204] As shown in Fig. 28(D), the bottom of the shallow recess 321 is further etched to form a second deep recess 322. The bottom of the second deep recess 322 is deeper than the bottom of the first insulating material 317, and the bottom of the first insulating material 317 is removed. Anisotropic dry etching using RIE can be used for this etching. A fluorine-based gas such as fluorocarbon can also be used as the etching gas.

[0205] 28(E), the mask conductive material 318 is removed. As a removal method, etching for silicon can be used. For example, an etching method using a gas containing a fluorine-based gas can be used.

[0206] As shown in Fig. 28(F), a third conductive material 323 is formed so as to fill the trench 200. The third conductive material 323 is also formed on the second insulating film 302. The third conductive material 323 is polysilicon doped with impurities, and a CVD method can be used as a method for forming the third conductive material 323. An example of a CVD method capable of forming polysilicon is a formation method using silane (SiH4).

[0207] As shown in FIG. 29(A), the exposed surface of the third conductive material 323 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the second insulating film 302.

[0208] 29(B), the second insulating film 302 is removed. The second insulating film 302 made of silicon nitride can be removed by wet etching. Examples of the etching liquid include phosphoric acid (H3PO4).

[0209] 29(C), the first insulating film 301 is removed. The first insulating film 301 made of silicon dioxide can be removed by wet etching. An example of the etching liquid is hydrofluoric acid (HF).

[0210] 29(D), a fourth insulating film 312 is formed on the exposed surface of the semiconductor substrate 1. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the fourth insulating film 312.

[0211] 29(E), a fifth insulating film 313 is formed on the fourth insulating film 312. The fifth insulating film 313 is made of silicon nitride, and a low-pressure CVD method for forming silicon nitride can be used as a forming method.

[0212] 29(F), a second resist material 314 is formed on the fifth insulating film 313. The second resist material 314 is patterned so as to open a region where a recess for an STI structure is to be formed.

[0213] 29(G), the fifth insulating film 313 and the fourth insulating film 312 present in the openings of the mask made of the second resist material 314 are sequentially etched to form a hard mask including the fifth insulating film 313. For this etching, dry etching for insulating films can be used.

[0214] 29(H), the second resist material 314 is removed. If the second resist material 314 is made of a resin, it can be removed using an organic solvent.

[0215] 30(A), the semiconductor substrate 1 is etched through the openings in the hard mask including the fifth insulating film 313 to form the first recess DP1 and the second recess DP2. As the etching method, a wet etching method or a dry etching method for silicon can be used. In this etching process, the top of the insulating film 2 can be positioned higher than the bottom surfaces of the first recess DP1 and the second recess DP2.

[0216] 30(B), a sixth insulating film 315 is formed on the exposed surfaces of the first recess DP1 and the second recess DP2. As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the sixth insulating film 315.

[0217] 30(C), a seventh insulating film 316 is formed so as to fill the first recess DP1 and the second recess DP2. As a forming method, a CVD method for forming silicon dioxide can be used, and a forming method using TEOS is exemplified, and silicon dioxide can be formed as the seventh insulating film 316. The seventh insulating film 316 is also formed on the fifth insulating film 313.

[0218] As shown in FIG. 30(D), the exposed surface of the seventh insulating film 316 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the fifth insulating film 313.

[0219] As shown in FIG. 30(E), the fifth insulating film 313 is removed. Wet etching can be used as a method for removing the fifth insulating film 313 made of silicon nitride. Phosphoric acid (H3PO4) is an example of an etching solution. Finally, a protective film is formed to cover the substrate surface, completing the structure having the protective film 14 shown in FIG. 25. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0220] FIG. 31 is a vertical cross-sectional view of a fourth semiconductor device including a trench structure without an STI structure.

[0221] The semiconductor device of this example is different from the semiconductor device shown in FIG. 25 in that it does not have an STI structure, but the other configurations are the same. The upper part of the insulating film 2 is continuous with the protective film 14. In the XZ cross section, the first trench 201 extending linearly from the bottom side is continuous with the lower surface of the protective film 14. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is the first bottom surface 141, and the bottom surface of the protective film 14 located inside the trench is the second bottom surface 142, and the bottom surface position is ZT. The third reference position BD3 is defined by the upper end position of the insulating film 2 part of the arc-shaped curved surface 2AA and the curved surface 2BB, which narrow in width in the depth direction. In this example, the bottom surface position ZT and the third reference position BD3 are the same in the depth direction, but can be different. This structure can be manufactured by forming the protective film 14 on the exposed surface of the substrate after the process of FIG. 29(D).

[0222] Next, a fifth semiconductor device will be described.

[0223] FIG. 32 is a vertical cross-sectional view (XZ cross-sectional view) of a fifth semiconductor device including a trench structure TR.

[0224] The semiconductor device 100 includes a trench structure TR. The trench structure TR of this example includes a DTI structure 20, a first STI structure 21, and a second STI structure 22. The DTI structure 20 is located between the first STI structure 21 and the second STI structure 22. The trench structure TR is annular in plan view, but the first STI structure 21 is located outside the second STI structure 22 in plan view.

[0225] The DTI structure 20 includes a trench 200 as a groove formed in the semiconductor substrate 1. In a plan view, the trench 200 surrounds the device 50 (see FIG. 3) provided in a region shallower than the first position Z1. The trench 200 (first trench 201) has a first outer inner surface 201A and a first inner inner surface 201B. The inner surface of the first trench 201 is covered with a first insulating film 2S. The inclination angle of the inner surface of the first trench 201 can satisfy the same angle range as that of the first trench 201 in the first semiconductor device described above. The width of the first trench 201 narrows along the depth direction (positive direction of the Z axis). In other words, the first trench 201 has a tapered shape.

[0226] The DTI structure 20 includes a first insulating film 2S. The first insulating film 2S is an insulating film corresponding to the insulating film 2 described above, and is in contact with the inner surface of the trench 200 (first trench 201). The first insulating film 2S includes an insulating film 2SA and an insulating film 2SB. The insulating film 2SA is in contact with a first outer inner surface 201A of the trench. The insulating film 2SB is in contact with a first inner inner surface 201B of the trench.

[0227] The first conductive film 11S (outer conductive region) is formed inside the first insulating film 2S. The first conductive film 11S includes a conductive film 11SA and a conductive film 11SB. The conductive film 11SA is in contact with the insulating film 2SA. The conductive film 11SB is in contact with the insulating film 2SB. The second insulating film 2T is formed inside the first conductive film 11S. The second insulating film 2T includes an insulating film 2TA and an insulating film 2TB. The insulating film 2TA is in contact with the conductive film 11SA. The insulating film 2TB is in contact with the conductive film 11SB. The first material region 11 is formed inside the second insulating film 2T. The first material region 11 is provided between the insulating film 2TA and the insulating film 2TB.

[0228] In this example, the first conductive film 11S and the first material region 11 include polysilicon doped with impurities. When the first conductive film 11S and the first material region 11 have a high impurity concentration (e.g., boron), the first conductive film 11S and the first material region 11 are easily etched. The conductivity type of the first conductive film 11S and the first material region 11 can be either p-type or n-type.

[0229] From this perspective, the first impurity concentration C1 of the first conductive film 11S and the first material region 11 can be set to the same concentration range as in the above-mentioned first semiconductor device.

[0230] The direction perpendicular to the thickness direction of the semiconductor substrate 1 is taken as the horizontal direction, and the maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction within the trench 200 satisfies the following range: 0.1 μm≦ΔW (maximum value)≦1 μm.

[0231] In this example, the depth at which the maximum value of the thickness ΔW is obtained is the maximum width W of the first trench 201. DTB (See Figure 33)

[0232] First trench 201 penetrates the interface (second position Z2) between underlying substrate 1A and epitaxial crystal region 1B.

[0233] The first STI structure 21 includes a first recess DP1 formed on the surface of the semiconductor substrate 1 (epitaxial crystal region 1B) and a first insulating region 13 filled in the first recess DP1. OUT The second STI structure 22 includes a second recess DP2 formed in the surface of the semiconductor substrate 1 and a second insulating region 13 filled in the second recess DP2. IN The material of the protective film 14 is the first insulating region 13. OUT and the second insulating region 13 IN If the protective film 14 and the second STI structure 22 are made of the same material, they are integrated. The protective film 14 covers the first material region 11 located on the upper part of the DTI structure 20. The protective film 14 covers the first STI structure 21 and the second STI structure 22.

[0234] The position of the upper main surface of the first material region 11 located at the top of the DTI structure 20 is defined as the reference position Z0. The position of the bottom surface of the first recess DP1 is defined as the first bottom position ZS. The distance from the reference position Z0 to the first bottom position ZS is defined as the depth ΔZ of the first recess DP1 or the second recess DP2. The STI structure has the function of suppressing leakage current between adjacent elements and ensuring a withstand voltage. From the viewpoint of such function, it is preferable that the recess depth ΔZ of the first recess DP1 and the second recess DP2 as viewed from the reference position Z0 has a depth of a certain value or more. The depth of the first recess DP1 (recess depth ΔZ) and the depth of the second recess DP2 (recess depth ΔZ) can be set to the same range as that described in the first semiconductor device.

[0235] The conductive region (first conductive film 11S, first material region 11) filled inside trench 200 extends to a position deeper than the deepest position (third position Z3) of insulating film 2. This is because insulating film 2 is etched until the bottom is removed in the step of FIG. 34(F). The deepest position of this conductive region is deeper than the deepest position (third position Z3) of insulating film 2 by a depth difference ΔZ3. An exemplary depth difference ΔZ3 can satisfy the range defined in the fourth semiconductor device. When insulating film 2 at the bottom of the trench is removed, depth difference ΔZ3 can also be set to 0.

[0236] FIG. 33 is an enlarged view of the fifth region S5 shown in FIG.

[0237] A first STI structure 21 is disposed on the outside of the DTI structure 20, and a second STI structure 22 is disposed on the inside. Each STI structure is formed by embedding an insulator (insulating region) in a recess. The maximum width W DTB The position of the outer end of trench 200 (first trench 201) that provides this is defined as a first position (X1), and the position of the inner end is defined as a second position (X6).

[0238] The horizontal thickness of the insulating film 2 is ΔW, and the maximum width W DTB is 1μm≦(W DTB It is preferable that the maximum width WDTB 1μm≦W DTB The thickness ΔW may be set to ≦10 μm. DTB can be used to find the horizontal thickness at the depth position that gives

[0239] The first recess DP1 extends outward from the first position (X1). The second recess DP2 extends inward from the second position (X6). A first insulating region 13 is formed in the first recess DP1. OUT The first insulating region 13 is located OUT As a result, the leakage current can be sufficiently suppressed. IN The second insulating region 13 is located IN This makes it possible to sufficiently suppress the leakage current.

[0240] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The position in the depth direction of the second bottom surface 142 (the bottom surface of the second recess DP2) of the first insulating region 13 is a first bottom surface position ZS. Between the first bottom surface position ZS and the first outer inner surface 201A of the trench is a first concave surface DA that is concave in the upward direction. Between the first bottom surface position ZS and the first inner inner surface 201B of the trench is a second concave surface DB that is concave in the upward direction. The position located at the deepest part of the first concave surface DA and the second concave surface DB is defined as an upper end position ZD. OUT The first bottom surface 141 and the second insulating region 13 IN The distance between the second bottom surface 142 and the maximum width W of the trench 200 DTB Greater than.

[0241] Maximum width W of trench 200 (first trench 201) DTBThe top end position ZD that provides this is set shallower than the first bottom position ZS, for example. The horizontal thicknesses of the insulating films 2TA and 2TB at the top end position ZD in the depth direction are each defined as a second thickness ΔW2. In this example, ΔW2 is smaller than ΔW (ΔW2<ΔW). The second thickness ΔW2 satisfies the following range, for example. That is, 0.1 μm≦ΔW2≦1 μm. When the second thickness ΔW2 exceeds the upper limit value and falls below the lower limit value, the seam suppression effect tends to be reduced.

[0242] The XZ cross section (a cross section including the width direction and depth direction of the first trench 201) and the intersection lines (first outer inner surface 201A, first inner inner surface 201B) formed by the intersection of the first trench 201 are each line segments and extend linearly. Since they extend linearly, there is an advantage that the reproducibility of shape control is high.

[0243] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0244] 34 to 37 are diagrams for explaining the fifth method for manufacturing a semiconductor device, in which the steps described below are carried out in order.

[0245] The steps in FIG. 34(A) to FIG. 34(D) are the same as those in FIG. 20(A) to FIG. 20(D).

[0246] As shown in Fig. 34(E), an insulating film 2 (first insulating film 2S in Fig. 32) is formed on the surface of the exposed deep bottom recess 307 (trench). As a forming method, in addition to thermal oxidation of silicon, a low pressure CVD method using TEOS or the like is used. Silicon dioxide can be formed as the insulating film 2.

[0247] As shown in FIG. 34(F), a portion of the insulating film 2 located on the bottom surface of the deep recess 307 (trench) is removed to expose the semiconductor substrate 1 located on the bottom surface of the deep recess 307. Anisotropic dry etching for insulating films can be used as a removal method. By this etching, the shape of the trench opening end surface of the third insulating film 303 located above the surface of the semiconductor substrate 1 in the XZ cross section becomes a gentle arc. The surfaces of the first upper position 2AT and the second upper position 2BT of the third insulating film 303 are deformed by the anisotropic dry etching so as to gently drop inside the trench.

[0248] As shown in Fig. 34(G), a fourth conductive material 324 (conductive film) (first conductive film 11S in Fig. 32) is formed so as to cover the surface of the insulating film 2 inside the trench and the surface of the third insulating film 303. The fourth conductive material 324 is polysilicon doped with impurities, and a CVD method can be used as a method for forming the fourth conductive material 324. As a CVD method capable of forming polysilicon, a formation method using silane (SiH4) is exemplified.

[0249] As shown in Fig. 34(H), an eighth insulating film 325 (the second insulating film 2T in Fig. 32) is formed so as to cover the fourth conductive material 324 inside and outside the trench. The eighth insulating film 325 can be formed by thermal oxidation of silicon.

[0250] 35(A), the eighth insulating film 325 located on the upper surface of the third insulating film 303 is etched. As the etching method, anisotropic dry etching of the insulating film can be used. The eighth insulating film 325 inside the trench is left.

[0251] 35(B), a fifth conductive material 326 (first material region 11 in FIG. 32) is formed to fill the inside of the trench 200 and cover the surface of the fourth conductive material 324. The fifth conductive material 326 is undoped polysilicon, and can be formed by using a CVD method using silane (SiH4) or the like.

[0252] As shown in FIG. 35(C), the exposed surface of the fifth conductive material 326 and the upper surface portion of the fourth conductive material 324 are subjected to chemical mechanical polishing (CMP) to expose the upper surface of the third insulating film 303.

[0253] 35(D), the exposed surface of the third insulating film 303 constituting the hard mask is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the second insulating film 302. By this process, the fifth conductive material 326 existing in the opening of the third insulating film 303 is also removed.

[0254] As shown in Fig. 35(E), the second insulating film 302 is removed. The second insulating film 302 made of silicon nitride can be removed by wet etching. Examples of the etching liquid include phosphoric acid (H3PO4).

[0255] 35(F), the first insulating film 301 is removed. The first insulating film 301 made of silicon dioxide can be removed by wet etching. An example of the etching liquid is hydrofluoric acid (HF).

[0256] 36(A), a fourth insulating film 312 is formed on the exposed surface of the semiconductor substrate 1. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the fourth insulating film 312.

[0257] 36(B), a fifth insulating film 313 is formed on the fourth insulating film 312. The fifth insulating film 313 is made of silicon nitride, and a low-pressure CVD method for forming silicon nitride can be used as a forming method.

[0258] 36(C), a second resist material 314 is formed on the fifth insulating film 313. The second resist material 314 is patterned so as to open a region where a recess for an STI structure is to be formed.

[0259] 36(D), the fifth insulating film 313 and the fourth insulating film 312 present in the openings of the mask made of the second resist material 314 are sequentially etched to form a hard mask including the fifth insulating film 313. For this etching, dry etching for insulating films can be used.

[0260] As shown in Fig. 36(E), the second resist material 314 is removed. If the second resist material 314 is made of a resin, it can be removed using an organic solvent.

[0261] As shown in Fig. 36(F), the semiconductor substrate 1 is etched through the openings in the hard mask including the fifth insulating film 313 to form the first recess DP1 and the second recess DP2. As the etching method, a wet etching method or a dry etching method for silicon can be used. In this etching step, the top of the insulating film 2 can be positioned higher than the bottom surfaces of the first recess DP1 and the second recess DP2.

[0262] 36(G), a sixth insulating film 315 is formed on the exposed surfaces of the first recess DP1 and the second recess DP2. As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the sixth insulating film 315.

[0263] 36(H), a seventh insulating film 316 is formed so as to fill the first recess DP1 and the second recess DP2. As a forming method, a CVD method for forming silicon dioxide can be used, and a forming method using TEOS is exemplified, and silicon dioxide can be formed as the seventh insulating film 316. The seventh insulating film 316 is also formed on the fifth insulating film 313.

[0264] As shown in FIG. 37(A), the exposed surface of the seventh insulating film 316 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the fifth insulating film 313.

[0265] As shown in FIG. 37(B), the fifth insulating film 313 is removed. Wet etching can be used as a method for removing the fifth insulating film 313 made of silicon nitride. Phosphoric acid (H3PO4) is an example of an etching solution. Finally, a protective film is formed to cover the substrate surface, completing the structure having the protective film 14 shown in FIG. 32. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0266] FIG. 38 is a vertical cross-sectional view of a fifth semiconductor device including a trench structure without an STI structure.

[0267] The semiconductor device of this example is different from the semiconductor device shown in FIG. 32 in that it does not have an STI structure, but the other configurations are the same. The upper part of the first insulating film 2S is continuous with the protective film 14. In the XZ cross section, the first trench 201 extending linearly from the bottom side is continuous with the lower surface of the protective film 14. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is the first bottom surface 141, and the bottom surface of the protective film 14 located inside the trench is the second bottom surface 142, and the bottom surface position is ZT. The top surface (reference position Z0) located at the top of the first material region 11 is set at a position higher than the bottom surface position ZT. This structure can be manufactured by forming the protective film 14 on the exposed surface of the substrate after the process of FIG. 36(A).

[0268] Next, the sixth semiconductor device will be described.

[0269] FIG. 39 is a vertical sectional view (XZ sectional view) of a sixth semiconductor device including a trench structure TR.

[0270] The semiconductor device 100 includes a trench structure TR. The trench structure TR of this example includes a DTI structure 20, a first STI structure 21, and a second STI structure 22. The DTI structure 20 is located between the first STI structure 21 and the second STI structure 22. The trench structure TR is annular in plan view, but the first STI structure 21 is located outside the second STI structure 22 in plan view.

[0271] The DTI structure 20 includes a trench 200 as a groove formed in a semiconductor substrate 1. In a plan view, the trench 200 surrounds a device 50 (see FIG. 3) provided in a region shallower than a first position Z1. The inner surface of the trench 200 is covered with an insulating film 2. The trench 200 includes a first trench 201 similar to the first and second semiconductor devices, and the inclination angle of the inner surface of the first trench 201 can satisfy the above-mentioned range. The width of the first trench 201 narrows along the depth direction (positive direction of the Z axis). In other words, the first trench 201 has a tapered shape.

[0272] A first material region 11 (conductive region) is provided within the trench 200. The first material region 11 is in contact with the insulating film 2 covering the trench 200. A buried insulating region 2U is provided in an upper region of the first material region 11. The buried insulating region 2U is provided at a central position in the width direction of the trench 200, and has a shape extending along the depth direction of the trench 200.

[0273] In this example, the first material region 11 includes polysilicon doped with impurities. If the first material region 11 has a high impurity concentration (e.g., boron), the first material region 11 is easier to etch. The conductivity type of the first material region 11 can be p-type or n-type.

[0274] From this perspective, the first impurity concentration C1 of the first material region 11 can be set to the same concentration range as that in the above-mentioned first semiconductor device.

[0275] The direction perpendicular to the thickness direction of the semiconductor substrate 1 is taken as the horizontal direction, and the maximum value of the thickness ΔW of the insulating film 2 in the horizontal direction in the trench 200 satisfies the following range: 0.1 μm≦ΔW≦1 μm. Note that the depth at which the maximum value of the thickness ΔW is obtained is the maximum width W of the first trench 201 in this example. DTB (See Figure 40)

[0276] The first trench 201 has a first outer inner surface 201A and a first inner inner surface 201B. The insulating film 2 has an outer insulating film 2A and an inner insulating film 2B. The outer insulating film 2A is in contact with the first outer inner surface 201A. The inner insulating film 2B is in contact with the first inner inner surface 201B.

[0277] First trench 201 penetrates the interface (second position Z2) between underlying substrate 1A and epitaxial crystal region 1B.

[0278] The first STI structure 21 includes a first recess DP1 formed on the surface of the semiconductor substrate 1 (epitaxial crystal region 1B) and a first insulating region 13 filled in the first recess DP1. OUT The second STI structure 22 includes a second recess DP2 formed in the surface of the semiconductor substrate 1 and a second insulating region 13 filled in the second recess DP2. IN The material of the protective film 14 is the first insulating region 13. OUT and the second insulating region 13 IN If the protective film 14 and the second STI structure 22 are made of the same material, they are integrated. The protective film 14 covers the first material region 11 located on the upper part of the DTI structure 20. The protective film 14 covers the first STI structure 21 and the second STI structure 22.

[0279] The first material region 11 includes a first conductive region 11A that is a region located deeper than the boundary position BD, and a second conductive region 11B that is a region located shallower than the boundary position BD. The first conductive region 11A narrows in width in the depth direction. The second conductive region 11B widens in width along the depth direction. The boundary position BD is set at a position that horizontally crosses the buried insulating region 2U.

[0280] The position of the upper main surface of the first material region 11 embedded in the top of the DTI structure 20 is defined as the reference position Z0. The position of the bottom surface of the first recess DP1 is defined as the first bottom position ZS. The distance from the reference position Z0 to the first bottom position ZS is defined as the depth ΔZ of the first recess DP1 or the second recess DP2. The STI structure has the function of suppressing leakage current between adjacent elements and ensuring a withstand voltage. From the viewpoint of such function, it is preferable that the recess depth ΔZ of the first recess DP1 and the second recess DP2 as viewed from the reference position Z0 has a depth of a certain value or more. The depth of the first recess DP1 (recess depth ΔZ) and the depth of the second recess DP2 (recess depth ΔZ) can be set to the same range as that described in the first semiconductor device.

[0281] The conductive region (first material region 11) filled inside trench 200 extends to a position deeper than the deepest position (third position Z3) of insulating film 2. This is because insulating film 2 is etched until its bottom is removed in the step of FIG. 41(F). The deepest position of this conductive region is deeper than the deepest position (third position Z3) of insulating film 2 by a depth difference ΔZ3. An exemplary depth difference ΔZ3 can satisfy the range defined in the fourth semiconductor device. When insulating film 2 at the bottom of the trench is removed, depth difference ΔZ3 can also be set to 0.

[0282] FIG. 40 is an enlarged view of the sixth region S6 shown in FIG.

[0283] The maximum dimension (first maximum width X2U) of the buried insulating region 2U in the width direction (X-axis direction) satisfies the following range. If the first maximum width X2U is below the lower limit, the tendency for the insulating material to be filled into the seam during manufacturing decreases, and if it exceeds the upper limit, the surrounding conductive region tends to become smaller. Therefore, it is preferable that the first maximum width X2U satisfies the following range, i.e., 0.1 μm≦X2U≦5 μm.

[0284] The maximum dimension (first maximum thickness Z2U) of the buried insulating region 2U in the depth direction (Z-axis direction) satisfies the following range. The first maximum thickness Z2U can be set during manufacturing so that a suitable first maximum width X2U is obtained. For example, it is preferable that the suitable first maximum thickness Z2U satisfies the following range. That is, 0.1 μm≦Z2U≦20 μm.

[0285] A first STI structure 21 is disposed on the outside of the DTI structure 20, and a second STI structure 22 is disposed on the inside. Each STI structure is formed by embedding an insulator (insulating region) in a recess. The maximum width W DTB The position of the outer end of the trench 200 that provides this is defined as a first position (X1), and the position of the inner end is defined as a second position (X6).

[0286] The thickness of the insulating film 2 is ΔW, and the maximum width W DTB can be set in the same range as in the fifth semiconductor device (FIG. 33).

[0287] The first recess DP1 extends outward from the first position (X1). The second recess DP2 extends inward from the second position (X6). A first insulating region 13 is formed in the first recess DP1. OUT The first insulating region 13 is located OUT As a result, the leakage current can be sufficiently suppressed. IN The second insulating region 13 is located IN This makes it possible to sufficiently suppress the leakage current.

[0288] First insulating region 13 OUT The first bottom surface 141 (the bottom surface of the first recess DP1) and the second insulating region 13 IN The position in the depth direction of the second bottom surface 142 (the bottom surface of the second recess DP2) is the first bottom surface position ZS. The first bottom surface position ZS can be set to a position shallower than the deepest position ZM of the buried insulating region 2U. OUT The first bottom surface 141 and the second insulating region 13 IN The distance between the bottom surface 142 of the trench 200 and the maximum width WDTB Greater than.

[0289] The XZ cross section (a cross section including the width direction and depth direction of the first trench 201) and the intersection lines (first outer inner surface 201A, first inner inner surface 201B) formed by the intersection of the first trench 201 are each line segments and extend linearly. Since they extend linearly, there is an advantage that the reproducibility of shape control is high.

[0290] A method for manufacturing a semiconductor device having the above-mentioned trench structure will now be described.

[0291] 41 to 44 are diagrams for explaining the sixth method for manufacturing a semiconductor device, in which the steps described below are carried out in order.

[0292] The steps in FIG. 41(A) to FIG. 41(F) are the same as the steps in FIG. 34(A) to FIG. 34(F).

[0293] As shown in FIG. 41(G), a first conductive material 309 (conductive film) is formed so as to cover the upper surfaces of the insulating film 2 and the third insulating film 303 inside the trench. The first conductive material 309 is polysilicon doped with impurities, and a CVD method can be used as a method for forming the first conductive material 309. An example of a CVD method capable of forming polysilicon is a formation method using silane (SiH4). The thickness of the first conductive material 309 is set so as to form a seam 310 (space) in the trench 200.

[0294] 41(H), a ninth insulating film 327 is formed on the surface of the first conductive material 309. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the ninth insulating film 327. The ninth insulating film 327 is also filled in the seams.

[0295] 42A, the ninth insulating film 327 on the first conductive material 309 is removed except for the ninth insulating film 327 in the seam. As an exemplary removal method, wet etching using hydrofluoric acid or the like can be used.

[0296] 42(B), a tenth conductive material 328 is formed so as to cover the first conductive material 309. The deepest part of the tenth conductive material 328 contacts the ninth insulating film 327 in the seam. The tenth conductive material 328 is undoped polysilicon, and can be formed by using a CVD method using silane (SiH4) or the like.

[0297] 42C, the exposed surfaces of the tenth conductive material 328 and the first conductive material 309 are chemically mechanically polished (CMP) to expose the upper surface of the third insulating film 303. A portion of the tenth conductive material 328 that is in contact with the ninth insulating film 327 in the seam remains.

[0298] 42(D), the exposed surface of the third insulating film 303 is chemically mechanically polished (CMP) to expose the upper surface of the second insulating film 302. By this process, the tenth conductive material 328 existing in the opening of the third insulating film 303 is also removed, and the top surface of the ninth insulating film 327 is exposed, and the ninth insulating film 327 becomes the above-mentioned buried insulating region 2U (see FIG. 39).

[0299] As shown in Fig. 42(E), the second insulating film 302 is removed. The second insulating film 302 made of silicon nitride can be removed by wet etching. Examples of the etching liquid include phosphoric acid (H3PO4).

[0300] As shown in Fig. 42(F), the first insulating film 301 is removed. The first insulating film 301 made of silicon dioxide can be removed by wet etching. An example of the etching liquid is hydrofluoric acid (HF).

[0301] 43(A), a fourth insulating film 312 is formed on the exposed surface of the semiconductor substrate 1. As a formation method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the fourth insulating film 312.

[0302] 43(B), a fifth insulating film 313 is formed on the fourth insulating film 312. The fifth insulating film 313 is made of silicon nitride, and a low-pressure CVD method for forming silicon nitride can be used as a forming method.

[0303] 43(C), a second resist material 314 is formed on the fifth insulating film 313. The second resist material 314 is patterned so as to open a region where a recess for an STI structure is to be formed.

[0304] 43(D), the fifth insulating film 313 and the fourth insulating film 312 present in the openings of the mask made of the second resist material 314 are sequentially etched to form a hard mask including the fifth insulating film 313. For this etching, dry etching for insulating films can be used.

[0305] As shown in Fig. 43(E), the second resist material 314 is removed. If the second resist material 314 is made of a resin, it can be removed using an organic solvent.

[0306] As shown in Fig. 43(F), the semiconductor substrate 1 is etched through the openings in the hard mask including the fifth insulating film 313 to form the first recess DP1 and the second recess DP2. As the etching method, a wet etching method or a dry etching method for silicon can be used. In this etching step, the top of the insulating film 2 can be positioned higher than the bottom surfaces of the first recess DP1 and the second recess DP2.

[0307] 43(G), a sixth insulating film 315 is formed on the exposed surfaces of the first recess DP1 and the second recess DP2. As a forming method, thermal oxidation of silicon can be used, and silicon dioxide can be formed as the sixth insulating film 315.

[0308] 43(H), a seventh insulating film 316 is formed so as to fill the first recess DP1 and the second recess DP2. As a forming method, a CVD method for forming silicon dioxide can be used, and a forming method using TEOS is exemplified, and silicon dioxide can be formed as the seventh insulating film 316. The seventh insulating film 316 is also formed on the fifth insulating film 313.

[0309] As shown in FIG. 44(A), the exposed surface of the seventh insulating film 316 is subjected to chemical mechanical polishing (CMP) to expose the upper surface of the fifth insulating film 313.

[0310] As shown in FIG. 44(B), the fifth insulating film 313 is removed. Wet etching can be used as a method for removing the fifth insulating film 313 made of silicon nitride. Phosphoric acid (H3PO4) is an example of an etching solution. Finally, a protective film is formed to cover the substrate surface, completing the structure having the protective film 14 shown in FIG. 39. The protective film 14 can be formed using a CVD method for forming silicon dioxide.

[0311] FIG. 45 is a vertical cross-sectional view of a sixth semiconductor device including a trench structure without an STI structure.

[0312] The semiconductor device of this example is different from the semiconductor device shown in FIG. 39 in that it does not have an STI structure, but the other configurations are the same. The upper part of the insulating film 2 is continuous with the protective film 14. In the XZ cross section, the first trench 201 extending linearly from the bottom side is continuous with the lower surface of the protective film 14. The bottom surface of the protective film 14 located outside the trench having a ring-shaped planar shape is the first bottom surface 141, and the bottom surface of the protective film 14 located inside the trench is the second bottom surface 142, and the bottom surface position is ZT. The first conductive region 11A is a part where the inner surface of the insulating film 2 extends linearly, the depth position where the inner surface curves is the boundary position BD, and the conductive material located shallower than the boundary position BD is the second conductive region 11B. The width of the second conductive region 11B narrows in the depth direction, but the deeper it becomes, the smaller the reduction rate of the width per unit depth becomes. The boundary position BD can be set at a position deeper than the bottom position ZT. The depth that gives the maximum value of the horizontal thickness ΔW of the insulating film 2 can be set, for example, at the boundary position BD. This structure can be manufactured by forming a protective film 14 on the exposed surface of the substrate after the step of FIG.

[0313] FIG. 46 is an enlarged view (FIGS. 46(A), (B), and (C)) of the first end region R1 and the second end region R2 shown in FIG.

[0314] As shown in Figure 46 (A), as an example of the structure of the first end region R1, the conductivity type of the first material region 11 can be p-type, and p-type impurities can be added to a position deeper than the deepest part of the first material region 11 to form a high-concentration impurity region 1P.

[0315] 46(B), as an example of the structure of the first end region R1, the conductivity type of the first material region 11 is p-type, but the impurity concentration of the outer semiconductor region 11P1 sandwiching the inner semiconductor region 11P2 can be made higher than the impurity concentration of the inner semiconductor region 11P2. A high-concentration impurity region 1P can be continuous with the deepest part of the outer semiconductor region 11P1.

[0316] 46(C), as an example of the structure of the second end region R2, the conductivity type of the top-side semiconductor region 11N (first material region 11) is n-type, and the conductivity type of the bottom-side semiconductor region 11P3 is p-type, forming a PN junction between them to form a diode. A reverse bias may be applied to the diode.

[0317] An example of the impurity concentration is as follows: 1P is 1 x 10 19 cm -3 ≦C 1P ≦1×10 22 cm ―3 The impurity concentration C of the outer semiconductor region 11P1 11P1 is 1 x 10 16 cm -3 ≦C 11P1 ≦1×10 19 cm ―3 The impurity concentration C of the inner semiconductor region 11P2 11P2 is 1 x 10 16 cm -3 ≦C 11P2 ≦1×10 22 cm ―3 The impurity concentration C of the bottom semiconductor region 11P3 11P3 is 1 x 10 17 cm -3 ≦C 11P3 ≦1×10 20 cm ―3 The impurity concentration C of the front-side semiconductor region 11N 11N is 1 x 10 12 cm -3 ≦C 11N ≦1×10 16 cm ―3 It is.

[0318] Each semiconductor region may contain impurities of a second conductivity type opposite to the first conductivity type in that semiconductor region.

[0319] FIG. 47 is an enlarged view of the interface region R3 shown in FIG.

[0320] The epitaxial crystal region 1B formed on the base substrate 1A includes a p-type first epitaxial layer 1B1 and an n-type second epitaxial layer 1B2. The n-type second epitaxial layer 1B2 is a first semiconductor layer 1B 21 , second semiconductor layer 1B 22 , third semiconductor layer 1B 23 The second semiconductor layer 1B is formed by stacking the above in order. 22 The impurity concentration of the first semiconductor layer 1B 21 and the third semiconductor layer 1B 23 The first semiconductor layer 1B 21 Impurity concentration C 1B21 , second semiconductor layer 1B 22 Impurity concentration C 1B22 , third semiconductor layer 1B 23 Impurity concentration C 1B23 Exemplary preferred ranges are as follows: 1×10 14 cm -3 ≦C 1B21 ≦1×10 18 cm ―3 , 1×10 16 cm -3 ≦C 1B22 ≦1×10 21 cm ―3 , 1×10 14 cm -3 ≦C 1B23 ≦1×10 17 cm ―3 It is.

[0321] First semiconductor layer 1B 21 The thickness of the second semiconductor layer 1B can be set to 0.1 μm or more and 5 μm or less, and preferably, 0.5 μm or more and 2.5 μm or less. 22 The thickness of the third semiconductor layer 1B can be set to 0.1 μm or more and 5 μm or less, and preferably, 0.5 μm or more and 2.5 μm or less. 23 The thickness can be set to 5 μm or more and 30 μm or less.

[0322] As described above, various embodiments of the present disclosure can be defined as follows.

[0323] Regarding the above-mentioned first semiconductor device (FIGS. 1 to 10), (A1) to (A13) are defined.

[0324] [A1] A semiconductor device comprising: a semiconductor substrate 1 including a trench 200 surrounding a device 50; an insulating film 2 covering the inner surface of the trench 200; and a conductive region (first material region 11, second material region 12) provided within the trench 200, wherein the trench 200 comprises a first trench 201 located on the bottom side of the trench 200, and a second trench 202 located on the surface side of the trench 200, continuous with the first trench 201, and narrowing in width along the depth direction, wherein a reduction in width of the second trench 202 per unit depth is greater than a reduction in width of the first trench 201 per unit depth.

[0325] [A2] The semiconductor device described in A1, wherein the semiconductor substrate 1 comprises a base substrate 1A and an epitaxial crystal region 1B formed on the base substrate 1A, and the first trench 201 penetrates an interface (second position Z2) between the base substrate 1A and the epitaxial crystal region 1B.

[0326] [A3] The semiconductor device according to A1 or A2, wherein the conductive region comprises a first material region 11 embedded in the first trench 201 and the second trench 202, and a second material region 12 embedded inside the first material region 11 and having etching characteristics different from those of the first material region 11.

[0327] [A4] The semiconductor device according to A3, wherein the first material region 11 includes polysilicon doped with an impurity, and the second material region 12 includes polysilicon having an impurity concentration lower than an impurity concentration of the first material region 11.

[0328] [A5] The first impurity concentration C1 of the first material region 11 and the second impurity concentration C2 of the second material region 12 are in the following relationship: 1×10 18 cm -3 ≦C1≦1×10 22 cm -3、 1×10 15 cm -3 ≦C2≦1×10 18 cm -3 The semiconductor device according to A3 or A4,

[0329] [A6] The semiconductor device according to any one of A3 to A5, wherein the second material region 12 includes a region 12A having a width that narrows toward the bottom surface of the trench 200.

[0330] [A7] The maximum width W of the second trench 202 DTB Regarding the outer end and the inner end of the second trench 202 that provide the above, the position of the outer end is a first position (X1), the position of the inner end is a second position (X6), and above the first position (X1), a first insulating region 13 in a first recess DP1 is OUT is located above the second position (X6), and a second insulating region 13 in a second recess DP2 is located above the second position (X6). IN The semiconductor device according to any one of A1 to A6, wherein:

[0331] [A8] The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B formed on the underlying substrate 1A. The maximum width W DTB Regarding the outer end and the inner end of the second trench 202 that provide the above, the position of the outer end is a first position (X1), the position of the inner end is a second position (X6), and the trench 200 includes a first recess DP1 and a second recess DP2 adjacent to each other in the width direction of the trench 200, and above the first position (X1), a first insulating region 13 in the first recess DP1 is provided. OUT The semiconductor device according to any one of A1 to A6, wherein a depth of the first recess DP1 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0332] [A9] Above the second position (X6), a second insulating region 13 in a second recess DP2 IN and a depth of the second recess DP2 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0333] [A10] The semiconductor device according to any one of A7 to A9, wherein the first recess DP1 has a depth of 100 nm or more.

[0334] [A11] The semiconductor device according to any one of A7 to A9, wherein the second recess DP2 has a depth of 100 nm or more.

[0335] [A12] The first insulating region 13 OUT the bottom surface 141 of the second insulating region 13 IN The distance between the bottom surface 142 and the DTC ) is the maximum width W of the second trench 202 DTB The semiconductor device according to A7 or A9,

[0336] [A13] The semiconductor device according to any one of A1 to A12, wherein a cross section (XZ cross section) including the width direction and depth direction of the second trench 202 and an inner surface of the second trench 202 intersect with each other to form a plurality of intersection lines (second outer inner surface 202A, second inner inner surface 202B), each of which extends linearly.

[0337] Regarding the above-mentioned second semiconductor device (FIGS. 1 to 3, 11 to 17), in addition to the above-mentioned A1 to A12, B14 is defined.

[0338] [B14] The semiconductor device according to any one of A1 to A12, wherein a cross section (XZ cross section) including the width direction and depth direction of the second trench 202 and a plurality of intersection lines (second outer inner surface 202A, second inner inner surface 202B) formed by the intersection of the second trench 202 and an inner surface of the second trench 202 each have an arc shape.

[0339] With respect to the above-mentioned first and second semiconductor devices, B15 is defined.

[0340] [B15] A process of etching the semiconductor substrate through an opening in a mask (a hard mask including a third insulating film 303) provided on the semiconductor substrate 1 to form a space immediately below the opening and immediately below a region outside both ends of the opening in the width direction (FIG. 6(D) and FIG. 13(D)); a process of dry etching the semiconductor substrate 1 through the opening to form a trench continuous with the space (FIG. 6(E) and FIG. 13(E)); a process of forming an insulating film 2 on the space and on the exposed surface of the trench (FIG. 6(F) and FIG. 13(F)); and a process of supplying a first conductive material 309 into the trench through the opening in the mask to form a first conductive region (11A) and to dry-etch the space. a step of supplying a first conductive material 309 into the second conductive region (11B) through the opening in the mask to form a second conductive region (11B) having a seam 310, and forming a first material region (11) including the first conductive region (11A) and the second conductive region (11B) (FIGS. 6(H) and 13(H)); a step of etching the second conductive region (11B) through the opening in the mask until reaching the seam 310 in the second conductive region (11B) (FIGS. 7(B) and 14(B)); and a step of supplying a second conductive material (upper conductive material 311) into the seam 310 through the opening in the mask to form a second material region 12 in the seam 310 (FIGS. 7(C) and 14(C)).

[0341] Regarding the above-mentioned third semiconductor device (FIGS. 1 to 3, 18 to 24), C1 to C12 are defined.

[0342] [C1] A semiconductor device comprising: a semiconductor substrate 1 including a trench 200 surrounding a device 50; an insulating film 2 covering the inner surface of the trench 200; and conductive regions (first material region 11, second material region 12) provided within the trench 200, wherein a direction perpendicular to a thickness direction of the semiconductor substrate 1 is defined as a horizontal direction, and a maximum value of a thickness ΔW of the insulating film 2 within the trench 200 along the horizontal direction is 0.1 μm or more and 1 μm or less.

[0343] [C2] The semiconductor device described in C1, wherein the semiconductor substrate 1 comprises a base substrate 1A and an epitaxial crystal region 1B formed on the base substrate 1A, and the trench 200 penetrates an interface (second position Z2) between the base substrate 1A and the epitaxial crystal region 1B.

[0344] [C3] A semiconductor device as described in C1 or C2, wherein the conductive region comprises a first material region 11 embedded in the trench 200 and a second material region 12 provided on top of the first material region 11 and having etching characteristics different from those of the first material region 11.

[0345] [C4] The semiconductor device according to C3, wherein the first material region 11 includes polysilicon doped with an impurity, and the second material region 12 includes polysilicon having an impurity concentration lower than the impurity concentration of the first material region 11.

[0346] [C5] The first impurity concentration C1 of the first material region 11 and the second impurity concentration C2 of the second material region 12 are in the following relationship: 1×10 18 cm -3 ≦C1≦1×10 22 cm -3 、 1×10 15 cm -3 ≦C2≦1×10 18 cm -3 The semiconductor device according to C3 or C4,

[0347] [C6] The maximum width W of the trench 200 DTB The following relationship exists: 1μm≦W DTB The semiconductor device according to any one of C1 to C5, wherein the thickness satisfies ≦10 μm.

[0348] [C7] A first recess DP1 and a second recess DP2 are adjacent to each other in the width direction of the trench 200, and a first insulating region 13 is formed in the first recess DP1. OUT is located within the second recess DP2, and a second insulating region 13 IN The semiconductor device according to any one of C1 to C6, wherein:

[0349] [C8] The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B formed on the underlying substrate 1A, and includes a first recess DP1 and a second recess DP2 adjacent to each other in a width direction of the trench. The first recess DP1 includes a first insulating region 13. OUT is located within the second recess DP2, and a second insulating region 13 IN and a depth of the first recess DP1 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0350] [C9] The semiconductor device according to C8, wherein the depth of the second recess DP2 is smaller than the depth (second position Z2) of the epitaxial crystal region 1B.

[0351] [C10] The semiconductor device according to any one of C7 to C10, wherein the first recess DP1 has a depth of 100 nm or more.

[0352] [C11] The semiconductor device according to any one of C7 to C11, wherein the second recess DP2 has a depth of 100 nm or more.

[0353] [C12] A method for manufacturing a semiconductor device, comprising the steps of: dry etching the semiconductor substrate 1 through an opening in a mask (a hard mask including a third insulating film 303) provided on the semiconductor substrate 1 to form a trench 200 (FIG. 20(D)); forming an insulating film 2 on the exposed surface of the trench 200 (FIG. 20(E)); and supplying a first conductive material 309 into the trench 200 through the opening in the mask to form a first material region (11) (FIG. 20(G)), wherein a direction perpendicular to a thickness direction of the semiconductor substrate 1 is defined as a horizontal direction, and a maximum value of a thickness ΔW of the insulating film 2 in the trench 200 along the horizontal direction is 0.1 μm or more and 1 μm or less.

[0354] Regarding the above-mentioned fourth semiconductor device (FIGS. 1 to 3, 25 to 31), D1 to D10 are defined.

[0355] [D1] A semiconductor device comprising: a semiconductor substrate 1 including a trench 200 surrounding a device 50; an insulating film 2 covering an inner surface of the trench 200; and a conductive region (first material region 11) provided in the trench 200, wherein the inner surface of the insulating film 2 comprises a first inner surface (first lower side 2AX, second lower side 2BX) located on the bottom side of the trench 200, and a second inner surface (curved surface 2AA, curved surface 2BB) located on the surface side of the trench 200, continuing from the first inner surface, and narrowing in width along a depth direction, wherein a cross section (XZ cross section) including the width direction and depth direction of the trench 200 and a plurality of intersection lines (second outer inner surface 202A, second inner inner surface 202B) formed by the intersection of the second inner surface (curved surface 2AA, curved surface 2BB) each have an arc shape, and the conductive region (first material region 11) extends to a position deeper than the deepest position (third position Z3) of the insulating film 2.

[0356] [D2] The semiconductor device described in D1, wherein the semiconductor substrate 1 comprises a base substrate 1A and an epitaxial crystal region 1B formed on the base substrate 1A, and the trench 200 penetrates an interface (second position Z2) between the base substrate 1A and the epitaxial crystal region 1B.

[0357] [D3] The semiconductor device according to D1 or D2, wherein the conductive region includes polysilicon to which an impurity is added.

[0358] [D4] The concentration of the impurity satisfies the range of the first impurity concentration C1 below, 1×10 18 cm -3 ≦C1≦1×10 22 cm -3 , D3. The semiconductor device according to claim 1 .

[0359] [D5] A first recess DP1 and a second recess DP2 are adjacent to each other in the width direction of the trench 200, and a first insulating region 13 is formed in the first recess DP1. OUT is located within the second recess DP2, and a second insulating region 13 IN The semiconductor device according to any one of D1 to D4, wherein

[0360] [D6] The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B formed on the underlying substrate 1A. The semiconductor substrate 1 includes a first recess DP1 and a second recess DP2 adjacent to each other in the width direction of the trench 200. The first recess DP1 includes a first insulating region 13. OUT is located within the second recess DP2, and a second insulating region 13 IN The semiconductor device according to any one of D1 to D4, wherein a depth of the first recess DP1 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0361] [D7] The semiconductor device according to D6, wherein the depth of the second recess DP2 is smaller than the depth (second position Z2) of the epitaxial crystal region 1B.

[0362] [D8] The semiconductor device according to any one of D5 to D7, wherein the first recess DP1 has a depth of 100 nm or more.

[0363] [D9] The semiconductor device according to any one of D5 to D8, wherein the second recess DP2 has a depth of 100 nm or more.

[0364] [D10] A process of etching the semiconductor substrate 1 to form a trench 200 (FIG. 27(D)), a process of filling the trench 200 with an insulating material (first insulating material 317) (FIG. 27(E)), and etching the insulating material (first insulating material 317) in the trench 200 through an opening in a mask (mask conductive material 318) provided on the semiconductor substrate 1 to form a space (shallow bottom recess 321) directly below the opening and directly below a region outside both ends of the opening in the width direction. a step of anisotropically etching the insulating material (first insulating material 317) in the trench 200 through the opening to form a recess (second deep recess 322) that is continuous with the space (shallow recess 321) and reaches into the semiconductor substrate 1 (FIG. 28(E)); and a step of supplying a conductive material (323) into the space (shallow recess 321) and the recess (second deep recess 322) to form a first material region 11 (FIG. 28(F)).

[0365] Regarding the above-mentioned fifth semiconductor device (FIGS. 1 to 3, 32 to 38), E1 to E11 are defined.

[0366] [E1] A semiconductor device comprising: a semiconductor substrate 1 including a trench 200 surrounding a device 50; a first insulating film 2S (insulating film 2SA, insulating film 2SB) covering an inner surface of the trench 200; an outer conductive region (first conductive film 11S) provided within the trench 200 on the inner side of the first insulating film 2S (insulating film 2SA, insulating film 2SB); a second insulating film 2T (insulating film 2TA, insulating film 2TB) provided within the trench 200 on the inner side of the outer conductive region (first conductive film 11S); and an inner conductive region (first material region 11) provided within the trench 200 on the inner side of the second insulating film 2T (insulating film 2TA, insulating film 2TB).

[0367] [E2] A semiconductor device as described in E1, wherein the semiconductor substrate 1 comprises a base substrate 1A and an epitaxial crystal region 1B formed on the base substrate 1A, and the trench 200 penetrates an interface (second position Z2) between the base substrate 1A and the epitaxial crystal region 1B.

[0368] [E3] The semiconductor device according to E1 or E2, wherein the outer conductive region (first conductive film 11S) includes polysilicon doped with an impurity, and the inner conductive region (first material region 11) includes polysilicon doped with an impurity.

[0369] [E4] Outer impurity concentration C of the outer conductive region (first conductive film 11S) OUT and the inner impurity concentration C of the inner conductive region (first material region 11) IN is the following relationship, 1 x 10 18 cm -3 ≦C OUT ≦1×10 22 cm -3 、 1×10 15 cm -3 ≦C IN ≦1×10 18 cm -3 The semiconductor device according to any one of E1 to E3, which satisfies the above.

[0370] [E5] The maximum width W of the trench 200 DTB The following relationship exists: 1μm≦W DTB The semiconductor device according to any one of E1 to E4, which satisfies the requirement of ≦10 μm.

[0371] [E6] A first recess DP1 and a second recess DP2 are adjacent to each other in the width direction of the trench 200, and a first insulating region 13 is formed in the first recess DP1. OUT is located within the second recess DP2, and a second insulating region 13 IN The semiconductor device according to any one of E1 to E5, wherein:

[0372] [E7] The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B formed on the underlying substrate 1A, and includes a first recess DP1 and a second recess DP2 adjacent to each other in the width direction of the trench 200. The first recess DP1 includes a first insulating region 13. OUT is located within the second recess DP2, and a second insulating region 13 INand a depth of the first recess DP1 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0373] [E8] The semiconductor device according to E7, wherein the depth of the second recess DP2 is smaller than the depth (second position Z2) of the epitaxial crystal region 1B.

[0374] [E9] The semiconductor device according to any one of E6 to E8, wherein the first recess DP1 has a depth of 100 nm or more.

[0375] [E10] The semiconductor device according to any one of E6 to E9, wherein the second recess DP2 has a depth of 100 nm or more.

[0376] [E11] A method for manufacturing a semiconductor device, comprising the steps of: etching a semiconductor substrate 1 to form a trench 200 (FIG. 34(D)); forming a first insulating film (insulating film 2, first insulating film 2S) in the trench 200 (FIG. 34(E)); forming a conductive film (fourth conductive material 324, first conductive film 11S) on the first insulating film (FIG. 34(G)); forming a second insulating film (eighth insulating film 325, second insulating film 2T) on the conductive film (fourth conductive material 324) (FIG. 34(H)); and supplying a conductive material (fifth conductive material 326) on the second insulating film (eighth insulating film 325, second insulating film 2T) in the trench 200 to form a conductive region (first material region 11 in FIG. 32) (FIG. 35(B)).

[0377] Regarding the above-mentioned sixth semiconductor device (FIGS. 1 to 3, 39 to 45), F1 to F11 are defined.

[0378] [F1] A semiconductor device comprising: a semiconductor substrate 1 including a trench 200 surrounding a device 50; an insulating film 2 covering the inner surface of the trench 200; a conductive region (first material region 11) provided within the trench 200; and a buried insulating region 2U provided at a central position in the width direction of the trench 200 and having a shape extending along the depth direction of the trench 200.

[0379] [F2] A semiconductor device as described in F1, wherein the semiconductor substrate 1 comprises a base substrate 1A and an epitaxial crystal region 1B formed on the base substrate 1A, and the trench 200 penetrates an interface (second position Z2) between the base substrate 1A and the epitaxial crystal region 1B.

[0380] [F3] The semiconductor device according to F1 or F2, wherein a first maximum thickness (Z2U) in a depth direction (Z direction) and a first maximum width (X2U) in a width direction (X direction) of the buried insulating region 2U satisfy the following relationships: 0.1 μm≦Z2U≦20 μm, 0.1 μm≦X2U≦5 μm.

[0381] [F4] The semiconductor device according to any one of F1 to F2, wherein the conductive region includes polysilicon to which an impurity is added.

[0382] [F5] The first impurity concentration C1 of the conductive region is expressed as follows: 18 cm -3 ≦C1≦1×10 22 cm -3 、 The semiconductor device according to F4,

[0383] [F6] A first recess DP1 and a second recess DP2 are adjacent to each other in the width direction of the trench 200, and a first insulating region 13 is formed in the first recess DP1. OUT is located within the second recess DP2, and a second insulating region 13 IN The semiconductor device according to any one of F1 to F5, wherein

[0384] [F7] The semiconductor substrate 1 includes an underlying substrate 1A and an epitaxial crystal region 1B formed on the underlying substrate 1A. The semiconductor substrate 1 includes a first recess DP1 and a second recess DP2 adjacent to each other in the width direction of the trench 200. The first recess DP1 includes a first insulating region 13. OUT is located within the second recess DP2, and a second insulating region 13 INand a depth of the first recess DP1 is smaller than a depth (second position Z2) of the epitaxial crystal region 1B.

[0385] [F8] The semiconductor device according to F7, wherein the depth of the second recess DP2 is smaller than the depth (second position Z2) of the epitaxial crystal region 1B.

[0386] [F9] The semiconductor device according to any one of F6 to F8, wherein the first recess DP1 has a depth of 100 nm or more.

[0387] [F10] The semiconductor device according to any one of F6 to F9, wherein the second recess DP2 has a depth of 100 nm or more.

[0388] [F11] A method for manufacturing a semiconductor device comprising the steps of: etching a semiconductor substrate 1 to form a trench 200 (Figure 41(D)); forming an insulating film 2 in the trench 200 (Figure 41(E)); supplying a first conductive material 309 onto the insulating film 2 to form a seam 310 in the trench 200 (Figure 41(G)); and forming an insulating film (ninth insulating film 327) in the seam 310 (Figure 41(H)).

[0389] It should be noted that, with regard to the above-mentioned first to sixth semiconductor devices and the manufacturing methods thereof, each element can be combined as necessary.

[0390] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Elements in different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims. [Explanation of symbols]

[0391] 1...semiconductor substrate, 1A...base substrate, 1B...epitaxial crystal region, 1B1...first epitaxial layer, 1B2...second epitaxial layer, 1B 21 ...First semiconductor layer, 1B 22 ...Second semiconductor layer, 1B 23 ...third semiconductor layer, 1P...highly doped impurity region, 2...insulating film, 2AT...first upper position, 2BT...second upper position, 2A...outer insulating film, 2AA...curved surface, 2AX...first lower side, 2B...inner insulating film, 2BB...curved surface, 2BX...second lower side, 2S...first insulating film, 2SA...insulating film, 2SB...insulating film, 2T...second insulating film, 2TA...insulating film, 2TB...insulating film, 2U...buried insulating region, 3...first main surface, 4...second main surface, 5A...first side, 5B...second side, 5C...third side, 5D...fourth side, 10...device region, 11...first material region, 11 OUT …First neighboring region, 11 IN ...second vicinity region, 11N...surface side semiconductor region, 11P1...outer semiconductor region, 11P2...inner semiconductor region, 11P3...bottom side semiconductor region, 11S...first conductive film, 11SA...conductive film, 11SB...conductive film, 11A...first conductive region, 11B...second conductive region, 12...second material region, 12A...region, 13 OUT …First isolation area, 13 IN...second insulating region, 14...protective film, 20...DTI structure, 21...first STI structure, 22...second STI structure, 27...mesa portion, 50...device, 51...first well region, 52...second well region, 53...drain region, 54...source region, 55...channel, 56...contact region, 57...planar gate structure, 58...gate insulating film, 59...gate electrode, 60...insulating portion, 61...shallow trench, 62...insulator, 63...drain contact electrode, 64...source contact electrode, 65...gate contact electrode, 7 1...first contact electrode, 72...second contact electrode, 73...third contact electrode, 100...semiconductor device, 101...chip, 141...first bottom surface, 142...second bottom surface, 200...trench, 201...first trench, 202...second trench, 201A...first outer inner surface, 201B...first inner inner surface, 202A...second outer inner surface, 202B...second inner inner surface, 301...first insulating film, 302...second insulating film, 303...third insulating film, 304...first resist material, 305...first opening, 306...surface side recess, 307...bottom deep recess, 309...first conductive material, 310...seam, 311...upper conductive material, 312...fourth insulating film, 313...fifth insulating film, 314...second resist material, 315...sixth insulating film, 316...seventh insulating film, 317...first insulating material, 318...mask conductive material, 319...third resist material, 320...second opening, 321...shallow bottom recess, 322...second deep bottom recess, 323...third conductive material, 324...fourth conductive material, 325...eighth insulating film, 326...fifth conductive material, 327...ninth insulating film, 328...tenth conductive material, DP1... First recess, DP2...second recess, TR...trench structure, TR1...first trench structure, TR2...second trench structure, BD...boundary position, BD2...boundary line, BD3...third reference position, DA...first recess surface, DB...second recess surface, R1...first end region, R2...second end region, R3...interface region, S1...first region, S2...second region, S3...third region, S4...fourth region, S5...fifth region, S6...sixth region, V1...first potential, V2...second potential, V3...third potential, VD...drain potential, VG...gate potential, VS...source potential, W DTB ...Maximum width, W DTC...width direction distance, W1...first width, W2...second width, W3...third width, X2U...first maximum width, θ141...first angle, θ142...second angle, Z0...reference position, Z1...first position, Z2...second position, Z3...third position, ZD...top end position, ZJ...pn junction position, ZM...deepest position, ZS...first bottom position, ZT...bottom position, ΔZ3...depth difference, Z2U...first maximum thickness.

Claims

1. a semiconductor substrate including a trench surrounding the device; an insulating film covering an inner surface of the trench; a conductive region disposed within the trench; Equipped with The trench is a first trench located on a bottom surface side of the trench; a second trench located on a surface side of the trench, continuous with the first trench, and narrowing in width along a depth direction; Equipped with A semiconductor device, wherein a reduction in width per unit depth of the second trench is greater than a reduction in width per unit depth of the first trench.

2. The semiconductor substrate is A base substrate; an epitaxial crystal region formed on the base substrate; Equipped with the first trench penetrates an interface between the underlying substrate and the epitaxial crystalline region; The semiconductor device according to claim 1 .

3. The conductive region is a first material region embedded within the first trench and the second trench; a second material region embedded within the first material region and having different etching characteristics than the first material region; Equipped with The semiconductor device according to claim 1 .

4. the first material region includes doped polysilicon; the second material region includes polysilicon having an impurity concentration lower than an impurity concentration of the first material region; The semiconductor device according to claim 3 .

5. A first impurity concentration C of the first material region １ and a second impurity concentration C of the second material region. ２is the following relationship: 1x10 １８ cm －３ ≦C １ ≦1×10 ２２ cm －３ , 1x10 １５ cm －３ ≦C ２ ≦1×10 １８ cm －３ , Fulfilling The semiconductor device according to claim 4.

6. The second material region has a region having a width that narrows toward a bottom surface of the trench. The semiconductor device according to claim 3 .

7. With respect to an outer end and an inner end of the second trench that provide a maximum width of the second trench, a position of the outer end is defined as a first position, a position of the inner end is defined as a second position, and a first recess and a second recess are provided adjacent to each other in a width direction of the trench, a first insulating region in the first recess is located above the first position; A second insulating region in the second recess is located above the second position. The semiconductor device according to claim 1 .

8. The semiconductor substrate is A base substrate; an epitaxial crystal region formed on the base substrate; Preparation, With respect to an outer end and an inner end of the second trench that provide a maximum width of the second trench, a position of the outer end is defined as a first position, a position of the inner end is defined as a second position, and a first recess and a second recess are provided adjacent to each other in a width direction of the trench, a first insulating region in the first recess is located above the first position; The depth of the first recess is smaller than the depth of the epitaxial crystal region. The semiconductor device according to claim 1 .

9. a second insulating region in the second recess is located above the second position; The depth of the second recess is smaller than the depth of the epitaxial crystal region. The semiconductor device according to claim 8.

10. The depth of the first recess is 100 nm or more. The semiconductor device according to claim 7.

11. The depth of the second recess is 100 nm or more. The semiconductor device according to claim 10.

12. a distance between a bottom surface of the first insulating region and a bottom surface of the second insulating region is smaller than a maximum width of the second trench; The semiconductor device according to claim 7.

13. A plurality of intersection lines formed by intersections of a cross section including a width direction and a depth direction of the second trench with an inner surface of the second trench each extend linearly. The semiconductor device according to claim 1 .

14. a plurality of intersection lines formed by intersections of a cross section including a width direction and a depth direction of the second trench with an inner surface of the second trench each have an arc shape; The semiconductor device according to claim 1 .

15. a step of etching the semiconductor substrate through an opening of a mask provided on the semiconductor substrate to form a space immediately below the opening and immediately below a region on the outer side of both ends of the opening in a width direction; dry etching the semiconductor substrate through the opening to form a trench continuous with the space; forming an insulating film on the space and exposed surfaces of the trench; supplying a first conductive material into the trench through the opening to form a first conductive region and supplying the first conductive material into the space to form a second conductive region having a seam, forming a first material region including the first conductive region and the second conductive region; etching the second conductive region through the opening until reaching the seam in the second conductive region; providing a second conductive material through the opening and into the seam to form a second material region in the seam; A method for manufacturing a semiconductor device comprising the steps of:

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