Semiconductor device

Abstract

To provide a semiconductor device that suppresses increase in an inductance.SOLUTION: A semiconductor device 10 includes a first conductive plate 21, a second conductive plate 22, a P terminal 30, a first semiconductor element 31, a second semiconductor element 32, an N terminal 40, an O terminal 50, a first terminal 61, a first gate terminal 71, and a second gate terminal 72. The second semiconductor element 32 is opposed to the first semiconductor element 31 in one direction Da. The first gate terminal 71 extends through an opening 405 of the N terminal 40. The second gate terminal 72 extends through the opening 405. Moreover, the first gate terminal 71 and the second gate terminal 72 are arranged between the first semiconductor element 31 and the second semiconductor element 32 and face each other. Additionally, a current path is formed among the P terminal 30, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32, and the N terminal 40.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, as described in Patent Document 1, a semiconductor module including a first metal wiring plate, a second metal wiring plate, a third metal wiring plate, a first semiconductor element, a second semiconductor element, a gate metal wiring plate, a first gate terminal, and a second gate terminal is known. In this semiconductor module, the first metal wiring plate constitutes a P terminal, which is one terminal. The second metal wiring plate constitutes an N terminal, which is the other terminal. The third metal wiring plate constitutes an output terminal. The first semiconductor element is disposed with a collector electrode facing one main surface of the first metal wiring plate. The second semiconductor element is disposed with a collector electrode facing one main surface of the third metal wiring plate. The gate metal wiring plate is connected to the gate electrode of the second semiconductor element. The first gate terminal rises from the gate electrode of the first semiconductor element toward the third metal wiring plate. The second gate terminal rises from the gate metal wiring plate toward the third metal wiring plate. In addition, the third metal wiring plate has a first through hole through which the first gate terminal can be inserted and a second through hole through which the second gate terminal can be inserted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-57543 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor module described in Patent Document 1, the second gate terminal is connected to the second semiconductor element via a gate metal wiring plate. This increases the distance of the current path from the second gate terminal to the second semiconductor element compared to a case where there is no gate metal wiring plate. This increases the inductance of the current path from the second gate terminal to the second semiconductor element. This increases the inductance of the semiconductor module.

[0005] An object of the present disclosure is to provide a semiconductor device that suppresses an increase in inductance. [Means for solving the problem]

[0006] The invention described in claim 1 is a semiconductor device comprising: a substrate (15); a first conductive portion (21) formed on the substrate and having conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in one direction (Da) intersecting a thickness direction (DT) of the substrate; a first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; a second conductive portion (22) formed on the substrate and having conductivity; a terminal (61) connected to the second electrode and extending in a direction intersecting the thickness direction and the one direction to be connected to the second conductive portion; a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; the second element faces the first element in one direction, the first gate terminal (71) is connected to the first gate electrode and extends to pass through the opening, a second gate terminal (72) is connected to the second gate electrode and extends to pass through the opening, and an output terminal (50) is connected to the second conductive portion and outputs a current in response to the on / off of the first element and the second element, the second element facing the first element in one direction, the first gate terminal and the second gate terminal being disposed between the first element and the second element and facing each other, and a current path (Cp) is formed among the first terminal, the first conductive portion, the first element, the terminal, the second conductive portion, the second element, and the second terminal.

[0007] This makes it possible to reduce the length of the current path from the first gate terminal and the second gate terminal passing through the common opening to the drive circuit that drives the first element and the second element, compared to when the first gate terminal and the second gate terminal do not face each other. Also, compared to when the first gate terminal and the second gate terminal do not face each other, the sizes of the first conductive portion, the terminal, the second conductive portion, the second terminal, etc. can be made smaller, so that the length of the current path is reduced. Therefore, the length of the current path within the semiconductor device is reduced, and an increase in the inductance of the semiconductor device is suppressed.

[0008] The invention described in claim 11 is a semiconductor device comprising: a substrate (15); a first conductive portion (21) formed on the substrate and having conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in one direction (Da) intersecting a thickness direction (DT) of the substrate; a first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; a second conductive portion (22) formed on the substrate and having conductivity; a first terminal (61) connected to the first conductive portion and extending in the opposite direction to the one direction to be connected to the second conductive portion; a second element (32) having a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; a third element (33) having a fifth electrode connected to the first conductive portion, a sixth electrode, and a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode based on an applied voltage; a fourth element (34) having a second terminal (63) connected to the second conductive portion by the gate electrode (61), a seventh electrode connected to the second conductive portion, an eighth electrode, and a fourth gate electrode that causes a current to flow between the seventh electrode and the eighth electrode based on an applied voltage; a second terminal (40) having a first extension portion (401) connected to the fourth electrode and extending in one direction, a second extension portion (402) connected to the eighth electrode and extending in one direction, and an opening (405) formed by the first extension portion and the second extension portion; a first gate terminal (71) extending through the opening, a second gate terminal (72) connected to the second gate electrode and extending through the opening, a third gate terminal (73) connected to the third gate electrode and extending through the opening, a fourth gate terminal (74) connected to the fourth gate electrode and extending through the opening, and an output terminal (50, 501, 502) connected to the second conductive portion and outputting a current in response to the on / off of the first element, the second element, the third element and the fourth element,The first element faces the third element in a direction intersecting the thickness direction and the one direction, the second element faces the first element in one direction and faces the fourth element in a direction intersecting the thickness direction and the one direction, the fourth element faces the third element in one direction, the first gate terminal and the third gate terminal are disposed between the first element and the third element and face each other, the second gate terminal and the fourth gate terminal are disposed between the second element and the fourth element and face each other, a first current path (Cp1) is formed between the first terminal, the first conductive part, the first element, the first terminal, the second conductive part, the second element and the second terminal, and a second current path (Cp2) is formed between the first terminal, the first conductive part, the third element, the second terminal, the second conductive part, the fourth element and the second terminal.

[0009] This allows the length of the current path from each gate terminal passing through the common opening to the drive circuit that drives the first element, the second element, the third element, and the fourth element to be reduced compared to when the gate terminals do not face each other. Also, compared to when the gate terminals do not face each other, the size of the first conductive portion, each terminal, the second conductive portion, the second terminal, etc. can be reduced, so the length of the current path is reduced. Therefore, since the length of the current path within the semiconductor device is reduced, an increase in the inductance of the semiconductor device is suppressed.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a perspective view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. [Diagram 3] FIG. [Figure 4] An enlarged view of arrow IV in Figure 3. [Diagram 5] Enlarged view from V in Figure 3. [Figure 6] Enlarged cross-sectional view of line VI-VI in Figure 3. [Figure 7] An enlarged cross-sectional view of line VII-VII in Figure 3. [Figure 8] FIG. 2 is an internal top view of the semiconductor device excluding an N terminal. [Figure 9] FIG. [Figure 10] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 11] FIG. 13 is an internal top view of a semiconductor device according to a third embodiment. [Figure 12] FIG. 13 is an internal top view of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 13 is an internal top view of a semiconductor device according to a fifth embodiment, with an N terminal removed. [Figure 14] FIG. [Figure 15] FIG. 13 is an internal top view of a semiconductor device according to a sixth embodiment, with an N terminal removed. [Figure 16] FIG. [Figure 17] FIG. 13 is an internal top view of a semiconductor device according to a seventh embodiment, with an N terminal removed. [Figure 18] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals, and the description thereof will be omitted.

[0013] (First embodiment) In the semiconductor device of this embodiment, an increase in inductance is suppressed. The semiconductor device is used, for example, to control a motor (not shown).

[0014] 1 to 9, the semiconductor device 10 includes a substrate 15, a first conductive plate 21, a P terminal 30, a first semiconductor element 31, a first bonding material 41, and a second conductive plate 22. The semiconductor device 10 also includes a first terminal 61, a second bonding material 42, a third bonding material 43, a second semiconductor element 32, a fourth bonding material 44, a second terminal 62, and a fifth bonding material 45. The semiconductor device 10 also includes an N terminal 40, a sixth bonding material 46, a first gate terminal 71, a second gate terminal 72, an O terminal 50, a first outgoing wiring 81, a second outgoing wiring 82, a sealing resin 85, and a current path Cp.

[0015] As shown in Figs. 2 to 9, substrate 15 is an insulating substrate made of resin or the like. First conductive plate 21 corresponds to a first conductive portion, and is formed in a plate shape from a metal such as aluminum. This makes first conductive plate 21 conductive. Moreover, first conductive plate 21 is formed on substrate 15.

[0016] The P terminal 30 corresponds to a first terminal, and is connected to the first conductive plate 21 in a thickness direction DT of the substrate 15. Furthermore, the P terminal 30 is formed of a metal such as aluminum in a plate shape extending in one direction Da perpendicular to the thickness direction DT from the boundary with the first conductive plate 21. The P terminal 30 is also connected to a power source (not shown).

[0017] The first semiconductor element 31 corresponds to the first element, and is, for example, a MOSFET element using Si or SiC. Note that MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor.

[0018] 6, the first semiconductor element 31 has a first drain electrode 311, a first source electrode 312, and a first gate electrode (not shown). The first drain electrode 311 corresponds to a first electrode and is connected to the first conductive plate 21 in the thickness direction DT via a first bonding material 41 such as solder. The first source electrode 312 corresponds to a second electrode and is connected to a first terminal 61 (described later) in the thickness direction DT via a second bonding material 42 such as solder. The first gate electrode causes a current to flow between the first drain electrode 311 and the first source electrode 312 based on a voltage applied to the first gate electrode.

[0019] The second conductive plate 22 corresponds to the second conductive portion, and is formed in a plate shape from a metal such as aluminum. This makes the second conductive plate 22 conductive. The second conductive plate 22 is formed on the substrate 15 as shown in Figs. 2 to 9. The second conductive plate 22 is separated from the first conductive plate 21, and is therefore insulated from the first conductive plate 21. As shown in Fig. 6, the second conductive plate 22 has both conductive portion ends 222. The both conductive portion ends 222 face in a direction perpendicular to the thickness direction DT and the one direction Da when the second conductive plate 22 is cut in a direction perpendicular to the one direction Da through both extension portion ends 412 described below.

[0020] The first terminal 61 is connected to the first source electrode 312 in the thickness direction DT via the second bonding material 42. The first terminal 61 is formed of a metal such as aluminum in a plate shape extending from the first source electrode 312 in a direction perpendicular to the thickness direction DT and the one direction Da toward the second conductive plate 22. As a result, the first terminal 61 is connected to the second conductive plate 22 in the thickness direction DT via the third bonding material 43 such as solder. The direction perpendicular to the thickness direction DT and the one direction Da corresponds to a direction intersecting the thickness direction DT and the one direction Da.

[0021] The second semiconductor element 32 corresponds to the second element and is, for example, a MOSFET element using Si or SiC. Furthermore, the second semiconductor element 32 faces the first semiconductor element 31 in one direction Da, as shown in Figures 4 and 5. The second semiconductor element 32 and the first semiconductor element 31 are lined up in order in the one direction Da.

[0022] 7, the second semiconductor element 32 has a second drain electrode 321, a second source electrode 322, and a second gate electrode (not shown). The second drain electrode 321 corresponds to a third electrode and is connected to the second conductive plate 22 via a fourth bonding material 44 such as solder. The second source electrode 322 corresponds to a fourth electrode and is connected to the second terminal 62 in the thickness direction DT via a fifth bonding material 45 such as solder. The second gate electrode causes a current to flow between the second drain electrode 321 and the second source electrode 322 based on a voltage applied to the second gate electrode. The second terminal 62 is formed in a plate shape from a metal such as aluminum.

[0023] N terminal 40 corresponds to the second terminal, and is formed in a plate shape from metal such as aluminum, etc. N terminal 40 has first extension portion 401, second extension portion 402, and opening 405, as shown in FIGS.

[0024] As shown in FIG. 7, the first extension 401 is connected to the second terminal 62 in the thickness direction DT via a sixth bonding material 46 such as solder. Therefore, the first extension 401 is connected to the second source electrode 322 via the sixth bonding material 46, the second terminal 62, and the fifth bonding material 45. Furthermore, the first extension 401 extends in a direction perpendicular to the thickness direction DT and the one direction Da. Furthermore, when the first extension 401 is projected in the thickness direction DT, the projected first extension 401 overlaps with the second conductive plate 22. Furthermore, L1, which is the minimum distance from the first extension 401 to the second conductive plate 22 in the thickness direction DT, is set to, for example, 0.2 to 1.5 mm.

[0025] As shown in Figs. 1 to 3, 6 and 9, two second extensions 402 are formed here. The second extensions 402 are connected to both ends of the first extension 401. The second extensions 402 extend from the first extension 401 in one direction Da. The second extensions 402 are connected to a power source. When the second extensions 402 are projected in the thickness direction DT, the projected second extensions 402 overlap the first conductive plate 21, the second conductive plate 22 and the first terminal 61. The minimum distance L2 from the second extensions 402 to the first terminal 61 in the thickness direction DT is, for example, 0.2 to 1.5 mm. The number of the second extensions 402 is not limited to two, and may be at least one.

[0026] 6, the second extension portion 402 has both extension ends 412. When the second extension portion 402 is cut in a direction perpendicular to the one direction Da, the both extension ends 412 face in a direction perpendicular to the thickness direction DT and the one direction Da. Furthermore, when the both extension ends 412 are projected in the thickness direction DT, the projected both extension ends 412 do not overlap with the both conductive portion ends 222.

[0027] 2 to 5 and 9, opening 405 is a space formed by first extension portion 401 and second extension portion 402. Here, opening 405 is formed in a quadrangle with rounded corners. The shape of opening 405 is not limited to a quadrangle, and may be a polygon, a circle, or the like.

[0028] The first gate terminal 71 is formed in a columnar shape from a metal such as copper. A plurality of the first gate terminals 71 are arranged at intervals in a direction perpendicular to the thickness direction DT and the one direction Da. As shown in Figs. 3 and 5, the first gate terminal 71 has a first joint portion 711, a first lead portion 712, and a first top portion 713.

[0029] The first joint portion 711 is connected to the first gate electrode via wiring, solder, or the like (not shown) of the first semiconductor element 31. The first lead portion 712 is connected to the first joint portion 711. Furthermore, the first lead portion 712 extends from the first joint portion 711 in the thickness direction DT. As a result, the first gate terminal 71 extends so as to pass through the opening 405. The first apex portion 713 is connected to the first lead portion 712. Also, here, the first apex portion 713 extends in a direction intersecting the thickness direction DT. Furthermore, the first apex portion 713 is connected to a drive circuit (not shown) that drives the first semiconductor element 31 and the second semiconductor element 32. Note that the first apex portion 713 is not limited to extending in a direction intersecting the thickness direction DT, and may extend in the thickness direction DT.

[0030] The second gate terminal 72 is formed in a columnar shape from a metal such as copper. Furthermore, the second gate terminals 72 are arranged at intervals in the direction in which the first gate terminals 71 are arranged. Furthermore, the second gate terminal 72 has a second joint portion 721, a second lead portion 722, and a second top portion 723, as shown in Figures 3 and 4.

[0031] The second joint portion 721 is connected to the second gate electrode via wiring, solder, or the like (not shown) of the second semiconductor element 32. The second lead portion 722 is connected to the second joint portion 721. Furthermore, the second lead portion 722 extends from the second joint portion 721 in the thickness direction DT. As a result, the second gate terminal 72 extends so as to pass through the opening 405. Therefore, the first gate terminal 71 and the second gate terminal 72 are disposed between the first semiconductor element 31 and the second semiconductor element 32 and face each other. The second apex 723 is connected to the second lead portion 722. Also, here, the second apex 723 extends in a direction from the boundary with the second lead portion 722 toward the first apex 713. Furthermore, the second apex 723 is connected to a drive circuit. The second top portion 723 is not limited to extending in a direction from the boundary with the second drawer portion 722 toward the first top portion 713, and may extend in the thickness direction DT.

[0032] The O terminal 50 corresponds to an output terminal, and is connected to the second conductive plate 22 in the thickness direction DT as shown in Figs. 2 to 5, 8 and 9. The O terminal 50 extends from the second conductive plate 22 in the direction opposite to the one direction Da. The O terminal 50 is connected to a motor (not shown). The O terminal 50 outputs a current to the motor according to the on / off states of the first semiconductor element 31 and the second semiconductor element 32.

[0033] 2, 3, 8 and 9, the first outgoing wiring 81 is formed in the same shape as the first gate terminal 71. The first outgoing wiring 81 is arranged together with the first gate terminal 71 in the direction in which the first gate terminals 71 are arranged. The first outgoing wiring 81 is connected to the first conductive plate 21 and the drive circuit.

[0034] The second outgoing wiring 82 is formed in the same shape as the second gate terminal 72. Moreover, the second outgoing wiring 82 is arranged together with the second gate terminal 72 in the direction in which the second gate terminals 72 are arranged. Furthermore, the second outgoing wiring 82 is connected to the second conductive plate 22 and the drive circuit.

[0035] As shown in FIG. 1, the sealing resin 85 covers the substrate 15, the first conductive plate 21, the first semiconductor element 31, the first bonding material 41, the second conductive plate 22, the first terminal 61, the second bonding material 42, and the third bonding material 43. The sealing resin 85 also covers the second semiconductor element 32, the fourth bonding material 44, the second terminal 62, the fifth bonding material 45, and the sixth bonding material 46. The sealing resin 85 also covers a part of the P terminal 30 so that the P terminal 30 protrudes from the sealing resin 85. The sealing resin 85 also covers the first extension portion 401 and a part of the N terminal 40 so that the second extension portion 402 protrudes from the sealing resin 85. The sealing resin 85 also covers a part of the O terminal 50 so that the O terminal 50 protrudes from the sealing resin 85. The sealing resin 85 covers the first gate terminal 71 such that a portion of the first top portion 713 is exposed to the outside of the sealing resin 85. The sealing resin 85 covers the second gate terminal 72 such that a portion of the second top portion 723 is exposed to the outside of the sealing resin 85. The sealing resin 85 covers the first outgoing wiring 81 such that a portion of the first outgoing wiring 81 is exposed to the outside of the sealing resin 85. The sealing resin 85 covers the second outgoing wiring 82 such that a portion of the second outgoing wiring 82 is exposed to the outside of the sealing resin 85.

[0036] As shown in Figures 8 and 9, a current path Cp is formed between the P terminal 30, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32 and the N terminal 40.

[0037] Here, for example, the direction of the current path Cp is assumed to be the direction from the P terminal 30 to the N terminal 40. At this time, the current path direction between the first terminal 61 and the second conductive plate 22 is opposite to the one direction Da. Furthermore, the current path direction in the second extension portion 402 is the one direction Da. Therefore, the current path direction between the first terminal 61 and the second conductive plate 22 is opposite to the current path direction in the second extension portion 402.

[0038] The semiconductor device 10 of the first embodiment is configured as described above. Next, the operation of the semiconductor device 10 when used for motor control will be described.

[0039] A control device (not shown) controls the voltage applied from the drive circuit to the first gate electrode via the first gate terminal 71 etc., and the voltage applied from the drive circuit to the second gate electrode via the second gate terminal 72 etc. This controls the on / off of the first semiconductor element 31 and the second semiconductor element 32. This controls the currents among the power supply, the P terminal 30, the N terminal 40, the O terminal 50, and the motor. This controls the motor.

[0040] As described above, the semiconductor device 10 is used for motor control. Next, how the semiconductor device 10 suppresses an increase in inductance of the semiconductor device 10 will be described.

[0041] In the semiconductor device 10, the second semiconductor element 32 faces the first semiconductor element 31 in one direction Da. The first gate terminal 71 extends to pass through the opening 405. The second gate terminal 72 extends to pass through the opening 405. The first gate terminal 71 and the second gate terminal 72 are disposed between the first semiconductor element 31 and the second semiconductor element 32 and face each other. Furthermore, a current path Cp is formed among the P terminal 30, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32, and the N terminal 40.

[0042] As a result, the length of the current path from the first gate terminal 71 and the second gate terminal 72 passing through the common opening 405 to the drive circuit can be reduced compared to when the first gate terminal 71 and the second gate terminal 72 do not face each other. Also, compared to when the first gate terminal 71 and the second gate terminal 72 do not face each other, the size of the first conductive plate 21, the first terminal 61, the second conductive plate 22, the N terminal 40, etc. can be reduced, so that the length of the current path Cp is reduced. Therefore, since the path length of the current in the semiconductor device 10 is reduced, an increase in the inductance of the semiconductor device 10 is suppressed. Furthermore, since an increase in the inductance of the semiconductor device 10 is suppressed, a decrease in the switching speed of the first semiconductor element 31 and the second semiconductor element 32 is suppressed. Therefore, the switching loss of the first semiconductor element 31 and the second semiconductor element 32 is suppressed.

[0043] In addition, in the semiconductor module described in Patent Document 1, a first through hole and a second through hole are formed in the third metal wiring plate, and the first gate terminal is inserted through the first through hole, and the second gate terminal is inserted through the second through hole. Furthermore, the shape and size of the first through hole correspond to the shape and size of the first gate terminal. Furthermore, the shape and size of the second through hole correspond to the shape and size of the second gate terminal. As a result, the distance from the first gate terminal to the inner surface of the first through hole and the distance from the second gate terminal to the inner surface of the second through hole are relatively small. For this reason, the first gate terminal and the second gate terminal are likely to come into contact with the third metal wiring plate, or to mechanically interfere with the third metal wiring plate.

[0044] In contrast, in the semiconductor device 10 of this embodiment, the N terminal 40 has a first extension portion 401, a second extension portion 402, and an opening 405. The first extension portion 401 extends in a direction perpendicular to the thickness direction DT and the one direction Da. The second extension portion 402 is connected to the first extension portion 401 and extends from the first extension portion 401 in the one direction Da. The opening 405 is a space formed by the first extension portion 401 and the second extension portion 402. In addition, the first gate terminal 71 and the second gate terminal 72 extend so as to pass through the opening 405.

[0045] As a result, the N terminal 40 extends in a direction away from and detouring the first gate terminal 71 and the second gate terminal 72. This makes it difficult for the N terminal 40 to come into contact with the first gate terminal 71 and the second gate terminal 72. This suppresses mechanical interference between the first gate terminal 71 and the second gate terminal 72.

[0046] Furthermore, the semiconductor device 10 of the first embodiment also provides the following advantages.

[0047] [1-1] The direction of the current path between the first terminal 61 and the second conductive plate 22 is opposite to the direction of the current path in the second extension portion 402 .

[0048] As a result, there are locations where the direction of the magnetic field caused by the current flowing between the first terminal 61 and the second conductive plate 22 is opposite to the direction of the magnetic field caused by the current flowing through the second extension portion 402. Therefore, the magnetic fields between the first terminal 61 and the second conductive plate 22 and the second extension portion 402 cancel each other out. Therefore, an increase in inductance between the first terminal 61 and the second conductive plate 22 and in the second extension portion 402 is suppressed, and therefore an increase in inductance of the semiconductor device 10 is suppressed.

[0049] [1-2] When second extension portion 402 is projected in thickness direction DT, the projected second extension portion 402 overlaps with second conductive plate 22.

[0050] As a result, the gap between the first terminal 61 and the second conductive plate 22 and the second extension portion 402 are closer than when the second extension portion 402 projected in the thickness direction DT does not overlap with the second conductive plate 22. This makes it easier for the magnetic fields between the first terminal 61 and the second conductive plate 22 and the second extension portion 402 to cancel each other out. This suppresses an increase in inductance between the first terminal 61 and the second conductive plate 22 and at the second extension portion 402, thereby suppressing an increase in inductance of the semiconductor device 10.

[0051] Second embodiment In the second embodiment, the shapes of the N terminal 40 and the second conductive plate 22 are different from those of the first embodiment. Specifically, in the first embodiment, when both ends 412 of the extension portion are projected in the thickness direction DT, the projected both ends 412 of the extension portion do not overlap both ends 222 of the conductive portion. In contrast, in the second embodiment, as shown in FIG. 10, both ends 412 of the extension portion projected in the thickness direction DT overlap both ends 222 of the conductive portion. The rest is the same as in the first embodiment. The second embodiment also provides the same effects as the first embodiment. In addition, the second embodiment also provides the effects described below.

[0052] [2] When both ends 412 of the extension portion are projected in the thickness direction DT, the projected both ends 412 of the extension portion overlap both ends 222 of the conductive portion.

[0053] This makes it possible to reduce the sizes of second extension portion 402 and second conductive plate 22 while maximizing the overlapping area between second extension portion 402 and second conductive plate 22, as compared with the case where extension portion ends 412 and conductive portion ends 222 projected in thickness direction DT do not overlap. This prevents semiconductor device 10 from becoming larger.

[0054] Third embodiment The third embodiment differs from the first embodiment in the form of the N terminal 40. Other than this, the third embodiment is similar to the first embodiment.

[0055] Specifically, as shown in FIG. 11, N terminal 40 has a third extension portion 403 in addition to first extension portion 401, second extension portion 402 and opening 405.

[0056] The third extension portion 403 is connected to the side of the second extension portion 402 opposite to the first extension portion 401. The third extension portion 403 extends in one direction Da from the boundary with the second extension portion 402. The third extension portion 403 forms an opening 405 together with the first extension portion 401 and the second extension portion 402. When the third extension portion 403 is projected in the thickness direction DT, the projected third extension portion 403 overlaps with the P terminal 30.

[0057] Here, for example, the direction of the current path Cp is assumed to be the direction from the P terminal 30 toward the N terminal 40. In this case, the current path direction between the second extension portion 402 and the third extension portion 403 is inward, perpendicular to the thickness direction DT and the one direction Da. Furthermore, the current path direction in the first terminal 61 is outward, perpendicular to the thickness direction DT and the one direction Da. Therefore, the current path direction between the second extension portion 402 and the third extension portion 403 is opposite to the current path direction in the first terminal 61.

[0058] In this case, the current path direction in the third extension 403 is one direction Da. Furthermore, the current path direction in the P terminal 30 is opposite to the one direction Da. Therefore, the current path direction in the third extension 403 is opposite to the current path direction in the P terminal 30.

[0059] The semiconductor device 10 of the third embodiment is configured as described above. The third embodiment also provides the same effects as the first embodiment. The third embodiment also provides the following effects.

[0060] [3-1] The direction of the current path between the second extension portion 402 and the third extension portion 403 is opposite to the direction of the current path in the first terminal 61.

[0061] As a result, there are locations where the direction of the magnetic field caused by the current flowing between the second extension portion 402 and the third extension portion 403 is opposite to the direction of the magnetic field caused by the current flowing through the first terminal 61. Therefore, the magnetic fields between the second extension portion 402 and the third extension portion 403 and the first terminal 61 cancel each other out. Therefore, an increase in inductance between the second extension portion 402 and the third extension portion 403 and at the first terminal 61 is suppressed, and an increase in inductance of the semiconductor device 10 is suppressed.

[0062] [3-2] The direction of the current path in the third extension portion 403 is opposite to the direction of the current path in the P terminal 30.

[0063] As a result, there are locations where the direction of the magnetic field caused by the current flowing through third extension 403 is opposite to the direction of the magnetic field caused by the current flowing through P terminal 30. As a result, the magnetic fields of third extension 403 and P terminal 30 cancel each other out. Therefore, an increase in the inductance of third extension 403 and P terminal 30 is suppressed, and an increase in the inductance of semiconductor device 10 is suppressed.

[0064] [3-3] When the third extension portion 403 is projected in the thickness direction DT, the projected third extension portion 403 overlaps with the P terminal 30.

[0065] As a result, the third extension portion 403 and the P terminal 30 are closer to each other than when the third extension portion 403 projected in the thickness direction DT does not overlap with the P terminal 30. This makes it easier for the third extension portion 403 and the P terminal 30 to cancel out each other's magnetic fields. This suppresses an increase in the inductance of the third extension portion 403 and the P terminal 30, thereby suppressing an increase in the inductance of the semiconductor device 10.

[0066] (Fourth embodiment) In the fourth embodiment, the shapes of the first terminal 61 and the N terminal 40 are different from those of the third embodiment. Specifically, in the third embodiment, when the third extension portion 403 is projected in the thickness direction DT, the projected third extension portion 403 does not overlap with the first terminal 61. In contrast, in the fourth embodiment, as shown in FIG. 12, the third extension portion 403 projected in the thickness direction DT overlaps with the first terminal 61. Other than this, the fourth embodiment is similar to the third embodiment. The fourth embodiment also provides the same effects as the third embodiment. In addition, the fourth embodiment also provides the effects described below.

[0067] [4] When the third extension portion 403 is projected in the thickness direction DT, the projected third extension portion 403 overlaps with the first terminal 61.

[0068] As a result, the third extension 403 and the first terminal 61 are closer to each other than when the third extension 403 projected in the thickness direction DT does not overlap with the first terminal 61. This makes it easier for the third extension 403 and the first terminal 61 to cancel out each other's magnetic fields. This suppresses an increase in inductance of the third extension 403 and the first terminal 61, thereby suppressing an increase in inductance of the semiconductor device 10.

[0069] Fifth embodiment In the fifth embodiment, the semiconductor device 10 includes a third semiconductor element 33, a fourth semiconductor element 34, a third gate terminal 73, and a fourth gate terminal 74 in addition to a first semiconductor element 31, a second semiconductor element 32, a first gate terminal 71, and a second gate terminal 72. Also, the shape of the first terminal 61 differs from that of the first embodiment. Other than these, the fifth embodiment is similar to the first embodiment.

[0070] 13 and 14, the third semiconductor element 33 corresponds to a third element and is, for example, a MOSFET element using Si or SiC. Furthermore, the third semiconductor element 33 faces the first semiconductor element 31 in a direction perpendicular to the thickness direction DT and the one direction Da.

[0071] The third semiconductor element 33 also has a third drain electrode 331, a third source electrode 332, and a third gate electrode (not shown). The third drain electrode 331 corresponds to a fifth electrode, and is connected to the first conductive plate 21 in the thickness direction DT via solder or the like. The third source electrode 332 corresponds to a sixth electrode, and is connected to the first terminal 61 in the thickness direction DT via solder or the like. The third gate electrode causes a current to flow between the third drain electrode 331 and the third source electrode 332 based on a voltage applied to the third gate electrode.

[0072] The fourth semiconductor element 34 corresponds to the fourth element and is, for example, a MOSFET element using Si or SiC. Furthermore, the fourth semiconductor element 34 faces the second semiconductor element 32 in a direction perpendicular to the thickness direction DT and the one direction Da. The fourth semiconductor element 34 also faces the third semiconductor element 33 in the one direction Da. The fourth semiconductor element 34 and the third semiconductor element 33 are lined up in order in the one direction Da.

[0073] The fourth semiconductor element 34 also has a fourth drain electrode 341, a fourth source electrode 342, and a fourth gate electrode (not shown). The fourth drain electrode 341 corresponds to a seventh electrode, and is connected to the second conductive plate 22 in the thickness direction DT via solder or the like. The fourth source electrode 342 corresponds to an eighth electrode, and is connected to the second terminal 62 in the thickness direction DT via solder or the like. The fourth gate electrode causes a current to flow between the fourth drain electrode 341 and the fourth source electrode 342 based on a voltage applied to the fourth gate electrode.

[0074] The third gate terminal 73 is formed in a columnar shape and is made of a metal such as copper. The third gate terminals 73 are arranged at intervals in the direction in which the first gate terminals 71 are arranged. The third gate terminal 73 has a third joint portion 731, a third lead portion 732, and a third top portion 733.

[0075] The third joint portion 731 is connected to the third gate electrode via wiring, solder, or the like (not shown) of the third semiconductor element 33. The third lead portion 732 is connected to the third joint portion 731. Furthermore, the third lead portion 732 extends from the third joint portion 731 in the thickness direction DT. As a result, the third gate terminal 73 extends so as to pass through the opening 405. The third apex 733 is connected to the third lead portion 732. Also, here, the third apex 733 extends in a direction intersecting the thickness direction DT. Furthermore, the third apex 733 is connected to a drive circuit (not shown) that drives the first semiconductor element 31, the second semiconductor element 32, the third semiconductor element 33, and the fourth semiconductor element 34. Note that the third apex 733 is not limited to extending in a direction intersecting the thickness direction DT, and may extend in the thickness direction DT.

[0076] The fourth gate terminal 74 is formed in a columnar shape and is made of a metal such as copper. Further, the fourth gate terminals 74 are arranged at intervals in the direction in which the second gate terminals 72 are arranged. Further, the fourth gate terminal 74 has a fourth joint portion 741, a fourth lead portion 742, and a fourth top portion 743.

[0077] The fourth joint 741 is connected to the fourth gate electrode via wiring, solder, or the like (not shown) of the fourth semiconductor element 34. The fourth lead 742 is connected to the fourth joint 741. Furthermore, the fourth lead 742 extends from the fourth joint 741 in the thickness direction DT. As a result, the fourth gate terminal 74 extends so as to pass through the opening 405. Therefore, the third gate terminal 73 and the fourth gate terminal 74 are disposed between the third semiconductor element 33 and the fourth semiconductor element 34 and face each other. The fourth apex 743 is connected to the fourth lead 742. Moreover, here, the fourth apex 743 extends in a direction from the boundary with the fourth lead 742 toward the third apex 733. Furthermore, the fourth apex 743 is connected to the drive circuit. The fourth apex 743 is not limited to extending in the direction from the boundary with the fourth drawn-out portion 742 toward the third apex 733, and may extend in the thickness direction DT. In addition, in order to avoid complexity of the drawings, the first drawn-out wiring 81 and the second drawn-out wiring 82 are omitted in Fig. 13 and Fig. 14.

[0078] The first terminal 61 is connected to a portion of the second conductive plate 22 on the opposite side to the third semiconductor element 33 with respect to the first semiconductor element 31. Furthermore, the first terminal 61 is connected to a portion of the second conductive plate 22 on the opposite side to the first semiconductor element 31 with respect to the third semiconductor element 33.

[0079] Further, a current path Cp is formed among the P terminal 30, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32, and the N terminal 40. In addition to this, a current path Cp is formed among the P terminal 30, the first conductive plate 21, the third semiconductor element 33, the first terminal 61, the second conductive plate 22, the fourth semiconductor element 34, and the N terminal 40.

[0080] The semiconductor device 10 of the fifth embodiment is configured as described above. The fifth embodiment also provides the same effects as the first embodiment. The fifth embodiment also provides the following effects.

[0081] [5] The first terminal 61 is connected to the side of the second conductive plate 22 opposite the third semiconductor element 33 to the first semiconductor element 31, and is connected to the side of the second conductive plate 22 opposite the third semiconductor element 33 to the first semiconductor element 31.

[0082] As a result, a current path is formed between the first terminal 61 and the second conductive plate 22 on the first semiconductor element 31 side, and a current path is also formed between the first terminal 61 and the second conductive plate 22 on the third semiconductor element 33 side. Therefore, bias in inductance is suppressed compared to a case where a current path is formed only on either the first semiconductor element 31 side or the third semiconductor element 33 side.

[0083] Sixth embodiment In the sixth embodiment, as shown in Fig. 15 and Fig. 16, the shapes of the P terminal 30, the first terminal 61, and the N terminal 40 are different from those of the fifth embodiment. The rest is the same as the fifth embodiment. Note that in Fig. 15 and Fig. 16, the first outgoing wiring 81 and the second outgoing wiring 82 are omitted to avoid complication of the figures.

[0084] The P terminal 30 has a first P terminal 301 and a second P terminal 302. The first P terminal 301 and the second P terminal 302 are connected to the first conductive plate 21. The first P terminal 301 and the second P terminal 302 are arranged at an interval in a direction perpendicular to the thickness direction DT and the one direction Da. The first P terminal 301 is arranged in the one direction Da with the first semiconductor element 31 and the second semiconductor element 32. The second P terminal 302 is arranged in the one direction Da with the third semiconductor element 33 and the fourth semiconductor element 34.

[0085] The first terminal 61 is connected to a portion of the second conductive plate 22 on the opposite side of the third semiconductor element 33 from the first semiconductor element 31, and to a portion of the third semiconductor element 33 on the opposite side of the first semiconductor element 31 from the first semiconductor element 31. In addition, the first terminal 61 is connected to a portion of the second conductive plate 22 between the first semiconductor element 31 and the third semiconductor element 33.

[0086] The N terminal 40 has a third extension 403 in addition to the first extension 401, the second extension 402, and the opening 405. Here, the third extension 403 is connected to the first extension 401. The third extension 403 extends in one direction Da from the boundary with the first extension 401. In addition, in a direction perpendicular to the thickness direction DT and the direction Da, the third extension 403 is disposed between the adjacent second extensions 402. In addition, the first semiconductor element 31 and the third semiconductor element 33 are disposed between the second extension 402 and the third extension 403 in a direction perpendicular to the thickness direction DT and the direction Da.

[0087] A first current path Cp1 is formed among the first P terminal 301, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32, and the N terminal 40. A second current path Cp2 is formed among the second P terminal 302, the first conductive plate 21, the third semiconductor element 33, the first terminal 61, the second conductive plate 22, the fourth semiconductor element 34, and the N terminal 40.

[0088] Here, for example, the direction of the first current path Cp1 is the direction from the first P terminal 301 to the N terminal 40. Also, the direction of the second current path Cp2 is the direction from the second P terminal 302 to the N terminal 40. At this time, the current path direction in the second conductive plate 22 is opposite to the one direction Da. Furthermore, the current path direction in the second extension portion 402 is the one direction Da. Moreover, the current path direction in the third extension portion 403 is the one direction Da. Therefore, the current path direction in the second conductive plate 22 is opposite to the current path direction in the second extension portion 402. Furthermore, the current path direction in the second conductive plate 22 is opposite to the current path direction in the third extension portion 403.

[0089] The semiconductor device 10 of the sixth embodiment is configured as described above. The sixth embodiment also provides the same effects as the fifth embodiment.

[0090] Seventh embodiment In the seventh embodiment, as shown in FIG. 17 and FIG. 18, the aspect of the first terminal 61 is different from that of the fifth embodiment. Also, the aspects of the first semiconductor element 31, the second semiconductor element 32, the third semiconductor element 33, and the fourth semiconductor element 34 are different from those of the fifth embodiment. Furthermore, the semiconductor device 10 includes a third terminal 63 in addition to the first terminal 61 and the second terminal 62. Also, the aspects of the first extension portion 401, the second extension portion 402, and the opening 405 of the N terminal 40 are different from those of the fifth embodiment. Furthermore, the form of the O terminal 50 is different from that of the fifth embodiment. Also, the aspects of the first gate terminal 71, the second gate terminal 72, the third gate terminal 73, and the fourth gate terminal 74 are different from those of the fifth embodiment. Other than these, the seventh embodiment is the same as the fifth embodiment. Note that in FIG. 17 and FIG. 18, the first outgoing wiring 81 and the second outgoing wiring 82 are omitted to avoid complication of the figures.

[0091] The first terminal 61 is connected to the first source electrode 312 via solder or the like. Furthermore, instead of extending in a direction perpendicular to the thickness direction DT and the one direction Da, the first terminal 61 extends from the first source electrode 312 in a direction opposite to the one direction Da. As a result, the first terminal 61 is connected to the second conductive plate 22.

[0092] The first semiconductor element 31 faces the third semiconductor element 33 in a direction perpendicular to the thickness direction DT and the one direction Da. The second semiconductor element 32 faces the first semiconductor element 31 in the one direction Da. The second semiconductor element 32 and the first semiconductor element 31 are lined up in order in the one direction Da. The second semiconductor element 32 faces the fourth semiconductor element 34 in a direction perpendicular to the thickness direction DT and the one direction Da. The fourth semiconductor element 34 faces the third semiconductor element 33 in the one direction Da. The fourth semiconductor element 34 and the third semiconductor element 33 are lined up in order in the one direction Da.

[0093] The third terminal 63 is connected to the third source electrode 332 via solder or the like. Furthermore, the third terminal 63 extends from the third source electrode 332 in a direction opposite to the one direction Da. As a result, the third terminal 63 is connected to the second conductive plate 22.

[0094] The first extension 401 is connected to the second terminal 62 in the thickness direction DT. The second terminal 62 is connected to the second semiconductor element 32 via solder or the like. Therefore, the first extension 401 is connected to the second source electrode 322 via the second terminal 62 or the like. The first extension 401 also extends in one direction Da. The first extension 401 is also connected to a power source. When the first extension 401 is projected in the thickness direction DT, the projected first extension 401 overlaps with the first conductive plate 21, the second conductive plate 22, and the first terminal 61.

[0095] The second extension 402 is connected to the second terminal 62 in the thickness direction DT. The second terminal 62 is connected to the fourth semiconductor element 34 via solder or the like. Therefore, the second extension 402 is connected to the fourth source electrode 342 via the second terminal 62 or the like. The second extension 402 also extends in one direction Da. Furthermore, the second extension 402 is connected to a power source. Furthermore, when the second extension 402 is projected in the thickness direction DT, the projected second extension 402 overlaps with the first conductive plate 21, the second conductive plate 22, and the third terminal 63. Furthermore, the second extension 402 is separated from the first extension 401 in a direction perpendicular to the thickness direction DT and the one direction Da. The opening 405 is a space formed by the first extension 401 and the second extension 402.

[0096] The O terminal 50 has a first O terminal 501 and a second O terminal 502. The first O terminal 501 and the second O terminal 502 are connected to the second conductive plate 22. The first O terminal 501 and the second O terminal 502 are arranged at intervals in a direction perpendicular to the thickness direction DT and the one direction Da. The first O terminal 501 faces the second semiconductor element 32 in the one direction Da. The first O terminal 501, the second semiconductor element 32, and the first semiconductor element 31 are arranged in order in the one direction Da. The second O terminal 502 faces the fourth semiconductor element 34 in the one direction Da. The second O terminal 502, the fourth semiconductor element 34, and the third semiconductor element 33 are arranged in order in the one direction Da.

[0097] The first gate terminal 71 is connected to the first gate electrode and extends to pass through the opening 405. The second gate terminal 72 is connected to the second gate electrode and extends to pass through the opening 405. The third gate terminal 73 is connected to the third gate electrode and extends to pass through the opening 405. The fourth gate terminal 74 is connected to the fourth gate electrode and extends to pass through the opening 405. The first gate terminal 71 and the third gate terminal 73 are disposed between the first semiconductor element 31 and the third semiconductor element 33 and face each other. The second gate terminal 72 and the fourth gate terminal 74 are disposed between the second semiconductor element 32 and the fourth semiconductor element 34 and face each other.

[0098] Furthermore, a first current path Cp1 is formed among the P terminal 30, the first conductive plate 21, the first semiconductor element 31, the first terminal 61, the second conductive plate 22, the second semiconductor element 32 and the first extension portion 401.

[0099] Here, for example, the direction of the first current path Cp1 is assumed to be from the P terminal 30 to the N terminal 40. At this time, the current path direction in the first terminal 61 is opposite to the one direction Da. Furthermore, the current path direction in the first extension portion 401 is the one direction Da. Therefore, the current path direction in the first terminal 61 is opposite to the current path direction in the first extension portion 401.

[0100] Furthermore, a second current path Cp2 is formed among the P terminal 30, the first conductive plate 21, the third semiconductor element 33, the third terminal 63, the second conductive plate 22, the fourth semiconductor element 34 and the second extension portion 402.

[0101] Here, for example, the direction of the second current path Cp2 is assumed to be from the P terminal 30 toward the N terminal 40. At this time, the current path direction in the third terminal 63 is opposite to the one direction Da. Furthermore, the current path direction in the second extension portion 402 is the one direction Da. Therefore, the current path direction in the third terminal 63 is opposite to the current path direction in the second extension portion 402.

[0102] The semiconductor device 10 of the seventh embodiment is configured as described above. The seventh embodiment also provides the same effects as the fifth embodiment.

[0103] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, in each of the above-described embodiments, it goes without saying that the elements constituting the embodiments are not necessarily essential, except in cases where they are particularly clearly stated as essential or where they are clearly considered essential in principle.

[0104] In each of the above embodiments, the first semiconductor element 31 corresponding to the first element and the second semiconductor element 32 corresponding to the second element are MOSFET elements. In contrast, the first semiconductor element 31 and the second semiconductor element 32 are not limited to being MOSFET elements and may be IGBT elements or the like. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0105] In each of the above embodiments, the first extension portion 401 of the N terminal 40 is connected to the second source electrode 322 via the sixth bonding material 46, the second terminal 62, and the fifth bonding material 45. In contrast, the second terminal 62 does not have to be formed. The first extension portion 401 and the second source electrode 322 may be connected via a bonding material such as solder without via the second terminal 62.

[0106] (In view of the present disclosure) [Point 1] A semiconductor device comprising: A substrate (15); A first conductive portion (21) formed on the substrate and having electrical conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in a direction (Da) intersecting a thickness direction (DT) of the substrate; a first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; A second conductive portion (22) formed on the substrate and having electrical conductivity; a terminal (61) connected to the second electrode and extending in a direction intersecting the thickness direction and the one direction, thereby being connected to the second conductive portion; a second element (32) having a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; a second terminal (40) having a first extension portion (401) connected to the fourth electrode and extending in a direction intersecting the thickness direction and the one direction, a second extension portion (402) connected to the first extension portion and extending from the first extension portion in the one direction, and an opening (405) formed by the first extension portion and the second extension portion; a first gate terminal (71) connected to the first gate electrode and extending through the opening; a second gate terminal (72) connected to the second gate electrode and extending through the opening; an output terminal (50) connected to the second conductive portion and outputting a current in response to turning on and off the first element and the second element; Equipped with the second element faces the first element in the one direction, the first gate terminal and the second gate terminal are disposed between the first element and the second element and face each other; The semiconductor device comprises a current path (Cp) formed among the first terminal, the first conductive portion, the first element, the terminal, the second conductive portion, the second element, and the second terminal. [Point 2] 2. The semiconductor device according to claim 1, wherein a current path direction between the terminal and the second conductive portion is opposite to a current path direction in the second extension portion. [Point 3] The semiconductor device according to aspect 2, wherein when the second extension portion is projected in the thickness direction, the projected second extension portion overlaps with the second conductive portion. [Point 4] When the second extension portion is cut in a direction perpendicular to the one direction, the second extension portion has both extension portion ends (412) facing in the thickness direction and in a direction perpendicular to the one direction, the second conductive portion has both conductive portion ends (222) facing the thickness direction and a direction perpendicular to the one direction when the second conductive portion is cut in a direction perpendicular to the one direction through both ends of the extension portion, A semiconductor device according to aspect 2 or 3, wherein when both ends of the extension portion are projected in the thickness direction, the projected both ends of the extension portion overlap both ends of the conductive portion. [Point 5] the second terminal has a third extension portion (403) that is connected to a side of the second extension portion opposite to the first extension portion in the thickness direction and in a direction intersecting the one direction and extends in the one direction, and forms the opening together with the first extension portion and the second extension portion; 5. The semiconductor device according to any one of Aspects 1 to 4, wherein a current path direction between the second extension portion and the third extension portion is opposite to a current path direction in the terminal. [Point 6] The semiconductor device according to aspect 5, wherein a current path direction in the third extension portion is opposite to a current path direction in the first terminal. [Point 7] The semiconductor device according to aspect 6, wherein when the third extension portion is projected in the thickness direction, the projected third extension portion overlaps with the first terminal. [Point 8] A semiconductor device according to any one of Aspects 5 to 7, wherein when the third extension portion is projected in the thickness direction, the projected third extension portion overlaps with the terminal. [Point 9] The semiconductor device includes: a third element (33) including a fifth electrode connected to the first conductive portion, a sixth electrode connected to the terminal, and a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode based on an applied voltage; a fourth element (34) including a seventh electrode connected to the second conductive portion, an eighth electrode connected to the first extension portion, and a fourth gate electrode that causes a current to flow between the seventh electrode and the eighth electrode based on an applied voltage; a third gate terminal (73) connected to the third gate electrode and extending through the opening; a fourth gate terminal (74) connected to the fourth gate electrode and extending through the opening; Equipped with the fourth element faces the third element in the one direction, the third gate terminal and the fourth gate terminal are disposed between the third element and the fourth element and face each other; The semiconductor device according to any one of aspects 1 to 8, wherein a current path is formed between the first terminal, the first conductive portion, the third element, the terminal, the second conductive portion, the fourth element and the second terminal. [Point 10] The semiconductor device of aspect 9, wherein the terminal is connected to the second conductive portion on the opposite side to the third element relative to the first element, and is connected to the second conductive portion on the opposite side to the first element relative to the third element. [Point 11] A semiconductor device comprising: A substrate (15); A first conductive portion (21) formed on the substrate and having electrical conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in a direction (Da) intersecting a thickness direction (DT) of the substrate; a first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; A second conductive portion (22) formed on the substrate and having electrical conductivity; a first terminal (61) connected to the second electrode and extending in a direction opposite to the one direction to be connected to the second conductive portion; a second element (32) having a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; a third element (33) including a fifth electrode connected to the first conductive portion, a sixth electrode, and a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode based on an applied voltage; a second terminal (63) connected to the sixth electrode and extending in a direction opposite to the one direction to be connected to the second conductive portion; a fourth element (34) including a seventh electrode connected to the second conductive portion, an eighth electrode, and a fourth gate electrode that causes a current to flow between the seventh electrode and the eighth electrode based on an applied voltage; a second terminal (40) having a first extension portion (401) connected to the fourth electrode and extending in the one direction, a second extension portion (402) connected to the eighth electrode and extending in the one direction, and an opening (405) formed by the first extension portion and the second extension portion; a first gate terminal (71) connected to the first gate electrode and extending through the opening; a second gate terminal (72) connected to the second gate electrode and extending through the opening; a third gate terminal (73) connected to the third gate electrode and extending through the opening; a fourth gate terminal (74) connected to the fourth gate electrode and extending through the opening; an output terminal (50, 501, 502) connected to the second conductive portion and outputting a current in response to turning on and off the first element, the second element, the third element, and the fourth element; Equipped with the first element faces the third element in a direction intersecting the thickness direction and the one direction, the second element faces the first element in the one direction and faces the fourth element in a direction intersecting the thickness direction and the one direction, the fourth element faces the third element in the one direction, the first gate terminal and the third gate terminal are disposed between the first element and the third element and face each other; the second gate terminal and the fourth gate terminal are disposed between the second element and the fourth element and face each other; a first current path (Cp1) is formed among the first terminal, the first conductive portion, the first element, the first terminal, the second conductive portion, the second element, and the second terminal; The semiconductor device further comprises a second current path (Cp2) formed among the first terminal, the first conductive portion, the third element, the second terminal, the second conductive portion, the fourth element, and the second terminal. [Explanation of symbols]

[0107] 15 Substrate 21 First conductive plate 22 Second conductive plate 30P terminal 31 First semiconductor element 32 Second semiconductor element 40N terminal 50 O terminal 71 First gate terminal 72 Second gate terminal

Claims

1. A semiconductor device comprising: A substrate (15); A first conductive portion (21) formed on the substrate and having electrical conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in a direction (Da) intersecting a thickness direction (DT) of the substrate; a first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; A second conductive portion (22) formed on the substrate and having electrical conductivity; a terminal (61) connected to the second electrode and extending in a direction intersecting the thickness direction and the one direction, thereby being connected to the second conductive portion; a second element (32) having a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; a second terminal (40) having a first extension portion (401) connected to the fourth electrode and extending in a direction intersecting the thickness direction and the one direction, a second extension portion (402) connected to the first extension portion and extending from the first extension portion in the one direction, and an opening (405) formed by the first extension portion and the second extension portion; a first gate terminal (71) connected to the first gate electrode and extending through the opening; a second gate terminal (72) connected to the second gate electrode and extending through the opening; an output terminal (50) connected to the second conductive portion and outputting a current in response to turning on and off the first element and the second element; Equipped with the second element faces the first element in the one direction, the first gate terminal and the second gate terminal are disposed between the first element and the second element and face each other; A semiconductor device, in which a current path (Cp) is formed among the first terminal, the first conductive portion, the first element, the terminal, the second conductive portion, the second element, and the second terminal.

2. The semiconductor device according to claim 1 , wherein a current path direction between the terminal and the second conductive portion is opposite to a current path direction in the second extension portion.

3. The semiconductor device according to claim 2 , wherein when the second extension portion is projected in the thickness direction, the projected second extension portion overlaps with the second conductive portion.

4. The second extension portion has both extension ends (412) facing in the thickness direction and in a direction perpendicular to the one direction when the second extension portion is cut in a direction perpendicular to the one direction, the second conductive portion has both ends (222) facing the thickness direction and a direction perpendicular to the one direction when the second conductive portion is cut in a direction perpendicular to the one direction through both ends of the extension portion, 3. The semiconductor device according to claim 2, wherein when both ends of the extension portion are projected in the thickness direction, the projected both ends of the extension portion overlap both ends of the conductive portion.

5. the second terminal has a third extension portion (403) that is connected to a side of the second extension portion opposite to the first extension portion in the thickness direction and in a direction intersecting the one direction and extends in the one direction, and forms the opening together with the first extension portion and the second extension portion; 3. The semiconductor device according to claim 1, wherein a current path direction between the second extension portion and the third extension portion is opposite to a current path direction in the terminal.

6. The semiconductor device according to claim 5 , wherein a current path direction in the third extension portion is opposite to a current path direction in the first terminal.

7. The semiconductor device according to claim 6 , wherein when the third extension portion is projected in the thickness direction, the projected third extension portion overlaps with the first terminal.

8. The semiconductor device according to claim 5 , wherein when the third extension portion is projected in the thickness direction, the projected third extension portion overlaps with the terminal.

9. The semiconductor device includes: a third element (33) having a fifth electrode connected to the first conductive portion, a sixth electrode connected to the terminal, and a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode based on an applied voltage; a fourth element (34) having a seventh electrode connected to the second conductive portion, an eighth electrode connected to the first extension portion, and a fourth gate electrode that causes a current to flow between the seventh electrode and the eighth electrode based on an applied voltage; a third gate terminal (73) connected to the third gate electrode and extending through the opening; a fourth gate terminal (74) connected to the fourth gate electrode and extending through the opening; Equipped with the fourth element faces the third element in the one direction, the third gate terminal and the fourth gate terminal are disposed between the third element and the fourth element and face each other; 3 . The semiconductor device according to claim 1 , wherein a current path is formed among the first terminal, the first conductive portion, the third element, the terminal, the second conductive portion, the fourth element, and the second terminal.

10. 10. The semiconductor device according to claim 9, wherein the terminal is connected to a side of the second conductive portion opposite the third element relative to the first element, and is connected to a side of the second conductive portion opposite the first element relative to the third element.

11. A semiconductor device comprising: A substrate (15); A first conductive portion (21) formed on the substrate and having electrical conductivity; a first terminal (30) connected to the first conductive portion and extending from the first conductive portion in a direction (Da) intersecting a thickness direction (DT) of the substrate; A first element (31) having a first electrode connected to the first conductive portion, a second electrode, and a first gate electrode that causes a current to flow between the first electrode and the second electrode based on an applied voltage; A second conductive portion (22) formed on the substrate and having electrical conductivity; a first terminal (61) connected to the second electrode and extending in a direction opposite to the one direction to be connected to the second conductive portion; a second element (32) having a third electrode connected to the second conductive portion, a fourth electrode, and a second gate electrode that causes a current to flow between the third electrode and the fourth electrode based on an applied voltage; a third element (33) having a fifth electrode connected to the first conductive portion, a sixth electrode, and a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode based on an applied voltage; a second terminal (63) connected to the sixth electrode and extending in a direction opposite to the one direction to be connected to the second conductive portion; a fourth element (34) having a seventh electrode connected to the second conductive portion, an eighth electrode, and a fourth gate electrode that causes a current to flow between the seventh electrode and the eighth electrode based on an applied voltage; a second terminal (40) having a first extension portion (401) connected to the fourth electrode and extending in the one direction, a second extension portion (402) connected to the eighth electrode and extending in the one direction, and an opening (405) formed by the first extension portion and the second extension portion; a first gate terminal (71) connected to the first gate electrode and extending through the opening; a second gate terminal (72) connected to the second gate electrode and extending through the opening; a third gate terminal (73) connected to the third gate electrode and extending through the opening; a fourth gate terminal (74) connected to the fourth gate electrode and extending through the opening; an output terminal (50, 501, 502) connected to the second conductive portion and outputting a current in response to turning on and off the first element, the second element, the third element, and the fourth element; Equipped with the first element faces the third element in a direction intersecting the thickness direction and the one direction, the second element faces the first element in the one direction and faces the fourth element in a direction intersecting the thickness direction and the one direction, the fourth element faces the third element in the one direction, the first gate terminal and the third gate terminal are disposed between the first element and the third element and face each other; the second gate terminal and the fourth gate terminal are disposed between the second element and the fourth element and face each other; a first current path (Cp1) is formed among the first terminal, the first conductive portion, the first element, the first terminal, the second conductive portion, the second element, and the second terminal; A semiconductor device in which a second current path (Cp2) is formed among the first terminal, the first conductive portion, the third element, the second terminal, the second conductive portion, the fourth element, and the second terminal.

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