Semiconductor integrated circuit having MOS switch

Abstract

To reduce influence of clock feed-through of an MOS switch.SOLUTION: An MOS switch 100 includes: a first main transistor MM1 of a first polarity; and a first dummy transistor MD1 of the first polarity whose both ends are connected to a first end e1 of the first main transistor MM1. A switch control circuit 110 supplies a first voltage V1 according to a control signal CNT to a gate of the first main transistor MM1, and supplies a second voltage V2 having an opposite phase to the first voltage V1 to a gate of the first dummy transistor MD1. The switch control circuit 110 is configured capable of adjusting slew rates of the first voltage V1 and the second voltage V2.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor integrated circuit including a metal oxide semiconductor field (MOS) switch. [Background technology]

[0002] A successive approximation register (SAR) is used as a medium to high resolution (e.g. 8 bits or more) A / D converter (ADC). A SAR-ADC samples and holds the input voltage and compares it with a first threshold voltage. Depending on the comparison result, it then determines a second threshold voltage and performs another comparison. By repeating this operation, the analog voltage is converted into a digital signal by a binary search. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-96375 A Summary of the Invention [Problem to be solved by the invention]

[0004] The SAR-ADC is equipped with a sample-and-hold circuit and a capacitive D / A converter (CDAC), which are composed of a combination of capacitors and switches (switched capacitor circuit). The switches are composed of MOS switches having MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). MOS switches include CMOS (Complementary Metal Oxide Semiconductor) switches (also called transfer gates), NMOS (N-channel Metal Oxide Semiconductor) switches, and PMOS (P-channel Metal Oxide Semiconductor) switches.

[0005] When a MOS switch is on, the voltages at both ends are equal. A MOSFET has parasitic capacitance, and when it is turned off, a charge transfer occurs due to clock feedthrough or charge injection. As a result, the terminal voltage of the MOS switch changes when the MOSFET is turned off. The effect of clock feedthrough is noticeable when one end of the MOS switch is connected to a high impedance node.

[0006] In order to reduce the effect of clock feedthrough, a method is known in which a dummy switch is connected to a MOS switch to cancel the error charge. However, even if the conventional cancellation method is applied, it is difficult to reduce the error charge to zero. In addition, since the characteristics of the circuit elements have power supply voltage dependence and temperature dependence, there is a limit to how precisely the offset can be canceled.

[0007] The present disclosure has been made in light of the above circumstances, and it is an exemplary purpose of an embodiment of the present disclosure to provide a semiconductor integrated circuit in which the influence of clock feedthrough of a MOS switch is reduced. [Means for solving the problem]

[0008] A semiconductor integrated circuit according to an embodiment of the present disclosure includes a MOS (Metal Oxide Semiconductor) switch, the MOS switch including a first main MOS transistor of a first polarity, a first dummy MOS transistor of a first polarity having both ends connected to a first end of the first main MOS transistor, and a switch control circuit configured to supply a first voltage in response to a control signal to a gate of the first main MOS transistor, supply a second voltage in phase opposite to the first voltage to a gate of the first dummy MOS transistor, and adjust the slew rates of the first voltage and the second voltage.

[0009] Any combination of the above components or conversion of the present disclosure between methods, devices, etc. are also effective as aspects of the present invention. Effect of the Invention

[0010] According to an embodiment of the present disclosure, the effect of clock feedthrough in a MOS switch can be reduced. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a comparative technique. [Diagram 2] FIG. 2 is a diagram for explaining the operation of the NMOS switch of FIG. [Diagram 3] FIG. 3 is a circuit diagram of a MOS switch according to the embodiment. [Figure 4] FIG. 4 is a diagram illustrating the slew rates of the first voltage and the second voltage. [Diagram 5] FIG. 5 is an operational waveform diagram of the MOS switch of FIG. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of the switch control circuit. [Figure 7] FIG. 7 is a circuit diagram of a MOS switch according to the first modification. [Figure 8] FIG. 8 is a circuit diagram of a MOS switch according to the second modification. [Figure 9]FIG. 9 is a circuit diagram of a MOS switch according to the third modification. [Figure 10] FIG. 10 is a circuit diagram of a MOS switch according to the fourth modification. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of the switch control circuit. [Figure 12] FIG. 12 is a circuit diagram of a MOS switch according to the fifth modification. [Figure 13] FIG. 13 is a circuit diagram of a semiconductor integrated circuit including a chopper comparator circuit. [Figure 14] FIG. 14 is a circuit diagram of a semiconductor integrated circuit including a sample-and-hold circuit. [Figure 15] FIG. 15 is a circuit diagram of a semiconductor integrated circuit including a switched capacitor circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0013] A semiconductor integrated circuit according to one embodiment includes a MOS (Metal Oxide Semiconductor) switch including a first main MOS transistor of a first polarity, a first dummy MOS transistor of a first polarity having both ends connected to a first end of the first main MOS transistor, and a switch control circuit configured to supply a first voltage in response to a control signal to a gate of the first main MOS transistor, supply a second voltage in phase opposite to the first voltage to a gate of the first dummy MOS transistor, and adjust slew rates of the first voltage and the second voltage.

[0014] According to this configuration, by optimizing the slew rate (slope) of the gate voltage applied to each of the main MOS transistor and the first dummy transistor, it is possible to reduce the influence of charge transfer due to clock feedthrough.

[0015] In one embodiment, the MOS switch may further include a second dummy MOS transistor of the first polarity, both ends of which are connected to the second end of the first main MOS transistor, and the switch control circuit may supply a second voltage to a gate of the second dummy MOS transistor.

[0016] In one embodiment, the MOS switch may further include a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor, and a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor. The switch control circuit may supply the second voltage to a gate of the second main MOS transistor and the first voltage to a gate of the third dummy MOS transistor.

[0017] In one embodiment, the MOS switch may further include a second dummy MOS transistor of a second polarity, both ends of which are connected to the second end of the first main MOS transistor, and a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor. The switch control circuit may supply the second voltage to a gate of the second dummy MOS transistor and the first voltage to a gate of the fourth dummy MOS transistor.

[0018] In one embodiment, the MOS switch may further include a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor, and a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor. The switch control circuit may be configured to supply a third voltage in phase with the second voltage to a gate of the second main MOS transistor, and to supply a fourth voltage in phase with the first voltage to a gate of the third dummy MOS transistor, and to be capable of adjusting slew rates of the third voltage and the fourth voltage.

[0019] In one embodiment, the MOS switch may further include a second dummy MOS transistor of a second polarity, both ends of which are connected to the second end of the first main MOS transistor, and a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor. The switch control circuit may supply the second voltage to a gate of the second dummy MOS transistor and the fourth voltage to a gate of the fourth dummy MOS transistor.

[0020] In one embodiment, the switch control circuit may include a logic circuit that generates complementary first and second control signals in response to a control signal, a first driver that generates a first voltage based on the first control signal, and a second driver that generates a second voltage based on the second control signal. The capabilities of each of the first driver and the second driver may be configured to be controllable.

[0021] In one embodiment, the first driver may include a plurality of first inverter elements connected in parallel and each of which may be individually enabled and disabled, and the second driver may include a plurality of second inverter elements connected in parallel and each of which may be individually enabled and disabled.

[0022] In one embodiment, the logic circuit may transition the first control signal and the second control signal substantially simultaneously.

[0023] In one embodiment, the logic circuit may include an input node that receives a control signal, a first output node at which a first control signal is generated, a second output node at which a second control signal is generated, a first inverter having an input connected to the input node and an output connected to the first output node, a second inverter having an input connected to the input node, a third inverter having an input connected to the output of the second inverter and an output connected to the second output node, a fourth inverter having an input connected to the second output node and an output connected to the first output node, and a fifth inverter having an input connected to the first output node and an output connected to the second output node.

[0024] In one embodiment, the semiconductor integrated circuit may include a chopper comparator circuit. The chopper comparator circuit may include an inverter and a switch connected between an input and an output of the inverter. The switch may be any of the MOS switches described above.

[0025] In one embodiment, the semiconductor integrated circuit may include a switched capacitor circuit. The switched capacitor circuit may include a capacitor and a switch connected to the capacitor. The switch may be any of the MOS switches described above.

[0026] In one embodiment, the semiconductor integrated circuit may include a sample-and-hold circuit. The sample-and-hold circuit may include a capacitor and a switch connected to the capacitor. The switch may be any of the MOS switches described above.

[0027] (Embodiment) In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0028] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0029] First, the effects of clock feedthrough and charge injection in MOS switches are explained.

[0030] 1 is a circuit diagram of a semiconductor integrated circuit 10 according to a comparative technique. The semiconductor integrated circuit 10 includes an NMOS switch 12, a capacitor C1, and a driver circuit 14. A constant voltage V A The first terminal is connected to the capacitor C1 and serves as a high impedance node. The driver circuit 14 supplies the gate of the NMOS switch 12 with a gate voltage Vg in accordance with a control signal CNT.

[0031] 2 is a diagram for explaining the operation of the NMOS switch 12 in FIG. 1. Before time t0, the control signal CNT is at a low level, the gate voltage Vg of the NMOS switch 12 is 0 V, and the NMOS switch 12 is in an off state. When the control signal CNT transitions to a high level at time t0, the gate voltage Vg of the NMOS switch 12 rises to V DD , and the NMOS switch 12 is turned on. When the NMOS switch 12 is turned on, the voltage V B is the voltage at the first terminal VA is equal to

[0032] When the control signal CNT transitions to a low level at time t1, the gate voltage Vg of the NMOS switch 12 drops to 0 V, and the NMOS switch 12 turns off. In an ideal switch, after turning off, the voltage V B is the voltage V A However, in the actual NMOS switch 12, a charge transfer occurs due to clock feedthrough, and the voltage V B is the voltage V A This voltage error ΔV becomes a problem in various circuits that use MOS switches.

[0033] These are the problems that occur with MOS switches. Below, we will explain the technology that can solve these problems.

[0034] 3 is a circuit diagram of a MOS switch 100 according to an embodiment. The MOS switch 100 includes a first main transistor MM1, a first dummy transistor MD1, and a switch control circuit 110. The MOS switch 100 is formed in a semiconductor integrated circuit. Nodes 102 and 104 are the input and output of the MOS switch 100.

[0035] The first main transistor MM1 is a MOSFET of a first polarity. In this embodiment, the first polarity is an N-channel, and the MOS switch 100 is an NMOS switch. A first end e1 of the first main transistor MM1 is connected to a node 104, and a second end e2 of the first main transistor MM1 is connected to a node 102.

[0036] The first dummy transistor MD1 is a MOSFET of the same first polarity as the first main transistor MM1, and both ends thereof are connected to the first terminal e1 of the first main transistor MM1.

[0037] The switch control circuit 110 supplies a first voltage V1 in response to a control signal CNT to the gate of the first main transistor MM1, and supplies a second voltage V2 in opposite phase to the first voltage V1 to the gate of the first dummy transistor MD1. The switch control circuit 110 is configured to be able to adjust the slew rates of the first voltage V1 and the second voltage V2.

[0038] The switch control circuit 110 can include a first driver 112 that outputs a first voltage V1, and a first driver 114 that outputs a second voltage V2. Each of the first driver 112 and the second driver 114 is configured to have a variable current supply capability (output impedance).

[0039] 4 is a diagram illustrating the slew rate of the first voltage V1 and the second voltage V2. When the current supply capacity of the first driver 112 is increased, the slew rate of the first voltage V1 increases, and conversely, when the current supply capacity of the first driver 112 is decreased, the slew rate of the first voltage V1 decreases. The same is true for the second voltage V2.

[0040] The above is the configuration of the MOS switch 100. Next, the operation will be described.

[0041] 5 is an operational waveform diagram of the MOS switch 100 of FIG. 3. As in FIG. 1, a constant voltage V A is applied and node 104 is a high impedance node.

[0042] Before time t0, the control signal CNT is at a low level, the first voltage V1, which is the gate voltage of the first main transistor MM1, is 0 V, and the first main transistor MM1 is in an off state. The second voltage V2, which is the gate voltage of the first dummy transistor MD1, is equal to or lower than the power supply voltage V DD It is.

[0043] When the control signal CNT transitions to a high level at time t0, the first voltage V1 is V DD, and the first main transistor MM1 is turned on. Conversely, the second voltage V2 supplied to the gate of the first dummy transistor MD1 transitions to 0 V. By turning on the first main transistor MM1, the voltage V B is the voltage V at node 102 A is equal to

[0044] When the control signal CNT transitions to a low level at time t1, the first voltage V1 drops to 0 V, and the first main transistor MM1 is turned off. At this time, the charge of the node 104 moves to the gate of the first main transistor MM1 via the parasitic capacitance of the first main transistor MM1.

[0045] On the other hand, the second voltage V2 supplied to the gate of the first dummy transistor MD1 is changed from 0 V to V DD Therefore, in the first dummy transistor MD1, charge moves from the gate to the node 104.

[0046] Here, the amount of charge transfer via the parasitic capacitance in the MOSFET depends on the slew rate of the gate voltage. Specifically, if the slew rate of the gate voltage is large, the amount of charge transfer is large, and if the slew rate of the gate voltage is small, the amount of charge transfer is small. As described above, in the embodiment, the slew rates of the first voltage V1 and the second voltage V2 are adjustable. Therefore, by optimizing the slew rates of the first voltage V1 and the second voltage V2 so that the amount of charge transfer generated in the first main transistor MM1 and the amount of charge transfer generated in the first dummy transistor MD1 are equal, the voltage error ΔV of the node 104 can be made close to 0.

[0047] Here, the first main transistor MM1 and the first dummy transistor MD1 have been described as N-channel MOSFETs, but the same technology can also be applied to PMOS switches in which they are P-channel MOSFETs.

[0048] 6 is a circuit diagram showing a configuration example of the switch control circuit 110. The switch control circuit 110 includes a first driver 112, a second driver 114, and a logic circuit 116. The logic circuit 116 generates a first control signal CNT1 and a second control signal CNT2 that are complementary to each other in response to a control signal CNT. The first driver 112 generates a first voltage V1 in response to the first control signal CNT1, and the second driver 114 generates a second voltage V2 in response to the second control signal CNT2.

[0049] The first driver 112 includes a plurality of first inverter elements 113 connected in parallel. The plurality of inverter elements 113 can be individually switched between enabled and disabled. In the configuration example of Fig. 6, a switch 115 is connected to the output of each inverter 113, and when the switch 115 is turned on, the corresponding inverter 113 is enabled, and when the switch 115 is turned off, the corresponding inverter 113 is disabled.

[0050] For example, the sizes of the inverter elements 113 may be binary weighted or equal. The current supply capability of the first driver 112, and therefore the slew rate of the first voltage V1, is controlled by the number of switches 115 that are on.

[0051] Similarly, the second driver 114 is configured similarly to the first driver 112, and includes a plurality of second inverter elements 117 connected in parallel, and a plurality of switches 119. The current supply capability of the second driver 114, i.e., the slew rate of the second voltage V2, is controlled by the number of switches 119 that are turned on.

[0052] Most simply, the logic circuit 116 can be configured with only one inverter INV1. In that case, however, the first control signal CNT1 will lag behind the second control signal CNT2.

[0053] 6 is configured so that the first control signal CNT1 and the second control signal CNT2 transition substantially simultaneously, that is, so that the delay amounts are equal. The logic circuit 116 includes a first inverter INV1 to a fifth inverter INV5.

[0054] The input of the first inverter INV1 is connected to the input node IN, and its output is connected to the first output node OUT1. The input of the second inverter INV2 is connected to the input node IN. The input of the third inverter INV3 is connected to the output of the second inverter INV2, and its output is connected to the second output node OUT2. The input of the fourth inverter INV4 is connected to the second output node OUT2, and its output is connected to the first output node OUT1. The input of the fifth inverter INV5 is connected to the first output node OUT1, and its output is connected to the second output node OUT2.

[0055] According to this configuration, it is possible to make the delay amounts of the first control signal CNT1 and the second control signal CNT2 consistent with respect to the control signal CNT.

[0056] Next, a modification of the MOS switch 100 will be described.

[0057] (Variation 1) Fig. 7 is a circuit diagram of a MOS switch 100A according to Modification 1. The MOS switch 100A further includes a second dummy transistor MD2 in addition to the MOS switch 100 of Fig. 3. The second dummy transistor MD2 is a MOSFET of a first polarity (N-channel), and both ends thereof are connected to the second end e2 of the first main transistor MM1, i.e., the node 102.

[0058] The switch control circuit 110A supplies the second voltage V2 to the gate of the second dummy MOS transistor MD2. With this configuration, when the node 102 is a high impedance node, fluctuations in the voltage of the node 102 can be suppressed.

[0059] (Variation 2) 8 is a circuit diagram of a MOS switch 100B according to Modification 2. The MOS switch 100B is a CMOS switch, and includes a second main transistor MM2 and a third dummy transistor MD3 in addition to the components of the MOS switch 100 in FIG.

[0060] The second main transistor MM2 is a P-channel MOSFET of a second polarity, and is connected in parallel with the first main transistor MM1.

[0061] The third dummy transistor MD3 is a P-channel MOSFET of the second polarity, and is connected in parallel to the first dummy transistor MD1. Similar to the first dummy transistor MD1, both ends of the third dummy transistor MD3 are also connected.

[0062] The switch control circuit 110B supplies the second voltage V2 to the gate of the second main transistor MM2, and supplies the first voltage V1 to the gate of the third dummy transistor MD3.

[0063] (Variation 3) 9 is a circuit diagram of a MOS switch 100C according to Modification 3. The MOS switch 100C further includes a second dummy transistor MD2 and a fourth dummy transistor MD4 in addition to the components of the MOS switch 100B in FIG.

[0064] The switch control circuit 110C supplies a second voltage V2 to the gate of the second dummy transistor MD2, and supplies a first voltage V1 to the gate of the fourth dummy transistor MD4.

[0065] (Variation 4) Fig. 10 is a circuit diagram of a MOS switch 100D according to Modification 4. The MOS switch 100D includes a first main transistor MM1, a second main transistor MM2, a first dummy transistor MD1, and a third dummy transistor MD3, similar to the MOS switch 100B in Fig. 8, but is different in the configuration of a switch control circuit 110D.

[0066] The switch control circuit 110D includes a third driver 120 and a fourth driver 122 in addition to the first driver 112 and the second driver 114. The switch control circuit 110D supplies a third voltage V3 in phase with the second voltage V2 to the gate of the second main transistor MM2, and supplies a fourth voltage V4 in phase with the first voltage V1 to the gate of the third dummy transistor MD3. The switch control circuit 110D is configured to be able to adjust the slew rates of the third voltage V3 and the fourth voltage V4.

[0067] Fig. 11 is a circuit diagram showing a configuration example of a switch control circuit 110D. The switch control circuit 110D further includes a third driver 120 and a fourth driver 122 in addition to the switch control circuit 110 of Fig. 6. The third driver 120 and the fourth driver 122 can be configured in the same manner as the first driver 112 and the second driver 114.

[0068] (Variation 5) Fig. 12 is a circuit diagram of a MOS switch 100E according to Modification 5. The MOS switch 100E has a configuration similar to that of the MOS switch 100D in Fig. 10, with the addition of a second dummy transistor MD2 and a fourth dummy transistor MD4.

[0069] The switch control circuit 110E supplies a second voltage V2 to the gate of the second dummy transistor MD2, and supplies a fourth voltage V4 to the gate of the fourth dummy transistor MD4.

[0070] (Application) Next, applications of the MOS switch (including modifications) will be described.

[0071] 13 is a circuit diagram of a semiconductor integrated circuit 300a including a chopper comparator circuit 200. The chopper comparator circuit 200 includes an inverter 202 and a switch 204. The switch 204 is connected between the input node and the output node of the inverter 202. A capacitor 302 is connected to the upstream of the chopper comparator circuit 200. The configuration of the MOS switch 100 described above can be adopted for the switch 204.

[0072] 14 is a circuit diagram of a semiconductor integrated circuit 300b including a sample-and-hold circuit 210. The sample-and-hold circuit 210 includes a capacitor 212 and a switch 214. The configuration of the MOS switch 100 described above can be adopted for the switch 214.

[0073] 15 is a circuit diagram of a semiconductor integrated circuit 300c including a switched capacitor circuit 220. In this example, the switched capacitor circuit 220 is a capacitive D / A converter. The configuration of the MOS switch 100 described above can be adopted for the switch SW.

[0074] The chopper comparator circuit, the sample-and-hold circuit, and the switched capacitor circuit (capacitive D / A converter) shown in Fig. 13 to Fig. 15 are components of a successive approximation register A / D converter (SAR-ADC). By using the above-mentioned MOS switch 100 in a SAR-ADC, the error voltage due to clock feedthrough can be reduced, thereby improving the conversion accuracy.

[0075] (Additional Note) The present specification discloses the following techniques:

[0076] (Item 1) Equipped with MOS (Metal Oxide Semiconductor) switches, The MOS switch is a first main MOS transistor of a first polarity; a first dummy MOS transistor of the first polarity, both ends of which are connected to a first end of the first main MOS transistor; a switch control circuit configured to supply a first voltage corresponding to a control signal to a gate of the first main MOS transistor and a second voltage having a phase opposite to that of the first voltage to a gate of the first dummy MOS transistor, and to be capable of adjusting a slew rate of the first voltage and the second voltage; A semiconductor integrated circuit comprising:

[0077] (Item 2) The MOS switch is a second dummy MOS transistor of the first polarity, both ends of which are connected to a second end of the first main MOS transistor; 2. The semiconductor integrated circuit according to item 1, wherein the switch control circuit supplies the second voltage to a gate of the second dummy MOS transistor.

[0078] (Item 3) The MOS switch is a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor; a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor; Further equipped with 2. The semiconductor integrated circuit according to item 1, wherein the switch control circuit supplies the second voltage to a gate of the second main MOS transistor and supplies the first voltage to a gate of the third dummy MOS transistor.

[0079] (Item 4) The MOS switch is a second dummy MOS transistor of the second polarity, both ends of which are connected to a second end of the first main MOS transistor; a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor; Further equipped with 4. The semiconductor integrated circuit according to item 3, wherein the switch control circuit supplies the second voltage to a gate of the second dummy MOS transistor and supplies the first voltage to a gate of the fourth dummy MOS transistor.

[0080] (Item 5) The MOS switch is a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor; a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor; Further equipped with The switch control circuit includes: 2. The semiconductor integrated circuit according to item 1, wherein a third voltage in phase with the second voltage is supplied to a gate of the second main MOS transistor, a fourth voltage in phase with the first voltage is supplied to a gate of the third dummy MOS transistor, and a slew rate of the third voltage and the fourth voltage is adjustable.

[0081] (Item 6) The MOS switch is a second dummy MOS transistor of the second polarity, both ends of which are connected to a second end of the first main MOS transistor; a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor; Further equipped with 6. The semiconductor integrated circuit according to item 5, wherein the switch control circuit supplies the second voltage to a gate of the second dummy MOS transistor and supplies the fourth voltage to a gate of the fourth dummy MOS transistor.

[0082] (Item 7) The switch control circuit includes: a logic circuit that generates complementary first and second control signals in response to the control signal; a first driver that generates the first voltage based on the first control signal; a second driver that generates the second voltage based on the second control signal; Including, 7. The semiconductor integrated circuit according to any one of items 1 to 6, wherein capabilities of the first driver and the second driver are configured to be controllable.

[0083] (Item 8) the first driver includes a plurality of first inverter elements connected in parallel and each of which can be individually enabled and disabled; 8. The semiconductor integrated circuit of item 7, wherein the second driver includes a plurality of second inverter elements connected in parallel and capable of being individually enabled and disabled.

[0084] (Item 9) 9. The semiconductor integrated circuit according to item 7 or 8, wherein the logic circuit transitions the first control signal and the second control signal substantially simultaneously.

[0085] (Item 10) The logic circuit includes: an input node for receiving the control signal; a first output node at which the first control signal is generated; a second output node at which the second control signal is generated; a first inverter having an input connected to the input node and an output connected to the first output node; a second inverter having an input connected to the input node; a third inverter having an input connected to the output of the second inverter and an output connected to the second output node; a fourth inverter having an input connected to the second output node and an output connected to the first output node; a fifth inverter having an input connected to the first output node and an output connected to the second output node; 10. The semiconductor integrated circuit according to item 8 or 9, comprising:

[0086] (Item 11) A chopper comparator circuit is provided. The chopper comparator circuit includes: An inverter; a switch connected between the input and output of the inverter; Equipped with 11. The semiconductor integrated circuit according to any one of items 1 to 10, wherein the switch is a MOS switch.

[0087] (Item 12) A switched capacitor circuit is provided. The switched capacitor circuit comprises: A capacitor; a switch connected to the capacitor; Equipped with 11. The semiconductor integrated circuit according to any one of items 1 to 10, wherein the switch is a MOS switch.

[0088] (Item 13) A sample and hold circuit is provided, The sample and hold circuit comprises: A capacitor; a switch connected to the capacitor; Equipped with 11. The semiconductor integrated circuit according to any one of items 1 to 10, wherein the switch is a MOS switch. [Explanation of symbols]

[0089] 100 MOS Switch MM1 First main transistor MM2 Second main transistor MD1 First dummy transistor MD2 Second dummy transistor MD3 Third dummy transistor MD4 4th dummy transistor V1 First voltage V2 Second voltage V3 Third voltage V4 4th voltage 110 Switch control circuit 112 1st Driver 114 2nd Driver 116 Logic Circuits

Claims

1. Equipped with a MOS (Metal Oxide Semiconductor) switch, The MOS switch is a first main MOS transistor of a first polarity; a first dummy MOS transistor of the first polarity, both ends of which are connected to a first end of the first main MOS transistor; a switch control circuit configured to supply a first voltage corresponding to a control signal to a gate of the first main MOS transistor and to supply a second voltage having a phase opposite to that of the first voltage to a gate of the first dummy MOS transistor, and to be capable of adjusting a slew rate of the first voltage and the second voltage; A semiconductor integrated circuit comprising:

2. The MOS switch is a second dummy MOS transistor of the first polarity, both ends of which are connected to a second end of the first main MOS transistor; 2. The semiconductor integrated circuit according to claim 1, wherein the switch control circuit supplies the second voltage to a gate of the second dummy MOS transistor.

3. The MOS switch is a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor; a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor; Further equipped with 2. The semiconductor integrated circuit according to claim 1, wherein said switch control circuit supplies said second voltage to a gate of said second main MOS transistor and supplies said first voltage to a gate of said third dummy MOS transistor.

4. The MOS switch is a second dummy MOS transistor of the second polarity, both ends of which are connected to a second end of the first main MOS transistor; a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor; Further equipped with 4. The semiconductor integrated circuit according to claim 3, wherein the switch control circuit supplies the second voltage to a gate of the second dummy MOS transistor and supplies the first voltage to a gate of the fourth dummy MOS transistor.

5. The MOS switch is a second main MOS transistor of a second polarity connected in parallel with the first main MOS transistor; a third dummy MOS transistor of the second polarity connected in parallel with the first dummy MOS transistor; Further equipped with The switch control circuit includes:

2. The semiconductor integrated circuit according to claim 1, configured to supply a third voltage having a phase in phase with the second voltage to a gate of the second main MOS transistor, supply a fourth voltage having a phase in phase with the first voltage to a gate of the third dummy MOS transistor, and adjust slew rates of the third voltage and the fourth voltage.

6. The MOS switch is a second dummy MOS transistor of the second polarity, both ends of which are connected to a second end of the first main MOS transistor; a fourth dummy MOS transistor of the second polarity connected in parallel with the second dummy MOS transistor; Further equipped with 6. The semiconductor integrated circuit according to claim 5, wherein said switch control circuit supplies said second voltage to a gate of said second dummy MOS transistor and supplies said fourth voltage to a gate of said fourth dummy MOS transistor.

7. The switch control circuit includes: a logic circuit that generates complementary first and second control signals in response to the control signal; a first driver that generates the first voltage based on the first control signal; a second driver that generates the second voltage based on the second control signal; Including, 7. The semiconductor integrated circuit according to claim 1, wherein capabilities of the first driver and the second driver are configured to be controllable.

8. The first driver includes a plurality of first inverter elements connected in parallel and each of which can be individually enabled and disabled; The semiconductor integrated circuit according to claim 7 , wherein the second driver includes a plurality of second inverter elements connected in parallel and capable of being individually enabled and disabled.

9. The semiconductor integrated circuit according to claim 7 , wherein the logic circuit causes the first control signal and the second control signal to transition substantially simultaneously.

10. The logic circuit includes: an input node for receiving the control signal; a first output node at which the first control signal is generated; a second output node at which the second control signal is generated; a first inverter having an input connected to the input node and an output connected to the first output node; a second inverter having an input connected to the input node; a third inverter having an input connected to the output of the second inverter and an output connected to the second output node; a fourth inverter having an input connected to the second output node and an output connected to the first output node; a fifth inverter having an input connected to the first output node and an output connected to the second output node; The semiconductor integrated circuit according to claim 8 .

11. A chopper comparator circuit is provided. The chopper comparator circuit includes: An inverter; a switch connected between the input and output of the inverter; Equipped with 7. The semiconductor integrated circuit according to claim 1, wherein said switch is a MOS switch.

12. A switched capacitor circuit is provided. The switched capacitor circuit comprises: A capacitor; a switch connected to the capacitor; Equipped with 7. The semiconductor integrated circuit according to claim 1, wherein said switch is a MOS switch.

13. A sample and hold circuit is provided, The sample and hold circuit comprises: A capacitor; a switch connected to the capacitor; Equipped with 7. The semiconductor integrated circuit according to claim 1, wherein said switch is a MOS switch.

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