Semiconductor device structure and method for fabricating same

Abstract

To provide a semiconductor device arrangement structure.SOLUTION: This structure includes: a substrate; an adhesive structure; and a first semiconductor device. The substrate includes an upper front surface, and the adhesive structure is positioned on the upper front surface and includes a first concave region. The first semiconductor device contains a lower front surface facing towards an adhesive layer and a conductive bump positioned in the first concave region under the lower front surface. The conductive bump contains a first part and a second part. The lower front surface is not in contact with the adhesive structure. The first part is directly in contact with the first concave region, and the second part is not directly in contact with the first concave region.SELECTED DRAWING: Figure 11B

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device array structure, and more particularly to a light emitting diode array structure having conductive bumps and a method for manufacturing the same. [Background technology]

[0002] Light-emitting diode (LED) crystallites (chips) are semiconductor elements that have characteristics such as low energy consumption, long life, small size, fast response speed, and stable light output, and are widely used in the fields of lighting and displays.

[0003] With the continuous evolution of science and technology, the brightness of LED chips is constantly improving, and the dimensions of LED chips are gradually shrinking, for example, to less than 100μm, less than 50μm, or even less than 30μm, so that the applications of LED chips are no longer limited to general lighting or backlighting light sources for LCD screens. LED chips can directly become the pixels of LED displays, which may become the trend of next-generation displays. Summary of the Invention [Problem to be solved by the invention]

[0004] An LED display is made up of millions, or even tens of millions, of LED chips. In order to accurately position such a huge number of LED chips on a display panel, a high-speed and reliable chip handling technology is required. [Means for solving the problem]

[0005] In an embodiment of the present disclosure, a semiconductor device array structure is provided, the structure includes a substrate, an adhesive structure, and a first semiconductor device, the substrate having an upper surface, the adhesive structure located on the upper surface and having a first recessed region, the first semiconductor device including a lower surface facing the adhesive layer and a conductive bump located in the first recessed region below the lower surface, the conductive bump including a first portion and a second portion, the lower surface not in contact with the adhesive structure, the first portion in direct contact with the first recessed region, and the second portion not in direct contact with the first recessed region.

[0006] In another embodiment of the present disclosure, a method for fabricating a semiconductor element array structure is provided, comprising providing a semiconductor element array structure, the semiconductor element array structure including a substrate, an adhesive structure, a first semiconductor element, and a second semiconductor element, the substrate having an upper surface, the adhesive structure being located on the upper surface, the first semiconductor element and the second semiconductor element being disposed on the adhesive structure, the first semiconductor element being capable of reducing a contact area between the first semiconductor element and the adhesive structure, a transfer structure being provided for simultaneously contacting the first semiconductor element and the second semiconductor element, and a moving and transferring structure being provided for transporting the first semiconductor element to the transfer structure. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 2 is a top view of a semiconductor element array structure according to an embodiment of the present disclosure. [Figure 1B] 1B is a cross-sectional view taken along line AA' in FIG. 1A. [Figure 1C] FIG. 13 is a top view of a semiconductor element array structure according to another embodiment of the present disclosure. [Figure 1D] 1D is a cross-sectional view taken along line AA' in FIG. 1C. [Figure 1E] FIG. 2 is a cross-sectional view of a semiconductor element array structure in another embodiment of the present disclosure. [Figure 2A] FIG. 2 is a three-dimensional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2B] 2B is a cross-sectional view taken along line BB' in FIG. 2A. [Figure 2C] FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 2D] FIG. 2 is a three-dimensional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 2E] FIG. 2E is a cross-sectional view taken along line BB' in FIG. 2D. [Figure 3A] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present disclosure. [Figure 3B] 3B is a cross-sectional view taken along line CC' in FIG. 3A. [Figure 3C] 3B is a cross-sectional view taken along line DD' in FIG. 3A. [Figure 4A] FIG. 2 is a cross-sectional view of a semiconductor element array structure in another embodiment of the present disclosure. [Figure 4B] 4B is a cross-sectional view of the semiconductor element array structure of FIG. 4A with one semiconductor element removed. [Figure 4C] FIG. 4B is a top view of the semiconductor element array structure of FIG. 4A with one semiconductor element removed. [Figure 4D] FIG. 2 is a cross-sectional view of a semiconductor element array structure in another embodiment of the present disclosure. [Figure 4E] FIG. 2 is a cross-sectional view of a semiconductor element array structure in another embodiment of the present disclosure. [Figure 5A] 1 is a flow chart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5B] 1 is a flow chart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5C] 1 is a flow chart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5D] 1 is a flow chart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 6A] 13 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 6B] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 6C] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 7A] 1 is a flow diagram for fabricating a semiconductor device in an embodiment of the present disclosure. [Figure 7B]1 is a flow diagram for fabricating a semiconductor device in an embodiment of the present disclosure. [Figure 7C] 1 is a flow diagram for fabricating a semiconductor device in an embodiment of the present disclosure. [Figure 7D] 1 is a flow diagram for fabricating a semiconductor device in an embodiment of the present disclosure. [Figure 8A] 4 is a flow diagram for fabricating a semiconductor device in another embodiment of the present disclosure. [Figure 8B] 4 is a flow diagram for fabricating a semiconductor device in another embodiment of the present disclosure. [Figure 8C] 4 is a flow diagram for fabricating a semiconductor device in another embodiment of the present disclosure. [Figure 8D] 4 is a flow diagram for fabricating a semiconductor device in another embodiment of the present disclosure. [Figure 9A] FIG. 2 is a three-dimensional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 9B] 9B is a cross-sectional view taken along line BB' in FIG. 9A. [Figure 10A] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 10B] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 10C] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 10D] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 10E] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 11A] 10D is an enlarged view of the semiconductor unit before region P in FIG. 10C is irradiated with laser energy. [Figure 11B] 10D is an enlarged view of the semiconductor element after region P in FIG. 10C has been irradiated with laser energy. [Figure 12A] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 12B] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 12C] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 12D] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 13A] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 13B] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 13C] 11 is a flow chart of transferring a semiconductor device in another embodiment of the present disclosure. [Figure 14] FIG. 2 is a cross-sectional view of a semiconductor element array structure in another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following examples, the concept of the present disclosure is described with the accompanying drawings, and the same reference numerals are used for similar or identical parts in the drawings or descriptions, and the shape, thickness or height of the elements in the drawings can be enlarged or reduced within a reasonable range. Each example listed in this disclosure is used only to explain the present disclosure and is not intended to limit the scope of the present disclosure. Any obvious and easily known modifications or changes made to the present disclosure shall not deviate from the spirit and scope of the present disclosure.

[0009] 1A is a top view of a semiconductor device array 1000 according to an embodiment of the present disclosure. The semiconductor device array 1000 includes a plurality of semiconductor devices 1 arranged in an array on a substrate 10. The semiconductor devices 1 can be light-emitting diodes (LEDs), laser diodes (LDs), or transistors. The semiconductor device array 1000 can be composed of a single type of semiconductor device 1 or different types of semiconductor devices 1. The substrate 10 can be used as a growth substrate for epitaxially growing the semiconductor devices 1, or as a temporary carrier (non-growth substrate) for mounting the semiconductor devices 1. The material of the substrate 10 includes, but is not limited to, germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, thermal release tape, UV release tape, chemical release tape, heat-resistant tape, blue tape, or dynamic release layer (DRL). Each semiconductor element 1 has a pair of conductive bumps 2a, 2b on the side away from the substrate 10 for electrically and physically connecting to an external circuit (e.g., a circuit board, a backplane, etc.). As shown in FIG. 1A, the projected shape of the conductive bumps 2a, 2b is approximately rectangular.

[0010] Fig. 1B is a cross-sectional view taken along line A-A' in Fig. 1A. The semiconductor element 1 has a pair of electrodes 3a, 3b on the side away from the substrate 10. The conductive bumps 2a, 2b are disposed directly on the electrodes 3a, 3b, respectively. The upper surfaces of the conductive bumps 2a, 2b are arc-shaped and non-parallel to the upper surfaces of the electrodes 3a, 3b.

[0011] It is particularly preferred to select different materials for the conductive bumps 2a, 2b and the electrodes 3a, 3b. The material of the electrodes 3a, 3b includes metals, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), or alloys thereof, or laminate combinations thereof. The material of the conductive bumps 2a, 2b can include low melting point metals or low liquidus melting point alloys (compared to the material of the electrodes 3a, 3b), whose melting point or liquidus melting point is below 210°C, such as bismuth (Bi), tin (Sn), indium (In), or alloys thereof. In one embodiment, the melting point of the low melting point metal or the liquidus melting point alloy is below 170°C. The material of the low liquidus melting point alloy can be a tin-indium alloy or a tin-bismuth alloy.

[0012] FIG. 1C is a top view of a semiconductor element array structure 1001 according to another embodiment of the present disclosure. The semiconductor element array structure 1001 includes a plurality of semiconductor elements 1 arranged in a predetermined pattern on a substrate 10. The substrate 10 has an approximately circular outer shape, and the material of the substrate 10 can be referred to in the relevant paragraph above. FIG. 1D is a cross-sectional view of line segment A-A' in FIG. 1C. In one embodiment, a secondary adhesive structure 4 is provided between each semiconductor element 1 and the substrate 10, and the semiconductor element 1 is temporarily fixed on the substrate 10 via the secondary adhesive structure 4. The semiconductor element 1 has a pair of electrodes 3a, 3b on the side away from the substrate 10, and the conductive bumps 2a, 2b are directly placed on the electrodes 3a, 3b, respectively. The upper surfaces of the conductive bumps 2a, 2b are arc-shaped. The adhesive structure 4 can be made of a polymer, for example, polyimide (PI), acrylic resin, epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), polycycloolefin (Cyclic Olefin Polymer (COP) or benzocyclobutane (BCB), and for the materials of the conductive bumps 2a, 2b and the electrodes 3a, 3b, reference can be made to the relevant paragraphs above.

[0013] 1D, the outer edge 42 of the secondary adhesive structure 4 is approximately flush with the outermost edge 19 of the semiconductor element 1. The thickness H4 of the secondary adhesive structure 4 is approximately 2-3 μm or 1-10 μm. That is, the secondary adhesive structure 4 has a maximum width W5 and the semiconductor element 1 has a maximum width W6, where W5 is approximately the same as W6. In another embodiment, the outer edge 42 is not flush with the outermost edge 19 of the semiconductor element 1, and the secondary adhesive structure 4 can be recessed or convex relative to the outermost edge 19 of the semiconductor element 1. That is, W5 can be smaller or larger than W6.

[0014] 1E is a cross-sectional view of a semiconductor element array 1003 in another embodiment of the present disclosure. The semiconductor element array 1003 includes a plurality of semiconductor elements 1 arranged in a predetermined pattern on a substrate 10. An adhesive structure 4' is provided between the semiconductor elements 1 and the substrate 10. The semiconductor elements 1 are temporarily fixed on the substrate 10 via the adhesive structure 4'. The semiconductor element 1 has a pair of electrodes 3a, 3b on the side away from the substrate 10. Conductive bumps 2a, 2b are provided directly on the electrodes 3a, 3b, respectively.

[0015] As shown in FIG. 1E, the adhesive structure 4' has a plateau portion 43 and a continuous portion 44. The continuous portion 44 is a continuous structure and is continuously distributed on the substrate 10, passing through the area below all the semiconductor elements 1 and between two adjacent semiconductor elements 1. The plateau portion 43 is located between the semiconductor element 1 and two adjacent continuous portions 44, and protrudes upward to contact a single semiconductor element 1. In one embodiment, the outer edge 42 of the plateau portion 43 is flush with or close to the outermost edge 19 of the semiconductor element 1. The plateau portion 43 has a thickness H4 of about 2 to 3 μm. The continuous portion 44 has a thickness H5 of about 0 to less than 1 μm. That is, the plateau portion 43 has a maximum width W5, the semiconductor element 1 has a maximum width W6, and W5 is approximately equal to W6. In another embodiment, outer edge 42 is not flush with outermost edge 19 of semiconductor device 1, and pedestal 43 may be recessed or convex relative to outermost edge 19 of semiconductor device 1. That is, W5 may be smaller or larger than W6.

[0016] FIG. 2A is a three-dimensional view of a semiconductor element 1 in an embodiment of the present disclosure. The maximum side length of the semiconductor element 1 does not exceed 100 μm or is 50 μm. For example, the maximum side length of the semiconductor element 1 is about 40 μm and the width is about 20 μm. The conductive bumps 2a, 2b have opposite polarities (e.g., positive and negative) and the minimum horizontal distance D between them is less than 40 μm, for example, the maximum side length of the semiconductor element is about 40 μm and D is about 15 μm. In one embodiment, the conductive bumps 2a, 2b completely cover the lower electrode (not shown) and have an outwardly convex arc shape and apexes 21a, 21b. Referring to FIG. 1A, the apexes 21a, 21b are located approximately at the geometric center of the conductive bumps 2a, 2b and / or the electrodes.

[0017] FIG. 2B is a cross-sectional view of the semiconductor device 1 along the line B-B' in FIG. 2A. The semiconductor device 1 is disposed on a substrate 10 and includes a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor overlapping layer 14 is an inclined surface and is not perpendicular to the upper surface 1051 of the substrate 10. In one embodiment, the semiconductor device 1 is, for example, an LED chip, and the semiconductor overlapping layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The first semiconductor layer 11 and the second semiconductor layer 13 can provide electrons and holes, respectively, and the electrons and holes are recombined in the active layer 12 to emit light. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are made of a III-V group semiconductor material, for example, Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P, where 0≦x, y≦1, (x+y)≦1. Depending on the material of the active layer 12, the LED chip can emit red light with a peak value between 610 nm and 650 nm, green light with a peak value between 530 nm and 570 nm, cyan light with a peak value between 500 nm and 485 nm, blue light with a peak value between 450 nm and 485 nm, violet light with a peak value between 400 nm and 450 nm, or ultraviolet light with a peak value between 280 nm and 400 nm. The maximum thickness of the semiconductor superposition layer 14 is about 10 μm or less. In one embodiment, the lower surface 17 of the first semiconductor layer 11 contacts the substrate 10 and is a rough surface, in other words, the upper surface of the substrate 10 in contact with the lower surface 17 of the first semiconductor layer 11 is also a rough surface. In another embodiment, the lower surface 17 of the first semiconductor layer 11 is a substantially flat surface (not shown). In another embodiment, the substrate 10 is a growth substrate for epitaxially growing the semiconductor superimposed layer 14, and the entire upper surface of the substrate 10 facing the semiconductor superimposed layer 14 is a rough surface (not shown), for example, a patterned sapphire substrate (PSS). In one embodiment, the semiconductor device 1 includes a carrier (not shown), which is located under the semiconductor superimposed layer 14 and is used to support the semiconductor superimposed layer 14, and the carrier can be an epitaxial growth substrate or a non-epitaxial growth substrate for the semiconductor superimposed layer 14, and the material of the carrier can be referred to the paragraph related to the substrate 10, and the selection of the material shall be in accordance with the feasibility of theory and practice.

[0018] As shown in FIG. 2B, the semiconductor overlapping layer 14 has a platform 16 for exposing the first semiconductor layer 11 to the outside of the active layer 12 and the second semiconductor layer 13. The protective layer 15 covers the upper surface of the second semiconductor layer 13, the sidewall of the first semiconductor layer 11, the sidewall of the active layer 12, the sidewall of the second semiconductor layer 13, and the upper surface of the first semiconductor layer 11 located in the platform 16. The protective layer 15 can be in direct contact with the substrate 10. In another embodiment, the protective layer 15 does not need to be in direct contact with the substrate 10. The protective layer 15 has a first opening 5a in the platform 16 that exposes a part of the first semiconductor overlapping layer 11. The hole protective layer 15 has a second opening 5b on the second semiconductor layer 13 that exposes a part of the second semiconductor layer 13. The first electrode 3a is located in the platform 16 and is partially formed on the protective layer 15, with the protective layer 15 located in the platform 16 and the protective layer 15 located partially outside the platform 16. The first electrode 3a has a first recess 6a formed in the first opening 5a and electrically connected to the first semiconductor layer 11. The first electrode 3a has a stepped outer shape at the position of the platform 16. The second electrode 3b has a portion located on the protective layer 15 other than the second opening 5b and a second recess 6b formed in the second opening 5b and electrically connected to the second semiconductor layer 13.

[0019] The protective layer 15 can be a single layer or a multi-layer structure and has the property of electrical insulation. The single layer structure material can include oxide, nitride, or polymer. The oxide can be aluminum oxide (Al2O3), silicon oxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), or aluminum oxide (AlO x ). The nitrides include aluminum nitride (AlN), silicon nitride (SiN xThe polymers can include polyimide or benzocyclobutane (BCB). The multilayer materials can include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium dioxide (TiO2), niobium pentoxide (Nb2O5), silicon nitride (SiN x ), or a combination of the above materials. The multi-layer structure may also form a Distributed Bragg Reflector (DBR).

[0020] Referring to FIG. 2B, the first conductive bump 2a is formed directly on the first electrode 3a. The first conductive bump 2a can completely or partially fill the first recess 6a of the first electrode 3a, and its outermost surface 22a has a macroscopically smooth and outwardly convex arc shape. The first conductive bump 2a has an apex 21a which is the region furthest from the first conductive bump 2a and the substrate 10. As shown, the outermost surface 22a of the first conductive bump 2a does not have any plane that is parallel to the bottom surface of the first conductive bump 2a but not parallel to the top surface of the first electrode 3a. The bottom surface 17 of the first semiconductor layer 11 is a rough surface, and the roughness of the outermost surface 22a of the first conductive bump 2a is less than the roughness of the bottom surface 17 of the first semiconductor layer 11 and less than the roughness of the top surface of the first electrode 3a.

[0021] Referring to FIG. 2B, the second conductive bump 2b directly covers the top of the second electrode 3b. The second conductive bump 2b can completely or partially fill the second recess 6b of the second electrode 3b, and its outermost surface 22b has a macroscopically smooth and outwardly convex arc shape. The second conductive bump 2b has an apex 21b which is the region furthest from the second conductive bump 2b and the substrate 10. As shown, the outermost surface 22b of the second conductive bump 2b does not have any plane that is parallel to the bottom surface of the second conductive bump 2b but not parallel to the top surface of the second electrode 3b. The roughness of the outermost surface 22b of the second conductive bump 2b is less than the roughness of the bottom surface 17 of the first semiconductor layer 11 and less than the roughness of the top surface of the second electrode 3b. In one embodiment, the top 21a of the first conductive bump 2a and the top 21b of the second conductive bump 2b are positioned at approximately the same horizontal height, which is advantageous for stable fixing of the semiconductor element 1 on a subsequent substrate. However, in reality, there may be a certain degree of height difference within the tolerance of manufacturing process technology. The bottom surfaces of the first conductive bump 2a and the second conductive bump 2b are usually conformally formed on the first electrode 3a and the second electrode 3b, respectively, and the bottom points of both bumps are often not positioned at the same horizontal height. Referring to FIG. 2B, the vertical distance from the top 21a of the first conductive bump 2a to the upper surface 151 of the protective layer 15 can be measured as a first thickness H1, and the first conductive bump 2a has a first (maximum) width W1, and H1 / W1 is between 0.1 and 0.4, preferably between 0.1 and 0.25. The vertical distance from the top 21b of the second conductive bump 2b to the upper surface 151 of the protective layer 15 can be measured as a second thickness H2, and the second conductive bump 2b has a second (maximum) width W2, where H2 / W2 is between 0.1 and 0.4, preferably between 0.1 and 0.25. H1 / W1 and H2 / W2 may be the same or different. The second thickness H2 of the second conductive bump 2b is 4 to 6 μm.

[0022] The more densely the first conductive bumps 2a are packed in the first recesses 6a of the first electrode 3a, the more densely the second conductive bumps 2b are packed in the second recesses 6b of the second electrode 3b, which can improve the reliability of the physical and electrical connection between the semiconductor device 1 and the circuit board (not shown), and reduce the probability of failure. In detail, if the structure of the semiconductor device 1 is as shown in FIG. 2b, but there are no conductive bumps 2a and 2b, when the semiconductor device 1 is soldered and fixed to the circuit board, the solder located between the first electrode 3a and the circuit board (not shown) may unexpectedly generate holes near the first recesses 6a, and the solder located between the second electrode 3b and the circuit board (not shown) may unexpectedly generate holes near the second recesses 6b. These holes will likely reduce the bonding strength between the semiconductor device 1 and the circuit board.

[0023] FIG. 2C is a cross-sectional view of a semiconductor device 1 according to another embodiment of the present disclosure. When the conductive bump forming process includes a heat treatment step, the conductive bump will likely have discretely dispersed particles 7 formed therein after the heat treatment step under the selection and combination of a specific conductive bump and electrode material. The difference between FIG. 2C and FIG. 2B is that the first conductive bump 2a and the second conductive bump 2b are dotted with particles 7 having a discrete distribution, irregular size, and irregular shape, and the material of the particles 7 is different from that of the conductive bumps 2a and 2b, but is the same as that of some of the electrodes 3a and 3b, for example, gold, platinum, or an alloy of the above materials. The shape of the particles 7 can be strip-shaped, polygonal, leaf-shaped, or droplet-shaped.

[0024] 2D-2E are diagrams of a semiconductor element 1' according to another embodiment of the present disclosure, in which the tops 21a and 21b are not at the same horizontal height, and the tops 21a are slightly lower than the tops 21b. FIG. 2E is a cross-sectional view of the semiconductor element 1' in FIG. 2D taken along line B-B'. The conductive bump 2a is located above the platform 16, and when the conductive bumps 2a and 2b have similar volumes, the tops 21a located on the conductive bump 2a are slightly lower than the tops 21b of the conductive bumps 2b, since some of the conductive bumps 2a need to fill the platform 16. In one embodiment, the first thickness H1 of the first conductive bump 2a is smaller than the second thickness H2 of the second conductive bump 2b by 0.4-1 μm.

[0025] FIG. 3A is a top view of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 3B is a cross-sectional view of the semiconductor device 1 along the line C-C' in FIG. 3A. FIG. 3C is a cross-sectional view of the semiconductor device 1 along the line D-D' in FIG. 3A. The semiconductor device 1 includes a semiconductor superimposed layer 14, an electrode 3, and a conductive bump 2 located on the semiconductor superimposed layer 14. As shown in FIG. 3A, the projected shape of the conductive bump 2 and the electrode 3 is approximately rectangular. As shown in FIG. 3B, the outermost surface 22 of the conductive bump 2 has a macroscopically smooth and outwardly convex arc shape. The outermost surface 22 and the upper surface of the electrode 3 are in contact with each other, and the tangent at the contact point of the conductive bump 2 and the upper surface of the electrode 3 form an included angle θ1. The included angle θ1 is close to 90 degrees, and preferably 70 degrees<θ1<90 degrees. 3C, the outermost surface 22 and the upper surface of the electrode 3 are in contact with each other, and the tangent line at the contact point of the conductive bump 2 and the upper surface of the electrode 3 form an included angle θ2. The included angle θ2 is < included angle θ1, and preferably 30 degrees < θ2 < 70 degrees. In other words, as shown in FIG. 3A, the cross-sectional shape of the conductive bump 2 parallel to the side length direction of the electrode 3 is different from the cross-sectional shape of the electrode 3 in the diagonal direction.

[0026] 4A is a semiconductor element array structure 2000 according to another embodiment of the present disclosure. The semiconductor element array structure 2000 includes a plurality of semiconductor elements 1 (for simplicity, only three semiconductor elements 1 are shown in the figure on one dimension, but the semiconductor element array structure 2000 can include m*n semiconductor elements 1, where m and n are positive integers) and a carrier 30. The semiconductor elements 1 are disposed on the carrier 30 in a manner that the conductive bumps 2 face the carrier 30 (also called flip chip). The carrier 30 can support and fix the semiconductor elements 1. The carrier 30 includes a substrate 31 and an adhesive structure 32, and the material of the substrate 31 can be glass, sapphire, or a polymer material, etc., and can be a light-transmitting material that transmits light of a specific wavelength emitted by a light-emitting diode or a laser diode. The adhesive structure 32 can include a thermal release adhesive, a photodegradable adhesive, a chemically removable adhesive, a heat-resistant adhesive, a blue film, or a tape with a dynamic release layer. In another embodiment, the adhesive structure 32 may include a polymer, such as polyimide (PI), acrylic resin, epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), cyclic olefin polymer (COP), or benzocyclobutane (BCB). When the semiconductor element 1 is arranged on the carrier 30 in a flip-chip manner, the smooth and convex outermost surface 22 of the conductive bump 2 directly contacts the adhesive structure 32. As shown in FIG. 4A, the conductive bump 2 is partially recessed into the adhesive structure 32, and the recessed portion has a maximum width W3 in the horizontal direction, and the conductive bump 2 itself has a maximum width W4, which is greater than the width W3.4C, the outermost surface 22 of the conductive bump 2 is smooth and arc-shaped, and the projected area of ​​the portion of the conductive bump 2 recessed into the adhesive structure 32 (e.g., the area of ​​the indentation 34) is smaller than the projected area of ​​the electrode 3, so that the adhesive force between the conductive bump 2 and the adhesive structure 32 can be reduced, which is favorable for the transfer process of transferring the semiconductor element 1 from the carrier 30 to another location via a subsequent transfer structure (not shown). The transfer process of the semiconductor element 1 will be described in the following paragraphs.

[0027] 4B and 4C respectively show a cross-sectional view and a top view after one semiconductor element is removed from the semiconductor element array structure 2000 of FIG. 4A. Referring to FIG. 4C, a removal area 33 (e.g., dotted area) can be defined on the upper surface of the carrier 30, which is an area exposed on the carrier 30 after the semiconductor element 1 is removed, that is, the projected area of ​​the semiconductor element 1. The removal area 33 includes a pressing mark 34. The pressing mark 34 is an area where the adhesive structure 32 is pressed by the conductive bump 2, and the pressing mark 34 has a projected area. In one embodiment, when the comparison value between the projected area of ​​the pressing mark 34 of the conductive bump 2 and the projected area of ​​the semiconductor element 1 is less than 0.2, the semiconductor element 1 can be relatively easily picked up from the carrier 30 and moved to another position.

[0028] 4D and 4E are cross-sectional views of semiconductor element array structures 3000 and 3001 in another embodiment of the present disclosure, respectively. FIG. 4D shows a semiconductor element array structure 3000. The semiconductor element array structure 3000 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a substrate 31 and an adhesive structure 32. The semiconductor element 1 is disposed on the carrier 30 in a manner that the conductive bumps 2 face the carrier 30. The conductive bumps 2 and the electrodes 3 are completely recessed in the adhesive structure 32 and completely covered by the adhesive structure 32. The adhesive structure 32 also covers the lower surface of the semiconductor element 1 that is not covered by the electrodes 3. By being temporarily fixed on the adhesive structure 32, the relative positions between the plurality of semiconductor elements 1 are maintained and will not be changed by the subsequent manufacturing process. FIG. 4E is a cross-sectional view of another semiconductor element array structure 3001. The semiconductor element array structure 3001 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a substrate 31 and a plurality of mutually separated sub-adhesive structures 32'', where one sub-adhesive structure 32'' is located under one semiconductor element 1 and has a width approximately equal to that of the semiconductor element 1, as shown in FIG. 4E. There is a passage 35 between two adjacent sub-adhesive structures 32'', the distance of which is greater than 0. A plurality of semiconductor elements 1 are disposed on the carrier 30 in a manner that the conductive bumps 2 face the carrier 30. The conductive bumps 2 and the electrodes 3 are completely recessed in the sub-adhesive structure 32'' and completely covered by the sub-adhesive structure 32''. The sub-adhesive structure 32'' also covers the lower surface of the semiconductor element 1 that is not covered by the electrodes 3.

[0029] 5A-5D are flow diagrams of transferring a semiconductor element 1 through a transfer structure 40 in an embodiment of the present disclosure. As shown in FIG. 5A, a plurality of semiconductor elements 1 are arranged on a carrier 30 in an array format. The semiconductor elements 1 are in contact with the adhesive structure 32 of the carrier 30 through a portion of the surface of the conductive bumps 2, and are temporarily fixed on the carrier 30. The transfer structure 40 is provided to move the semiconductor element 1 from the carrier 30 to another location. The transfer structure 40 has a plurality of gripping portions 41, and each gripping portion 41 corresponds to a position of the semiconductor element 1 to be gripped. As shown in FIG. 5B , the transfer structure 40 approaches the semiconductor element 1, brings the gripping portion 41 into contact with the semiconductor element 1, and then moves upward to detach the semiconductor element 1 held by the gripping portion 41 from the carrier 30; since the adhesive force between the gripping portion 41 and the held semiconductor element 1 is greater than the adhesive force between the semiconductor element 1 and the carrier 30, the semiconductor element 1 that is not in contact with the gripping portion 41 remains on the carrier 30.

[0030] Next, as shown in FIG. 5C, the semiconductor element 1 temporarily fixed on the transfer structure 40 and the gripping part 41 is moved to above a predetermined position on the target substrate 50. At this predetermined position, the semiconductor element 1 may be in contact with the target substrate 50 or not, and is finally placed or fixed directly on the target substrate 50. In this step, the adhesive force between the gripping part 41 and the semiconductor element 1 is smaller than that between the semiconductor element 1 and the target substrate 50, and an adhesive structure can be arranged on the surface of the target substrate 50 (not shown) to increase the adhesive force between the semiconductor element 1 and the target substrate 50. Next, as shown in FIG. 5D, the semiconductor element 1 is separated from the transfer structure 40 and stays on the target substrate 50, and the transfer structure 40 can move to the same or a different carrier 30 to grip other semiconductor elements 1. After the transfer, the semiconductor element 1 is arranged on the target substrate 50 in a manner that the conductive bumps 2 face the target substrate 50. The target substrate 50 may be a backplane of a display, a TFT substrate, a substrate having a redistribution layer (RDL), or a sub-mount of a package. In another embodiment, the target substrate 50 may be a temporary substrate similar to the substrate 30. In Figs. 5A to 5D, the contact manner between the semiconductor element 1 and the substrate 30 is not limited to the manner shown in Fig. 4A, and may be the manner shown in Figs. 4D and 4E.

[0031] 6A-6C are flow charts of transferring a semiconductor element 1 according to another embodiment of the present disclosure. As shown in FIG. 6A, a plurality of semiconductor elements 1 are arranged on a carrier 30 in an array format. Each semiconductor element 1 is in contact with an adhesive structure 32 of the carrier 30 through a part of the surface of a conductive bump 2, and is temporarily fixed on the carrier 30. Next, the structure of FIG. 6A is inverted or the target substrate 50 is moved to position the semiconductor element 1 between the carrier 30 and the target substrate 50, but the semiconductor element 1 is not in direct contact with the target substrate 50, for example, the semiconductor element 1 is suspended above the target substrate 50, as shown in FIG. 6B. Laser energy L1 is provided to irradiate a specific position of the adhesive structure 32 from the upper side of the substrate 31, and the specific position corresponds to one semiconductor element 1 to be transferred. The laser energy L1 can be a single-shot laser or a multi-shot laser. In one embodiment, a single position of one semiconductor element 1 or one adhesive structure 32 can be irradiated with one laser or multiple lasers in one irradiation process. In another embodiment, multiple positions of one semiconductor element 1 or one adhesive structure 32 can be irradiated with one or multiple lasers in one irradiation process, respectively. As shown in FIG. 6C, the adhesive structure 32 irradiated with the laser energy L1 reduces the adhesive force between the semiconductor element 1 and the adhesive structure 32, or the force of moving the semiconductor element 1 downward becomes greater than the adhesive force of the adhesive structure 32 to the semiconductor element 1, so that the semiconductor element 1 falls from the carrier 30 to the target substrate 50. After the transfer, the semiconductor element 1 is placed on the target substrate 50 in a manner that the conductive bumps 2 are separated from the target substrate 50. In another embodiment, in the step of FIG. 6B, the semiconductor element 1 is first directly contacted with the target substrate 50, and then the semiconductor element 1 can be more accurately aligned to the target substrate 50 by irradiating the laser energy L1. After the step of FIG. 6C, optionally a cleaning step can be performed to remove any remaining sub-adhesive structures 32 ″ on the semiconductor element 1 .The cleaning step can include dry etching or wet etching, and the dry etching can be an oxygen plasma etching process. In Fig. 6A to Fig. 6C, the contact manner between the semiconductor element 1 and the carrier 30 is not limited to the manner shown in Fig. 4A, and can also be the manner shown in Fig. 4D and Fig. 4E.

[0032] 7A to 7D are flow charts for fabricating a semiconductor device 1 according to an embodiment of the present disclosure. As shown in FIG. 7A, a plurality of semiconductor units 200 are disposed on a substrate 10. The semiconductor units 200 include a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor units 200 are disposed on the substrate 10 in a manner that the first electrode 3a and the second electrode 3b are spaced apart from the substrate 10. The first electrode 3a and the second electrode 3b each have a recess, and the description of the related structure can be referred to the related paragraph above. Then, two groups of adhesives 80 separated from each other are formed on the first electrode 3a and the second electrode 3b, respectively. The adhesive 80 includes a resin 81 and a plurality of conductive particles 82 dispersed in the resin 81. In one embodiment, the manner of forming the adhesive 80 can be a manner via printing, coating, spraying, or dispensing. Among them, the printing method can include aerosol jet printing or ink-jet printing. The material of the resin 81 includes thermosetting plastic and flux. The thermosetting plastic can be epoxy resin, silicone, polymethyl methacrylate, and episulfide. The melting point of the conductive particles 82 is lower than the solidification temperature of the resin 81. In one embodiment, the material of the conductive particles 82 can be gold, silver, or copper. In another embodiment, the material of the conductive particles 82 can be a metal with a low melting point or an alloy with a low liquidus melting point (compared to the material of the electrodes 3a and 3b). In one embodiment, the melting point or liquidus temperature of the metal with a low melting point or the alloy with a low liquidus melting point is lower than 210° C. In another embodiment, the melting point or liquidus temperature of the low melting metal or low liquidus temperature alloy is lower than 170° C. The low liquidus temperature alloy material can be a tin alloy, for example, a tin-indium alloy, a tin-bismuth alloy.

[0033] As shown in FIG 7B, laser energy L2 is used to irradiate the adhesive 80 or a nearby area to heat the adhesive 80. The laser energy L2 can include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L2 is an infrared pulse mode laser beam, with a wavelength in the range of 750 nm to 2000 nm and a spot size of 0.004 to 0.002 cm. 2 The beam diameter is 100-500 μm, the pulse duration is less than 20 ms, the repetition frequency is 500-4000 Hz, the duty cycle is 1%-10%, the laser power is 100 W, and the laser energy is 595-850 J / cm. 2As shown in FIG. 7C, during the heating process, the conductive particles 82 aggregate on the first electrode 3a and the second electrode 3b to form the first conductive bump 2a and the second conductive bump 2b having a convex arc outer surface. The semiconductor unit 200 having the first conductive bump 2a and the second conductive bump 2b is referred to as the semiconductor element 1 herein. In one embodiment, at least a part of the resin 81 migrates onto the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b are solidified, and the resin 81 covering them is also heated, but is not completely solidified (Uncured) and is in a liquid or semi-liquid state. 7D, a cleaning step is performed to remove the unsolidified resin 81 and expose the first conductive bump 2a and the second conductive bump 2b to the outside environment and to allow them to contact a carrier or target substrate during subsequent transfer. The cleaning step can be performed using a solvent, which can include N-Methylpyrrolidinone (NMP), Methyl Ethyl Ketone (MEK), Acetone (Ace), or Isopropyl Alcohol (IPA).

[0034] 8A-8D are flow charts for fabricating a semiconductor device 1 according to another embodiment of the present disclosure. As shown in FIG. 8A, a plurality of semiconductor units 200' are disposed on a substrate 10. The semiconductor units 200' include a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The first electrode 3a and the second electrode 3b of the semiconductor units 200' are spaced apart from the substrate 10. The first electrode 3a and the second electrode 3b each have a recess, and the description of the related structure can be referred to the related paragraph above. Using electroplating, chemical plating, or deposition, a first bonding pad 23a and a second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b, respectively. The outer surface 24a of the first bonding pad 23a and the outer surface 24b of the second bonding pad 23b are approximately conformal with the upper surfaces of the first electrode 3a and the second electrode 3b, that is, the outlines of the two are similar. A single group of adhesive 83 is formed on the semiconductor unit 200', the first bonding pad 23a, and the second bonding pad 23b. The adhesive 83 includes only resin in this example. In another embodiment, the adhesive 83 includes resin and a relatively low concentration of conductive particles (compared to the conductive particles in FIG. 7A). In one embodiment, the manner of forming the adhesive 80 can be formed by printing, coating, spraying, or dispensing. Among them, the printing manner can include aerosol jet printing or inkjet printing. For the material of the first bonding pad 23a and the second bonding pad 23b, please refer to the paragraph related to the conductive bumps 2a and 2b. For the resin material, please refer to the paragraph related to the conductive bumps 2a and 2b.

[0035] As shown in FIG. 8B, the first bonding pad 23a and the second bonding pad 23b or their adjacent regions are irradiated with laser energy L3 to heat the adhesive 83, the first bonding pad 23a and the second bonding pad 23b. The laser energy L3 may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L3 is an infrared laser beam having a wavelength in the range of 750 nm to 2000 nm. As shown in FIG. 8C, during the heating process, the first bonding pad 23a and the second bonding pad 23b are melted in the adhesive 83 by the heat and are condensed on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles, the conductive particles move toward the first electrode 3a and the second electrode 3b in part or in whole even after being heated), forming the first conductive bump 2a and the second conductive bump 2b having an outwardly convex and arc-shaped outer surface. A semiconductor unit 200' having the first conductive bump 2a and the second conductive bump 2b is referred to as a semiconductor element 1 here. At least a part of the adhesive 83 migrates onto the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b after being subjected to heat. After being heated, the first conductive bump 2a and the second conductive bump 2b are solidified, and the adhesive 83 (or resin) covering thereon also assumes a liquid or semi-liquid state. Then, as shown in FIG. 8D, a cleaning step is performed to remove the unsolidified adhesive 83 (or resin) and expose the first conductive bump 2a and the second conductive bump 2b to the outside environment so that they can be contacted with a carrier or a target substrate during subsequent transfer. For the cleaning step, reference can be made to the description in the relevant paragraph of FIG. 7D above.

[0036] 7D and 8D, the adhesive 80, 83 between the conductive bumps 2a, 2b may not be completely removed and may remain on the semiconductor unit 200. It is preferable that the maximum horizontal height of the remaining adhesive does not exceed the conductive bumps 2a, 2b so as not to affect the subsequent transfer and die bonding processes.

[0037] FIG. 9A is a three-dimensional view of a semiconductor device 20 according to another embodiment of the present disclosure. FIG. 9B is a cross-sectional view of the semiconductor device 20 along the line B-B' in FIG. 9A. Referring to FIG. 9A, the semiconductor device 20 has two first conductive bumps 2a and second conductive bumps 2b separated from each other on the upper side. Between the first conductive bump 2a and the second conductive bump 2b, there is at least one group of residual adhesive 84 covering the semiconductor device 20. The residual adhesive 84 has an irregular shape and an unfixed area. Referring to FIG. 9B, the semiconductor device 20 has a semiconductor overlap layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor overlap layer 14 is an inclined surface and is not perpendicular to the upper surface 1051 of the substrate 10. The semiconductor overlap layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The remaining adhesive 84 is located on the protective layer 15 between the first conductive bump 2a and the second conductive bump 2b. The highest point of the remaining adhesive 84 is not higher than the highest point of the first conductive bump 2a and the second conductive bump 2b. Since the height of the remaining adhesive 84 does not exceed the conductive bumps 2a and 2b, it does not affect the subsequent transfer and die bonding processes.

[0038] 10A-10E are flow charts of transferring a semiconductor device 20' according to another embodiment of the present disclosure. For the structure of the semiconductor device 20', please refer to the drawings and paragraphs related to the semiconductor devices 1, 1', and 20, and for the semiconductor device array structure 5001, please refer to FIG. 4E and the paragraphs related to the semiconductor device array structure 3001, in which the semiconductor device array structure 5001 includes a plurality of semiconductor units 300, the semiconductor units 300 are disposed on the carrier 30 in a flip chip manner, and a first bonding pad 53a and a second bonding pad 53b are disposed below a first electrode 3a and a second electrode 3b of the semiconductor units 300, respectively.

[0039] In FIG. 10A, the plurality of semiconductor units 300 are disposed on the carrier 30 such that the electrodes 3a, 3b (bonding pads 53a, 53b) face the orientation of the carrier 30, the carrier 30 includes a substrate 31, the upper surface of the substrate 31 includes a plurality of mutually separated sub-adhesive structures 32″, the sub-adhesive structures 32″ are located under the semiconductor units 300 and have approximately the same width as the semiconductor units 300. Between two adjacent sub-adhesive structures 32″, there is a passage 53 with a distance greater than 0, and the plurality of semiconductor units 300 are disposed on the carrier 30 in such a manner that the bonding pads 53a, 53b are embedded opposite the adhesive structures 32. The carrier 30 has an approximately square or circular outer shape, and for the material, reference can be made to the paragraph describing the substrate 10. In this step, the first and second bonding pads 53a and 53b are located on the electrodes 3a and 3b, respectively, and the outer surfaces 54a and 54b are generally conformal to the upper surfaces of the first and second electrodes 3a and 3b, i.e., the contours of the two are similar. In one embodiment, the outer edge of the sub-adhesive structure 32'' is not flush with the outermost edge of the semiconductor unit 300, but can be recessed or protruding outward relative to the outermost edge of the semiconductor unit 300.

[0040] Next, as shown in FIG. 10B, a photomask 5300 is placed above the corresponding position of the semiconductor element array structure 5001. The photomask 5300 includes a light-transmitting substrate 5301 (e.g., glass) and a light-shielding metal layer 5302 (e.g., gold) located thereon. The light-shielding metal layer 5302 has an opening 5305, the size of which corresponds to the underlying semiconductor unit 300 or an array region including a plurality of semiconductor units 300 (not shown, including m'×n' semiconductor units 300, where m' and n' are positive integers and m' and n' are not 1 at the same time). In this embodiment, the laser energy L4 is irradiated onto the semiconductor unit 300 through the opposite side of the substrate 31, so a material that can transmit the laser energy L4 must be selected as the substrate 31.

[0041] 10C, laser energy L4 is provided from above the photomask 5300 through the position of the opening 5305 to irradiate one or more corresponding semiconductor units 300 below. The (these) semiconductor units 300 irradiated with the laser energy L4 are formed to become semiconductor elements 20'. More specifically, the laser energy L4 is irradiated toward the first bonding pad 53a and the second bonding pad 53b of the (these) semiconductor units 300 corresponding to the opening 5305 or their surrounding areas, and the laser energy L4 can be a single-shot laser or a multi-shot laser. That is, in one embodiment, the position of this (these) semiconductor unit 300 can be irradiated with one or more shots of laser in the irradiation process, and the first bonding pad 53a and the second bonding pad 53b irradiated with the laser energy L4 receive heat and are condensed on the first electrode 3a and the second electrode 3b to form the first conductive bump 2a and the second conductive bump 2b having the outwardly convex and arc-shaped outer surface. In this step, the structure having the conductive bumps 2a and 2b is called a semiconductor element 20'. The contact area between the conductive bumps 2a and 2b of the semiconductor element 20' and the lower sub-adhesive structure 32'' is smaller than that of the bonding pads 53a and 53b of the semiconductor unit 300. Therefore, the semiconductor element 20' is easy to hold in the semiconductor element arrangement structure 5001 relative to the semiconductor unit 300. A more detailed mechanism will be described in the enlarged area views of Figures 11A-11B below.

[0042] Next, as shown in FIG. 10D, a transfer structure 500 is provided to transfer the semiconductor element 20' from the carrier 30 to another location. At this time, the transfer structure 500 does not have a protruding gripping portion, and the entire structure is an adhesive layer 502 having adhesive power (for example, Polydimethylsiloxane (PDMS) or an adhesive tape having adhesive power), and the adhesive layer 502 has a gripping surface 501, and the size of the gripping surface 501 is several times larger than the semiconductor element 20' to be gripped. The transfer structure 500 approaches the semiconductor unit 300 and the semiconductor element 20', and at the same time, brings the gripping surface 501 into contact with the semiconductor unit 300 and the semiconductor element 20', and then moves further upward to stick the semiconductor element 20' onto the gripping surface 501 and separates from the carrier 30 (the sub-adhesive structure 32''), but the semiconductor unit 300 is not gripped. At this time, the adhesive force between the gripping surface 501 and the semiconductor unit 300 is smaller than that between the semiconductor unit 300 and the sub-adhesive structure 32'', but the adhesive force between the gripping surface 501 and the semiconductor element 20' is larger than that between the semiconductor element 20' and the sub-adhesive structure 32''. Therefore, after the transfer structure 500 is separated upward from the sub-adhesive structure 32'', the semiconductor unit 300 below the transfer structure 500 still remains on the carrier 30, and the semiconductor element 20' is selectively gripped and temporarily fixed on the gripping surface 501.

[0043] Finally, the transfer structure 500 and the semiconductor element 20' temporarily fixed on the gripping surface 501 are moved together to above a predetermined position on the target substrate 70. A surface circuit 180 can be selectively placed on this predetermined position, and the semiconductor element 20' after transfer can or cannot contact the target substrate 70. As shown in Fig. 10E, when the semiconductor element 20' is separated from the transfer structure 500 and transported onto the target substrate 70, the conductive bumps 2a, 2b can be directly heated and melted to solder (electrically connect) to the underlying surface circuit 180.

[0044] In one embodiment, according to the requirements of the optoelectronic properties of the semiconductor devices 20', the transfer structure 500 can repeatedly move to the same or different carriers 30 to selectively hold the semiconductor devices 20' that meet the optoelectronic property criteria to the target substrate 70, and the selective transfer manner can transfer one semiconductor device 20' at a time, or transfer multiple semiconductor devices 20' in the array area at a time. After the transfer, the multiple semiconductor devices 20' are electrically connected to the surface circuit 180 disposed on the target substrate 70 in the above manner. The target substrate 70 can be a backplane of a display device, a circuit board having a thin-film transistor (TFT) therein, a circuit board having a redistribution layer (RDL) on or in the surface, or a sub-mount of a package body. In another embodiment, the target substrate 70 can be a temporary support structure similar to the carrier 30, and does not have a surface circuit.

[0045] 11A-11B are enlarged views of the region P in FIG. 10C before and after irradiation with laser energy L4. As shown in FIG. 11A, the semiconductor unit 300 includes a semiconductor superimposed layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The first bonding pad 53a and the second bonding pad 53b are formed under the first electrode 3a and the second electrode 3b, respectively, by electroplating, chemical plating, or deposition. The outer surface 54a of the first bonding pad 53a and the outer surface 54b of the second bonding pad 53b are substantially conformal with the lower surfaces of the first electrode 3a and the second electrode 3b, i.e., the outlines of both are similar. In addition, the outer surfaces 54a, 54b have recesses corresponding to the upper electrodes 3a, 3b, rough textures (compared to the lower surfaces of the electrodes 3a, 3b), or both. In this case, the first bonding pad 53a, the second bonding pad 53b and the electrodes 3a, 3b are completely recessed into the sub-adhesive structure 32'' and are completely covered by the sub-adhesive structure 32''. The sub-adhesive structure 32'' is in direct contact with the lower surface 15' of the semiconductor unit 300 that is not covered by the electrodes 3a, 3b. As shown, the shapes of the recessed regions 6a', 6b' formed by the sub-adhesive structure 32'' correspond to the first bonding pad 23a and the second bonding pad 23b.

[0046] As shown in FIG. 11B, after being irradiated with laser energy L4, the first bonding pad 53a and the second bonding pad 53b melt due to heat in the sub-adhesive structure 32'' and coalesce under the first electrode 3a and the second electrode 3b to form the first conductive bump 2a and the second conductive bump 2b having a convex and arc-shaped outer surface. The semiconductor unit 300 having the first conductive bump 2a and the second conductive bump 2b is referred to as the semiconductor element 20' herein. More specifically, since the first electrode 3a and the second electrode 3b are made of a metal material, when melted due to heat, the first bonding pad 53a and the second bonding pad 53b, which are also made of a metal material, coalesce within the upper electrodes 3a and 3b, respectively, as substrates, to form the conductive bumps 2a and 2b with relatively low surface area and surface energy. The conductive bumps 2a and 2b push out the sub-adhesive structure 32'' to lift the semiconductor element 20' out of the sub-adhesive structure 32''. 11B, the contact area between the conductive bumps 2a, 2b and the sub-adhesive structure 32'' is smaller than the contact area between the first bonding pad 53a and the second bonding pad 53b and the sub-adhesive structure 32'' in FIG. 11A, and the lower surface 15' of the semiconductor element 20' and the sub-adhesive structure 32'' are separated by a distance D1. Therefore, the adhesive force of the semiconductor element 20' on the sub-adhesive structure 32'' is smaller than the adhesive force of the semiconductor unit 300.

[0047] In one embodiment, the secondary adhesive structure 32'' solidifies after being subjected to heat and contacts the outer surfaces 54a, 54b of the bonding pads 53a, 53b. Therefore, the recessed regions 6a', 6b' still retain the inner contours corresponding to the bonding pads 53a, 53b after the semiconductor element 20' is removed. In another embodiment, the secondary adhesive structure 32'' has some fluidity when melted by heat, so that the recessed regions 6a', 6b' become smoother and less rough after the semiconductor element 20' is removed, and the secondary adhesive structure 32'' is slightly deformed, but the roughness of the recessed regions 6a', 6b' is still rougher than that of the outer surfaces of the conductive bumps 2a, 2b.

[0048] 12A-12D are flow charts for transferring a semiconductor device 20' according to another embodiment of the present disclosure. As shown in FIG. 12A, a semiconductor device arrangement structure 5001 contacts a transfer structure 500 having an adhesive force with a back surface of a semiconductor device unit 300 facing down. In this embodiment, the transfer structure 500 includes a support layer 503 and an adhesive layer 502 (e.g., Polydimethylsiloxane (PDMS), adhesive tape). The adhesive layer 502 has a gripping surface 501, and the semiconductor unit 300 contacts the gripping surface 501. The transfer structure 500 can selectively apply pressure toward the carrier 30 to ensure that the back surface of the semiconductor unit 300 is bonded to the gripping surface 501.

[0049] 12B, a photomask 5300 is placed above the semiconductor element array structure 5001. The photomask 5300 includes a light-transmitting substrate 5301 (e.g., glass, quartz, sapphire) and a light-shielding metal layer 5302 (e.g., gold, chromium, tungsten) located thereon. The light-shielding metal layer 5302 has an opening 5305, the size of which can cover one or more semiconductor units 300 below.

[0050] 12C, laser energy L5 is provided from above the photomask 5300 through the opening 5305 to irradiate one or more semiconductor units 300 below. The (these) semiconductor units 300 irradiated with the laser energy L5 become the semiconductor element 20′.

[0051] As shown in Fig. 12D, when the carrier 30 is separated from the transfer structure 500, the semiconductor element 20' is separated from the secondary adhesive structure 32'' and transferred onto the gripping surface 501. Next, referring to Fig. 10E, the semiconductor element 20' is placed in a predetermined position on the target substrate 70 via the transfer structure 500.

[0052] 13A-13C are flow charts for transferring a semiconductor element 20' according to another embodiment of the present disclosure. In this embodiment, there is no need to use a photomask. As shown in FIG. 13A, laser energy L6 is applied in a scanning manner to directly cover the surface of all the semiconductor units 300.

[0053] As shown in Fig. 13B, after the laser energy L6 is applied, all the semiconductor units 300 are formed on the semiconductor element 20', so that the adhesive force between the semiconductor element 20' and the carrier 30 (the sub-adhesive structure 32'') is smaller than the adhesive force between the semiconductor units 300 and the carrier 30 (the sub-adhesive structure 32''). For the structures and formation steps of the semiconductor units 300 and the semiconductor element 20', please refer to Figs. 11A-11B and related paragraphs.

[0054] As shown in FIG. 13C, a transfer structure 500 having a gripping portion 504 protruding by using an adhesive layer 502 grips a specific semiconductor element 20'. In one embodiment, the gripping portion 504 and the semiconductor element 20' have similar projected areas, and the gripping portion 504 can grip one semiconductor element 20' at a time. After the transfer structure 500 is moved to the specific semiconductor element 20' and the gripping portion 504 contacts the semiconductor element 20', the transfer structure 500 further moves upward to separate the semiconductor element 20' gripped by the gripping portion 504 from the transport carrier 30 (secondary adhesive structure 32''), while the semiconductor element 20' not in contact with the gripping portion 504 is still retained on the carrier 30 (secondary adhesive structure 32''). At this time, the adhesive force between the gripping portion 504 and the semiconductor element 20' is greater than the adhesive force between the semiconductor element 20' and the carrier 30 (secondary adhesive structure 32''). Then, the semiconductor device 20' is placed in place on the target substrate via the transfer structure 500 as described above.

[0055] FIG. 14E shows a side view of another semiconductor element array structure 6001. As shown in FIG. 14, the semiconductor unit 400 is a vertical type light emitting diode chip. The semiconductor unit 400 includes a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The first bonding pad 53a is formed under the first electrode 3a by electroplating, chemical plating, or deposition. The outer surface 54a of the first bonding pad 53a is approximately conformal with the lower surface of the first electrode 3a, that is, the outlines of the two are similar. The first electrode 3a and the first bonding pad 53a are located under the semiconductor overlapping layer 14 and embedded in the adhesive layer 52, while the second electrode 3b is located above the semiconductor overlapping layer 14. That is, the first electrode 3a (and the first bonding pad 53a) and the second electrode 3b are located on opposite sides of the semiconductor overlapping layer 14, respectively. Besides, the entire upper surface of the semiconductor superposition layer 14 can be selectively coated with a light-transmitting conductive layer 77 (eg, indium tin oxide) to enhance the surface current spreading effect of the semiconductor unit 400 .

[0056] As shown in FIG. 14, a plurality of secondary adhesive structures 32″ are disposed on the carrier 30 and are separated from each other, and the secondary adhesive structures 32″ are located below the semiconductor units 222 and have a width approximately equal to that of the semiconductor units 222. Between two adjacent secondary adhesive structures 32″, there is a passage 63 with a distance greater than 0. For the method of transferring the semiconductor units 222 in the semiconductor element array structure 6001, reference can be made to FIG. 5A-FIG. 5D, FIG. 6A-FIG. 6C, FIG. 10A-FIG. 10E, FIG. 12A-FIG. 12D, FIG. 13A-FIG. 13C and related paragraphs. Wherein, when the laser energy is applied to the semiconductor units 222, only the first bonding pads 53a embedded in the secondary adhesive structures 32″ are transformed into arc-shaped conductive bumps (not shown), thereby reducing the adhesive force between the semiconductor units 222 and the carrier 30 (secondary adhesive structures 32″).

[0057] It should be understood that the various embodiments of the present disclosure can be combined or substituted for each other under appropriate circumstances, and are not limited to the particular embodiments described, for example, in the various embodiments, the semiconductor units and semiconductor devices can include a growth substrate or can not include a growth substrate.

[0058] Each embodiment recited in this disclosure is used only to illustrate the present disclosure and is not intended to limit the scope of the present disclosure. Any obvious and easily understood modifications or changes made to the present disclosure by any person shall not depart from the spirit and scope of the present disclosure. [Explanation of symbols]

[0059] 1000, 1001, 1003, 2000, 3000, 3001, 5000, 5001, 6001 Semiconductor element array structure 1, 1', 20, 20' Semiconductor element 10, 30, 5301 Board 2a-1 Part 1 2a-2 2nd part 2, 2a, 2b Conductive bump 3, 3a, 3b electrode 4, 32'' secondary adhesive structure 4, 32 Adhesive structure 5a 1st hole 5b 2nd hole 6a, 6b Recess 6a', 6b' recessed area 7 particles 11 First semiconductor layer 12 Active layer 13 Second semiconductor layer 14 Semiconductor Overlay Layer 15 Protective layer 15', 17 lower surface 16 Platform 18 areas 19 Outermost edge 21a, 21b top 22, 22a, 22b outermost surface 23a, 23b, 53a, 53b Bonding pads 24a, 24b, 32', 54a, 54b outer surface 30 Carrier 33, P area 34 Indentation Aisles 35, 53, 63 40,500 relocation structure 41, 504 Gripping part 42 Outer edge 43 High ground 44 Continuous section 50, 70 target board 77 Transparent conductive layer 80, 83, 84 Adhesive 81 Resin 82 Conductive Particles 151, 1051 Upper surface 180 Surface circuit 200, 200', 300, 400 Semiconductor Units 501 Gripping surface 502 Adhesive layer 503 Supporter layer 5300 Photomask 5302 Light-shielding metal layer 5305 Aperture A-A', B-B', C-C', D-D' line segment D, D1 distance H1, H2 thickness L1, L2, L3, L4, L5, L6 Laser Energy W1, W2, W3, W4, W5, W6 width θ1, θ2 included angle

Claims

1. a substrate having an upper surface; an adhesive structure located on the upper surface and having a first recessed region; a first semiconductor element, a lower surface facing the adhesive structure and not in contact with the adhesive structure; a first semiconductor element having a conductive bump located below the lower surface, the conductive bump having a first portion that contacts the adhesive structure within the first recessed area and a second portion that does not contact the adhesive structure within the first recessed area.

2. 2. The semiconductor element structure of claim 1, further comprising a second semiconductor element, the second semiconductor element comprising a bonding pad, the adhesive structure further comprising a second recessed region, and in a cross-sectional view, the bonding pad has a shape corresponding to the second recessed region.

3. 3. The semiconductor device structure of claim 2, wherein the bonding pad has a first outer surface, the conductive bump has a second outer surface, and the first outer surface has a recess and / or a rougher texture than the second outer surface.

4. 3. The semiconductor element structure of claim 2, wherein the adhesive structure includes a first adhesive structure and a second adhesive structure separated from each other, and the first semiconductor element is disposed on the first adhesive structure, and the second semiconductor element is disposed on the second adhesive structure.

5. A semiconductor element structure as described in claim 3, wherein the second outer surface is arc-shaped.

6. The semiconductor device structure of claim 1 , wherein the first adhesive structure has a first maximum width and the first semiconductor device has a second maximum width, and the first maximum width is approximately equal to the second maximum width.

7. a substrate having an upper surface; an adhesive structure located on the upper surface; a first semiconductor element and a second semiconductor element disposed on the adhesive structure, applying laser energy to the first semiconductor element such that an adhesive force between the first semiconductor element and the adhesive structure is smaller than an adhesive force between the second semiconductor element and the adhesive structure; providing a transfer structure that simultaneously contacts the first semiconductor element and the second semiconductor element, wherein an adhesive force between the transfer structure and the first semiconductor element is greater than an adhesive force between the second semiconductor element and the adhesive structure; and The method of fabricating a semiconductor device structure further comprises: moving the transfer structure to transport the first semiconductor device to the transfer structure.

8. 8. The method of claim 7, further comprising providing a photomask having an opening, wherein the laser energy is applied to the one semiconductor element through the opening.

9. 8. The method of claim 7, wherein the first semiconductor element includes a first conductive bonding pad, and after the step of applying laser energy, the shape of the first conductive bonding pad is modified.

10. A method for manufacturing a semiconductor element structure as described in claim 7, wherein the first semiconductor element includes a first conductive bonding pad, the second semiconductor element includes a second conductive bonding pad, and after the step of applying laser energy, the contact area between the first conductive bonding pad and the adhesive structure is smaller than the contact area between the second conductive bonding pad and the adhesive structure.

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