Signal output circuit

Abstract

To increase surge resistance in a signal output circuit.SOLUTION: A signal output circuit includes: an output stage (110) having a plurality of output transistors connected in series between an output terminal (OUT) and a reference terminal (GND); gate wiring (Wa) to which gates of respective output transistors are commonly connected; a drive circuit (4) for conducting or breaking an electrical path between the output terminal and the reference terminal through the output stage by supplying a gate signal to the gate wiring; an insertion transistor (121) inserted between the gate wiring and the reference terminal; and surge response circuits (122 and 123) connected to the output terminal, the reference terminal, and a control electrode of the insertion transistor, for turning off the respective output transistors by turning on the insertion transistor through driving the control electrode of the insertion transistor based on a surge voltage of specific polarity when the surge voltage of the specific polarity is applied at the output terminal seen from the reference terminal.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a protection circuit and an electronic component. [Background technology]

[0002] 2. Description of the Related Art Circuits are used to protect internal circuits of various electronic components from surge voltages caused by static electricity or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-158154 A Summary of the Invention [Problem to be solved by the invention]

[0004] Protection is also required for the output terminals for signal output, but there is room for improvement in technology for increasing the surge resistance of the output terminals.

[0005] An object of the present disclosure is to provide a signal output circuit that contributes to improving surge resistance. [Means for solving the problem]

[0006] The signal output circuit of the present disclosure comprises an output stage having a plurality of output transistors connected in series between an output terminal and a reference terminal, a gate wiring to which the gates of each output transistor are commonly connected, a drive circuit configured to connect or disconnect an electrical path between the output terminal and the reference terminal via the output stage by supplying a gate signal to the gate wiring, an insertion transistor inserted between the gate wiring and the reference terminal, and a surge response circuit connected to the output terminal, the reference terminal, and a control electrode of the insertion transistor, and configured to turn on the insertion transistor by driving the control electrode of the insertion transistor based on the surge voltage of the specific polarity when a surge voltage of the specific polarity is applied to the output terminal as viewed from the reference terminal, thereby turning off each output transistor. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a signal output circuit that contributes to improving surge resistance. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic configuration diagram of an electronic component according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the electronic component according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a configuration diagram of electronic components and peripheral circuits in a state where the electronic components and peripheral circuits are installed in a device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of an output block and peripheral circuits according to a first reference example. [Diagram 5] FIG. 5 is a circuit diagram of an output block and peripheral circuits according to a second reference example. [Figure 6] FIG. 6 is a diagram for explaining behavior when a surge occurs according to the second reference example. [Figure 7] FIG. 7 is a characteristic diagram of an output transistor according to the second reference example. [Figure 8]FIG. 8 is a characteristic diagram of an electrostatic protection element according to the second reference example. [Figure 9] FIG. 9 is a circuit diagram of an output block and peripheral circuits according to an example EX_A1 belonging to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram for explaining behavior at the time of surge occurrence, relating to Example EX_A1 belonging to the embodiment of the present disclosure. [Figure 11] FIG. 11 is a characteristic diagram of an output transistor according to Example EX_A1 belonging to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a circuit diagram of an output block and peripheral circuits according to an example EX_A2 belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a circuit diagram of an output block and peripheral circuits according to an example EX_A3 belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a circuit diagram of an output block and peripheral circuits according to Example EX_A4 belonging to the embodiment of the present disclosure. [Figure 15] FIG. 15 is a circuit diagram of an output block and peripheral circuits according to Example EX_A5 belonging to the embodiment of the present disclosure. [Figure 16] FIG. 16 is a circuit diagram of an output block and peripheral circuits according to an example EX_B1 belonging to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram for explaining behavior at the time of surge occurrence according to Example EX_B1 belonging to the embodiment of the present disclosure. [Figure 18] FIG. 18 is a circuit diagram of an output block and peripheral circuits according to an example EX_B2 belonging to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a circuit diagram of an output block and peripheral circuits according to an example EX_B3 belonging to an embodiment of the present disclosure. [Figure 20] FIG. 20 is a circuit diagram of an output block and peripheral circuits according to an example EX_B4 belonging to an embodiment of the present disclosure. [Figure 21] FIG. 21 is a circuit diagram of an output block and peripheral circuits according to an example EX_B5 belonging to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a block diagram of a signal output circuit according to Example EX_C1 belonging to the embodiment of the present disclosure. [Diagram 23] FIG. 23 is a diagram illustrating a configuration example of a signal output circuit according to an example EX_C1 belonging to an embodiment of the present disclosure. [Figure 24] FIG. 24 is a diagram showing another configuration example of the signal output circuit according to Example EX_C1 belonging to the embodiment of the present disclosure. [Diagram 25] FIG. 25 is a diagram showing still another configuration example of the signal output circuit according to Example EX_C1 belonging to the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, examples of the embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a rule. In this specification, for the sake of simplicity, a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, etc. may be written, and the name of the information, signal, physical quantity, functional part, circuit, element, or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, the output terminal referred to by "OUT" described later (see FIG. 1) may be written as output terminal OUT or abbreviated as terminal OUT, but they all refer to the same thing.

[0010] First, some terms used in describing the embodiments of the present disclosure are explained. A level refers to a level of potential, and a high level has a higher potential than a low level for any signal or voltage of interest.

[0011] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on-state refers to the state where the drain and source of the transistor are conducting, and the off-state refers to the state where the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source. Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off, respectively.

[0012] Regarding the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., unless otherwise specified, it may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0014] Fig. 1 shows a schematic configuration of an electronic component 1 according to an embodiment of the present disclosure. The electronic component 1 includes a functional circuit 2 and a signal output circuit 3. The signal output circuit 3 includes a drive circuit 4 and an output block 5. The electronic component 1 is also provided with a power supply terminal VDD, an output terminal OUT, and a ground terminal GND. As internal wiring provided in the electronic component 1, power supply wiring W VDD , output wiring W OUT and ground wiring W GND are shown. The power supply wiring W VDD is connected to the power supply terminal VDD. The output terminal OUT is connected to the output wiring W OUT . The ground terminal GND is connected to the ground wiring W GNDIn relation to the output terminal OUT, the power supply terminal VDD and the ground terminal GND can also be called reference terminals.

[0015] The functional circuit 2 and the driving circuit 4 are each connected to a power supply wiring W VDD and ground wiring W GND The output block 5 is connected to at least the output wiring W OUT Furthermore, the output block 5 is connected to the power supply wiring W VDD and ground wiring W GND 1. The connection is not shown in FIG. 1.

[0016] FIG. 2 is an external perspective view of the electronic component 1. The electronic component 1 is a component (semiconductor device) formed by sealing a semiconductor integrated circuit in a housing (package) made of resin, and each circuit constituting the electronic component 1 is integrated with a semiconductor. The semiconductor integrated circuit is formed on a semiconductor substrate, and a functional circuit 2 and a signal output circuit 3 can be included in the semiconductor integrated circuit. The housing of the electronic component 1 is provided with a plurality of external terminals exposed from the housing to the outside of the electronic component 1. The power supply terminal VDD, the output terminal OUT, and the ground terminal GND are some of the plurality of external terminals provided on the electronic component 1. Other external terminals are also provided on the electronic component 1. Note that the number of external terminals and the type of housing shown in FIG. 2 are merely examples and are arbitrary.

[0017] Various devices can be configured using the electronic component 1. When the electronic component 1 is incorporated in a device (hereinafter referred to as an "apparatus-embedded state"), as shown in FIG. 3, the electronic component 1 receives a power supply voltage V PWR Specifically, when the DC voltage source VS is installed in the device, the negative output terminal and the ground terminal GND are connected to a ground having a potential of 0V, while the positive output terminal of the DC voltage source VS is connected to a power supply terminal VDD. The DC voltage source VS receives a positive power supply voltage V from its positive output terminal with respect to the potential of its negative output terminal. PWR Therefore, when the device is installed, the positive power supply voltage V is applied to the power supply terminal VDD as viewed from the ground terminal GND.PWR is added.

[0018] When the function circuit 2 and the signal output circuit 3 are installed in the device, the power supply voltage V PWR The electronic component 1 operates based on the above. In the state where the electronic component 1 is incorporated in the device, the functional circuit 2 executes a predetermined functional operation. For example, the electronic component 1 may be a component of a switching regulator and may be a power supply control device (so-called power supply IC) that controls the operation of the switching regulator. The switching regulator generates an output voltage by stepping down or stepping up an input voltage. In this case, the functional circuit 2 controls the switching of a switching element that switches the input voltage in the functional operation. Alternatively, for example, the electronic component 1 may be a component of a motor drive system and may be a motor driver that controls the drive of a three-phase motor. In this case, the functional circuit 2 supplies a necessary drive voltage (for example, a sinusoidal drive voltage obtained by using pulse width modulation) to the coils of each phase of the three-phase motor in the functional operation. In addition, the electronic component 1 may be a component that realizes an arbitrary functional operation (for example, a reset IC, an LED driver).

[0019] In the device-installed state, the output terminal OUT is connected to an external circuit EX provided outside the electronic component 1. The functional operation includes a signal output operation realized by using the signal output circuit 3. In the signal output operation, under the control of the functional circuit 2, the output block 5 outputs an output signal S OUT The output signal S is output to the external circuit EX through the output terminal OUT. OUT has a signal potential of low level or high level. Specifically, in the device-integrated state, the functional circuit 2 supplies the control signal CNT having a value of "0" or "1" to the driving circuit 4, and the driving circuit 4 controls the output block 5 in response to the control signal CNT. In the device-integrated state, when the driving circuit 4 receives the control signal CNT having a value of "0", it outputs a low-level output signal S to the output block 5. OUT On the other hand, when the control signal CNT having a value of "1" is received, the output block 5 outputs a high-level output signal S OUT The value of the control signal CNT and the output signal S OUTThe relationship between the levels can also be reversed from that described above.

[0020] The state in which the electronic component 1 is not incorporated into a device is called the component stand-alone state. In the component stand-alone state, a surge voltage may be applied between the output terminal OUT and the ground terminal GND, between the output terminal OUT and the power supply terminal VDD, or between the power supply terminal VDD and the ground terminal GND. The surge voltage is a voltage that is generated for a very short time due to static electricity, etc., and the magnitude of the surge voltage is 100 times the power supply voltage V PWR A surge protection circuit (not shown) that protects the functional circuit 2 and the drive circuit 4 from a surge voltage applied between the power supply terminal VDD and the ground terminal GND is provided in the electronic component section 1. The surge protection circuit may have any configuration, including a known configuration.

[0021] In the present embodiment, attention is focused on a configuration for protecting the output block 5 from a surge voltage applied between the output terminal OUT and the ground terminal GND, or between the output terminal OUT and the power supply terminal VDD. In the following description, the electronic component 1 is assumed to be in a standalone state unless otherwise specified.

[0022] FIG. 4 shows an output block 900A and peripheral circuits according to a first reference example. The output block 900A realizes a signal output circuit with an open drain configuration. The output block 900A includes a single output transistor 910 and an electrostatic protection element 930. The output transistor 910 is an N-channel MOSFET. The drain and source of the output transistor 910 are connected to the output terminal OUT and the ground terminal GND, respectively. In the first reference example, the drive circuit 4 is connected to the gate of the output transistor 910. The electrostatic protection element 930 is connected to the terminals OUT and GND, and protects the output stage (the output transistor 910 in the first reference example of FIG. 4) from a surge voltage applied between the output terminal OUT and the ground terminal GND.

[0023] In the first reference example, the withstand voltage between the terminals OUT and GND is limited to the withstand voltage of a single MOSFET or less. There is also a demand for an increase in the withstand voltage between the terminals OUT and GND. In order to meet this demand, a method of configuring an output stage with a series circuit of multiple MOSFETs is being considered.

[0024] FIG. 5 shows an output block 900B and its peripheral circuits according to the second reference example. The output block 900B also realizes a signal output circuit with an open drain configuration. The output block 900B includes output transistors 911H and 911L and an electrostatic protection element 930 connected in series between the output terminal OUT and the ground terminal GND. The output transistors 911H and 911L are N-channel MOSFETs having the same structure and characteristics. In the second reference example, an output stage is configured by a series circuit of a plurality of MOSFETs. Specifically, the drain of the output transistor 911H is connected to the output terminal OUT, the source of the output transistor 911H and the drain of the output transistor 911L are connected to each other, and the source of the output transistor 911L is connected to the ground terminal GND. In the second reference example, the gates of the output transistors 911H and 911L are connected to each other, and the drive circuit 4 is connected to the gates of the output transistors 911H and 911L. The electrostatic protection element 930 is connected to the terminals OUT and GND, and protects the output stage (output transistors 911H and 911L in the second reference example of FIG. 5) from a surge voltage applied between the terminals OUT and GND.

[0025] In the second reference example, the withstand voltage between the terminals OUT and GND is greater than in the first reference example. However, the withstand voltage between the terminals OUT and GND in the second reference example is not twice that of the first reference example. This will be explained with reference to Figs. 6 and 7. Now, in the second reference example, as shown in Fig. 6, assume that a positive surge voltage is applied to the output terminal OUT as viewed from the ground terminal GND. At this time, the output wiring W OUTThe gate voltage Vg of the output transistors 911H and 911L increases through the parasitic capacitance between the gate of the output transistor 911H and the gate of the output transistor 911H, and the channels of the output transistors 911H and 911L become conductive. The drain currents of the output transistors 911H and 911L generated in the above case are represented by the symbols "Id_H" and "Id_L", respectively. The drain-source voltage of the output transistor 911H generated in the above case is represented by the symbol "Vds_H", and the drain-source voltage of the output transistor 911L is represented by the symbol "Vds_L". Due to the surge voltage, a surge current flows through an electric path passing through the output transistors 911H and 911L and an electric path passing through the electrostatic protection element 930. The surge current flowing through the former electric path is called a surge current Isg. Therefore, "Isg=Id_H=Id_L".

[0026] 7 shows the relationship between the drain-source voltage Vds and the drain current Id in an arbitrary output transistor (here, output transistor 911H or 911L). Waveform 951 shows the relationship when the gate-source voltage Vgs of the output transistor is 0V, waveform 952 shows the relationship when the gate-source voltage Vgs of the output transistor is 1V, and waveform 953 shows the relationship when the gate-source voltage Vgs of the output transistor is 2V.

[0027] For the sake of concrete explanation, consider a case where the gate voltage Vg rises to 2V due to the occurrence of the positive surge voltage. In this case, the gate-source voltage Vgs_L of the output transistor 911L becomes 2V, so the output transistor 911L follows the waveform 953. At this time, it is assumed that the drain-source voltage Vds_L is 1V. In this case, the gate-source voltage Vgs_H of the output transistor 911H becomes 1V (=Vg-Vds_L), so the output transistor 911L follows the waveform 952.

[0028] Thus, in the above case, "Vgs_L > Vgs_H". In FIG. 7, plots 955L and 955H represent the operating points of output transistors 911L and 911H, respectively, when the gate voltage Vg has risen to 2V. Since the drain currents Id_H and Id_L based on the surge voltage are equal, inevitably "Vds_L < Vds_H". When the voltage Vds_H at the operating point 955H is equal to the breakdown voltage of the output transistor 911H, the combined breakdown voltage of the output transistors 911H and 911L is the sum of the voltage Vds_H at the operating point 955H and the voltage Vds_L at the operating point 955L. That is, the combined breakdown voltage of the output transistors 911H and 911L does not become twice the breakdown voltage of a single output transistor (it becomes much smaller than twice).

[0029] In FIG. 8, characteristic 960 shows the IV characteristic of the electrostatic protection element 930. In FIG. 8, the dashed line 962 indicates the breakdown voltage of a single output transistor, and the dashed line 964 indicates twice the breakdown voltage of a single output transistor. In the second reference example, two output transistors are connected in series, but the breakdown voltage according to the dashed line 964 cannot be obtained, and the actual breakdown voltage is like the dashed line 963. In the characteristic of the dashed line 963, before the electrostatic protection element 930 breaks down, the voltage between the terminal OUT and GND may exceed the breakdown voltage of the output stage (911H and 911L), and proper protection of the output stage cannot be obtained.

[0030] Embodiments of the present disclosure include the following Examples EX_A1 to EX_A5, EX_B1 to EX_B5, and EX_C1. The configurations and operations for realizing proper protection of the output stage will be described in these examples. The matters described above in this embodiment are applied to the following respective examples (except for the matters related to the first and second reference examples) unless otherwise specified and without contradiction. Regarding matters conflicting with the above-described matters in each example, the description in each example may take precedence. Also, without contradiction, matters described in any one of the following plurality of examples can be applied to any other example (that is, it is also possible to combine any two or more of the plurality of examples).

[0031] [Example EX_A1] An example EX_A1 will be described. An output block 100_A1 according to the example EX_A1 and its peripheral circuits are shown in Fig. 9. In the example EX_A1, the output block 100_A1 is used as the output block 5 in Fig. 1.

[0032] The output block 100_A1 includes an output stage 110 including output transistors 111 and 112, a gate-off circuit 120 including an insert transistor 121, a capacitor 122, a resistor 123, and a current limiting resistor 124, and a clamp circuit 130. The output transistors 111 and 112 are configured by N-channel MOSFETs. The output transistors 111 and 112 may have the same structure and characteristics. The insert transistor 121 is configured by an NPN bipolar transistor.

[0033] The output transistors 111 and 112 are connected in series between the terminals OUT and GND. OUT (and therefore connected to the output terminal OUT). The source of the output transistor 111 is connected to the drain of the output transistor 112. The source of the output transistor 112 is connected to the ground wiring W. GND (and therefore connected to the ground terminal GND). The gates of the output transistors 111 and 112 are commonly connected to a gate wiring Wa.

[0034] The drive circuit 4 is connected to the gate wiring Wa. In the device-installed state, the drive circuit 4 supplies a high-level or low-level gate signal to the gate wiring Wa. When a high-level gate signal is supplied to the gate wiring Wa, the output transistors 111 and 112 are both turned on, and an electrical path between the terminals OUT and GND via the output stage 110 is made conductive. When a low-level gate signal is supplied to the gate wiring Wa, the output transistors 111 and 112 are both turned off, and the above-mentioned electrical path is interrupted. The output block 100_A1 forms a signal output circuit 3 with an open drain configuration. Therefore, in the device-installed state, for example, outside the electronic component 1, a wiring connected to the output terminal OUT and a power supply voltage V PWR Alternatively, a pull-up resistor may be inserted between the line and another line to which a positive power supply voltage is applied.

[0035] The insert transistor 121 is connected to the gate wiring Wa and the ground wiring W GND Specifically, the collector of the insertion transistor 121 is connected to the gate wiring Wa, and the emitter of the insertion transistor 121 is connected to the ground wiring W GND (and therefore connected to the ground terminal GND).

[0036] The first end of the capacitor 122 is connected to the output wiring W OUT A second end of the capacitor 122 is connected to a predetermined node 125. A first end of the resistor 123 is connected to the node 125. A second end of the resistor 123 is connected to the ground wiring W. GND The current-limiting resistor 124 is inserted in series between the node 125 and the base of the insertion transistor 121. More specifically, a first end of the current-limiting resistor 124 is connected to the node 125, and a second end of the current-limiting resistor 124 is connected to the base of the insertion transistor 121.

[0037] The clamp circuit 130 is connected in parallel to the output stage 110. The clamp circuit 130 is connected to the output wiring W OUT and ground wiring W GNDThe clamp circuit 130 is configured with one or more protection diodes 131 (electrostatic protection elements). When the clamp circuit 130 is configured with a single protection diode 131, the anode of the protection diode 131 is connected to the ground wiring W. GND , while the cathode of the protection diode 131 is connected to the output wiring W OUT When the clamp circuit 130 is configured with a series circuit of a plurality of protection diodes 131, the forward direction of each protection diode 131 is connected to the ground wiring W. GND From output wiring W OUT For example, when the clamp circuit 130 is configured with the first and second protection diodes 131, the cathode of the first protection diode 131 is connected to the output wiring W. OUT , the anode of the first protection diode 131 is connected to the cathode of the second protection diode 131, and the anode of the second protection diode 131 is connected to the ground wiring W GND In the following, unless otherwise specified, it is assumed that the clamp circuit 130 is configured with a single protection diode 131.

[0038] Referring to Figure 10, a positive surge voltage V SGP The behavior of the output block 100_A1 in the positive surge case CS1 will be described assuming a positive surge voltage V SGP is an example of a surge voltage of a specific polarity. Note that FIG. 10 also illustrates the parasitic capacitance added to each output transistor. The drain-source voltage of the output transistor 111 is represented by the symbol “V DSH " and the drain-source voltage of the output transistor 112 is represented by the symbol "V DSL In the positive surge case CS1, the current flowing from the output terminal OUT through the output stage 110 to the ground terminal GND is called the surge current I SG1 The current flowing from the output terminal OUT through the clamp circuit 130 to the ground terminal GND is called the surge current I SG2 It is called.

[0039] Surge voltage V SGPis a voltage that occurs for a very short time due to static electricity or the like, and in the positive surge case CS1, the potential of the output terminal OUT rises steeply from the potential of the ground terminal GND. Therefore, in the positive surge case CS1, a surge voltage V SGP The surge response signal RP1 is generated based on the surge voltage V SGP The waveform is roughly similar to that of the surge voltage V SGP In conjunction with the rise and fall of the surge response signal RP1, the potential of the surge response signal RP1 also rises and falls. The surge response signal RP1 generates a base current in the insert transistor 121, turning the insert transistor 121 on. When the insert transistor 121 is on, the potential of the gate wiring Wa rises and falls to the ground wiring W GND Since the potential of the output transistor 111 and the output transistor 112 are both turned off, the output transistors 111 and 112 are both turned off.

[0040] In addition, a positive surge voltage V SGP Immediately after the application of the voltage, the potential of the gate wiring Wa temporarily rises compared to the potential of the ground wiring WGND due to the influence of the parasitic capacitance added to the output stage 110, and as a result, the output transistors 111 and 112 may be turned on for a very short time before the insertion transistor 121 is turned on. However, since this very short time is sufficiently short (for example, a few nanoseconds), no damage is caused to the output transistors 111 and 112.

[0041] FIG. 11 shows the drain-source voltage V DS and the drain current I D Waveform 651 represents the relationship between the gate-source voltage V GS is 0V, and waveform 652 shows the relationship when the gate-source voltage V GS is 1V, and waveform 653 shows the relationship when the gate-source voltage V GS 7. This relationship is shown when the input voltage Vout is 2 V. Waveforms 651 to 653 are equivalent to waveforms 951 to 953 in FIG.

[0042] In the positive surge case CS1 according to this embodiment, the gate-source voltage V GS is maintained at approximately 0 V. This causes a surge current I SG1 is a current that flows only through the parasitic capacitance of the output transistors 111 and 112 and is sufficiently small. SG1 flows equally through the output transistors 111 and 112, so the drain-source voltage V DSH and the drain-source voltage V DSL In FIG. 11, plot 655 shows a surge voltage V between terminals OUT and GND. SGP represents the operating points of the output transistors 111 and 112 when

[0043] In the positive surge case CS1, a voltage according to the magnitude of the surge and the characteristics of the clamp circuit 130 is generated between the terminals OUT and GND, and a surge current I SG2 flows.

[0044] The protection diode 131 is a short-term surge voltage V SGP The protection diode 131 is a component designed to be able to withstand the application of a surge voltage V. The reverse breakdown voltage is defined as an electrical characteristic of the protection diode 131. The reverse breakdown voltage is also called Zener voltage. Of the voltages applied to the protection diode 131, the voltage that makes the cathode potential of the protection diode 131 higher than the anode potential of the protection diode 131 is called the reverse voltage. The current that flows from the cathode to the anode of the protection diode 131 is called the reverse current. When the reverse voltage of the protection diode 131 reaches the reverse breakdown voltage, the reverse current becomes considerably large, and in the region where the reverse voltage is equal to or higher than the reverse breakdown voltage, the reverse current increases sharply as the reverse voltage increases. Surge voltage V SGP Although it depends on the amount of static charge that causes the surge current, it is typically I SG2 The surge current I SG1 Much larger than .

[0045] The output stage 110 and the clamp circuit 130 are designed so that the reverse breakdown voltage of the protection diode 131 is smaller than the withstand voltage of the output stage 110. SGP When a surge voltage V SGP Based on surge current I SG2 By passing through it, the magnitude of the voltage generated between the terminals OUT and GND is limited to less than the withstand voltage of the output stage 110. The withstand voltage of the output stage 110 is the sum of the withstand voltages of the output transistors 111 and 112. The withstand voltage of the output transistor 111 may be understood to refer to the withstand voltage between the drain and source of the output transistor 111 when the gate-source voltage of the output transistor 111 is 0V. The same applies to the other output transistor (here, output transistor 112).

[0046] In the positive surge case CS1, the voltage V DSH Although the surge current I SG1 is very small, so the output transistor 111 can withstand it sufficiently. The same applies to the output transistor 112. In addition, in the case where a negative surge voltage is applied to the output terminal OUT as viewed from the ground terminal GND, a surge current based on the negative surge voltage flows through the protective diode 131 in the forward direction of the protective diode 131, so that the voltage generated between the terminals OUT and GND is sufficiently small.

[0047] In this manner, the gate-off circuit 120 prevents a positive surge voltage V SGP When the potential of the gate line Wa is applied, the potential of the ground line W GND or ground wiring W GNDThe output transistors 111 and 112 are turned off by lowering the potential of the gate-off circuits 120a to 120c to be described later (the same applies to the gate-off circuits 120a to 120c; see FIGS. 12 to 14). In the gate-off circuit 120, a surge response circuit is formed by a capacitor 122 and a resistor 123. The surge response circuit (122, 123) detects a positive surge voltage V SGP When applied, the surge voltage V SGP The control electrode (base) of the insert transistor 121 is driven based on the surge response signal RP1 to turn on the insert transistor 121, thereby turning off the output transistors 111 and 112. The current limiting resistor 124 limits the base current to the insert transistor 121 based on the surge response signal RP1 so that the base current does not become excessive.

[0048] According to this embodiment, the withstand voltage of the output stage can be increased by the number of stacked output transistors in the output stage. That is, according to the output block 100_A1, the withstand voltage of the output stage 110 can be increased to twice the withstand voltage of one output transistor.

[0049] [Example EX_A2] An example EX_A2 will be described. An output block 100_A2 according to the example EX_A2 and its peripheral circuits are shown in Fig. 12. In the example EX_A2, the output block 100_A2 is used as the output block 5 in Fig. 1.

[0050] The output block 100_A2 is obtained by performing a first substitution on the output block 100_A1 of FIG. 9. The first substitution corresponds to replacing the capacitor 122 of FIG. 9 with a Zener diode 126. Except for the first substitution, the output blocks 100_A1 and 100_A2 have the same configuration. In the output block 100_A2, the anode of the Zener diode 126 is connected to the node 125, and the cathode of the Zener diode 126 is connected to the output wiring W. OUT(and therefore connected to the output terminal OUT). The gate-off circuit in the output block 100_A2 is a gate-off circuit 120a including an insertion transistor 121, a Zener diode 126, a resistor 123, and a current limiting resistor .

[0051] In the output block 100_A2, in the above-mentioned positive surge case CS1, the surge voltage V SGP The magnitude of exceeds the Zener voltage of the Zener diode 126, and the surge voltage V SGP A surge response signal RP1 based on this is generated at a node 125 (see FIG. 10). Therefore, similarly to the embodiment EX_A1, the insert transistor 121 is turned on based on the surge response signal RP1, and the output transistors 111 and 112 are turned off.

[0052] In the gate-off circuit 120a, a surge response circuit is formed by a Zener diode 126 and a resistor 123. The surge response circuit (126, 123) detects a positive surge voltage V SGP is applied (see FIG. 10), a surge response signal RP1 occurs at node 125 accompanied by a breakdown phenomenon (zener phenomenon or avalanche phenomenon) of zener diode 126, turning on the insertion transistor 121 and thereby turning off each of the output transistors 111 and 112.

[0053] [Example EX_A3] An example EX_A3 will be described. An output block 100_A3 according to the example EX_A3 and its peripheral circuits are shown in Fig. 13. In the example EX_A3, the output block 100_A3 is used as the output block 5 in Fig. 1.

[0054] The output block 100_A3 is obtained by performing a second substitution on the output block 100_A1 in FIG. 9. The second substitution corresponds to replacing the insert transistor 121 in FIG. 9 with an insert transistor 127. With the second substitution, the current limiting resistor 124 is omitted in the output block 100_A3. Except for the second substitution, the output blocks 100_A1 and 100_A3 have the same configuration. The insert transistor 127 is an N-channel MOSFET. In the output block 100_A3, the drain of the insert transistor 127 is connected to the gate wiring Wa, and the source of the insert transistor 127 is connected to the ground wiring W. GND , and the gate of the insert transistor 127 is connected to a node 125. The gate-off circuit in the output block 100_A3 is a gate-off circuit 120b that is composed of the insert transistor 127, a capacitor 122, and a resistor 123.

[0055] The surge response circuit (122, 123) in the output block 100_A3 applies a positive surge voltage V SGP When the surge response signal RP1 is applied, the voltage at node 125 (the voltage of the surge response signal RP1) is supplied to the control electrode (gate) of the insertion transistor 127 to turn on the insertion transistor 127, thereby turning off each of the output transistors 111 and 112.

[0056] [Example EX_A4] An example EX_A4 will be described. FIG. 14 shows an output block 100_A4 according to the example EX_A4 and its peripheral circuit. In the example EX_A4, the output block 100_A4 is used as the output block 5 of FIG. 1. The output block 100_A4 is obtained by performing the above-mentioned first and second substitutions on the output block 100_A1 of FIG. 9. Therefore, the gate-off circuit in the output block 100_A4 is a gate-off circuit 120c having an insertion transistor 127, a Zener diode 126, and a resistor 123.

[0057] In the output block 100_A4, the anode of the Zener diode 126 is connected to the node 125, and the cathode of the Zener diode 126 is connected to the output wiring W. OUT In the output block 100_A4, the drain of the insert transistor 127 is connected to the gate wiring Wa, and the source of the insert transistor 127 is connected to the ground wiring W. GND , and the gate of insert transistor 127 is connected to node 125.

[0058] In the gate-off circuit 120c, a surge response circuit is formed by a Zener diode 126 and a resistor 123. The surge response circuit (126, 123) detects a positive surge voltage V SGP is applied (see FIG. 10), a surge response signal RP1 occurs at node 125 accompanied by a breakdown phenomenon (zener phenomenon or avalanche phenomenon) of zener diode 126, turning on insertion transistor 127 and thereby turning off each of output transistors 111 and 112.

[0059] [Example EX_A5] An example EX_A5 will be described. In the examples EX_A1 to EX_A4, the total number of output transistors provided in the output stage 110 is arbitrary as long as it is two or more, and the output stage 110 may be formed by a series circuit of three or more output transistors. As an example, an output block 100_A5 and its peripheral circuits are shown in FIG. 15. The output block 100_A5 can be used as the output block 5 in FIG. 1.

[0060] Output block 100_A5 is obtained by performing a third substitution on output block 100_A1 of FIG. 9. The third substitution corresponds to replacing output stage 110 of FIG. 9 with output stage 110a. Except for the third substitution, output blocks 100_A1 and 100_A5 have the same configuration as each other. Output stage 110a is composed of output transistors 111-113. Output transistors 111-113 are N-channel type MOSFETs. Output transistors 111-113 may have the same structure and characteristics as each other.

[0061] In the output block 100_A5, the output transistors 111 to 113 are connected in series to each other between the terminals OUT and GND. OUT , the source of the output transistor 111 is connected to the drain of the output transistor 112, the source of the output transistor 112 is connected to the drain of the output transistor 113, and the source of the output transistor 113 is connected to the ground wiring W GND The gates of the output transistors 111 to 113 are commonly connected to a gate wiring Wa, which makes it possible to increase the withstand voltage of the output stage 110a to three times that of one output transistor.

[0062] The matters described in the embodiment EX_A1 are also applied to the output block 100_A5. However, in this application, the output stage 110 in the embodiment EX_A1 is replaced with the output stage 110a in the embodiment EX_A5, and the output transistors 111 and 112 in the embodiment EX_A1 are replaced with the output transistors 111 to 113 in the embodiment EX_A5. The output stage 110a may be a series circuit of four or more output transistors. The third substitution may be applied to the output blocks 100_A2, 100_A3, or 100_A4.

[0063] [Example EX_B1] An embodiment EX_B1 will be described. The output block 5 of FIG. 1 may be provided between the terminals OUT and VDD. In this case, the configuration of the output block described in each of the above embodiments may be applied to the output block between the terminals OUT and VDD. This will be described. FIG. 16 shows an output block 200_B1 according to the embodiment EX_B1 and its peripheral circuit. In the embodiment EX_B1, the output block 200_B1 is used as the output block 5 of FIG. 1.

[0064] The output block 200_B1 includes an output stage 210 including output transistors 211 and 212, a gate-off circuit 220 including an insert transistor 221, a capacitor 222, a resistor 223, and a current limiting resistor 224, and a clamp circuit 230. The output transistors 211 and 212 are configured by P-channel MOSFETs. The output transistors 211 and 212 may have the same structure and characteristics. The insert transistor 221 is configured by a PNP bipolar transistor.

[0065] The output transistors 211 and 212 are connected in series between the terminals OUT and VDD. OUT (and therefore connected to the output terminal OUT). The source of the output transistor 211 is connected to the drain of the output transistor 212. The source of the output transistor 212 is connected to the power supply wiring W VDD (and therefore connected to the power supply terminal VDD). The gates of the output transistors 211 and 212 are commonly connected to a gate wiring Wb.

[0066] The driving circuit 4 is connected to the gate wiring Wb. In the device-embedded state, the driving circuit 4 supplies a high-level or low-level gate signal to the gate wiring Wb. When a low-level gate signal is supplied to the gate wiring Wb, the output transistors 211 and 212 are both turned on, and an electric path between the terminals OUT and VDD via the output stage 210 is made conductive. When a high-level gate signal is supplied to the gate wiring Wb, the output transistors 211 and 212 are both turned off, and the electric path is interrupted. The output block 200_B1 forms a signal output circuit 3 having an open drain configuration. Therefore, in the device-embedded state, for example, a pull-down resistor may be inserted between the wiring connected to the output terminal OUT and the wiring having the ground potential outside the electronic component 1.

[0067] The insert transistor 221 is connected to the gate wiring Wb and the power supply wiring W VDDSpecifically, the collector of the insertion transistor 221 is connected to the gate wiring Wb, and the emitter of the insertion transistor 221 is connected to the power supply wiring W VDD (and therefore connected to the power supply terminal VDD).

[0068] The first end of the capacitor 222 is connected to the output wiring W OUT The second end of the capacitor 222 is connected to a predetermined node 225. The first end of the resistor 223 is connected to the node 225. The second end of the resistor 223 is connected to the power supply wiring W. VDD The current-limiting resistor 224 is inserted in series between the node 225 and the base of the insertion transistor 221. More specifically, a first end of the current-limiting resistor 224 is connected to the node 225, and a second end of the current-limiting resistor 224 is connected to the base of the insertion transistor 221.

[0069] The clamp circuit 230 is connected in parallel to the output stage 210. The clamp circuit 230 is connected to the output wiring W OUT and power wiring W VDD The clamp circuit 230 is configured with one or more protection diodes 231 (electrostatic protection elements). When the clamp circuit 230 is configured with a single protection diode 231, the cathode of the protection diode 231 is connected to the power supply wiring W. VDD while the anode of the protection diode 231 is connected to the output wiring W OUT When the clamp circuit 230 is configured with a series circuit of a plurality of protection diodes 231, the forward direction of each protection diode 231 is connected to the output wiring W. OUT From power supply wiring W VDD For example, when the clamp circuit 230 is configured with the first and second protection diodes 231, the anode of the first protection diode 231 faces the output wiring W. OUT , the cathode of the first protection diode 231 is connected to the anode of the second protection diode 231, and the cathode of the second protection diode 231 is connected to the power supply wiring W VDD In the following, unless otherwise specified, it is assumed that the clamp circuit 230 is configured with a single protection diode 231.

[0070] Referring to Figure 17, a negative surge voltage V SGN The behavior of the output block 200_B1 in the negative surge case CS2 will be described assuming a negative surge case CS2 in which a negative surge voltage V SGN is an example of a surge voltage of a specific polarity. Note that FIG. 17 also illustrates the parasitic capacitance added to each output transistor. The drain-source voltage of the output transistor 211 is represented by the symbol “V DS1 " and the drain-source voltage of the output transistor 212 is represented by the symbol "V DS2 In the negative surge case CS2, the current flowing from the power supply terminal VDD through the output stage 210 to the output terminal OUT is represented as a surge current I SG3 The current flowing from the power supply terminal VDD through the clamp circuit 230 to the output terminal OUT is called the surge current I SG4 It is called.

[0071] Surge voltage V SGN is a voltage that occurs for a very short time due to static electricity or the like, and in the negative surge case CS2, the potential of the output terminal OUT drops sharply from the potential of the power supply terminal VDD. Therefore, in the negative surge case CS2, a surge voltage V SGN The surge response signal RP2 is generated based on the surge voltage V SGN The waveform is roughly similar to that of the surge voltage V SGN In conjunction with the fall and rise of the surge response signal RP2, the potential of the surge response signal RP2 also falls and rises. The surge response signal RP2 generates a base current in the insert transistor 221, turning the insert transistor 221 on. When the insert transistor 221 is on, the potential of the gate wiring Wb falls to the potential of the power supply wiring W VDD Therefore, both the output transistors 211 and 212 are turned off.

[0072] In addition, when viewed from the power supply terminal VDD, a negative surge voltage V SGN Immediately after the application of the voltage, the potential of the gate wiring Wb is lowered to the potential of the power supply wiring WVDD As a result, the output transistors 211 and 212 may be turned on for a very short time before the insert transistor 221 is turned on. However, since the very short time is sufficiently short (for example, a few nanoseconds), no damage is caused to the output transistors 211 and 212.

[0073] In the negative surge case CS2 according to this embodiment, the gate-source voltage V GS is maintained at approximately 0 V. This causes a surge current I SG3 is a current that flows only through the parasitic capacitance of the output transistors 211 and 212 and is sufficiently small. SG3 flows equally through the output transistors 211 and 212, the drain-source voltage V DS1 and the drain-source voltage V DS2 are essentially equal.

[0074] In the negative surge case CS2, a voltage according to the magnitude of the surge and the characteristics of the clamp circuit 230 is generated between the terminals OUT and VDD, and a surge current I SG4 flows.

[0075] The protection diode 231 is a short-term surge voltage V SGN The protection diode 231 is a component designed to be able to withstand the application of a surge voltage V. The reverse breakdown voltage is defined as an electrical characteristic of the protection diode 231. The reverse breakdown voltage is also called Zener voltage. Of the voltages applied to the protection diode 231, a voltage that makes the cathode potential of the protection diode 231 higher than the anode potential of the protection diode 231 is called the reverse voltage. A current that flows from the cathode to the anode of the protection diode 231 is called the reverse current. When the reverse voltage of the protection diode 231 reaches the reverse breakdown voltage, the reverse current becomes considerably large, and in a region where the reverse voltage is equal to or higher than the reverse breakdown voltage, the reverse current increases sharply as the reverse voltage increases. Surge voltage V SGNAlthough it depends on the amount of static charge that causes the surge current, it is typically I SG4 The surge current I SG3 Much larger than .

[0076] The output stage 210 and the clamp circuit 230 are designed so that the reverse breakdown voltage of the protection diode 231 is smaller than the withstand voltage of the output stage 210. SGN When a surge voltage V SGN Based on surge current I SG4 By passing through it, the magnitude of the voltage generated between the terminals OUT and VDD is limited to less than the withstand voltage of the output stage 210. The withstand voltage of the output stage 210 is the sum of the withstand voltages of the output transistors 211 and 212. The withstand voltage of the output transistor 211 may be understood to refer to the withstand voltage between the drain and source of the output transistor 211 when the gate-source voltage of the output transistor 211 is 0V. The same applies to the other output transistor (here, the output transistor 212).

[0077] In the negative surge case CS2, the voltage V DS1 Although the surge current I SG3 is very small, so the output transistor 211 can withstand it sufficiently. The same applies to the output transistor 212. In addition, in the case where a positive surge voltage is applied to the output terminal OUT as viewed from the power supply terminal VDD, a surge current based on the positive surge voltage flows through the protective diode 231 in the forward direction of the protective diode 231, so the voltage generated between the terminals OUT and VDD is sufficiently small.

[0078] In this way, the gate-off circuit 220 prevents a negative surge voltage V SGN When the potential of the gate line Wb is applied to the power line W VDD or the power supply wiring W VDDThe output transistors 211 and 212 are turned off by raising the potential of the gate-off circuits 220a to 220c described below (the same applies to the gate-off circuits 220a to 220c; see FIGS. 18 to 20). In the gate-off circuit 220, a surge response circuit is formed by a capacitor 222 and a resistor 223. The surge response circuit (222, 223) detects a negative surge voltage V SGN When applied, the surge voltage V SGN The control electrode (base) of the insert transistor 221 is driven based on the surge response signal RP2 to turn on the insert transistor 221, thereby turning off the output transistors 211 and 212. The current limiting resistor 224 limits the base current to the insert transistor 221 based on the surge response signal RP2 so that the base current does not become excessive.

[0079] According to this embodiment, the withstand voltage of the output stage can be increased by the number of stacked output transistors in the output stage. That is, according to the output block 200_B1, the withstand voltage of the output stage 210 can be increased to twice the withstand voltage of one output transistor.

[0080] [Example EX_B2] An embodiment EX_B2 will be described. An output block 200_B2 according to the embodiment EX_B2 and its peripheral circuits are shown in Fig. 18. In the embodiment EX_B2, the output block 200_B2 is used as the output block 5 in Fig. 1.

[0081] The output block 200_B2 is obtained by performing a fourth substitution on the output block 200_B1 of FIG. 16. The fourth substitution corresponds to replacing the capacitor 222 of FIG. 16 with a Zener diode 226. Except for the fourth substitution, the output blocks 200_B1 and 200_B2 have the same configuration. In the output block 200_B2, the cathode of the Zener diode 226 is connected to the node 225, and the anode of the Zener diode 226 is connected to the output wiring W. OUT(and therefore connected to the output terminal OUT). The gate-off circuit in the output block 200_B2 is a gate-off circuit 220a including an insertion transistor 221, a Zener diode 226, a resistor 223, and a current limiting resistor 224.

[0082] In the output block 200_B2, in the above-mentioned negative surge case CS2, the surge voltage V SGN The magnitude of exceeds the Zener voltage of the Zener diode 226, and the surge voltage V SGN A surge response signal RP2 based on this is generated at the node 225 (see FIG. 17). Therefore, similarly to the embodiment EX_B1, the insert transistor 221 is turned on based on the surge response signal RP2, and the output transistors 211 and 212 are turned off.

[0083] In the gate-off circuit 220a, a surge response circuit is formed by a Zener diode 226 and a resistor 223. The surge response circuit (226, 223) detects a negative surge voltage V SGN is applied (see FIG. 17), a surge response signal RP2 occurs at a node 225 accompanied by a breakdown phenomenon (zener phenomenon or avalanche phenomenon) of a zener diode 226, turning on the insertion transistor 221, thereby turning off the output transistors 211 and 212.

[0084] [Example EX_B3] An example EX_B3 will be described. An output block 200_B3 according to the example EX_B3 and its peripheral circuits are shown in Fig. 19. In the example EX_B3, the output block 200_B3 is used as the output block 5 in Fig. 1.

[0085] The output block 200_B3 is obtained by performing a fifth substitution on the output block 200_B1 of FIG. 16. The fifth substitution corresponds to replacing the insert transistor 221 of FIG. 16 with an insert transistor 227. With the fifth substitution, the current limiting resistor 224 is omitted in the output block 200_B3. Except for the fifth substitution, the output blocks 200_B1 and 200_B3 have the same configuration. The insert transistor 227 is a P-channel MOSFET. In the output block 200_B3, the drain of the insert transistor 227 is connected to the gate wiring Wb, and the source of the insert transistor 227 is connected to the power supply wiring W VDD , and the gate of the insert transistor 227 is connected to a node 225. The gate-off circuit in the output block 200_B3 is a gate-off circuit 220b that is composed of the insert transistor 227, a capacitor 222, and a resistor 223.

[0086] The surge response circuit (222, 223) in the output block 200_B3 detects a negative surge voltage V SGN is applied, the voltage of node 225 (the voltage of surge response signal RP2) is supplied to the control electrode (gate) of insertion transistor 227 to turn on insertion transistor 227, thereby turning off each of output transistors 211 and 212.

[0087] [Example EX_B4] An example EX_B4 will be described. FIG. 20 shows an output block 200_B4 according to the example EX_B4 and its peripheral circuit. In the example EX_B4, the output block 200_B4 is used as the output block 5 of FIG. 1. The output block 200_B4 is obtained by performing the above-mentioned fourth and fifth substitutions on the output block 200_B1 of FIG. 16. Therefore, the gate-off circuit in the output block 200_B4 is a gate-off circuit 220c having an insertion transistor 227, a Zener diode 226, and a resistor 223.

[0088] In the output block 200_B4, the cathode of the Zener diode 226 is connected to the node 225, and the anode of the Zener diode 226 is connected to the output wiring W. OUT In the output block 200_B4, the drain of the insert transistor 227 is connected to the gate wiring Wb, and the source of the insert transistor 227 is connected to the power supply wiring W VDD , and the gate of insert transistor 227 is connected to node 225.

[0089] In the gate-off circuit 220c, a surge response circuit is formed by a Zener diode 226 and a resistor 223. The surge response circuit (226, 223) detects a negative surge voltage V SGN is applied (see FIG. 17), a surge response signal RP2 occurs at a node 225 accompanied by a breakdown phenomenon (zener phenomenon or avalanche phenomenon) of a zener diode 226, turning on the insertion transistor 227, thereby turning off the output transistors 211 and 212.

[0090] [Example EX_B5] An embodiment EX_B5 will be described. In the embodiments EX_B1 to EX_B4, the total number of output transistors provided in the output stage 210 is arbitrary as long as it is two or more, and the output stage 210 may be formed by a series circuit of three or more output transistors. As an example, an output block 200_B5 and its peripheral circuits are shown in FIG. 21. The output block 200_B5 can be used as the output block 5 in FIG. 1.

[0091] The output block 200_B5 is obtained by performing a sixth substitution on the output block 200_B1 of FIG. 16. The sixth substitution corresponds to replacing the output stage 210 of FIG. 16 with the output stage 210a. Except for the sixth substitution, the output blocks 200_B1 and 200_B5 have the same configuration as each other. The output stage 210a is composed of output transistors 211-213. The output transistors 211-213 are P-channel type MOSFETs. The output transistors 211-213 may have the same structure and characteristics as each other.

[0092] In the output block 200_B5, the output transistors 211 to 213 are connected in series to each other between the terminals OUT and VDD. OUT , the source of the output transistor 211 is connected to the drain of the output transistor 212, the source of the output transistor 212 is connected to the drain of the output transistor 213, and the source of the output transistor 213 is connected to the power supply wiring W VDD The gates of the output transistors 211 to 213 are commonly connected to a gate wiring Wb, which makes it possible to increase the withstand voltage of the output stage 210a to three times that of one output transistor.

[0093] The matters described in the embodiment EX_B1 are also applied to the output block 200_B5. However, in this application, the output stage 210 in the embodiment EX_B1 is replaced with the output stage 210a in the embodiment EX_B5, and the output transistors 211 and 212 in the embodiment EX_B1 are replaced with the output transistors 211 to 213 in the embodiment EX_B5. The output stage 210a may be a series circuit of four or more output transistors. The sixth substitution may be applied to the output block 200_B2, 200_B3, or 200_B4.

[0094] [Example EX_C1] An embodiment EX_C1 will be described. In the state where the device is installed (see FIG. 3), the signal output circuit 3 outputs a high-level or low-level signal S from the output terminal OUT. OUT 22 shows the configuration of a signal output circuit 3 according to the embodiment EX_C1. The signal output circuit 3 according to the embodiment EX_C1 includes output blocks 100 and 200 and a drive circuit 4. In the embodiment EX_C1, the output block 5 in FIG.

[0095] The output block 100 is connected to terminals OUT and GND. The output block 200 is connected to terminals OUT and VDD. In a state where the device is installed, the output blocks 100 and 200 output a high-level or low-level output signal S in response to a signal supplied from the drive circuit 4. OUT is generated at the output terminal OUT (see Figure 3).

[0096] In the signal output circuit 3 of FIG. 22, the output block 100 may be any one of the above-mentioned output blocks 100_A1 to 100_A5.

[0097] 23, an output block 100_A1 may be used as the output block 100, while an output block 200a may be used as the output block 200. The output block 200a includes an output transistor 201 and a clamp circuit 202. The output transistor 201 is a P-channel MOSFET. In the output block 200a, the drain and source of the output transistor 201 are connected to the output wiring W, OUT , power wiring W VDD The gate of the output transistor 201 is connected to the drive circuit 4. The clamp circuit 202 is made up of a protection diode 203. The anode and cathode of the protection diode 203 are connected to the output wiring W OUT , power wiring W VDD The clamp circuit 202 may be formed of a plurality of protection diodes 203. When a surge voltage is applied between the terminals OUT and VDD, the clamp circuit 202 passes a surge current based on the surge voltage through itself, thereby limiting the magnitude of the voltage generated between the terminals OUT and VDD to less than the withstand voltage of the output transistor 201.

[0098] 23 sets the signal level of the output terminal OUT to a high level or a low level by controlling the gate potentials of the output transistors 111, 112, and 201. In the state where the drive circuit 4 is installed in the device, the drive circuit 4 in Fig. 23 can set the signal level of the output terminal OUT to a low level by turning on the output transistors 111 and 112 while turning off the output transistor 201, and can set the signal level of the output terminal OUT to a high level by turning off the output transistors 111 and 112 while turning on the output transistor 201.

[0099] It is often more difficult to increase the withstand voltage of an N-channel MOSFET than that of a P-channel MOSFET. In such a case, the configuration of Fig. 23 is useful. In Fig. 23, the output block 100_A1 may be replaced with any of the output blocks 100_A2 to 100_A5.

[0100] In the signal output circuit 3 of FIG. 22, the output block 200 may be any one of the above-mentioned output blocks 200_B1 to 200_B5.

[0101] 24, an output block 100a may be used as the output block 100, while an output block 200_B1 may be used as the output block 200. The output block 100a includes an output transistor 101 and a clamp circuit 102. The output transistor 101 is an N-channel MOSFET. In the output block 100a, the drain and source of the output transistor 101 are connected to the output wiring W OUT , Ground wiring W GND The gate of the output transistor 101 is connected to the drive circuit 4. The clamp circuit 102 is made up of a protection diode 103. The anode and cathode of the protection diode 103 are connected to the ground wiring W GND , output wiring W OUTThe clamp circuit 102 may be formed of a plurality of protection diodes 103. When a surge voltage is applied between the terminals OUT and GND, the clamp circuit 102 passes a surge current based on the surge voltage through itself, thereby limiting the magnitude of the voltage generated between the terminals OUT and GND to less than the withstand voltage of the output transistor 101.

[0102] 24 sets the signal level of the output terminal OUT to a high level or a low level by controlling the gate potentials of the output transistors 101, 211, and 212. In the state where the drive circuit 4 is installed in the device, the drive circuit 4 in Fig. 24 can set the signal level of the output terminal OUT to a low level by turning on the output transistor 101 while turning off the output transistors 211 and 212, and can set the signal level of the output terminal OUT to a high level by turning off the output transistor 101 while turning on the output transistors 211 and 212.

[0103] Depending on the manufacturing process, it may be easier to increase the withstand voltage of an N-channel MOSFET than that of a P-channel MOSFET. In such a case, the configuration of Fig. 24 is useful. In Fig. 24, the output block 200_B1 may be replaced with any of the output blocks 200_B2 to 200_B5.

[0104] In the signal output circuit 3 of FIG. 22, the output block 100 may be any of the output blocks 100_A1 to 100_A5 described above, and the output block 200 may be any of the output blocks 200_B1 to 200_B5 described above.

[0105] For example, as shown in FIG. 25, an output block 100_A1 may be used as the output block 100, while an output block 200_B1 may be used as the output block 200.

[0106] 25 sets the signal level of the output terminal OUT to a high level or a low level by controlling the gate potentials of the output transistors 111, 112, 211, and 212. In the device-installed state, the drive circuit 4 in Fig. 25 can set the signal level of the output terminal OUT to a low level by turning on the output transistors 111 and 112 while turning off the output transistors 211 and 212, and can set the signal level of the output terminal OUT to a high level by turning off the output transistors 111 and 112 while turning on the output transistors 211 and 212.

[0107] In FIG. 25, the output block 100_A1 may be replaced with any one of the output blocks 100_A2 to 100_A5, and instead of or in addition to this replacement, the output block 200_B1 may be replaced with any one of the output blocks 200_B2 to 200_B5.

[0108] <<Additional Notes>> The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0109] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0110] A signal output circuit according to one aspect of the present disclosure includes an output stage (110 or 210) having a plurality of output transistors connected in series between an output terminal (OUT) and a reference terminal (GND or VDD), a gate wiring (Wa or Wb) to which the gates of the output transistors are commonly connected, a drive circuit (4) configured to make or break an electric path between the output terminal and the reference terminal via the output stage by supplying a gate signal to the gate wiring, an insertion transistor (e.g., 121 or 221) inserted between the gate wiring and the reference terminal, and a control electrode of the insertion transistor, and configured to apply a surge voltage (V SGP Or V SGN and a surge response circuit (e.g., 122 and 123, or 222 and 223) configured to turn on the insertion transistor by driving the control electrode of the insertion transistor based on a surge voltage of the specific polarity when a surge voltage of the specific polarity is applied, thereby turning off each output transistor.

[0111] This makes it possible to improve the surge resistance of the signal output circuit.

[0112] In the signal output circuit of the above first configuration, the surge response circuit may have a capacitor (122 or 222) connected between the output terminal and a specified node (125 or 225), and a resistor (123 or 223) connected between the specified node and the reference terminal, and may be configured (second configuration) to turn on the insertion transistor based on a surge response signal (RP1 or RP2) generated at the specified node when a surge voltage of the specific polarity is applied between the output terminal and the reference terminal.

[0113] In the signal output circuit of the first configuration, the surge response circuit may have a Zener diode (126 or 226) connected between the output terminal and a specified node, and a resistor (123 or 223) connected between the specified node and the reference terminal, and may be configured (third configuration) to turn on the insertion transistor based on a surge response signal (RP1 or RP2) generated at the specified node accompanied by a breakdown phenomenon of the Zener diode when a surge voltage of the specific polarity is applied between the output terminal and the reference terminal.

[0114] In the signal output circuit according to any one of the first to third configurations, a clamp circuit (130 or 230) is provided that is connected in parallel to the output stage, and the clamp circuit generates a current (I SG2 or I SG4 ) may be passed through the output stage itself to limit the voltage generated between the output terminal and the reference terminal to less than the withstand voltage of the output stage (fourth configuration).

[0115] In the signal output circuit according to any one of the first to fourth configurations, each output transistor is an N-channel type field effect transistor (e.g., 111, 112), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage (V SGP ) (fifth configuration).

[0116] In the signal output circuit according to the second or third configuration, each output transistor is an N-channel type field effect transistor (e.g., 111, 112), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage (V SGP ), the insert transistor is composed of an NPN bipolar transistor (121), a control electrode of the insert transistor is a base, a collector and an emitter of the insert transistor are connected to the gate wiring (Wa) and the reference terminal (GND), respectively, and the surge response circuit may be configured to turn on the insert transistor by supplying a current to the base of the insert transistor through the specified node (125) when the positive surge voltage is applied to the output terminal as viewed from the reference terminal (sixth configuration).

[0117] In the signal output circuit according to the second or third configuration, each output transistor is an N-channel type field effect transistor (e.g., 111, 112), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage (V SGP ), the insert transistor is composed of an N-channel field effect transistor (127), a control electrode of the insert transistor is a gate, the drain and source of the insert transistor are connected to the gate wiring (Wa) and the reference terminal (GND), respectively, and the surge response circuit may be configured to turn on the insert transistor by supplying the voltage of the specified node (125) to the gate of the insert transistor when the positive surge voltage is applied to the output terminal as viewed from the reference terminal (seventh configuration).

[0118] In the signal output circuit according to any one of the first to fourth configurations, each output transistor is configured by a P-channel type field effect transistor (e.g., 211, 212), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage (V SGN ) (eighth configuration).

[0119] In the signal output circuit according to the second or third configuration, each output transistor is configured by a P-channel type field effect transistor (e.g., 211, 212), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage (V SGN ), the insert transistor is composed of a PNP bipolar transistor (221), a control electrode of the insert transistor is a base, a collector and an emitter of the insert transistor are connected to the gate wiring (Wb) and the reference terminal (VDD), respectively, and the surge response circuit may be configured to turn on the insert transistor by supplying a current to the base of the insert transistor through the specified node (225) when the negative surge voltage is applied to the output terminal as viewed from the reference terminal (9th configuration).

[0120] In the signal output circuit according to the second or third configuration, each output transistor is configured by a P-channel type field effect transistor (e.g., 211, 212), the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage (V SGN), the insert transistor is composed of a P-channel field effect transistor (227), a control electrode of the insert transistor is a gate, the drain and source of the insert transistor are connected to the gate wiring (Wb) and the reference terminal (VDD), respectively, and the surge response circuit may be configured to turn on the insert transistor by supplying the voltage of the specified node (225) to the gate of the insert transistor when the negative surge voltage is applied to the output terminal as viewed from the reference terminal (10th configuration). [Explanation of symbols]

[0121] 1. Electronic Components 2. Functional Circuit 3 Signal output circuit 4. Drive circuit 5 Output Block VDD Power supply pin OUT Output terminal GND Ground terminal W VDD power wiring W OUT Output Wiring W GND Ground wiring CNT Control Signal S OUT Output Signal EX external circuit VS Voltage Source V PWR Power supply voltage 900A, 900B Output Block 910, 911H, 911L Output transistors 930 Electrostatic protection element Isg Surge current Vds_H, Vds_L Drain-source voltage Vgs_H, Vgs_L Gate-source voltage Id_H, Id_L drain current Vg Gate voltage 100_A1~100_A5 Output block 110, 110a output stage 111, 112, 113 Output transistors 120, 120a to 120c Gate off circuit 121, 127 Insertion transistor 122 Capacitor 123 Resistance 124 Current limiting resistor 125 nodes 126 Zener Diode 130 Clamp Circuit 131 Protection Diode V SGP Surge Voltage I SG1 , I SG2 Surge Current RP1 Surge response signal V DSH , V DSL Drain-Source Voltage 200_B1~200_B5 Output block 210, 210a output stage 211, 212, 213 Output transistors 220, 220a to 220c Gate off circuit 221, 227 Insertion transistor 222 Capacitor 223 Resistance 224 Current limiting resistor 225 nodes 226 Zener Diode 230 Clamp Circuit 231 Protection Diode V SGN Surge Voltage I SG3 , I SG4 Surge Current RP2 Surge response signal V DS1 , V DS2 Drain-Source Voltage 100, 200, 100a, 200b output blocks 101, 201 Output transistor 102, 202 Clamp circuit 103, 203 Protection diode

Claims

1. an output stage having a plurality of output transistors connected in series between an output terminal and a reference terminal; a gate wiring to which the gates of the output transistors are commonly connected; a drive circuit configured to supply a gate signal to the gate wiring to make or break an electrical path between the output terminal and the reference terminal via the output stage; an insertion transistor inserted between the gate wiring and the reference terminal; a surge response circuit connected to the output terminal, the reference terminal, and the control electrode of the insert transistor, and configured to turn on the insert transistor by driving the control electrode of the insert transistor based on the surge voltage of the specific polarity when a surge voltage of a specific polarity is applied to the output terminal as viewed from the reference terminal, thereby turning off each output transistor. , a signal output circuit.

2. The surge response circuit has a capacitor connected between the output terminal and a predetermined node, and a resistor connected between the predetermined node and the reference terminal, and turns on the insertion transistor based on a surge response signal generated at the predetermined node when a surge voltage of the specific polarity is applied between the output terminal and the reference terminal.

2. The signal output circuit according to claim 1.

3. The surge response circuit has a Zener diode connected between the output terminal and a predetermined node, and a resistor connected between the predetermined node and the reference terminal, and turns on the insertion transistor based on a surge response signal that occurs at the predetermined node accompanied by a breakdown phenomenon of the Zener diode when a surge voltage of the specific polarity is applied between the output terminal and the reference terminal.

2. The signal output circuit according to claim 1.

4. a clamp circuit connected in parallel to the output stage; When a surge voltage of the specific polarity is applied between the output terminal and the reference terminal, the clamp circuit limits the voltage generated between the output terminal and the reference terminal to less than the withstand voltage of the output stage by passing a current based on the surge voltage through the clamp circuit itself.

2. The signal output circuit according to claim 1.

5. Each output transistor is composed of an N-channel type field effect transistor, the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage.

5. A signal output circuit according to claim 1.

6. each output transistor is an N-channel field effect transistor, the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage; the insertion transistor is configured by an NPN-type bipolar transistor, a control electrode of the insertion transistor is a base, and a collector and an emitter of the insertion transistor are connected to the gate wiring and the reference terminal, respectively; The surge response circuit supplies a current to a base of the insert transistor through the predetermined node when the positive surge voltage is applied to the output terminal as viewed from the reference terminal, thereby turning on the insert transistor.

4. The signal output circuit according to claim 2 or 3.

7. each output transistor is an N-channel field effect transistor, the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a positive surge voltage; The insertion transistor is configured by an N-channel type field effect transistor, a control electrode of the insertion transistor is a gate, and a drain and a source of the insertion transistor are connected to the gate wiring and the reference terminal, respectively; The surge response circuit supplies a voltage of the predetermined node to a gate of the insert transistor when the positive surge voltage is applied to the output terminal as viewed from the reference terminal, thereby turning on the insert transistor.

4. The signal output circuit according to claim 2 or 3.

8. Each output transistor is composed of a P-channel type field effect transistor, the direction from the drain to the source of each output transistor coincides with the direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage.

5. A signal output circuit according to claim 1.

9. each output transistor is a P-channel field effect transistor, a direction from a drain to a source of each output transistor coincides with a direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage; the insertion transistor is configured by a PNP type bipolar transistor, a control electrode of the insertion transistor is a base, and a collector and an emitter of the insertion transistor are connected to the gate wiring and the reference terminal, respectively; The surge response circuit supplies a current to a base of the insert transistor through the predetermined node when the negative surge voltage is applied to the output terminal as viewed from the reference terminal, thereby turning on the insert transistor.

4. The signal output circuit according to claim 2 or 3.

10. each output transistor is a P-channel field effect transistor, a direction from a drain to a source of each output transistor coincides with a direction from the output terminal to the reference terminal, and the surge voltage of the specific polarity is a negative surge voltage; The insertion transistor is configured by a P-channel type field effect transistor, a control electrode of the insertion transistor is a gate, and a drain and a source of the insertion transistor are connected to the gate wiring and the reference terminal, respectively; When the negative surge voltage is applied to the output terminal as viewed from the reference terminal, the surge response circuit supplies the voltage of the predetermined node to the gate of the insert transistor to turn on the insert transistor.

4. The signal output circuit according to claim 2 or 3.

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