Semiconductor device

Abstract

To reduce thermal resistance in a semiconductor device in which a semiconductor element is mounted on graphite to dissipate heat.SOLUTION: A semiconductor device includes a chip-like semiconductor element 10, and anisotropic graphite 30 having a surface 31 on which a semiconductor device is arranged and a c-axis direction along the surface, and the semiconductor element 10 is joined onto the surface 31 of the anisotropic graphite 30 via a first bonding layer 20. A ceramic substrate 70 is disposed on the opposite side of the semiconductor element 10, sandwiching the anisotropic graphite 30 therebetween. A metal plate 50 made of a metal plate-like member is disposed between the anisotropic graphite 30 and the ceramic substrate 70.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device in which a semiconductor element is mounted on anisotropic graphite to dissipate heat. [Background technology]

[0002] Patent Document 1 proposes a semiconductor package in which a semiconductor element is mounted on an anisotropic graphite composite. The anisotropic graphite composite is constructed by combining a rectangular plate-shaped anisotropic graphite, a metal layer for bonding, and an insulating inorganic material layer. A semiconductor element is bonded onto the plate-shaped anisotropic graphite, and an inorganic material layer is disposed on the side of the anisotropic graphite opposite the semiconductor element to ensure insulation, while a cooler is bonded to the inorganic material layer to construct a semiconductor package. The anisotropic graphite and the inorganic material layer are bonded together with a thin metal layer of about 8 μm to 50 μm that is made of plating or a metallic brazing material.

[0003] In this structure, the directions along one side of the surface of the anisotropic graphite and the other side perpendicular to the one side are defined as the X-axis and Y-axis, respectively, and the thickness direction of the anisotropic graphite perpendicular to the X-axis and Y-axis is defined as the Z-axis. The crystal orientation of the anisotropic graphite is defined as the Z-axis direction. In addition, the semiconductor element is arranged on the surface of the anisotropic graphite with one side of the square chip-shaped semiconductor element facing the X-axis direction and the other side perpendicular to the X-axis direction facing the Y-axis direction, thereby improving heat dissipation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-100006 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor package of Patent Document 1, the crystal orientation of the anisotropic graphite is oriented in the Z-axis direction, and although heat conduction in the X-axis and Z-axis directions is good, heat conduction in the Y-axis direction is not good. Furthermore, in a structure in which the anisotropic graphite and the inorganic material layer are simply joined with a thin metal layer, the effect of transferring heat in the Y-axis direction within the anisotropic graphite is low, and the heat generated by the semiconductor element cannot be released. For this reason, the thermal resistance of the semiconductor package cannot be reduced.

[0006] An object of the present disclosure is to reduce thermal resistance in a semiconductor device in which a semiconductor element is mounted on graphite to dissipate heat. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present disclosure includes: A chip-shaped semiconductor element (10); anisotropic graphite (30) having a surface (31) on which the semiconductor device is placed, the c-axis direction being one direction along the surface; a first bonding layer (20) for bonding the semiconductor element onto the one surface of the anisotropic graphite; a plate-shaped insulating member (70) that is disposed on the opposite side of the anisotropic graphite from the semiconductor element and insulates the anisotropic graphite; a metal plate (50) configured as a metal plate-shaped member disposed between the anisotropic graphite and the insulating member; a second bonding layer (40) that bonds the anisotropic graphite and the metal plate; and a third bonding layer (60) that bonds the metal plate and the insulating member.

[0008] In this way, the metal plate is provided between the anisotropic graphite and the insulating member, which allows heat to be transferred to the outer edge side of the anisotropic graphite via the metal plate, thereby making it possible to reduce the thermal resistance of the semiconductor device.

[0009] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a perspective view of the semiconductor device shown in FIG. [Diagram 3] FIG. 1 is a cross-sectional view of a semiconductor device shown as a reference structure. [Figure 4] 4 is a diagram showing a simulation result of how heat is transferred in the semiconductor device having the reference structure shown in FIG. [Diagram 5] 2 is a diagram showing a simulation result of how heat is transferred in the semiconductor device according to the first embodiment shown in FIG. 1. [Figure 6] 1 is a diagram showing the relationship between the thickness of a metal plate and the thermal resistance [° C. / W] of a semiconductor device. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following, including other embodiments described below, the same reference numerals will be used to denote the same or equivalent parts in each embodiment.

[0012] (First embodiment) A first embodiment of the present disclosure will be described with reference to Figures 1 to 6. In the drawings attached to this specification, an X-axis, a Y-axis, and a Z-axis are shown. In the description, an arbitrary direction is defined as the X-axis, a direction perpendicular to the X-axis is defined as the Y-axis, and a direction perpendicular to the X-axis and Y-axis is defined as the Z-axis.

[0013] 1 and 2, the semiconductor device of this embodiment includes a semiconductor element 10, a first bonding layer 20, anisotropic graphite 30, a second bonding layer 40, a metal plate 50, a third bonding layer 60, and a ceramic substrate 70. The ceramic substrate 70 is bonded to a cooler 80, thereby cooling the semiconductor element 10.

[0014] The semiconductor element 10 is a semiconductor chip in which, for example, a power element is built. Examples of the power element include an IGBT (insulated gate bipolar transistor) and a MOSFET (metal-oxide-semiconductor field-effect transistor). Here, the semiconductor element 10 is a semiconductor chip in which a vertical IGBT is built. As shown in FIG. 2, the semiconductor element 10 is provided with an upper electrode 11. The upper electrode 11 is an electrode connected to an emitter or the like in the vertical IGBT, and is disposed on one surface 12 of the semiconductor element 10. Although not shown, a control electrode (not shown) connected to a gate or the like of the vertical IGBT is disposed at a location on the one surface 12 different from the upper electrode 11. These upper electrode 11 and control electrode are electrically connectable to the outside by being connected to a bonding wire or a conductor component. Although not shown, a lower electrode (not shown) is disposed on the other surface opposite to the one surface 12. The bottom electrode is an electrode connected to a collector or the like in a vertical IGBT, and is connected to anisotropic graphite 30 via first bonding layer 20. As described below, first bonding layer 20 is made of a conductive material, and anisotropic graphite 30 is a conductor, so that the bottom electrode can also be electrically connected to the outside by connecting a conductive part to anisotropic graphite 30 for external extraction.

[0015] The semiconductor element 10 has a rectangular plate-like top surface, and is disposed such that one pair of opposing sides 12a of one surface 12 is aligned along the X-axis, the other pair of opposing sides 12b is aligned along the Y-axis, and the thickness direction is aligned along the Z-axis. In this specification, "along" the X-axis, Y-axis, etc. preferably means parallel, but is not necessarily limited to being parallel, and also includes being inclined with respect to the axis.

[0016] First bonding layer 20 is made of a conductive bonding material such as solder, silver paste, silver sheet, etc. The thickness of first bonding layer 20 is arbitrary, but is set to, for example, 0.02 to 0.05 mm. This first bonding layer 20 electrically and physically bonds semiconductor element 10 to anisotropic graphite 30.

[0017] The anisotropic graphite 30 is a graphite having anisotropy of thermal conductivity and functions as a heat spreader. The thickness of the anisotropic graphite 30 is arbitrary, but is set to, for example, 2 mm.

[0018] As shown in FIG. 2, anisotropic graphite 30 has a crystal structure of a graphite structure formed by overlapping graphite layers of hexagonal plate-like crystals, the overlapping direction of the graphite layers is the c-axis, and the plane direction of the graphite layers normal to the c-axis is the a-axis. Anisotropic graphite 30 has a rectangular plate-like upper surface shape, and one of two opposing sides 31a on one surface 31 of anisotropic graphite 30 is arranged along the X-axis, the other opposing two sides 31b are arranged along the Y-axis, and the thickness direction is arranged along the Z-axis. In other words, anisotropic graphite 30 has an a-axis arranged along the X-axis and Z-axis, and a c-axis arranged along the Y-axis. The size of anisotropic graphite 30 is such that two sides 31a are larger than two sides 12a of semiconductor element 10 in the X-axis direction, and two sides 31b are larger than two sides 12b of semiconductor element 10 in the Y-axis direction. Semiconductor element 10 is bonded to one surface 31 of this anisotropic graphite 30 at approximately the center thereof via first bonding layer 20 .

[0019] Anisotropic graphite 30 has a high thermal conductivity of about 1700 [W / mK] in the a-axis direction, i.e., the X-axis direction and the Z-axis direction, but a low thermal conductivity of about 7 [W / mK] in the c-axis direction, i.e., the Y-axis direction. Therefore, when semiconductor element 10 generates heat, heat moves easily in the direction along the a-axis within anisotropic graphite 30 due to high thermal conductivity, but heat moves less easily in the direction along the c-axis compared to the direction along the a-axis due to low thermal conductivity.

[0020] The second bonding layer 40 and the third bonding layer 60 are provided to bond the metal plate 50 to the anisotropic graphite 30 and the ceramic substrate 70. The second bonding layer 40 and the third bonding layer 60 may be made of different materials, but are made of the same material here, for example, a bonding material with high thermal conductivity such as silver paste or silver solder, and are made of a conductive material here. The thickness of the second bonding layer 40 and the third bonding layer 60 is arbitrary, but both are, for example, 0.02 to 0.05 mm. The second bonding layer 40 physically bonds the anisotropic graphite 30 and the metal plate 50, and the third bonding layer 60 physically connects the metal plate 50 and the ceramic substrate 70. In addition, in the case of this embodiment, since the second bonding layer 40 is made of a conductive material, the second bonding layer 40 also electrically bonds the anisotropic graphite 30 and the metal plate 50.

[0021] The metal plate 50 corresponds to the first metal plate, and is a plate-like member made of metal having a thermal conductivity higher than at least the c-axis direction of the ceramic substrate 70 and the anisotropic graphite 30. The metal plate 50 is sandwiched between the anisotropic graphite 30 and the ceramic substrate 70 and bonded therebetween via the second bonding layer 40 and the third bonding layer 60. The metal plate 50 has a rectangular shape on the upper surface, and is arranged such that one of two opposing sides 51a on the surface 51 of the metal plate 50 is aligned along the X-axis, the other opposing two sides 51b is aligned along the Y-axis, and the thickness direction is aligned along the Z-axis. The size of the metal plate 50 is the same as or larger than the anisotropic graphite 30, that is, the two sides 51a are equal to or larger than the two sides 31a of the anisotropic graphite 30, and the other two sides 51b are equal to or larger than the two sides 31b of the anisotropic graphite 30. Anisotropic graphite 30 is arranged so as not to protrude from metal plate 50 when viewed from the Z-axis direction. However, it is permissible that two sides 51a of metal plate 50 are slightly smaller than two sides 31a of anisotropic graphite 30, or that two sides 51b of metal plate 50 are slightly smaller than two sides 31b of anisotropic graphite 30, due to manufacturing errors or the like.

[0022] The metal plate 50 is made of a metal material such as gold, silver, copper, aluminum, molybdenum, tungsten, etc. The thickness of the metal plate 50 is set to 0.2 mm or more and 3.0 mm or less, preferably 1 mm or more and 2 mm or less, and more preferably 1.5 mm ± 0.1 mm.

[0023] The ceramic substrate 70 is an insulating member disposed on the opposite side of the semiconductor element 10 with the anisotropic graphite 30 interposed therebetween. The ceramic substrate 70 is made of an insulating plate-like member having high thermal conductivity, for example, aluminum nitride or alumina. The ceramic substrate 70 transfers heat generated by the semiconductor element 10 to the cooler 80 via the anisotropic graphite 30 and the metal plate 50 while providing insulation between the metal plate 50, the anisotropic graphite 30, the semiconductor element 10, and the like, and is cooled by transferring the heat generated by the semiconductor element 10 to the cooler 80 via the anisotropic graphite 30 and the metal plate 50. The ceramic substrate 70 also has a rectangular top surface, and is disposed such that one of two opposing sides 71a of the surface 71 of the ceramic substrate 70 is aligned along the X-axis, the other of two opposing sides 71b is aligned along the Y-axis, and the thickness direction is aligned along the Z-axis. The size of the ceramic substrate 70 is the same as or larger than that of the metal plate 50, that is, two sides 71a are equal to or larger than the two sides 51a of the metal plate 50, and the other two sides 71b are equal to or larger than the two sides 51b of the metal plate 50. The thickness of the ceramic substrate 70 is arbitrary, but is set to a thickness that can suppress creeping discharge, for example, 0.32 mm.

[0024] The cooler 80 dissipates heat by exchanging heat with cooling water or air, and is made of, for example, a metal member. The shape of the cooler 80 is arbitrary, and it may be configured with heat dissipation fins, etc. The ceramic substrate 70 is attached to the surface of the cooler 80.

[0025] The semiconductor device of this embodiment has the above-mentioned structure. Next, the operation and effect of the semiconductor device of this embodiment will be described.

[0026] As described above, in the semiconductor device of this embodiment, the metal plate 50 made of a metal plate-like member is disposed between the anisotropic graphite 30 and the ceramic substrate 70. By providing the metal plate 50 made of such a plate-like member, heat can be easily transferred in the Y-axis direction of the anisotropic graphite 30, and the heat generated by the semiconductor element 10 can be easily released. This makes it possible to reduce the thermal resistance of the semiconductor device. The reason why such an effect is obtained will be explained below based on a simulation.

[0027] As a reference structure, a simulation of heat transfer was performed for a structure in which anisotropic graphite 30 and a ceramic substrate 70 are bonded by a thin second bonding layer 40 without a metal plate 50 as shown in FIG. 3. This structure corresponds to the semiconductor package described in Patent Document 1. Similarly, a simulation of heat transfer was performed for a semiconductor device having the structure of this embodiment shown in FIG. 1. FIGS. 4 and 5 show the simulation results of the reference structure shown in FIG. 3 and the semiconductor device of this embodiment shown in FIG. 1, respectively. Note that FIGS. 4 and 5 show the results of heat transfer analysis by CAE (Computer Aided Engineering) in a cross section along the Y-axis direction, and the wider the hatching interval, the lower the temperature.

[0028] 4, in the reference structure, it is found that the temperature is low at both ends of anisotropic graphite 30 in the Y-axis direction. This indicates that the heat generated by semiconductor element 10 is not sufficiently transmitted in the Y-axis direction. Thus, in the reference structure, the effect of transmitting heat in the Y-axis direction within anisotropic graphite 30 is low, and the heat generated by semiconductor element 10 cannot be released, so the thermal resistance of the semiconductor device cannot be reduced.

[0029] In contrast, in the semiconductor device of this embodiment, it is found that the temperature is higher at both ends of anisotropic graphite 30 in the Y-axis direction compared to the reference structure. This indicates that the heat generated by semiconductor element 10 is sufficiently transmitted in the Y-axis direction. Thus, in the semiconductor device of this embodiment, the effect of transmitting heat in the Y-axis direction within anisotropic graphite 30 is high, and the heat generated by semiconductor element 10 can be dissipated. This makes it possible to reduce the thermal resistance of the semiconductor device.

[0030] Such a difference is considered to occur due to whether or not metal plate 50 is interposed between anisotropic graphite 30 and ceramic substrate 70. In the reference structure, since only a thin second bonding layer 40 exists, heat is unlikely to spread through second bonding layer 40, and heat is not sufficiently transferred in the direction of arrow A1 in the figure, that is, in the Y-axis direction of anisotropic graphite 30. As a result, heat is not transferred to a wide range in anisotropic graphite 30, and the range over which heat is transferred to ceramic substrate 70 is also narrow. For this reason, the thermal resistance of the semiconductor device cannot be reduced.

[0031] On the other hand, when metal plate 50 is interposed as in the semiconductor device of this embodiment, heat transferred from semiconductor element 10 to anisotropic graphite 30 spreads via metal plate 50 as indicated by arrow A2 in the figure, and is also transferred in the Y-axis direction within anisotropic graphite 30. This results in a state similar to that in which heat is transferred from semiconductor element 10 to a wide range within anisotropic graphite 30. As a result, heat is transferred to a wider range of ceramic substrate 70, enabling cooling over a wider area, and thus making it possible to reduce the thermal resistance of the semiconductor device.

[0032] In addition, while the thermal resistance can be reduced by providing the metal plate 50 as in the semiconductor device of this embodiment, a study was also conducted on what thickness the metal plate 50 should be. As a result, it was found that the relationship between the thickness of the metal plate 50 and the thermal resistance [°C / W] of the semiconductor device is as shown in FIG.

[0033] Specifically, as shown in FIG. 6, the thermal resistance gradually decreased when the metal plate 50 was provided, compared to when the thickness of the metal plate 50 was 0, that is, when the metal plate 50 was not provided. In particular, the decrease in thermal resistance was remarkable when the thickness of the metal plate 50 was in the range of 0.2 mm or more and 3.0 mm, and the thermal resistance decreased further when the thickness was in the range of 1.0 mm or more and 2.0 mm or more. The thermal resistance decreased the most when the thickness of the metal plate 50 was 1.5 mm. Note that the thermal resistance decreased the most when the thickness of the metal plate 50 was 1.5 mm, but within a range of ±0.1 mm from that, the thermal resistance was equivalent to that when the thickness was 1.5 mm. Note that if the metal plate 50 is too thick, the distance from the anisotropic graphite 30 to the cooler 80 increases, which may suppress the cooling effect, so the thickness of the metal plate 50 is preferably 3.0 mm or less.

[0034] The relationship between the thickness of the metal plate 50 and the thermal resistance varies slightly depending on the material of the metal plate 50 and the structure of the semiconductor device, but basically shows the same tendency.

[0035] Therefore, in the semiconductor device of this embodiment, the thickness of the metal plate 50 is set to 0.2 mm or more and 3.0 mm or less, preferably 1 mm or more and 2 mm or less, and more preferably 1.5 mm±0.1 mm.

[0036] As described above, in the semiconductor device of the present embodiment, the metal plate 50 is provided between the anisotropic graphite 30 and the ceramic substrate 70. This allows heat to be transferred to the outer edge side of the anisotropic graphite 30 via the metal plate 50. Specifically, it is possible to enhance the effect of transferring heat in the Y-axis direction in the anisotropic graphite 30. This makes it possible to reduce the thermal resistance of the semiconductor device.

[0037] Specifically, the thermal resistance of the semiconductor device can be reduced by making the thickness of the metal plate 50 0.2 mm or more and 3.0 mm or less, and preferably 1.0 mm or more and 2.0 mm or less. In particular, it is preferable to make the thickness of the metal plate 50 1.5 mm±0.1 mm, since this further reduces the thermal resistance of the semiconductor device.

[0038] Second embodiment The second embodiment will be described. This embodiment is different from the first embodiment in that the structure between the semiconductor element 10 and the anisotropic graphite 30 is changed, and other points are the same as those in the first embodiment, so only the points different from the first embodiment will be described.

[0039] 7, the semiconductor device of this embodiment includes a metal plate 90 corresponding to the second metal plate between the semiconductor element 10 and the anisotropic graphite 30. The material that can be used to form the metal plate 90 is the same as that of the metal plate 50. The metal plate 90 may be made of the same material, thickness, and dimensions as the metal plate 50, or may be made of a different material, thickness, and dimensions. Here, the metal plate 90 is made of the same material, thickness, and dimensions as the metal plate 50.

[0040] Specifically, a metal plate 90 is bonded onto one surface 31 of anisotropic graphite 30 via a fourth bonding layer 100. The metal plate 90 has a rectangular shape on the top surface, and is disposed such that one pair of opposing sides 91a on a surface 91 of the metal plate 90 are aligned along the X-axis, the other pair of opposing sides 91b are aligned along the Y-axis, and the thickness direction is aligned along the Z-axis. A semiconductor element 10 is bonded onto the surface of the metal plate 90 via a first bonding layer 20. The semiconductor element 10 is positioned approximately at the center of the surface 91 of the metal plate 90. The material that can form the fourth bonding layer 100 is the same as that of the second bonding layer 40 and the third bonding layer 60.

[0041] In this way, by disposing metal plate 90 between semiconductor element 10 and anisotropic graphite 30, heat can be spread and transmitted in the Y-axis direction by metal plate 90 as well. Therefore, heat transmission in the Y-axis direction can be promoted by metal plate 90 in addition to metal plate 50, and the thermal resistance of the semiconductor device can be further reduced.

[0042] Third embodiment A third embodiment will be described. In this embodiment, the structure around the anisotropic graphite 30 is changed from that in the first and second embodiments, and other aspects are the same as those in the first and second embodiments, so only the parts that differ from the first and second embodiments will be described. Here, the case where the structure of this embodiment is applied to the structure of the first embodiment will be described, but it can also be applied to the structure of the second embodiment.

[0043] 8, the semiconductor device of this embodiment includes metal plate 110 so as to cover the periphery of anisotropic graphite 30, specifically, a plane along the Z-axis which is the normal direction of one surface 31, that is, side surfaces 32 of anisotropic graphite 30. This metal plate 110 corresponds to a covering metal plate. Metal plate 110 is disposed so as to cover at least side surfaces 32 of anisotropic graphite 30 which are parallel to the Z-axis and Y-axis, but in this embodiment, metal plate 110 is disposed so as to cover the entire surfaces of four side surfaces 32 of anisotropic graphite 30.

[0044] The material that can constitute the metal plate 90 is the same as that of the metal plate 50. The metal plate 110 may be made of the same material, thickness, and dimensions as the metal plate 50, or may be made of a different material, thickness, and dimensions. Here, the metal plate 90 is made of the same material, thickness, and dimensions as the metal plate 50. In this embodiment, the thickness direction of the metal plate 110 is the normal direction of each side surface 32 that it covers.

[0045] Specifically, metal plate 110 is bonded onto side surface 32 of anisotropic graphite 30 via bonding layer 120 corresponding to a side bonding layer. Metal plate 110 has a quadrangular shape when viewed from the thickness direction, and each side has a dimension corresponding to each side of side surface 32 of anisotropic graphite 30. Note that the material that can form bonding layer 120 is similar to that of second bonding layer 40 and third bonding layer 60.

[0046] In this way, when metal plate 110 is arranged so as to cover side surface 32 of anisotropic graphite 30, heat is transferred through metal plate 110, and heat is likely to spread in the Y-axis direction. Therefore, heat transfer in the Y-axis direction can be promoted by metal plate 110 in addition to metal plate 50, and it is possible to further reduce the thermal resistance of the semiconductor device.

[0047] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0048] For example, in each of the above embodiments, the ceramic substrate 70 is used as the insulating member, but the insulating member is not limited to the ceramic substrate 70 and may be made of other insulating materials.

[0049] In addition, in each of the above embodiments, an example has been given in which one semiconductor device, which includes one semiconductor element 10, one anisotropic graphite 30, one metal plate 50, and one ceramic substrate 70, is joined to one cooler 80. However, this is merely an example, and a configuration in which two or more sets of semiconductor devices are joined to the same cooler 80 may also be used.

[0050] Also, the structure in which one semiconductor element 10 is disposed for each of the anisotropic graphite 30, metal plate 50, and ceramic substrate 70 has been given as an example. However, even in this case, a structure in which two semiconductor elements 10 are disposed for each of the anisotropic graphite 30, metal plate 50, and ceramic substrate 70 may be used. For example, when the semiconductor elements 10 constitute the semiconductor switching elements of the upper arm and the lower arm of an inverter circuit, the semiconductor elements 10 of the upper arm and the lower arm are connected in series. In such a case, if one semiconductor element 10 is mounted on the surface of the anisotropic graphite 30 with the other semiconductor element 10 reversed, these can be connected in series.

[0051] Furthermore, the upper surface shape of the semiconductor element 10, anisotropic graphite 30, metal plate 50, and ceramic substrate 70 does not necessarily have to be rectangular, and may be, for example, a rectangular shape with each corner or some corners cut out.

[0052] (In view of the present disclosure) The present disclosure described above can be understood from the following viewpoints, for example.

[0053] [First viewpoint] A semiconductor device comprising: A chip-shaped semiconductor element (10); anisotropic graphite (30) having a surface (31) on which the semiconductor element is placed, the c-axis direction being one direction along the surface; a first bonding layer (20) for bonding the semiconductor element onto the one surface of the anisotropic graphite; a plate-shaped insulating member (70) that is disposed on the opposite side of the anisotropic graphite from the semiconductor element and insulates the anisotropic graphite; a metal plate (50) configured as a metal plate-shaped member disposed between the anisotropic graphite and the insulating member; a second bonding layer (40) that bonds the anisotropic graphite and the metal plate; and a third bonding layer (60) that bonds the metal plate and the insulating member. [Second viewpoint] The semiconductor device according to the first aspect, wherein the metal plate has a thickness of not less than 0.2 mm and not more than 3.0 mm. [Third Perspective] The semiconductor device according to the first aspect, wherein the metal plate has a thickness of not less than 1.0 mm and not more than 2.0 mm. [Fourth viewpoint] The semiconductor device according to the first aspect, wherein the metal plate has a thickness of 1.5±0.1 mm. [Fifth viewpoint] The semiconductor device according to any one of the first to fourth aspects, wherein the metal plate is made of a metal material having a higher thermal conductivity than the insulating member. [Sixth viewpoint] The metal plate is a first metal plate (50), a second metal plate (90) disposed on said one side of the anisotropic graphite; and a fourth bonding layer (100) that bonds the second metal plate to the anisotropic graphite, The semiconductor device according to any one of first to fifth aspects, wherein the semiconductor element is bonded onto the second metal plate via the first bonding layer. [Seventh viewpoint] a coating metal plate (110) that covers at least a surface along the c-axis of the anisotropic graphite among the side surface (32) along the normal direction of the one surface of the anisotropic graphite; The semiconductor device according to any one of the first to sixth aspects, further comprising a side bonding layer (120) that bonds the coated metal plate to the anisotropic graphite. [Explanation of symbols]

[0054] 10 Semiconductor elements 20 1st bonding layer 30 Anisotropic graphite 31 one side 40 Second bonding layer 50 metal plate 60 Third bonding layer 70 Ceramic Substrate 80 Cooler

Claims

1. A semiconductor device comprising: A chip-shaped semiconductor element (10); Anisotropic graphite (30) having a surface (31) on which the semiconductor element is placed, the c-axis direction being one direction along the surface; a first bonding layer (20) for bonding the semiconductor element onto the one surface of the anisotropic graphite; a plate-shaped insulating member (70) disposed on the opposite side of the anisotropic graphite from the semiconductor element and insulating the anisotropic graphite; A metal plate (50) constituted by a metal plate-shaped member arranged between the anisotropic graphite and the insulating member; A second bonding layer (40) that bonds the anisotropic graphite and the metal plate; A third bonding layer (60) that bonds the metal plate and the insulating member.

2. 2. The semiconductor device according to claim 1, wherein the metal plate has a thickness of 0.2 mm or more and 3.0 mm or less.

3. 2. The semiconductor device according to claim 1, wherein the metal plate has a thickness of 1.0 mm or more and 2.0 mm or less.

4. 2. The semiconductor device according to claim 1, wherein the metal plate has a thickness of 1.5±0.1 mm.

5. The semiconductor device according to claim 1 , wherein the metal plate is made of a metal material having a higher thermal conductivity than the insulating member.

6. The metal plate is a first metal plate (50), a second metal plate (90) disposed on said one side of the anisotropic graphite; a fourth bonding layer (100) that bonds the second metal plate to the anisotropic graphite; The semiconductor device according to claim 1 , wherein the semiconductor element is bonded onto the second metal plate via the first bonding layer.

7. a coated metal plate (110) that covers at least a surface along the c-axis of the anisotropic graphite among the side surfaces (32) along the normal direction of the one surface of the anisotropic graphite; 7. The semiconductor device according to claim 1, further comprising a side bonding layer (120) for bonding said coated metal plate to said anisotropic graphite.

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