Wiring substrate and manufacturing method for the same

Abstract

To provide a multilayer wiring substrate that reduces warping caused by a residual copper ratio being different between each wiring layer and a designing method for the same.SOLUTION: A multilayer wiring substrate 100 is provided with a first conductor part 13 and first insulator parts 11, 12 above a first surface of a core insulating layer 1 and a second conductor part 13 and second insulator parts 21, 22 below a second surface of the core insulating layer. A ratio of the volume of the first conductor part to the total volume of the first conductor part and the first insulators is denoted as A, and a ratio of the volume of the second conductor part to the total volume of the second conductor part and the insulator parts is denoted as B. A / B is denoted as X and an elastic modulus E (unit: GPa) and thermal expansion coefficient α (unit: ppm) of the first and second insulators satisfy the following equation. α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X-1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)-0.0014039))SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] In recent years, electronic devices have become larger due to the increasing number of chips mounted on them and the need for higher integration in response to demands for higher functionality. In addition, multilayer wiring boards used in these devices are required to have reduced warpage in order to improve chip mounting reliability.

[0003] Patent Document 1 discloses a wiring board A including a core substrate 15, insulating layers 16a-16d laminated in equal numbers on the top and bottom surfaces of core substrate 15, and conductor layers 13 deposited with different occupancy rates on the top and bottom surfaces of core substrate 15 and on the surfaces of insulating layers 16a-16d. In wiring substrate A, the conductor layers 13 on the top and bottom surfaces of core substrate 15 and the conductor layers 13 positioned at the same rank on the top and bottom sides of core substrate 15 are formed so that the conductor thickness with the larger occupancy rate is thinner than the conductor thickness with the smaller occupancy rate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-139632 A Summary of the Invention [Problem to be solved by the invention]

[0005] In order to reduce warping of a multilayer wiring board, it is ideal to make the total conductor volume and the total resin volume common in the first buildup layer provided on the first surface of the core insulating layer and the second buildup layer provided on the second surface opposite the first surface. However, because the wiring patterns are different between the first buildup layer and the second buildup layer, it is difficult to match the remaining copper ratio (copper area), and from the standpoint of wiring connection reliability and via structure workability, it is also practically difficult to match the thickness of the conductor and resin between the first buildup layer and the second buildup layer.

[0006] The present invention has been made in consideration of these problems, and aims to provide a multilayer wiring board and a design method thereof that can reduce warping without changing the area or thickness (volume) of the conductors or insulating resin. [Means for solving the problem]

[0007] In order to solve the above problems, one representative multilayer wiring board of the present invention is: A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; wherein the first conductor portion and the second conductor portion have the same volume.

[0008] Furthermore, another representative multilayer wiring board of the present invention is a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; A multilayer wiring board comprising: A represents a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion; A ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B, Let A / B be X, The elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the first and second insulating portions satisfy the following formula (1). α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X- 1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)-0.0014039))…(1) In addition, when the right side of the formula (1) is β, α may be in the range of 0.9β<α<1.1β. Effect of the Invention

[0009] According to the present invention, even if the residual copper ratio of the conductor in each conductor layer is different between the conductor layer provided on the first surface side of the core substrate and the conductor layer provided on the second surface side of the core substrate, warping of the wiring substrate can be suppressed.Furthermore, such a highly reliable wiring substrate can be manufactured. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a multilayer wiring board according to a first embodiment of the present invention. [Diagram 2] 3A to 3C are explanatory diagrams showing an example of a method for producing a core substrate according to the present invention. [Diagram 3] 1A to 1C are explanatory views showing a multilayer wiring board and a manufacturing method thereof according to a first embodiment of the present invention. [Figure 4] 1A to 1C are explanatory views showing a multilayer wiring board and a manufacturing method thereof according to a first embodiment of the present invention. [Diagram 5]FIG. 1 is a cross-sectional view showing an example of a semiconductor device on which a semiconductor element of the present invention is mounted. [Figure 6] FIG. 6 is a diagram explaining two types of warping states. [Figure 7] FIG. 7 is a graph showing the relationship between the amount of warpage and the variable X. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The dimensional ratios in the drawings may differ from the actual ratios for the convenience of explanation, and the number of layers and part of the configuration may be omitted from the drawings. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0012] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The boundary surface between the core insulating layer 1 and the insulator portion 11 is referred to as a first surface, and the boundary surface between the core insulating layer 1 and the insulator portion 12 is referred to as a second surface.

[0013] In addition, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "Z-axis positive direction" and the "Z-axis negative direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0014] Furthermore, the term "layer" does not necessarily refer to a state in which an object is uniformly formed. It may refer to an object having a pattern with gaps, or a collection of individual objects. For example, the term "conductor layer" may refer to multiple conductors formed on the same surface among surfaces parallel to the main surface of a core substrate.

[0015] <First embodiment> First, a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing a multilayer wiring board according to a first embodiment of the present invention. It should be noted that a semiconductor element can be mounted on the multilayer wiring board of the present disclosure by applying flip chip connection via solder bumps.

[0016] (Structure of multilayer wiring board) The multilayer wiring board 100 has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductor material are alternately laminated. Specifically, the multilayer wiring board 100 includes a core insulating layer 1, a plurality of insulator parts 11, 12, 21, 22, and a plurality of conductor parts 13, 23, 43, 53. The conductor parts 43 and 53 function as pad parts. Further, a through hole 3 is provided in the core insulating layer 1, and a conductor portion 23 serving as a through electrode is provided on the side wall of the through hole. In the example of FIG. 1, the center of the through hole is sealed with a hole filling resin 4. The conductor portion 13 and the conductor portions 43 and 53, which are pad portions, may be connected by conductive portions called vias.

[0017] In addition, a solder resist layer 17 is formed above the insulating portion 12 and below the insulating portion 22, and in the openings of the solder resist layer 17, conductor portions 53, which are pad portions, are disposed. Furthermore, a solder bump 20 is formed above a conductor portion 53 which is a pad portion disposed above the insulating portion 12 .

[0018] (insulation part) The insulating portions 11, 12, 21, and 22 are made of a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a resin mixture thereof, such as an epoxy resin, an acrylic resin, a phenolic resin, a melamine resin, a silicone resin, a polyimide resin, a polyphenylene ether resin, a maleimide resin, a liquid crystal polymer, a fluororesin, or a combination of two or more of these, and may contain an inorganic filler or an organic filler.

[0019] (Conductor) The conductor 13 may have, in order from the lower insulator 11 side, a seed layer 13a and a plating layer 13b (see FIG. 3). The conductor 13 may include various patterns such as wiring, vias, pads, shields, grounds, and dummies, but FIG. 1 shows wiring, vias, and pads. Adjacent conductors 13 are formed spaced apart in the surface direction of the insulator 11.

[0020] Here, the conductor portion excluding the solder bump 20 disposed above the core insulating layer is defined as a first conductor portion, The insulator portion excluding the solder resist layer 17, which is disposed above the core insulating layer, is defined as a first insulator portion, The conductor portion disposed below the core insulating layer is defined as a second conductor portion, When the insulator portion excluding the solder resist layer 17 disposed below the core insulating layer is defined as the second insulator portion, In the multilayer wiring board of the first embodiment, the first conductor portion and the second conductor portion are formed to have the same volume. Alternatively, a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion is A, A ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B, Let A / B be X, The elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the first and second insulators are It may be formed so as to satisfy the following formula (1). The method of deriving the following equation (1) will be described later. α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X- 1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)-0.0014039))…(1) In addition, when the right side of the formula (1) is β, α may be in the range of 0.9β<α<1.1β.

[0021] By satisfying these conditions, the multilayer wiring board of the first embodiment can suppress warping to 0.1 μm or less when the board is 67.5 mm×67.5 mm in size, even when the temperature changes from 260° C. to 22° C.

[0022] Furthermore, the elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the first insulating portion and the second insulating portion may satisfy the following expressions (2) and (3). 15≦α≦50…(2) 4≦E≦16…(3)

[0023] <Derivation of Equation (1)> The above-mentioned formula (1) is introduced by performing a warpage simulation using plate theory for a multilayer wiring board.

[0024] <Simulation model> In the simulation of warpage, the entire multilayer wiring board was modeled, and hereinafter referred to as "multilayer wiring board model A." Specifically, the planar shape of the multilayer wiring board model A was a rectangle of 67.5 mm x 67.5 mm. In addition, the thickness of the core board (including the core insulating layer 1 and the conductive parts 43 formed on the first and second surfaces) was 1200 μm, the thickness of the conductor part 13 was 15 μm, the thickness of the insulator parts 11, 12, 21, and 22 was 30 μm, and the thickness of the solder resist layer 17 was 15 μm. In the multilayer wiring board model A, a first conductor portion and a first insulator portion are provided above the first surface of the core insulating layer, a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer, a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion being A, A ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B, The values ​​of A and B were changed, and a simulation was performed by applying a temperature load (260°C → 22°C) to multilayer wiring board model A, and the warpage at 22°C was calculated. The software used for the evaluation is a viscoelastic laminate thermal warpage analysis program made by Mechanical Design Co., Ltd. The input values ​​are XY dimensions, layer thickness, layer thickness elastic modulus, linear expansion coefficient, and Poisson's ratio, and the output is the amount of warpage. The physical properties can be selected from temperature-dependent data on CTE and elastic modulus, and viscoelasticity (WLF / Arrhenius) for elastic modulus. However, in this example, all materials are set as elastic bodies.

[0025] Here, A / B is set to X.

[0026] Table 1 shows the results of the warpage simulation described above. [Table 1]

[0027] In Example 1, the volume ratio of the first insulating portion was 70%, the volume ratio of the first conductor portion was 30%, the volume ratio of the second insulating portion was 62.5%, and the volume ratio of the second conductor portion was 37.5%. In this case, the multilayer wiring board model A had a warp of 181 μm in the negative direction. Here, the positive direction means that the center of the multilayer wiring board model A goes down and the ends go up as shown in Fig. 5(A), whereas the negative direction means that the center of the multilayer wiring board model A goes up and the ends go down as shown in Fig. 5(B).

[0028] In Example 2, the volume ratio of the first insulating portion was 70%, the volume ratio of the first conductor portion was 30%, the volume ratio of the second insulating portion was 70%, and the volume ratio of the second conductor portion was 30%. In this case, the multilayer wiring board model A hardly warped.

[0029] In Example 3, the volume ratio of the first insulating portion was 70%, the volume ratio of the first conductor portion was 30%, the volume ratio of the second insulating portion was 75%, and the volume ratio of the second conductor portion was 25%. In this case, the multilayer wiring board model A had a warp of 145 μm in the positive direction.

[0030] In comparative example 1, the volume ratio of the first insulating portion was 60%, the volume ratio of the first conductor portion was 40%, the volume ratio of the second insulating portion was 50%, and the volume ratio of the second conductor portion was 50%.In this case, the multilayer wiring board model A experienced a warp of 179 μm in the negative direction.

[0031] In comparative example 2, the volume ratio of the first insulating portion was 60%, the volume ratio of the first conductor portion was 40%, the volume ratio of the second insulating portion was 60%, and the volume ratio of the second conductor portion was 40%.In this case, almost no warping occurred in the multilayer wiring board model A.

[0032] In Comparative Example 3, the volume ratio of the first insulating portion was 60%, the volume ratio of the first conductor portion was 40%, the volume ratio of the second insulating portion was 66.7%, and the volume ratio of the second conductor portion was 33.3%. In this case, the multilayer wiring board model A had a warp of 148 μm in the positive direction.

[0033] When the relationship between the amount of warpage and the variable X is graphed for the above-mentioned Example and Comparative Example, the graphs for the Example and Comparative Example almost match, as shown in Figure 7. From this result, it was found that the amount of warpage of the multilayer wiring board depends on the variable X, regardless of the total volume of the conductor.

[0034] From the above results, it is believed that the amount of warping can be minimized when the variable X = 0, but it is generally difficult to precisely control the copper volume and remaining copper ratio of the wiring board, and there are limitations to designing wiring where X = 0. Therefore, we devised a method to reduce the amount of warping by controlling the linear expansion coefficient and elastic modulus of the insulating resin according to the value of X.

[0035] The elastic modulus is the storage modulus measured by dynamic mechanical analysis (DMA). The storage modulus reflects the elastic properties of a material and is a value that indicates how difficult a material is to deform. The storage modulus is obtained by measurement using a dynamic viscoelasticity measuring device. By measuring while heating, the storage modulus at a desired temperature can be measured.

[0036] The coefficient of thermal expansion (CTE) is a value that indicates the rate of change in length in response to an increase in temperature within a certain temperature range. The CTE is obtained by measurement using a thermomechanical analyzer (TMA). In this embodiment, the coefficient of thermal expansion of the core layer is obtained from a temperature range of, for example, 30°C to 240°C.

[0037] When X=0.8 (Example 1), a simulation was performed with the elastic modulus E (unit: GPa) and thermal expansion coefficient α (unit: ppm / °C) of the insulating layer in the ranges of 4≦E≦15 and 15≦α≦50, as shown in Table 2. From these results, it is possible to select a combination of elastic modulus E and thermal expansion coefficient α that results in a warpage amount close to 0. [Table 2]

[0038] Similarly, when X=1.2 (Example 3) is simulated with the elastic modulus E (unit: GPa) and thermal expansion coefficient α (unit: ppm) of the insulating layer in the range of 4≦E≦15 and 15≦α≦50, the results are shown in Table 3. From these results, it is possible to select a combination of elastic modulus E and thermal expansion coefficient α that results in a warpage close to 0. [Table 3]

[0039] Next, in order to generalize the simulation results, the experimental results were statistically analyzed (regression analysis) to be expressed as a formula. The amount of warpage was set as the objective variable, and the explanatory variables were X, E, and α alone, as well as the interaction between X and α and the interaction between X and E. The squared terms of α, E, and X were not used because their effect on the amount of warpage was found to be small. As a result of performing multiple regression analysis on the results in the table using the above-mentioned objective variables and explanatory variables, the amount of warpage could be expressed by the prediction formula (10). Warpage=-0.383748+X*0.3086234+α*0.0014039+E*0.0023566-0.060395*(X-1)*(α-32.5)-0.113792*(X-1)*(E-10) …(10) The prediction results using equation (10) are shown in Tables 4 and 5. Comparing with the simulation results, there are some differences in the predicted warpage, but it can be seen that the combination of CTE and elastic modulus that results in the warpage closest to 0 is almost the same. [Table 4] [Table 5]

[0040] Regarding formula (10), if the amount of warpage is set to 0 and α is expressed using the formulas for E and X, we obtain formula (1). α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X-1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)- 0.0014039))...Equation (1) When this relational expression is satisfied, the amount of warping can be said to be minimum. In addition, when the right side of the formula (1) is β, α may be in the range of 0.9β<α<1.1β.

[0041] <Design and manufacturing method of multilayer wiring board according to the first embodiment> A method for designing and manufacturing the multilayer wiring board 100 according to the first embodiment will be described. First, a process for producing a core substrate will be described with reference to Fig. 2. Fig. 2 is an explanatory diagram showing an example of the method for manufacturing the core substrate of the present invention.

[0042] (Making the core board) First, through holes 3 for electrically connecting the front and back surfaces are formed by using a drill or the like in a core insulating layer 1 having copper foil 2 attached to both sides (FIG. 2(a)).

[0043] Next, the conductor 23 is formed on the surface of the copper foil 2 and the wall surface of the through hole 3 by electroless plating and electrolytic plating (FIG. 2(b)). The same material as that of the seed layer 13a can be used for the electroless plating of the conductor 23. Also, the same material as that of the plating layer 13b can be used for the electrolytic plating of the conductor 23.

[0044] Next, the through-holes 3 are filled with filling resin 4. Any excess filling resin 4 that protrudes from the through-holes 3 is removed by buffing or the like (FIG. 2(c)). Note that if the through-holes 3 are completely filled with plating in the step shown in FIG. 2(b), this step is omitted.

[0045] Next, the conductor portion 33 is formed on the entire surface by electroless plating and electrolytic plating (FIG. 2(d)). In the step shown in FIG. 2(b), if the through-hole 3 is completely filled with plating or if the conductor portion 33 is not required on the filling resin, this step may be omitted.

[0046] Next, a resist is applied or laminated, and a resist pattern 6 is formed by photolithography on the portions of the conductor parts 23, 33 that are to remain as conductors (FIG. 2(e)).

[0047] Next, the portions of the conductor portions 23 and 33 where the resist pattern 6 is not formed are removed by etching to form a plurality of conductors (FIG. 2(f)).

[0048] Next, the resist pattern 6 is removed to form a core substrate having conductor portions 43 that are pad portions (FIG. 2(g)). The conductor portions 43 are electrically connected to the wiring substrate that is laminated on the core substrate.

[0049] The method for producing the core substrate has been described above, but this is only one example and other methods may be used. Next, the process of laminating insulating resin and conductors on the produced core substrate to produce the multilayer wiring substrate 100 will be described. The insulating resin and conductors are laminated on both sides of the core substrate.

[0050] 3 and 4 are explanatory diagrams showing the multilayer wiring board and the manufacturing method according to the first embodiment of the present invention. Note that in the subsequent explanatory diagrams of the manufacturing method, the core insulating layer 1 of the core substrate is omitted.

[0051] (Making multi-layer wiring boards) First, an insulator portion 11 is formed on a core substrate, and then a via opening 8 is formed by using a laser such as UV or CO2 in the case of a thermosetting resin, or by photolithography in the case of a photosensitive resin, so that a pad portion 43 for electrical connection in the lower layer is exposed (Figure 3(a)). Here, a material is selected for the insulator portion 11 such that the elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) satisfy the condition of the following formula (1). α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X-1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)- 0.0014039))...Equation (1) In addition, when the right side of the formula (1) is β, α may be in the range of 0.9β<α<1.1β.

[0052] Next, a seed layer 13a is formed by electroless plating or sputtering on the upper surface of the insulator portion 11, the wall surface of the via opening 8, and the pad portion 43 that corresponds to the bottom surface of the via opening 8 (FIG. 3(b)).

[0053] (Seed layer) The seed layer 13a is laminated on the insulator portion 11. There is no particular limitation on the material constituting the seed layer 13a, but when it is formed by electroless plating, for example, metal materials such as Cu, Pd, Al, Sn, Ni, and Cr can be used. When it is formed by sputtering, for example, materials such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, Cu alloy, or a combination of two or more of these can be used.

[0054] Next, a resist is applied or laminated onto the seed layer 13a, and then exposed and developed to form a resist pattern 16 corresponding to the pattern of the plating layer 13b (FIG. 3(c)).

[0055] Next, a plating layer 13b is formed by electrolytic plating on the seed layer 13a on which the resist pattern 16 has been formed (FIG. 3(d)).

[0056] (Plating layer) The plating layer 13b is laminated on the upper surface of the seed layer 13a (the surface opposite to the insulator portion 11). The material constituting the plating layer 13b is mainly a metal, and the type is not particularly limited, but for example, Cu and Cu alloys, Ag and Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, Fe, or a combination of two or more of these materials can be used. Next, the resist pattern 16 is removed (FIG. 3(e)).

[0057] Next, the seed layer 13a (the seed layer 13a not covered with the plating layer 13b) exposed by removing the resist pattern 16 is removed by etching (FIG. 3(f)).

[0058] Next, the insulator portion 12 is laminated so as to cover the conductor portion 13 and the underlying insulator portion 11. A material is also selected for the insulator portion 12, whose elastic modulus E (unit: GPa) and thermal expansion coefficient α (unit: ppm) satisfy the requirements of the above-mentioned formula (1). When a desired number of layers of circuits are formed, this step is omitted.

[0059] The above steps are repeated until a circuit with the desired number of layers is formed (FIG. 4(g)).

[0060] After forming the desired number of layers of circuits, a solder resist layer 17 is formed on the outermost layer by coating or lamination (FIG. 4(h)).

[0061] Solder resist openings 18 are formed on the pad portions 53 by photolithography or the like (FIG. 4(i)). The solder resist layer 17 is, for example, a photosensitive epoxy resin, which may contain an inorganic filler. When a non-photosensitive thermosetting resin is used, the solder resist openings 18 are formed by a UV laser, a CO2 laser, photolithography, or the like.

[0062] Next, a surface treatment layer 19 is formed on the pads 53 in the solder resist openings 18 (FIG. 4(l)).

[0063] Next, the multilayer wiring board 100 can be formed by forming the solder bumps 20 in the solder resist openings 18 on the mounting side of the semiconductor element 34 (silicon chip) (FIG. 4(m)). The solder bumps 20 can be formed by screen printing when solder paste is used, and when solder balls are used, the solder bumps 20 can be formed by screen printing flux, then mounting the solder balls by ball transfer, and melting them by reflow.

[0064] 5 shows an example of a mounting state, and shows a state (semiconductor device) in which a semiconductor element 34 (silicon chip) is mounted on a multilayer wiring board 100. In this semiconductor device, electrode terminals of the semiconductor element 34 are electrically connected to corresponding pad portions 53 on the multilayer wiring board 100 via conductive materials such as solder bumps 20 (flip-chip mounting). Furthermore, the gap between the mounted semiconductor element 34 and the multilayer wiring board 100 is filled with underfill resin 35 such as a thermosetting epoxy resin, and mechanical bonding between the semiconductor element 34 and the multilayer wiring board 100 is ensured by heat curing.

[0065] On the other hand, solder bumps 20 used as external connection terminals are formed on pad portions 53 exposed from the solder resist layer 17 on the side opposite to the mounting surface side of the semiconductor element 34 after mounting the semiconductor element 34. Through the solder bumps 20, the multilayer wiring board 100 is mounted on a motherboard or the like. [Explanation of symbols]

[0066] 1 Core insulation layer 2 Copper foil 3 Through Hole 4. Hole filling resin 6, 16 Resist pattern 8 Via opening 11, 12, 21, 22 Insulation section 13, 33 Conductor 13a Seed layer 13b Plating layer 16 Resist Pattern 17 Solder resist layer 18 Solder resist opening 19 Surface treatment layer 20 Solder Bumps 23 Conductor 34 Semiconductor elements 35 Underfill resin 43, 53 Conductor part (pad part) 100 Multilayer wiring board

Claims

1. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; Equipped with The first conductor portion and the second conductor portion have the same volume.

2. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; Equipped with A represents a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion, a ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B; Let A / B be X, The elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the first and second insulators satisfy the following formula (1): α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X- 1)*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)-0.0014039))…(1) In addition, when the right side of the formula (1) is β, α may be in the range of 0.9β<α<1.1β.

3. 2. The multilayer wiring board according to claim 1, The elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the first insulator portion and the second insulator portion satisfy the following formulas (2) and (3). １５≦α≦５０…（２） 4≦E≦16…(3)

4. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; A method for designing a multilayer wiring board comprising: A represents a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion, a ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B; a first step of performing a warpage simulation for at least two values ​​of X within the ranges shown in the following formulas (2) and (3), where A / B is X, the elastic modulus of the first insulator portion and the second insulator portion is E (unit: GPa), and the thermal expansion coefficient is α (unit: ppm); １５≦α≦５０ ・・・（２） 4≦E≦16 ... (3) A second step of performing a multiple analysis by ignoring the square terms of α, E, and X on the result of the warpage simulation in the first step, and calculating the amount of warpage and a relational expression between α, E, and X; A third step of calculating a relational expression of α, E, and X when the amount of warpage is set to 0 in the relational expression obtained in the second step; Using the relational expression obtained in the third step, the elastic modulus E (unit: GPa) and the thermal expansion coefficient α (unit: ppm) of the insulator used in the multilayer wiring board are determined. A method for designing a multilayer wiring board.

5. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core insulation layer having a first surface and a second surface opposite to the first surface; a first conductor portion and a first insulator portion provided above the first surface of the core insulating layer; a second conductor portion and a second insulator portion provided below the second surface of the core insulation layer; A method for designing a multilayer wiring board comprising: A represents a ratio of the first conductor portion to a total volume of the first conductor portion and the first insulator portion, a ratio of the second conductor portion to a total volume of the second conductor portion and the second insulator portion is B; A step of calculating A / B as X; A method for designing a multilayer wiring board, comprising selecting a material such that the elastic modulus of the first insulator portion and the second insulator portion is E (unit: GPa) and the thermal expansion coefficient is α (unit: ppm), where E and α satisfy the following formulas (1) to (3). α=(E*(0.0023566-0.113792*(X-1))-0.113792*(X-1)*10+0.060395*(X-1 )*32.5-0.383748+X*0.3086234) / ((0.060395*(X-1)-0.0014039))・・・(1) １５≦α≦５０ ・・・（２） 4≦E≦16 ... (3)

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