Semiconductor device

Abstract

To provide a display device capable of narrowing a frame and having excellent display characteristics.SOLUTION: A display device has a switch portion or a buffer portion, a logic circuit portion, and a pixel portion. The pixel portion has a first inverted staggered thin film transistor and a pixel electrode connected to a wiring of the first inverted staggered thin film transistor. The switch portion or the buffer portion has a second inverted staggered thin film transistor having a first gate electrode and a second gate electrode sandwiching a first insulating layer, a semiconductor layer, and a second insulating layer therebetween. The logic circuit portion has an inverter circuit composed of a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor. The first to fourth inverted staggered thin film transistors have the same polarity. The inverter circuit is an EDMOS circuit.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a display device having a drive circuit and an inverted staggered thin film transistor in a pixel portion. . [Background technology]

[0002] As a type of field effect transistor, it is a transistor with a semiconductor layer formed on a substrate with an insulating surface. A thin film transistor in which a channel forming region is formed is known. The semiconductor layer to be used is made of amorphous silicon, microcrystalline silicon, or polycrystalline silicon. A typical application of thin film transistors is in liquid crystal television sets. These transistors are in practical use as switching transistors for each pixel that constitutes a display screen.

[0003] In order to reduce the cost of the display device, the number of external components is reduced and the gate driver is There are display devices that are configured with thin film transistors using amorphous silicon or microcrystalline silicon. (See Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-049832 A Summary of the Invention [Problem to be solved by the invention]

[0005] A thin-film transistor in which the channel formation region is formed in an amorphous silicon layer has a high field-effect mobility. In addition, the thin film transistors tend to deteriorate over a long period of use. This causes a problem of the threshold voltage shifting and the on-current decreasing. A thin-film transistor in which the channel formation region is formed in the silicon layer, like a gate driver. In order to configure a driver circuit, the width of the channel forming region is increased and the area of ​​the thin film transistor is reduced. By increasing the on-state current, a sufficient on-state current can be obtained even if the on-state current decreases due to the shift in the threshold voltage. The input current is ensured.

[0006] Alternatively, the number of thin film transistors constituting the driving circuit may be increased to improve the driving efficiency of each thin film transistor. By shortening the operation time, deterioration of the thin film transistor is reduced and sufficient on-current is ensured. is.

[0007] For this reason, the driving circuit is a thin film transistor in which the channel forming region is formed in an amorphous silicon layer. In display devices that form a path, the driving circuit occupies a large area, which hinders the narrowing of the frame of the display device. As a result, the area of ​​the pixel portion, which is the display region, becomes smaller.

[0008] On the other hand, thin-film transistors in which the channel formation region is formed in a microcrystalline silicon layer are Compared to silicon-based thin-film transistors, the field-effect mobility is improved, but the off-current is As a result, there is a problem that sufficient switching characteristics cannot be obtained.

[0009] Thin-film transistors, in which the channel formation region is formed in a polycrystalline silicon layer, are The field effect mobility is much higher than that of a thin-film transistor, and a high on-current can be obtained. The thin film transistor has the above-mentioned characteristics, and is therefore suitable for use as a switching transistor provided in a pixel. It is possible to configure not only transistors for switching but also driver circuits that require high-speed operation. can.

[0010] However, thin-film transistors in which the channel formation region is formed from a polycrystalline silicon layer are Compared to forming a thin-film transistor using a silicon layer, a crystallization process for the semiconductor layer is required. However, the increase in manufacturing cost is a problem. The laser annealing technology required for this is a technology that can be used for large-screen LCD panels because the irradiation area of ​​the laser beam is small. However, there is a problem in that it is not possible to efficiently produce

[0011] Therefore, one embodiment of the present invention is capable of reducing manufacturing costs and has excellent image display characteristics. Another object of the present invention is to provide a display device having a high light-emitting property. It is an object of the present invention to provide a display device which is capable of reducing the size and the frame thereof. [Means for solving the problem]

[0012] The present invention has a driver circuit section and a pixel section, and the driver circuit section includes a logic circuit section and a switch section or The display device has a buffer section, and the TFTs constituting the driver circuit section and pixel section are polarized. The switch section or buffer section has a large on-current flow. The logic circuit is made of depletion-type TFTs. and an inverter circuit composed of enhancement-type TFTs (hereafter referred to as EDMOS circuit) The present invention is characterized in that it is composed of:

[0013] A dual-gate inverted staggered TFT is a TFT that can pass a large on-current. Alternatively, a depletion type inverted staggered TFT is used.

[0014] An EDMOS circuit is a device that uses two or more inverted staggered TFTs with different threshold voltages, typically The TFTs are of the depression type and the enhancement type. The FT includes a first gate electrode, a first gate insulating layer, and a gate insulating film formed on the first gate insulating layer. a semiconductor layer formed on the semiconductor layer; a second gate insulating layer formed on the second gate insulating layer; A second gate electrode is formed in a dual-gate inverted staggered thin film transistor. By doing so, it is possible to control the threshold voltage and configure an EDMOS circuit.

[0015] Or, as a depletion type TFT, impurity elements that act as donors are added to the channel formation region. The inverted staggered TFT with a semiconductor layer doped with ZnO was used as an enhancement type TFT. In addition, a semiconductor layer to which no impurity element serving as a donor is added is used in the channel formation region. An EDMOS circuit can be constructed with the above.

[0016] Alternatively, as a depletion-type TFT, impurities that act as acceptors are added to the channel formation region. The enhancement type TFT is an inverted staggered TFT with a semiconductor layer that is not doped with any metal elements. A semiconductor layer in which impurity elements that act as acceptors are added to the channel formation region as a TFT By using this, an EDMOS circuit can be constructed.

[0017] In addition, the inverted staggered TFT manufactured in the display device of the present invention has a gate electrode and a gate A gate insulating layer formed on the electrode, a semiconductor layer formed on the gate insulating layer, and a semiconductor layer A doped semiconductor layer that functions as a source region and a drain region and a wiring are formed on the doped semiconductor layer. The semiconductor layer formed on the gate insulating layer has a microcrystalline semiconductor layer formed on the gate insulating layer side. The gate insulating layer has an amorphous semiconductor layer on the source region and drain region side. A microcrystalline semiconductor layer is formed on the side of the source region and the drain region, and an amorphous semiconductor layer is formed on the side of the source region and the drain region. A pyramidal microcrystalline semiconductor region and a filling layer are formed between the microcrystalline semiconductor layer and the amorphous semiconductor layer. Therefore, the on-current of the inverted staggered TFT is increased while , the off-current can be suppressed.

[0018] The on-state current is the current that flows between the source and drain electrodes when the transistor is on. For example, in the case of an n-type transistor, the gate voltage is This is the current that flows between the source and drain electrodes when the voltage is higher than the threshold voltage of the transistor.

[0019] The off-state current is the current flowing between the source and drain electrodes when the transistor is off. For example, in the case of an n-type transistor, the gate voltage is This is the current that flows between the source and drain electrodes when the voltage is lower than the threshold voltage of the transistor.

[0020] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted. Effect of the Invention

[0021] According to the present invention, it is possible to reduce the cost of a display device and improve the display characteristics of an image. In addition, it is possible to narrow the frame of the display device, thereby expanding the display area of ​​the display device. It is possible. [Brief description of the drawings]

[0022] [Figure 1] 1 is a block diagram illustrating an entire display device according to an embodiment of the present invention. [Diagram 2] 2 is a diagram illustrating an arrangement of wiring, input terminals, and the like in a display device according to one embodiment of the present invention. [Diagram 3] FIG. 2 is a block diagram illustrating a configuration of a shift register circuit. [Figure 4] FIG. 1 illustrates an example of a flip-flop circuit. [Diagram 5] FIG. 1 shows a layout diagram (top view) of a flip-flop circuit. [Figure 6] FIG. 4 is a timing chart for explaining the operation of the shift register circuit. [Figure 7] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention. [Figure 8] 1A and 1B are a cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 9] 1 is a cross-sectional view illustrating a thin film transistor in a display device according to one embodiment of the present invention. [Figure 10] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention. [Figure 11] 1A and 1B are a cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 12] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention. [Figure 13] 1A and 1B are a cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 14] 1A and 1B are a cross-sectional view and a top view illustrating a driver circuit in a display device according to one embodiment of the present invention. [Figure 15]1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating a multi-tone mask that can be applied to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 20] 1A to 1C are plan views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 24] 1 is an equivalent circuit diagram illustrating a protection circuit applied to a display device according to an embodiment of the present invention. [Diagram 25] 1A and 1B are diagrams illustrating a terminal portion of a display device according to one embodiment of the present invention. [Figure 26] 1A and 1B are diagrams illustrating a terminal portion of a display device according to one embodiment of the present invention. [Figure 27] 1A and 1B are diagrams illustrating an example of a liquid crystal display device according to an embodiment of the present invention. [Figure 28] 1A and 1B are diagrams illustrating an example of a light-emitting display device according to one embodiment of the present invention. [Figure 29] 1A to 1C are diagrams illustrating examples of electronic devices to which an embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention will be described below with reference to the drawings. The present invention is not limited to the embodiments described herein. It will be readily understood by those skilled in the art that various changes can be made in mode and details. Therefore, the present invention should not be construed as being limited to the following embodiments and examples. In addition, when explaining the configuration of the present invention using the drawings, The reference numerals are commonly used even among different drawings.

[0024] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to a block diagram or the like. Reveal.

[0025] FIG. 1(A) shows an example of a block diagram of an active matrix type liquid crystal display device. The liquid crystal display device shown in A) has a pixel section 1 having a plurality of pixels each having a display element on a substrate 100. 01, a scanning line driving circuit 102 for controlling the scanning lines connected to the gate electrodes of the pixels, and a selection and a signal line driver circuit 103 that controls input of a video signal to the selected pixel.

[0026] FIG. 1B is a block diagram of an active matrix type light emitting display device to which the present invention is applied. The light-emitting display device shown in FIG. 1B has a plurality of pixels each having a display element over a substrate 110. A pixel section 111 having a number of pixels, and a first scanning line for controlling a scanning line connected to a gate electrode of each pixel. A first scanning line driver circuit 112 and a second scanning line driver circuit 113, which are connected to the input terminals of the first scanning line driver circuit 112 and the second scanning line driver circuit 113, A signal line driver circuit 114 controls the input. (Thin Film Transistor, hereafter referred to as TFT) and current control T In the case where two TFTs are arranged, the light-emitting display device shown in FIG. 1B has a switching TFT. The signal input to the first scanning line connected to the gate electrode of the first scanning line driver circuit 112 is and a signal input to the second scanning line connected to the gate electrode of the current control TFT. The second scanning line driver circuit 113 generates the signal. The signals input to the two scanning lines may be generated by a single scanning line driver circuit. In addition, for example, the operation of the switching element can be controlled by the number of TFTs that the switching element has. A plurality of first scanning lines used for controlling the pixel may be provided for each pixel. In this case, Alternatively, all of the signals input to the first scanning lines may be generated by a single scanning line driver circuit. Alternatively, a plurality of scanning line driving circuits may be provided and each of them may generate the signal.

[0027] In this embodiment, the scanning line driving circuit 102, the first scanning line driving circuit 112, the second scanning line driving circuit In the embodiment shown, the driving circuit 113 and the signal line driving circuits 103 and 114 are formed in the display device. , the scanning line driving circuit 102, the first scanning line driving circuit 112, or the second scanning line driving circuit 1 A part of the signal line driver circuit 103 and 11 may be implemented as a semiconductor device such as an IC. A part of 4 may be implemented as a semiconductor device such as an IC.

[0028] FIG. 2 shows a signal input terminal, a scanning line, a signal line, and a protection circuit including a nonlinear element, which constitute a display device. A diagram for explaining the positional relationship between the scanning line and the pixel portion. The pixel section 127 is formed by intersecting the pixel line 123 and the signal line 124. The pixel portion 127 corresponds to the pixel portion 101 and the pixel portion 111 shown in FIG.

[0029] The pixel section 127 is configured with a plurality of pixels 128 arranged in a matrix. 1, a pixel TFT 129 connected to a scanning line 123 and a signal line 124, a storage capacitor 130, and a pixel It is configured to include an electrode 131 .

[0030] In the pixel configuration shown here, in the storage capacitor 130, one electrode and the pixel TFT 129 The pixel electrode 1 is connected to the capacitance line 132, and the other electrode is connected to the capacitance line 132. 31 drives display elements (liquid crystal elements, light emitting elements, contrast media (electronic ink), etc.) The other electrodes of these display elements are connected to a common terminal 133. There are.

[0031] The protection circuit is disposed between the pixel section 127 and the signal line input terminal 122. The protection circuit is disposed between the scanning line driver circuit and the pixel section 127. By providing a path, a surge caused by static electricity or the like is prevented from occurring in the scanning line 123, the signal line 124, and the capacitance line 137. The pixel TFT 129 and the like are configured not to be destroyed by the application of a voltage. The protection circuit is configured to release the charge to the common wiring when a surge voltage is applied. is.

[0032] In this embodiment, a protection circuit 134 for the scanning line 123, a protection circuit 135 for the signal line 124, In this example, a protection circuit 136 for the capacitance wiring 137 is provided. In addition, when the scanning line driving circuit is not implemented by a semiconductor device such as an IC, Therefore, the protection circuit 134 does not need to be provided on the scanning line 123 side.

[0033] Using the TFT of the present invention in each of these circuits has the following advantages.

[0034] It is preferable that the pixel TFT has high switching characteristics. By increasing the switching characteristic, the contrast ratio of the display device can be increased. In order to increase the on-current, it is effective to increase the on-current and decrease the off-current. The pixel TFT that uses this has a large on-current and a small off-current, so the switching characteristics are This makes it possible to realize a thin-film transistor with a high contrast ratio. can.

[0035] The driving circuit is roughly divided into a logic circuit section and a switch section or a buffer section. The TFT to be provided may be configured so that the threshold voltage can be controlled. Alternatively, it is preferable that the TFT provided in the buffer section has a large on-current. It is possible to control the threshold voltage of the TFT in the logic circuit section, and the switch section or buffer section It is possible to increase the on-current of the TFT provided in the display. This reduces the area and contributes to narrowing the frame.

[0036] The protection circuit is provided on the periphery of the pixel area, which is one of the obstacles to narrowing the frame. On the other hand, the display device described in this specification can reduce the area of ​​the protection circuit, This can prevent the framing from being hindered.

[0037] (Embodiment 2) In this embodiment mode, a circuit diagram of a driver circuit of the display device described in the first embodiment will be described. 3 to 6.

[0038] First, a shift register circuit constituting the scanning line driving circuit shown in the first embodiment will be described. do.

[0039] The shift register circuit shown in FIG. 3 has a plurality of flip-flop circuits 201 and a control signal line 202, control signal line 203, control signal line 204, control signal line 205, control signal line 206, and a reset line 207.

[0040] As shown in the shift register circuit of FIG. 3, in the flip-flop circuit 201, the first input A start pulse SSP is input to the terminal IN via the control signal line 202, and the following stages The input terminal IN is connected to the output signal terminal S of the previous flip-flop circuit 201. OUT is connected In addition, the reset terminal RES of the Nth stage (N is a natural number) is the same as that of the (N+3)th stage. Flip-flop circuit output signal terminal S out and reset line 207. The clock terminal CLK of the Nth stage flip-flop circuit 201 is connected to a control signal line 203. Assuming that the first clock signal CLK1 is input through the (N+1)th stage, The clock terminal CLK of the flip-flop circuit 201 is connected to a second control signal line 204. The clock signal CLK2 is input to the (N+2)th flip-flop circuit 2 A third clock signal CLK is input to the clock terminal CLK of the clock 01 through a control signal line 205. 3 is input to the clock terminal C of the (N+3)th flip-flop circuit 201. A fourth clock signal CLK4 is input to LK via a control signal line 206. The clock terminal CLK of the (N+4)th flip-flop circuit 201 receives the control signal A first clock signal CLK1 is input via a line 203. The flop circuit 201 has a gate output terminal G out Therefore, the Nth flip-flop circuit Output SRoutN.

[0041] Although the connection between the flip-flop circuit 201 and the power supply and the power supply line is not shown, The flip-flop circuit 201 is supplied with a power supply potential Vdd and a power supply potential GND via a power supply line. are being provided.

[0042] In addition, the power supply potential described in this specification corresponds to the potential difference when the reference potential is 0V. Therefore, the power supply potential is sometimes called the power supply voltage.

[0043] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, A and B are also connected electrically. Being electrically connected means that there is an object between A and B that has some electrical effect. In this case, A and B are roughly the same node through the object. In the case of the MOS type, A and B are connected via a switching element such as a TFT, and the switching element When A and B are approximately at the same potential due to the conduction of The potential difference across the resistor element is small enough not to affect the operation of the circuit including A and B. When considering the circuit operation, A and B can be regarded as the same node. This indicates a state where there is no support.

[0044] Next, in FIG. 4, the flip-flop circuit 201 included in the shift register circuit shown in FIG. The flip-flop circuit 201 shown in FIG. The logic circuit section 211 includes a TFT 213 to a TFT 218. The switch section 212 includes TFTs 219 to 222. The path section 211 is a circuit that outputs a signal to a switch section 212 in the subsequent stage in response to a signal input from the outside. The switch unit 212 is a circuit for switching the output signal. The TFT, which functions as a switch, is turned on or off in response to a signal input from the control circuit section 211. The circuit switches the voltage across the TFT and outputs a current according to the size and structure of the TFT.

[0045] In the flip-flop circuit 201, the input terminal IN is connected to the gate terminal of the TFT 214, The reset terminal is connected to the gate terminal of the TFT 213. The clock terminal CLK is connected to the first terminal of the TFT 219 and the second terminal of the TFT 22. The power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of the TFT 214. The power supply potential GND is supplied to the first terminal of the TFT 216 and the second terminal of the TFT 216. The power supply lines are connected to the second terminal of the TFT 213, the second terminal of the TFT 215, and the second terminal of the TFT 217. a second terminal of the TFT 218, a second terminal of the TFT 220, and a second terminal of the TFT 222; In addition, the first terminal of the TFT 213, the second terminal of the TFT 214, 5, the gate terminal of TFT218, the gate terminal of TFT219, and the first terminal of TFT22 The first terminal and the gate terminal of the TFT 216 are connected to each other. denotes the gate terminal of the TFT 215, the first terminal of the TFT 217, the first terminal of the TFT 218, T It is connected to the gate terminal of the TFT220 and the gate terminal of the TFT222. Output terminal G out is connected to the second terminal of the TFT 219 and the first terminal of the TFT 220. Output signal terminal Sout The second terminal of the TFT 221 and the first terminal of the TFT 222 are is connected to the terminal.

[0046] In this case, the TFTs 213 to 222 are all N-type TFTs. However, the TFTs 213 to 222 may be P-type TFTs. .

[0047] A TFT has at least three terminals including a gate, a drain, and a source. The element has a channel forming region between a drain region and a source region, and the drain region A current can flow through the channel forming region and the source region. The drain may be switched depending on the TFT structure and operating conditions, so it is unclear which is the drain. It is difficult to identify which is the source and which is the drain. The regions that function as the source and drain are not called the source or drain, but are called, for example, In this case, the terminal that functions as the gate is written as the first terminal and the second terminal. In this case, it is referred to as the gate terminal.

[0048] Next, an example of a layout diagram of the flip-flop circuit 201 shown in FIG. 4 is shown in FIG.

[0049] The flip-flop circuit of FIG. 5 includes a power supply line 231 to which a power supply potential Vdd is supplied, a reset line 232, control signal line 203, control signal line 204, control signal line 205, control signal line 206, a control signal line 233, a power supply line 234 to which a power supply potential GND is supplied, a logic circuit unit 211, and The logic circuit section 211 includes a switch section 212. The logic circuit section 211 includes a TFT 213 to a TFT 218. The switch section 212 includes TFTs 219 to 222. 5, the gate output terminal G out Wiring connected to output signal terminal S out Connected to The wiring is also shown.

[0050] In FIG. 5, a semiconductor layer 235, a first wiring layer 236, a second wiring layer 237, a third wiring layer The first wiring layer 236 is a gate insulating layer. The second wiring layer 237 is formed from a layer that forms a source electrode of the TFT. The third wiring layer 238 is formed from a layer that forms a drain electrode. However, the present invention is not limited to this, and may be formed, for example, by a third wiring layer. The layer 238 may be formed as a wiring layer separate from the layer forming the pixel electrodes.

[0051] The connections between the circuit elements in FIG. 5 are as described in FIG. 4. Since the flip-flop circuit to which the first clock signal is input is shown, Connections to signal line 204 through control signal line 206 are not shown.

[0052] In this embodiment, in the layout diagram of the flip-flop circuit in FIG. By controlling the threshold voltage of the TFT216 or TFT217 in the EDMO Typically, the TFT 216 is a depletion type. The TFT 217 is configured as an enhancement type EDMOS circuit 223, and a switch The TFTs 219 to 222 in the unit 212 are dual-gate TFTs or One of its features is that it is a pressure-type TFT.

[0053] The channel forming region of the depletion type TFT 216 is formed by doping a layer having an impurity element serving as a donor. The channel forming region of the enhancement type TFT 217 is a semiconductor layer that functions as a donor. By using a semiconductor layer that is not doped with an impurity element, the EDMOS circuit 223 can be formed. This can be done.

[0054] Alternatively, the channel formation region of the depletion type TFT216 is filled with impurities that act as acceptors. The semiconductor layer is not doped with any metal elements, and the channel of the enhancement type TFT217 is formed. By making the region a semiconductor layer containing an impurity element that acts as an acceptor, an EDMOS circuit 2 23 can be formed.

[0055] Alternatively, use the depletion mode TFT216 or enhancement mode TFT217. The depletion is achieved by controlling the potential of the back gate electrode. The TFT 216 can be formed as a junction type TFT or an enhancement type TFT 217. Therefore, an EDMOS circuit 223 can be formed.

[0056] For this reason, the TFT of the display device is either an n-channel TFT or a p-channel TFT. It can be formed with TFTs of only one polarity.

[0057] In addition, the TFT 216 in the logic circuit section 211 passes a current in response to the power supply potential Vdd. The TFT is a dual-gate TFT or a depletion-type TFT216. By increasing the current flowing through the TFT, the TFT size can be reduced without compromising performance. It is possible to standardize the system.

[0058] In addition, in the TFT constituting the switch unit 212, the amount of current flowing through the TFT is increased, And because it can be switched on and off quickly, it can be used without compromising performance. The area occupied by the TFT can be reduced. In addition, the area in which the TFTs 219 to 220 are arranged in the switch section 212 can be reduced. As shown in the figure, the FT 222 is a semiconductor layer 235 connected to a first wiring layer 236 and a third wiring layer 237. 38 to sandwich the two layers, forming a dual-gate TFT.

[0059] In addition, in FIG. 5, the dual gate type TFT has a semiconductor layer 235 and a first wiring layer 236, The third wiring layer is connected to the first wiring layer 236 through a contact hole 239 and has the same potential. Although an example in which the wiring layer 238 is sandwiched between the wiring layer 238 and the wiring layer 238 has been shown, the present invention is not limited to this configuration. For example, a control signal line may be provided separately for the third wiring layer 238. The potential of the third wiring layer 23 may be controlled independently of the first wiring layer 236. 8 controls the threshold voltage of the TFT, increasing the amount of current flowing through the TFT, improving performance. The area occupied by the TFT and the circuit formed by the TFT can be reduced without reducing the performance. The area occupied can be reduced.

[0060] In the layout diagram of the flip-flop circuit shown in FIG. The shape of the channel forming region of T222 may be U-shaped (U-shaped or horseshoe-shaped). In addition, in Figure 5, the size of each TFT is the same, but the output varies depending on the size of the downstream load. Force signal terminal S out or gate output terminal G out The size of each TFT connected to the May be changed.

[0061] Next, the operation of the shift register circuit shown in FIG. 3 will be described using the timing chart shown in FIG. FIG. 6 shows the control signal lines 202 to 206 shown in FIG. The start pulse SSP, the first clock signal CLK1 to the fourth clock signal CLK2 are supplied. CLK4, and the output signal terminals S of the first to fifth flip-flop circuits. out from The output signals Sout1 to Sout5 are shown. In the explanation of FIG. 6, The reference characters given to the respective elements in FIG. 5 are also used.

[0062] FIG. 6 shows a case where each of the TFTs in the flip-flop circuit is an N-type TFT. 1 is a timing chart showing the first clock signal CLK1 and the fourth clock signal C As shown in the figure, LK4 is shifted by 1 / 4 wavelength (a section divided by dotted lines). It has become.

[0063] First, during the period T1, a start pulse SSP is applied to the first stage flip-flop circuit. When the signal is input at a high level, the logic circuit section 211 switches the TFTs 219 and 221 of the switch section. At this time, the first clock signal C Since LK1 is at the L level, Sout1 is at the L level.

[0064] During the period T1, the flip-flop circuits from the second stage onwards receive a signal at the IN terminal. Since no signal is input, the shifter does not operate and outputs a low level. In the following description, each flip-flop circuit of the register circuit outputs an L level. .

[0065] Next, in the period T2, in the first stage flip-flop circuit, the logic The circuit unit 211 controls the switch unit 212. In the period T2, the first clock signal CL Since K1 is at the H level, Sout1 is at the H level. Also, in the period T2, In the flip-flop circuit, Sout1 is input to the IN terminal at a H level, and the logic circuit section 211 turns on TFT219 and TFT221 of the switch section, and TFT220 and TFT At this time, since the second clock signal CLK2 is at the L level, ut2 is at L level.

[0066] During the period T2, the flip-flop circuits from the third stage onwards receive a signal at the IN terminal. Since no input is input, the L level is output without operating.

[0067] Next, during a period T3, the first stage flip-flop circuit holds the state of the period T2. The logic circuit section 211 controls the switch section 212 so that the The first clock signal CLK1 is at H level, and Sout1 is at H level. During the period T3, in the second stage flip-flop circuit, the logic circuit section 2 11 controls the switch unit 212. In the period T3, the second clock signal CLK2 is H Since the third flip-flop in the period T3 is at the H level, Sout2 is at the H level. In the drop circuit, Sout2 is input to the IN terminal at a H level, and the logic circuit unit 211 is switched The TFTs 219 and 221 in the switch section are turned on, and the TFTs 220 and 222 are turned off. At this time, the third clock signal CLK3 is at the L level, so Sout3 is at the L level. .

[0068] During the period T3, the flip-flop circuits from the fourth stage onwards receive a signal at the IN terminal. Since no input is input, the L level is output without operating.

[0069] Next, during a period T4, the first clock signal CLK1 is at the L level, and Sout1 is During the period T4, the second-stage flip-flop circuit The logic circuit unit 211 controls the switch unit 212 so that the state of 3 is maintained. During the period T4, the second clock signal CLK2 is at the H level, and Sout2 is at the H level. In the third stage flip-flop circuit, the same signal is output during the period T4 as in the period T3. Similarly, the logic circuit unit 211 controls the switch unit 212. In the period T4, the third clock Since the clock signal CLK3 is at H level, Sout3 is at H level. In the fourth flip-flop circuit, Sout3 is input to the IN terminal at a H level, and the logic The logic circuit unit 211 turns on the TFT 219 and the TFT 221 of the switch unit 212, 20 and TFT 222 are turned off. At this time, the fourth clock signal CLK4 is at the L level. Therefore, Sout4 is at the L level.

[0070] During the period T4, the flip-flop circuits from the 5th stage onwards receive a signal at the IN terminal. Since no input is input, the L level is output without operating.

[0071] Next, during a period T5, the first stage flip-flop circuit holds the state of the period T4. The logic circuit unit 211 controls the switch unit 212 so that Therefore, the first clock signal CLK1 is at the L level, and Sout1 is at the L level. During the period T5, in the second stage flip-flop circuit, the logic circuit part 211 controls the switch unit 212. In the period T5, the second clock signal CLK2 is Since the output of the third stage is at the L level, Sout2 is at the L level. In the flip-flop circuit, the logic circuit unit 211 switches so as to hold the state of the period T4. Therefore, during the period T5, the third clock signal CLK3 is During the period T5, the fourth flip-flop is turned on. In the flip-flop circuit, the logic circuit section 211 controls the switch section 212 in the same manner as in the period T4. During the period T5, the fourth clock signal CLK4 is at the H level, so that Sout4 is The fifth and subsequent flip-flop circuits are at the H level. The wiring is the same as that of a flip-flop circuit, and the timing of the input signal is also the same. Therefore, the description will be omitted.

[0072] As shown in the shift register circuit of Figure 3, Sout4 is the first stage flip-flop circuit. During the period T5, Sout4 becomes H level, and this signal The reset signal is input to the reset terminal RES of the first flip-flop circuit. As a result, the TFT 219 and the TFT 221 of the switch unit 212 are turned off, and the TFT 22 0 and TFT222 are turned on. Then, Sout1 of the first stage flip-flop circuit is , the L level is output until the next start pulse SSP is input.

[0073] By the above-described operation, the flip-flop circuits in the second and subsequent stages can The logic circuit is reset based on the reset signal output from the Sou As shown in t1 to Sout5, a signal with a waveform shifted by 1 / 4 wavelength of the clock signal is The shift register circuit may be an output shift register circuit.

[0074] In addition, the logic circuit section 211 includes an enhancement type and a depletion type flip-flop circuit. The TFT of the EDMOS circuit combined with the junction type, the dual gate type By providing the TFT, the current flowing through the TFT constituting the logic circuit unit 211 can be reduced. The amount of current can be increased, and the area occupied by the TFT and This makes it possible to reduce the area occupied by the circuitry formed by the TFT. In the TFT constituting the portion 212, the amount of current flowing through the TFT is increased, and the TFT is turned on and off. Fast switching speeds reduce the area occupied by TFTs without compromising performance Furthermore, the area occupied by the circuitry formed by the TFTs can be reduced. The display device can have a narrower frame, be smaller, and have higher performance.

[0075] In addition, a latch circuit, a level shifter circuit, and the like are provided in the signal line driver circuit shown in the first embodiment. A buffer section is provided at the final stage of transmitting a signal from the signal line driver circuit to the pixel section, and the current The signal line driver circuit sends the amplified signal to the pixel section. A TFT with a large current, typically a dual-gate TFT or a depletion-type TFT. By providing T, it is possible to reduce the area of ​​the TFT, and the area occupied by the signal line driver circuit is Therefore, it is possible to reduce the area of ​​the display device, thereby making it possible to realize a display device with a narrower frame, a smaller size, and higher performance. In addition, the shift register, which is a part of the signal line driver circuit, requires high-speed operation. Therefore, it is preferable to mount the display device using an IC or the like.

[0076] (Embodiment 3) In this embodiment, in the display device shown in the first and second embodiments, The structures of thin film transistors in a circuit section, a switch section, and a pixel section are shown. In thin film transistors, n-type has higher carrier mobility than p-type. If all thin film transistors formed on the substrate are standardized to the same polarity, the number of processes can be reduced. Therefore, in this embodiment, an n-type thin film transistor will be described. do.

[0077] 7 and 8A show a logic circuit section 391 and a switch section 392 of the display device according to the present embodiment. 393 and a cross-sectional view of one embodiment (structure 1) of a pixel portion 395.

[0078] The EDMOS circuit is shown in the logic circuit section 391 of the display device shown in FIG. Either the depletion type TFT or the enhancement type TFT has a gate electrode 3 3 and a back gate electrode 373. In addition, the other of the depletion type TFT or enhancement type TFT is a TF In addition, the cross-sectional view CD of the logic circuit unit 391 shown in FIG. The cross-sectional view CE of the logic circuit portion 391 shown in (A) is the same as the cross-sectional view CD and CE of the top view of FIG. Corresponds to each one.

[0079] In the switch section 393 of the display device shown in FIG. A dual gate TFT 300c having a pole 374 is formed.

[0080] The switching element in the pixel of the pixel section 395 of the display device shown in FIG. In addition, the second gate insulating layer 379, the capacitance wiring 353, and the wiring 375 form This forms a capacitive element 300e.

[0081] The TFT 300a includes a gate electrode 303, a first semiconductor layer 333a, and a second semiconductor layer 333b on a substrate 301. The second semiconductor layer 333b, the third semiconductor layer 363, the gate electrode 303 and the first semiconductor The first gate insulating layer 309 is provided between the first and second semiconductor layers 333a and 363. and impurity semiconductor layers 355 and 356 which function as a source region and a drain region. The first semiconductor layer 333a and the second semiconductor layer 333b are connected to the wiring 346 and 347. The second semiconductor layer 333b, the third semiconductor layer 363, the first gate insulating layer 309, and the impurity A second insulating film covering the impurity semiconductor layers 355 and 356 and the wirings 346 and 347 in contact with the impurity semiconductor layers. A second gate insulating layer 379 is formed, and the gate electrode 30 is connected to the second gate insulating layer 379. In a region facing the first gate electrode 373, a back gate electrode 373 is provided.

[0082] The TFT 300b includes a gate electrode 304, a first semiconductor layer 333a, and a second semiconductor layer 333b on a substrate 301. The second semiconductor layer 333b, the third semiconductor layer 363, the gate electrode 304 and the first semiconductor The first gate insulating layer 309 is provided between the first and second semiconductor layers 333a and 363. and impurity semiconductor layers 356 and 357 functioning as a source region and a drain region. The semiconductor layer includes wirings 347 and 348 in contact with the semiconductor layer.

[0083] As shown in FIG. 8A, the gate electrode 303 of the TFT 300a and the and the wiring 347 of the TFT 300b are formed on the insulating layer 381 at the same time as the pixel electrode 383. The two terminals are connected via a wire 384.

[0084] The TFT 300c includes a gate electrode 305, a first semiconductor layer 334a, and a second semiconductor layer 334b ​​on a substrate 301. The second semiconductor layer 334b, the third semiconductor layer 364, the gate electrode 305 and the first semiconductor The first gate insulating layer 309 is provided between the first and second semiconductor layers 334a and 364. and impurity semiconductor layers 358 and 359 functioning as a source region and a drain region. The first semiconductor layer 334a and the wiring 349 and 350 are in contact with the semiconductor layer. The second semiconductor layer 334b, the third semiconductor layer 364, the first gate insulating layer 309, and the non- A second gate insulating layer 379 covering the pure semiconductor layers 358 and 359 and the wirings 349 and 350 is formed, and in a region facing the gate electrode 305 via the second gate insulating layer 379, It has a back gate electrode 374 .

[0085] The TFT 300d includes a gate electrode 306, a first semiconductor layer 335a, and a second semiconductor layer 335b on a substrate 301. The second semiconductor layer 335b, the third semiconductor layer 365, the gate electrode 306 and the first semiconductor The first gate insulating layer 309 is provided between the first and second semiconductor layers 335a and 365. The impurity semiconductor layers 360 and 361 function as a source region and a drain region, respectively. The semiconductor layer includes wirings 351 and 352 in contact with the semiconductor layer.

[0086] The capacitor 300e includes a second gate insulating layer 379, a capacitor wiring 353, and a wiring 375. It consists of:

[0087] The substrate 301 may be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of this manufacturing process. A plastic substrate or the like having a sufficient heat resistance can be used. When this is not required, a metal substrate such as a stainless steel alloy with an insulating layer on its surface is used. The glass substrate may be, for example, barium borosilicate glass or aluminoborosilicate glass. It is preferable to use a non-alkali glass substrate such as an acid glass or an aluminosilicate glass. The substrate 301 is a 3rd generation (550 mm x 650 mm) or 3.5th generation (600 mm ×720mm, or 620mm×750mm), 4th generation (680mm×880mm, or 730mm x 920mm), 5th generation (1100mm x 1300mm), 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm×2400mm), 9th generation (2400mm×2800mm, 2450m 10th generation (2950mm x 3400mm) and other glass substrates It is possible.

[0088] The gate electrodes 303 to 306 and the capacitance wiring 307 are made of molybdenum, titanium, chromium, or tantalum. , tungsten, aluminum, copper, neodymium, scandium, or other metal materials, The insulating film can be formed in a single layer or a multilayer structure using an alloy material containing the above as a main component. Semiconductor layers such as polycrystalline silicon doped with impurity elements such as phosphorus, and AgPdC An alloy may also be used.

[0089] For example, the gate electrodes 303 to 306 and the capacitance wiring 307 may have a two-layer laminate structure. Two-layer structure with a molybdenum layer on a tungsten layer or a molybdenum layer on a copper layer A laminated bilayer structure, or a bilayer structure with a titanium nitride layer or a tantalum nitride layer laminated on a copper layer Preferably, the titanium nitride layer and the molybdenum layer are laminated to form a two-layer structure. The laminated structure is a tungsten layer or a tungsten nitride layer, and an aluminum and silicon layer. A titanium nitride layer or a titanium layer is laminated with an alloy of aluminum and titanium or an alloy of aluminum and titanium. It is preferable to form a laminate in which a metal layer that functions as a barrier layer is formed on a layer with low electrical resistance. By stacking, electrical resistance is low and diffusion of metal elements from the metal layer to the semiconductor layer is prevented. It can be stopped.

[0090] The first gate insulating layer 309 is formed by depositing silicon oxide using a CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer or a silicon oxynitride layer is formed in a single layer or by stacking. The first gate insulating layer 309 can be formed of a silicon oxide or an oxide. By forming the first semiconductor layers 333a to 335a from silicon nitride, the first semiconductor layers 333a to 335a are microcrystalline semiconductors. When used as a dielectric layer, it is possible to reduce fluctuations in the threshold voltage of a thin film transistor.

[0091] In this specification, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The content is high, and preferably, it is measured by Rutherford backscattering spectrometry (RBS). rford Backscattering Spectrometry) and hydrogen forward Using the hydrogen forward scattering method (HFS: Hydrogen Forward Scattering) When measured, the composition range was 50-70 atomic % oxygen, 0.5-15 atomic % nitrogen, This refers to a material that contains 25 to 35 atomic % silicon and 0.1 to 10 atomic % hydrogen. Silicon nitride oxide is a material that contains more nitrogen than oxygen. Therefore, preferably, the composition range is 5 to 100% oxygen as measured by RBS and HFS. ~30 atomic %, nitrogen 20~55 atomic %, silicon 25~35 atomic %, hydrogen 10~3 0 atomic %. However, silicon oxynitride or silicon oxynitride When the total of the atoms constituting the silicon is taken as 100 atomic %, the content of nitrogen, oxygen, silicon and hydrogen is The ownership ratio shall be within the above range.

[0092] The first semiconductor layers 333a to 336a are formed of microcrystalline semiconductor layers. It is a semiconductor with an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystalline). A conductor is a semiconductor that has a third stable state in terms of free energy and has short-range order. That is, it is a crystalline semiconductor having lattice distortion, and the crystal grain size is preferably 2 nm or more and 200 nm or less. Preferably, the diameter of the columnar grains is 10 nm or more and 80 nm or less, more preferably, 20 nm or more and 50 nm or less. The crystals or needle-like crystals grow in the normal direction to the substrate surface. In some cases, grain boundaries are formed at the interfaces of the needle-like crystals.

[0093] Microcrystalline silicon, a typical example of a microcrystalline semiconductor, has a Raman spectrum that is different from that of single-crystal silicon. Indicates 520cm -1 The wave number is shifted to the lower side than that of single crystal silicon. 520cm -1 and 480 cm, which indicates amorphous silicon. -1 Between the microcrystalline silicon There is a peak in the Mann spectrum. Also, to terminate dangling bonds, It contains at least 1 atomic % or more of hydrogen or halogen. The lattice distortion is further reduced by adding rare gas elements such as fluorine, argon, krypton, or neon. By promoting the growth of the crystals, the stability of the crystals is increased, and a good microcrystalline semiconductor can be obtained. Such a description is given, for example, in US Pat. No. 4,409,134.

[0094] In addition, secondary ion mass spectrometry of oxygen and nitrogen contained in the first semiconductor layers 333a to 336a was performed. The concentration measured by the method is 1×10 18 atoms / cm 3 By making it less than This is preferable because it can improve the crystallinity of the semiconductor layers 333a to 336a.

[0095] The third semiconductor layers 363 to 366 are amorphous semiconductor layers or amorphous semiconductor layers containing halogen. The amorphous semiconductor layer is formed of a nitrogen-containing amorphous semiconductor layer. The nitrogen contained may be present, for example, as an NH group or an NH2 group. The layer is formed using amorphous silicon.

[0096] When the third semiconductor layers 363 to 365 are formed of an amorphous semiconductor layer containing nitrogen, the amorphous semiconductor The slope is steeper than the band tail of the conductor band gap, As a result, the off-current of the thin film transistor is can be reduced.

[0097] FIG. 9 shows the first gate insulating layer 309 of FIG. 7 and the gate insulating layer 302 functioning as a source region and a drain region. 1 shows an enlarged view of the area between the impurity semiconductor layers 355 to 361.

[0098] As shown in FIG. 9A, the second semiconductor layers 333b to 335b are a to 335a and the third semiconductor layers 363 to 365. The layers 333b to 335b include a microcrystalline semiconductor region 367 and The first semiconductor layer 333a has an amorphous semiconductor region 368 filled therebetween. A microcrystalline semiconductor region 367 extending in a convex shape from the third semiconductor layers 363 to 365 The amorphous semiconductor region 368 is formed of the same material as the amorphous semiconductor region 368. In particular, the amorphous semiconductor region is formed of an amorphous semiconductor region containing halogen or an amorphous semiconductor region containing nitrogen. This may be done.

[0099] The third semiconductor layers 363 to 365 are amorphous semiconductor layers having low electrical conductivity and high resistivity. An amorphous semiconductor layer having a halogen, an amorphous semiconductor layer having nitrogen, or an amorphous semiconductor layer having an NH group By forming the thin film transistor using an amorphous semiconductor layer, the off-current of the thin film transistor can be reduced. In addition, in the second semiconductor layers 333b to 335b, the pyramidal microcrystalline semiconductor regions 367 Therefore, when a voltage is applied to the wiring while the thin film transistor is on, the The resistance in the direction of the gate electrode, i.e., the resistance between the semiconductor layer and the source region or the drain region, is It is possible to lower the ON current of the thin film transistor and to increase the ON current of the thin film transistor.

[0100] As shown in FIG. 9B, the second semiconductor layers 333b to 335b are It may be a structure provided between 333a to 335a and the impurity semiconductor layers 355 to 361. That is, between the second semiconductor layers 333b to 335b and the impurity semiconductor layers 355 to 361 In this structure, the third semiconductor layer is not formed. The microcrystalline semiconductor region 367 and the amorphous semiconductor region filled between the microcrystalline semiconductor region 367 Specifically, the first semiconductor layers 333a to 335a have a micro-structure extending in a convex shape. The semiconductor device is formed of a crystalline semiconductor region 367 and an amorphous semiconductor region 368. In the structure, the ratio of the microcrystalline semiconductor region 367 to the amorphous semiconductor region 368 is low. Furthermore, it is preferable that the carriers are arranged between the pair of impurity semiconductor layers 355 to 361. In the flow region, the ratio of the microcrystalline semiconductor region 367 is preferably low. In addition, the off-state current of the thin film transistor can be reduced. In the case of 335b, the vertical direction when a voltage is applied to the wiring while the thin film transistor is on Resistance in the thickness direction, i.e., between the semiconductor layer and the source or drain region It is possible to reduce the resistance and increase the on-current of the thin film transistor. .

[0101] The microcrystalline semiconductor region 367 is formed by the first gate insulating layer 309 and the third semiconductor layers 363 to 366. The crystal grains are convex and narrow toward the top from the first gate insulating layer 309 to the first gate insulating layer 309. Alternatively, the crystal grains may be convex crystal grains whose width increases toward the semiconductor layer 363 of FIG.

[0102] In the second semiconductor layers 333b to 335b, the microcrystalline semiconductor region 367 is From the insulating layer 309 to the third semiconductor layers 363 to 365, the crystal grains are convex and narrow at the tip. In this case, the first semiconductor layers 333a to 335a are closer to the third semiconductor layers 363 to 365a. This is because the proportion of the microcrystalline semiconductor region is higher in the first semiconductor layers 333a to 333b than in the second semiconductor layer 333c. A microcrystalline semiconductor region 367 grows in the film thickness direction from the surface of 35a. When the hydrogen flow rate relative to silane is low or the concentration of nitrogen-containing source gas is high, microcrystals The growth of crystal grains in the semiconductor region 367 is suppressed, and the crystal grains become pyramidal. This is because only the poor semiconductor region is deposited.

[0103] In addition, the second semiconductor layers 333b to 335b preferably contain nitrogen. The interface between the crystal grains in the crystalline semiconductor region 367 and the microcrystalline semiconductor region 367 and the amorphous semiconductor At the interface with region 368, nitrogen, typically an NH or NH2 group, is bonded to the silicon atom. This is because when the dangling bonds of the first semiconductor are bonded, the defects are reduced. The nitrogen concentration in layers 333b to 335b is 1×10 19 atoms / cm 3 More than 1×10 21 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 〜1×10 21 atoms / cm 3 By this, the dangling bonds of silicon atoms are substituted with nitrogen, preferably The NH group is easily bridged, and carriers flow more easily. The dangling bonds of the semiconductor atoms are terminated with NH2 groups, and the defect levels disappear. As a result, when a voltage is applied between the source and drain electrodes in the on-state, The resistance in the direction of the thickness (the thickness direction) decreases. In other words, the field effect mobility and on-current of the thin film transistor increase. do.

[0104] In addition, by reducing the oxygen concentration in the second semiconductor layers 333b to 335b, a microcrystalline semiconductor The carriers at the interface between the amorphous semiconductor region 367 and the amorphous semiconductor region 368 and at the interface between the crystal grains This reduces the binding that inhibits the movement of apoptosis.

[0105] In this case, the first semiconductor layers 333a to 335a refer to regions having approximately the same thickness. In addition, the interfaces between the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b At the flat portion at the interface between the microcrystalline semiconductor region 367 and the amorphous semiconductor region 368, , refers to the region extending from the region closest to the first gate insulating layer 309.

[0106] The total thickness of the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b That is, from the interface of the first gate insulating layer 309 to the protruding portions of the second semiconductor layers 333b to 335b The distance between the tips of the portions is 3 nm to 80 nm, preferably 5 nm to 30 nm. This reduces the off-current of the TFT.

[0107] The impurity semiconductor layers 355 to 362 are made of amorphous silicon doped with phosphorus, The thin film transistor is formed of a p-channel type thin film. When a transistor is formed, the impurity semiconductor layers 355 to 362 are doped with boron. The second insulating layer is formed of microcrystalline silicon, amorphous silicon doped with boron, etc. The semiconductor layers 333b to 336b or the third semiconductor layers 363 to 366 and the wirings 346 to 35 2. When the capacitor wiring 353 is in ohmic contact with the impurity semiconductor layers 355 to 3 62 does not need to be formed.

[0108] The impurity semiconductor layers 355 to 362 are made of microcrystalline silicon doped with phosphorus or boron. When the second semiconductor layers 333b to 336b are made of microcrystalline silicon to which silicon is added, or between the third semiconductor layers 363 to 366 and the impurity semiconductor layers 355 to 362, By forming a semiconductor layer, typically a microcrystalline silicon layer, the characteristics of the interface are improved. As a result, the impurity semiconductor layers 355 to 362 and the second semiconductor layers 333b to 333c are formed. 6b or the third semiconductor layer 363 to 366. As a result, a current flows through the source region, the semiconductor layer, and the drain region of the thin film transistor. By increasing the amount of ZnO, the on-current and the field effect mobility can be increased.

[0109] The wirings 346 to 352 and the capacitance wiring 353 are made of aluminum, copper, titanium, neodymium, or sintered material. Candium, molybdenum, chromium, tantalum, tungsten, etc., as a single layer, Alternatively, the aluminum layer may be formed by doping with an element to prevent hillocks. Alloy (Al-Nd alloy that can be used for gate electrodes 303 to 306 and capacitance wiring 307) The semiconductor device may be formed by using crystalline silicon to which an impurity element serving as a donor is added. The layer in contact with the crystalline silicon to which the donor impurity element is added may be made of titanium. , tantalum, molybdenum, tungsten or nitrides of these elements, It is also possible to form a laminated structure in which aluminum or an aluminum alloy is formed on the aluminum substrate. The upper and lower surfaces of aluminum or aluminum alloy are treated with titanium, tantalum, molybdenum, A laminated structure in which tungsten or a nitride of these elements is sandwiched therebetween may also be used.

[0110] The second gate insulating layer 379 can be formed similarly to the first gate insulating layer 309. .

[0111] The back gate electrodes 373 and 374 and the wiring 375 are connected to the wirings 346 to 352 and the capacitance wiring 353. It can be formed in the same manner as above.

[0112] The insulating layer 381 can be formed using an inorganic insulating layer or an organic resin layer. The layers are silicon oxide, silicon oxynitride, silicon nitride oxide, and DLC (Diamond-Like Carbon). For the organic resin layer, for example, acrylic , epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, etc. Also, siloxane polymers can be used.

[0113] The pixel electrode 383 and the wiring 384 are made of indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide with tin oxide, Indium oxide with titanium oxide, Titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, or silicon oxide The insulating film can be formed using indium tin oxide or the like to which silicon is added.

[0114] The pixel electrode 383 and the wiring 384 are made of a conductive polymer having light-transmitting properties (conductive polymer The wiring 384 and the pixel electrode 385 can be formed using a conductive composition containing a conductive material. The electrode 383 has a sheet resistance of 10000 Ω / □ or less and a wavelength of 550 nm. The light transmittance is preferably 70% or more. It is preferable that the resistivity of the film is 0.1 Ω·cm or less.

[0115] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples of the polymerizable compound include polyaniline, a derivative thereof, and a copolymer of two or more of these.

[0116] In the dual gate type TFT, the gate electrode 303 and the back gate electrode 373 are electrically connected to each other. By changing the phase, it is possible to control the threshold voltage. In this case, either the depletion type TFT or the enhancement type TFT is used as a dual The TFT 300a is a gate type TFT, and the TFT 300b is a depletion type TFT or an enhancement type TFT. The other TFT is the TFT 300b shown in FIG. 7, forming an EDMOS circuit. It can be achieved.

[0117] In addition, in a dual-gate TFT, the channel through which carriers flow is the first gate insulator. Since there are two locations, one near the interface on the edge layer 309 side and the other near the interface on the second gate insulating layer 379 side, This increases the amount of carrier movement, and the on-current of the thin film transistor can be increased. Therefore, the TFT formed in the switch section 393 is provided with a dual TFT capable of increasing the on-current. By forming a gate-type TFT 300c, it is possible to reduce the area of ​​the TFT. This makes it possible to reduce the area of ​​the drive circuit of the display device.

[0118] Next, the logic circuit section 391, the switch section 393, and the pixel section of the display device according to the present embodiment will be described. Cross-sectional views of one embodiment (structure 2) of 395 are shown in FIGS.

[0119] FIG. 10 shows an EDMOS circuit of the logic circuit section 391 of the display device. As a pressure-type TFT 401a, an impurity that gives one conductivity type to the channel forming region is A TFT is formed having a first semiconductor layer to which an element is added. A TFT 401b of the type is formed. Note that, in the cross-sectional view CD of the logic circuit unit 391 shown in FIG. 11A is a cross-sectional view of the logic circuit portion 391 shown in FIG. 11B. Compatible with both CD and CE.

[0120] In the switch portion 393 of the display device shown in FIG. 10, one conductivity type is imparted to the channel forming region. In this case, the first semiconductor layer is doped with an impurity element that acts as a donor. A depletion type TFT 401c having a first semiconductor layer doped with an impurity element is formed. It is done.

[0121] The TFT 401a includes a gate electrode 303 and an impurity source for imparting one conductivity type on a substrate 301. A first semiconductor layer 427a, a second semiconductor layer 427b, and a third semiconductor layer 469, a gate electrode 303 and a first semiconductor doped with an impurity element that gives one conductivity type. The first gate insulating layer 309 is provided between the first and second semiconductor layers 427a and 469. and impurity semiconductor layers 459 and 460 which function as source and drain regions. The semiconductor device further includes wirings 451 and 452 in contact with the semiconductor layers 459 and 460 .

[0122] The TFT 401b includes a gate electrode 304, a first semiconductor layer 454a, a second semiconductor layer 454b, and a third semiconductor layer 454c on a substrate 301. The second semiconductor layer 454b, the third semiconductor layer 470, the gate electrode 304 and the first semiconductor The first gate insulating layer 309 provided between the layer 454a and the third semiconductor layer 470 and impurity semiconductor layers 461 and 462 which function as a source region and a drain region. The wirings 452 and 453 are in contact with the semiconductor layers 461 and 462 .

[0123] As shown in FIG. 11A, the gate electrode 303 of the TFT 401a and the The wiring 452 of the TFT 401a and the TFT 401b are formed on the insulating layer 381 at the same time as the pixel electrode 383. The two terminals are connected by a wiring 384.

[0124] The TFT 401c includes a gate electrode 305 and an impurity source for imparting one conductivity type on a substrate 301. The first semiconductor layer 428a, the second semiconductor layer 428b, and the third semiconductor layer 428a are doped with silicon. 71 and a first gate insulator provided between the gate electrode 305 and the first semiconductor layer 428a. The insulating layer 309 and the third semiconductor layer 471 function as source and drain regions. and a wiring 454 in contact with the impurity semiconductor layers 463 and 464. , 455.

[0125] The TFT 401d includes a gate electrode 306, a first semiconductor layer 455a, a second semiconductor layer 455b, and a third semiconductor layer 455c on a substrate 301. The second semiconductor layer 455b, the third semiconductor layer 472, the gate electrode 306 and the first semiconductor The first gate insulating layer 309 provided between the layer 455a and the third semiconductor layer 472 and impurity semiconductor layers 465 and 466 which function as a source region and a drain region. Wirings 456 and 457 are in contact with the semiconductor layers 463 and 464 .

[0126] The first semiconductor layers 427a and 428a to which an impurity element that imparts one conductivity type is added are In the case of the ferroelectric material, impurity elements acting as donors are added. It is an element belonging to group 15 of the periodic table, and representative elements include phosphorus, arsenic, and antimony. In the present embodiment, the first semiconductor layer 427a to which an impurity element that imparts one conductivity type is added is a donor. A microcrystalline semiconductor layer to which phosphorus, which is an impurity element serving as a valence electrode, is added is formed.

[0127] The first semiconductor layers 454a to 456a are the first semiconductor layers 333a to 333c shown in the above "Structure 1". It can be formed in the same manner as 336a.

[0128] The second semiconductor layers 427b, 428b, 454b to 456b are the second semiconductor layers shown in the above "Structure 1". It can be formed in the same manner as the semiconductor layers 333b to 336b.

[0129] The third semiconductor layers 469 to 473 are the third semiconductor layers 363 to 366 shown in the above "Structure 1". It can be formed in the same manner as above.

[0130] In this case, the second semiconductor layers 427b, 428b, A third semiconductor layer 469 is provided between the impurity semiconductor layers 454b to 456b and the impurity semiconductor layers 459 to 467. 9B, the third semiconductor layer 469 It is not necessary to set ~473.

[0131] The impurity semiconductor layers 459 to 467 are the same as the impurity semiconductor layers 355 to 362 shown in the above "Structure 1". It can be formed in the same manner as above.

[0132] The wirings 451 to 458 are formed in the same manner as the wirings 346 to 353 shown in the above "Structure 1". can be done.

[0133] In FIG. 10, the depletion type TFT 401a of the EDMOS circuit is A first semiconductor layer is formed in which an impurity element that imparts one conductivity type is added to a channel formation region. The channel forming region of the depletion type TFT 401a is The first semiconductor layer 454a of the TFT 401b is formed in the same manner as the first semiconductor layer 454a of the TFT 401b. An impurity element that imparts one conductivity type, typically an acceptor, is added to the channel formation region of 401b. The first semiconductor layer may be doped with an impurity element that serves as an acceptor. The impurity elements are elements belonging to group 13 of the periodic table, and a representative example is boron. .

[0134] Here, in the logic circuit section 391, a depletion type TFT or an enhancement type TFT is used. An impurity element that gives one conductivity type is added to one channel formation region of a TFT. The semiconductor layer can be used to form an EDMOS circuit.

[0135] In addition, in the case of a depletion-type TFT, the threshold voltage is shifted to the negative side, so that the on-state Since it is possible to increase the current in the switching state, the TF formed in the switch unit 393 By forming a depletion-type TFT on T, which can increase the on-current, It is possible to reduce the area of ​​T, and the area of ​​the drive circuit of the display device can be reduced. Cut.

[0136] Next, the logic circuit section 391, the switch section 393, and the pixel A cross-sectional view of one embodiment (structure 3) of portion 395 is shown in FIG. 12 and FIG.

[0137] FIG. 12 shows an EDMOS circuit of the logic circuit section 391 of the display device. As the pressure-type TFT 401a, the channel forming region shown in the above "Configuration 2" is The TFT 401a has a first semiconductor layer to which an impurity element that imparts one conductivity type is added. In addition, as the enhancement type TFT 401b, the TFT shown in the above "Configuration 2" is formed. In addition, the cross-sectional view CD of the logic circuit unit 391 shown in FIG. 13(A) is a cross-sectional view CE of the logic circuit portion 391 shown in FIG. 13(B) Compatible with both CD and CE.

[0138] In the switch section 393 of the display device shown in FIG. A dual-gate TFT 403c having an electrode 482 is formed.

[0139] The switching element in the pixel of the pixel section 395 of the display device shown in FIG. d. Also, a pixel electrode 481 connected to the wiring of the TFT 401d and a wiring 458 The second gate insulating layer 379 and the first gate insulating layer 379 form a capacitor 403e.

[0140] The TFT 401a shown in FIG. 12 has a structure similar to that shown in FIG. As shown in the figure, the gate electrode 303 and the wiring 4 connecting the TFT 401a and the TFT 401b are 52 and a wiring 483 formed simultaneously with the pixel electrode 481 on the second gate insulating layer 379. The difference is that they are connected in

[0141] The TFT 403c includes a gate electrode 305 and an impurity source for imparting one conductivity type on a substrate 301. A first semiconductor layer 428a, a second semiconductor layer 428b, and a third semiconductor layer 471, and a first gate electrode provided between the gate electrode 305 and the first semiconductor layer 428a. The insulating layer 309 and the third semiconductor layer 471 function as a source region and a drain region. and a wiring 45 in contact with the impurity semiconductor layers 463 and 464. 4, 455. Also, the gate electrode 305 and A back gate electrode 482 is provided in the opposing region. It can be formed at the same time as the pole 481 .

[0142] In place of the TFT 403c, the dual-gate TFT 30 shown in the above "Structure 1" is used. 0c may be formed.

[0143] The pixel electrode 481 connected to the TFT 401d is formed on the second gate insulating layer 379. .

[0144] The capacitor 403e is formed by connecting the wiring 458, the second gate insulating layer 379, and the pixel electrode 48. It is formed by 1.

[0145] The display device shown in FIG. 12 includes a pixel electrode 481, a back gate electrode 482, a gate electrode Since it is possible to form a wiring 483 that connects the electrode 303 and the wiring 452, The number of masks can be reduced.

[0146] Next, a cross-sectional view of one form of an EDMOS circuit applicable to the above-mentioned "Structure 1" to "Structure 3" (structure Structure 4) is shown in Figure 14.

[0147] FIG. 14A shows an EDMOS circuit in a logic circuit section 391 of a display device. As the depletion type TFT 480a, the above-mentioned "Structure 2" and "Structure 3" are shown. A first semiconductor layer in which an impurity element that imparts one conductivity type is added to a channel forming region. In addition, as an enhancement type TFT 480b, a TFT having the structure The TFT 300b shown in "Structure 1" is formed in the same structure as the TFT 300b shown in FIG. A cross-sectional view CD of the circuit portion 391 corresponds to a top view CD of FIG.

[0148] The EDMOS circuit shown in FIG. 14 includes a gate electrode 486 of a depletion-type TFT 480a. However, depletion type TFT480a and enhancement type TFT480b are connected. The wiring 485 is directly connected to the first gate insulating layer 309 through an opening formed in the first gate insulating layer 309. do.

[0149] Therefore, the gate electrode 486 and the wiring 485 are directly connected to each other, and therefore, as shown in FIG. In comparison with the EDMOS circuit shown in FIG. 1, the contact resistance between the gate electrode 486 and the wiring 485 is reduced. It is possible.

[0150] In addition, the field effect mobility of the TFT is 5 cm 2 / V sec, typically 0 .5~3cm 2 In the case of / V·sec, as shown in "Structure 1" to "Structure 3", A depression type TFT and an enhancement type TFT are connected, and a depression type The wiring that connects to the gate electrode of the TFT is formed at the same time as the back gate electrode or pixel electrode. By using this method, it is possible to reduce the number of masks. 5cm 2 / V·sec or more, as shown in Figure 14, a depletion-type TFT The wiring for connecting the enhancement type TFT is formed on the first gate insulating layer 309. By directly connecting the gate electrode of the depression type TFT to the opening, Since the increase in contact resistance can be reduced, high-speed operation of TFTs can be maintained.

[0151] The TFTs shown in the EDMOS circuits of "Structure 1" to "Structure 4" are also used as inverters, switches, etc. The present invention can also be applied to soft resistors, buffer circuits, protection circuits, diodes, etc.

[0152] In the TFTs shown in "Structure 1" to "Structure 4," the first gate insulating layer and the impurity A structure in which only the first semiconductor layer and the third semiconductor layer are laminated between the semiconductor layers may be used. .

[0153] In the display device described above, the TFTs formed in the driver circuit and pixel portion have an inverse staggered structure. The polarity of each TFT is either n-channel or p-channel. Furthermore, since part of the driving circuit is formed on the substrate, It is possible to reduce the cost of the device. In addition, it is possible to reduce the number of diodes required for TFTs that require a large amount of current. By providing an Al-gate type TFT or a depletion type TFT, the area of ​​the TFT can be increased. Since the size can be reduced, the frame of the display device can be narrowed, and the display area can be expanded. In addition, in the pixel area, TFTs with high on-state current and low off-state current are used for each pixel. Because it is used as a switching element, it will result in a display device with high contrast and good image quality. .

[0154] (Embodiment 4) Here, a manufacturing method of the display device shown in FIG. 7 will be described with reference to FIGS. In this embodiment mode, a manufacturing method (Method 1) of an n-type thin film transistor will be described.

[0155] As shown in FIG. 15A, gate electrodes 303 to 306 and a capacitance wiring 307 are provided on a substrate 301. Next, a first gate insulating film is formed to cover the gate electrodes 303 to 306 and the capacitance wiring 307. An edge layer 309 and a first semiconductor layer 311 are formed.

[0156] As the substrate 301, the substrate 301 described in Embodiment 3 can be used as appropriate.

[0157] The gate electrodes 303 to 306 and the capacitance wiring 307 are the same as those of the gate electrodes 303 to 306 shown in the third embodiment. The gate electrodes 303 to 306 and the capacitance wiring 307 are formed using the materials shown in the drawings. The capacitance wiring 307 is formed on the substrate 301 by sputtering or vacuum deposition. A conductive layer is formed from the material, and a photolithography method or an inkjet method is applied to the conductive layer. The conductive layer can be formed by forming a mask by a method such as a mask forming method, and etching the conductive layer using the mask. In addition, conductive nanopastes such as silver, gold, or copper can be applied to a substrate by the inkjet method. The gate electrodes 303 to 306 and the capacitors 303 to 306 may be formed by discharging the gate electrodes 303 to 306 and baking them. In order to improve the adhesion between the wiring 307 and the substrate 301, a nitride layer of the above metal material is formed on the substrate 301. 01 and the gate electrodes 303 to 306 and the capacitance wiring 307. A conductive layer is formed on a substrate 301, and etching is performed using a resist mask formed using a photomask. Switch.

[0158] The side surfaces of the gate electrodes 303 to 306 and the capacitance wiring 307 may be tapered. In a later step, an insulating layer, a semiconductor layer, and a wiring layer are formed on the gate electrode 303. Therefore, the gate electrodes 303 to 305 are not cut at the step portions. In order to form the side of the capacitance wiring 307 into a tapered shape, the resist mask is recessed. Etching can be performed while maintaining the same.

[0159] In addition, the gate wiring (scanning line) and the capacitance wiring are formed by the process of forming the gate electrodes 303 to 306. The scanning line is a wiring for selecting pixels, and the capacitance line is a wiring for selecting pixels. The line refers to a wiring connected to one electrode of a storage capacitor of a pixel. However, it is not limited to this. In addition to the gate wiring and / or the capacitance wiring, the gate electrodes 303 to 306 are provided This is also fine.

[0160] The first gate insulating layer 309 is formed using the material for the first gate insulating layer 309 shown in the third embodiment. The first gate insulating layer 309 can be formed by a CVD method or a sputtering method. The first gate insulating layer 309 can be formed by a high frequency Alternatively, the film may be formed using a microwave plasma CVD apparatus having a frequency of 1 GHz or higher. When the first gate insulating layer 309 is formed using a microwave plasma CVD apparatus, a gate electrode and The breakdown voltage between the drain electrode and the source electrode can be improved, resulting in high reliability. A thin film transistor can be obtained. In addition, the first gate insulating layer 309 is made of an organic silicon. The first gate insulating layer is formed by forming a silicon oxide layer by CVD using lanthanum gas. It is possible to reduce the hydrogen content in the thin film transistor, thereby reducing the variation in the threshold voltage of the thin film transistor. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(O C2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethyl Trimethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OM CTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2 H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. A containing compound can be used.

[0161] The first semiconductor layer 311 may be made of microcrystalline silicon, microcrystalline silicon germanium, or microcrystalline silicon. The first semiconductor layer 311 is formed using germanium or the like. It is preferable that the thickness of the film is 3 nm or more and 10 nm or less.

[0162] The first semiconductor layer 311 is formed by depositing silicon or gel in a reaction chamber of a plasma CVD apparatus. The deposition gas containing manganese is mixed with hydrogen and formed by glow discharge plasma. Alternatively, a deposition gas containing silicon or germanium, hydrogen, helium, neon, It is formed by mixing with rare gases such as krypton and using glow discharge plasma. The flow rate of hydrogen is preferably 10 to 2000 times that of the deposition gas containing germanium. It is usually diluted 10 to 200 times to produce microcrystalline silicon, microcrystalline silicon germanium, and microcrystalline Form germanium, etc.

[0163] Representative examples of deposition gases containing silicon or germanium include SiH4, Si2H6 , GeH4, Ge2H6, etc.

[0164] Before forming the first semiconductor layer 311, the inside of the processing chamber of the CVD apparatus is evacuated while the CVD apparatus is being cooled. A deposition gas containing silicon or germanium is introduced to remove impurity elements in the processing chamber. By this, the first gate insulating layer 309 and the first semiconductor layer of the thin film transistor to be formed later are formed. It is possible to reduce impurity elements at the interface of the semiconductor layer, and improve the electrical characteristics of the thin film transistor. It is possible to improve the performance.

[0165] Next, as shown in FIG. 15(B), a second semiconductor layer 313 and a Then, a third semiconductor layer 315 is formed. Here, a partially crystalline semiconductor layer is formed from the first semiconductor layer 311. The second semiconductor layer 313 and the third semiconductor layer 315 are formed under the conditions for growth. In a reaction chamber of the Zuma CVD apparatus, a deposition gas containing silicon or germanium; The first semiconductor layer 311 is mixed with hydrogen and formed by glow discharge plasma. The flow rate of hydrogen to the deposition gas containing silicon or germanium is set higher than that of the deposition condition of In other words, the second semiconductor layer 313 is formed under conditions that reduce crystal growth. As the film is deposited, the crystal growth of the first semiconductor layer is inhibited, and a third semiconductor layer that does not include microcrystalline semiconductor regions is formed. A layer 315 can be formed.

[0166] Alternatively, a deposit containing silicon or germanium is formed in a reaction chamber of a plasma CVD apparatus. A second semiconductor is formed by mixing a volatile gas, hydrogen, and a gas containing nitrogen and using glow discharge plasma. Then, the first semiconductor layer 311 is formed on the first insulating layer 312 and the third semiconductor layer 315 is formed on the second insulating layer 313. The flow rate of hydrogen was reduced for deposition gases containing silicon or germanium compared to the film conditions. At the same time, by mixing a gas containing nitrogen, crystal growth in the second semiconductor layer 313 is promoted. The third semiconductor layer 315 can be formed so as to be suppressed and not include a microcrystalline semiconductor region.

[0167] In this embodiment, in the initial stage of deposition of the second semiconductor layer 313, the first semiconductor layer The film is deposited on the entire surface using 311 as a seed crystal. After this, the crystal growth is partially suppressed. Then, a pyramidal microcrystalline semiconductor region grows (middle stage of deposition). The crystal growth of the third semiconductor layer 315 (later deposition stage) is suppressed and does not include a microcrystalline semiconductor region. Therefore, the first semiconductor layer shown in the third embodiment is This corresponds to a film formed in the initial stage of deposition of the first semiconductor layer 311 and the second semiconductor layer 313. In addition, the second semiconductor layer shown in the third embodiment is the same as the second semiconductor layer 31 shown in the third embodiment. These correspond to the pyramidal microcrystalline semiconductor region and amorphous semiconductor region formed in the middle of the deposition of 3. In addition, the third semiconductor layer shown in the third embodiment is a second semiconductor layer formed in the later stage of deposition shown in the present embodiment. This corresponds to the semiconductor layer 315 in FIG.

[0168] Next, as shown in FIG. 15(C), an impurity layer that imparts one conductivity type is formed on the third semiconductor layer 315. A semiconductor layer to which an impurity is added (hereinafter, referred to as an impurity semiconductor layer 317) is formed. A conductive layer 319 is formed on the conductive layer 317 .

[0169] The impurity semiconductor layer 317 is formed by ionizing silicon or gel in a reaction chamber of a plasma CVD apparatus. A deposition gas containing chromium, hydrogen, and phosphine (diluted with hydrogen or silane) Mix and form by glow discharge plasma. Deposition properties including silicon or germanium The gas is diluted with hydrogen to produce amorphous silicon doped with phosphorus, fine silicon doped with phosphorus, crystalline silicon, amorphous silicon germanium doped with phosphorus, microcrystalline silicon doped with phosphorus Crystalline silicon germanium, phosphorus-doped amorphous germanium, phosphorus-doped The resulting mixture is then processed to form microcrystalline germanium.

[0170] The conductive layer 319 is made of the same material and thickness as the wirings 346 to 352 and the capacitor wiring 353 shown in the third embodiment. The conductive layer 319 can be formed by a CVD method, a sputtering method, or the like. The conductive layer 319 is formed by using a vacuum deposition method. The paste is then discharged using a screen printing method or an inkjet method, and then baked. It may be formed by

[0171] Next, as shown in FIG. 16A, second resist masks 321 to 32 are formed on the conductive layer 319. Form 4.

[0172] The resist masks 321 to 323 have regions with different thicknesses. The mask can be formed by using a multi-tone mask. This is preferable because the number of photomasks required is reduced, and the number of manufacturing steps is also reduced. The method includes the steps of forming a pattern of a semiconductor layer and isolating a source region and a drain region. In this step, a multi-tone mask can be used.

[0173] A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity. Representative examples include: Exposure is performed with three levels of light intensity: exposed area, half-exposed area, and unexposed area. A multi-tone mask is used. By this, it is possible to produce a film having multiple (typically two) thicknesses by a single exposure and development process. A resist mask can be formed. Therefore, by using a multi-tone mask, This allows the number of masks to be reduced.

[0174] 19(A-1) and 19(B-1) show cross-sectional views of a typical multi-tone mask. FIG. 19(A-1) shows a graytone mask 490, and FIG. 19(B-1) shows a halftone Mask 495 is shown.

[0175] The gray-tone mask 490 shown in FIG. 19(A-1) is a light-transmitting substrate 491 having a shielding layer. A light-shielding portion 492 formed by a light-shielding film, and a diffraction grating portion provided by a pattern of the light-shielding film. It consists of 493.

[0176] The diffraction grating section 493 is a structure including slits and dots spaced at intervals equal to or less than the resolution limit of the light used for exposure. The light transmittance is controlled by having a grating or mesh. The slits, dots or meshes provided in the It may be something like that.

[0177] The light-transmitting substrate 491 can be made of quartz or the like. The light-shielding film constituting the grating portion 493 may be formed of a metal, and is preferably made of chromium or Alternatively, the insulating layer may be made of chromium oxide or the like.

[0178] When the gray-tone mask 490 is irradiated with light for exposure, the pattern shown in FIG. In this way, the light transmittance in the area overlapping the light shielding portion 492 is 0%, and The light transmittance in the area where the diffraction grating portion 493 is not provided is 100%. The light transmittance of the grating portion 493 is in the range of about 10 to 70%, and the slits of the diffraction grating, This can be adjusted by adjusting the spacing of the dots or meshes.

[0179] The halftone mask 495 shown in FIG. 19(B-1) is a semi-transparent mask formed on a light-transmitting substrate 496. The semi-transparent portion 497 is formed of a transparent film, and the light-shielding portion 498 is formed of a light-shielding film. It has been made.

[0180] The semi-transparent portion 497 is a film of MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. The light-shielding portion 498 can be formed using a material similar to the light-shielding film of a gray-tone mask. It may be formed using a metal, and is preferably provided using chromium or chromium oxide.

[0181] When the halftone mask 495 is irradiated with light for exposure, the pattern shown in FIG. In this way, the light transmittance in the area overlapping the light shielding portion 498 is 0%, and the light transmittance in the area overlapping the light shielding portion 498 or The light transmittance in the area where the semi-transparent portion 497 is not provided is 100%. The light transmittance of the portion 497 is generally in the range of 10 to 70%, and depends on the type of material used to form the portion 497 or the This can be adjusted according to the thickness of the film to be formed.

[0182] By using a multi-tone mask for exposure and development, a resist mask with regions of different thicknesses can be created. A sc can be formed.

[0183] Next, the first semiconductor layer 311 and the second semiconductor layer 322 are formed by using the resist masks 321 to 324. 313, the third semiconductor layer 315, the impurity semiconductor layer 317, and the conductive layer 319 are etched. By this process, the first semiconductor layer 311, the second semiconductor layer 313, and the third semiconductor layer 315, the impurity semiconductor layer 317 and the conductive layer 319 are separated for each element, and the first semiconductor layer 33 3a to 336a, second semiconductor layers 333b to 336b, and third semiconductor layers 333c to 336 c, the impurity semiconductor layers 329 to 332 and the conductive layers 325 to 328 are formed (FIG. 16(B) ) for more information.

[0184] Next, the resist masks 321 to 324 are recessed to form the separated resist masks 337 to A resist mask 344 and a recessed resist mask 345 are formed. The recession of the resist mask is performed by using oxygen. In this case, the laser is formed on the gate electrode so as to separate the gate electrodes. By ashing the resist masks 321 to 323, the resist masks 337 to 344 are formed. It is possible to form (see FIG. 16(C)).

[0185] Next, the conductive layers 325 to 328 are etched using the resist masks 337 to 345. The lines 346 to 352 and the capacitance wiring 353 are formed (see FIG. 17(A)). The etching of 328 is preferably performed by wet etching. As a result, the conductive layers 325 to 328 are isotropically etched. The wiring 352 and the capacitance wiring 353 are recessed inward from the resist masks 337 to 345. 46 to 352 function not only as source electrodes and drain electrodes but also as signal lines. However, the present invention is not limited to this, and the signal line, the source electrode, and the drain electrode may be provided separately.

[0186] Next, the third semiconductor layers 333c to 336c and the non- A part of each of the pure semiconductor layers 329 to 332 is etched. Here, dry etching is used. Through this process, the third semiconductor layers 363 to 366 functioning as buffer layers are formed. Then, the impurity semiconductor layers 355 to 362 are formed. After that, the resist masks 337 to 345 (See FIG. 17A). Note that the cross-sectional view of the pixel portion 395 in FIG. 17A is the same as that in FIG. 1 corresponds to a cross-sectional view taken along line AB in the plan view of the pixel portion shown in FIG.

[0187] In this embodiment, after the conductive layers 325 to 328 are wet-etched, the resist mask 3 is removed. 37 to 345 are left, and the third semiconductor layers 333c to 336c and the impurity semiconductor layer 329 are Since a part of each of the conductive layers 325 to 332 is dry etched, 28 is isotropically etched, and the side surfaces of the wirings 346 to 352 and the capacitance wiring 353 and the impurity The side surfaces of the semiconductor layers 355 to 362 do not coincide with each other, and the side surfaces of the wirings 346 to 352 and the capacitance wiring 353 The side surfaces of the impurity semiconductor layers 355 to 362 are formed on the outer sides of the insulating layer 351 .

[0188] Next, after removing the resist masks 337 to 345, dry etching may be performed. The dry etching conditions are such that the exposed third semiconductor layers 363 to 366 are not damaged. and the etching rate for the third semiconductor layers 363 to 366 is low. In other words, the exposed surfaces of the third semiconductor layers 363 to 366 are hardly damaged. The thickness of the exposed third semiconductor layers 363 to 366 is hardly reduced. The etching gas used is Cl2, CF4, or N2. The method of etching is not particularly limited, and may be an inductively coupled plasma (ICP) type. ly Coupled Plasma) method, capacitively coupled plasma (CCP: Capac itively coupled plasma, electron cyclotron resonance plasma (ECR:Electron Cyclotron Resonance) method, reactivity Using the reactive ion etching (RIE) method, etc. It is possible.

[0189] Next, water plasma, ammonia plasma, nitrogen plasma, etc. are applied to the surfaces of the third semiconductor layers 363 to 366. Plasma or the like may be irradiated.

[0190] Water plasma treatment is a process in which gas containing water as the main component, such as water vapor (H2O vapor), is injected into the reaction space. This can be done by introducing gas and generating plasma.

[0191] As described above, after the impurity semiconductor layers 355 to 362 are formed, the third semiconductor layer 363 Further dry etching is performed under conditions that do not damage the 366, and the third semiconductor It is possible to remove impurities such as residues present on the substrate layers 363 to 366. By performing water plasma treatment following the etching, the resist mask residue can be removed. Water plasma treatment ensures insulation between the source and drain regions. This reduces the off-state current of the completed thin film transistor and improves the electrical characteristics. It is possible to reduce the variation in the

[0192] Through the above steps, a thin film transistor can be manufactured.

[0193] Next, a second gate insulating layer 371 is formed on the first gate insulating layer 309. The logic circuit section 391 has a dual-gate type TFT 300a, the switch section 393 has a dual-gate type TFT 300b, and the In the region where the capacitor element of the pixel section 395 and the TFT 300c of the buffer gate type are formed, Then, gate electrodes 373 and 374 and a capacitance wiring 375 are formed (see FIG. 17(B)).

[0194] The second gate insulating layer 371 can be formed in the same manner as the first gate insulating layer 309. .

[0195] The back gate electrodes 373 to 374 and the capacitance wiring 375 are connected to the wirings 346 to 352 and the capacitance wiring 3 The materials and manufacturing method shown in 53 can be used appropriately.

[0196] Next, as shown in FIG. 18A, an insulating layer 372 is formed. The insulating layer 381 shown in embodiment 3 can be used as appropriate.

[0197] Next, the insulating layer 372 and the second gate insulating layer 371 are partially etched to form a logic circuit section. A wiring 347 connecting the dual gate type TFT 300a and the TFT 300b of 391; An opening is formed to expose the gate electrode 303 and the wiring 352 of the pixel portion 395. The opening can be formed by photolithography. The dual-gate TFT 300a and the TFT 300b, a wiring 347 connecting the gate electrode 303, and a wiring 384 connecting the pixel portion 3 A pixel electrode 383 is formed to be connected to the wiring 352 of the wiring 347 and the gate electrode 30 For the connection of the pixel portion 39 in FIG. 18(A), see FIG. 18(B). The cross-sectional view of No. 5 corresponds to the cross-sectional view taken along line AB in the plan view of the pixel portion shown in FIG. 20(B).

[0198] The wiring 384 and the pixel electrode 383 are formed by a sputtering method using the material shown in Embodiment 3. After forming the thin film using the above method, a resist mask formed by a photolithography process was used to The thin film can be formed by etching the thin film with a light-transmitting conductive polymer. The conductive composition containing the above-mentioned is applied or printed, and then baked to form the conductive film. The cross-sectional view of the pixel section 395 in FIG. 17(A) is taken along line A-A in the plan view of the pixel section shown in FIG. This corresponds to the cross-sectional view of B.

[0199] The wiring 384 connects the dual-gate TFT 300a and the TFT 300b of the logic circuit unit 391 to each other. b is connected to the gate electrode 303, An EDMOS circuit can be formed using FT300b.

[0200] By the above steps, a display device as shown in FIG. 8 can be manufactured.

[0201] Next, a manufacturing method (Method 2) of the display device shown in FIG. 10 will be described with reference to FIGS. show.

[0202] As shown in FIG. 21A, gate electrodes 303 to 306 and a capacitance wiring 307 are provided on a substrate 301. Next, a first gate insulating film is formed to cover the gate electrodes 303 to 306 and the capacitance wiring 307. The first semiconductor layer 411 is formed by doping the edge layer 309 with an impurity element that gives one conductivity type. do.

[0203] As the substrate 301, the substrate 301 described in Embodiment 3 can be used as appropriate.

[0204] The gate electrodes 303 to 306, the capacitance wiring 307 and the first gate insulating layer 309 are formed in the above-mentioned "method It can be formed in the same manner as in "Method 1".

[0205] The first semiconductor layer 411 to which an impurity element that imparts one conductivity type is added is the first semiconductor layer 3. 11 is formed by adding an impurity element to be a donor or an impurity element to be an acceptor. The donor impurity elements are elements in group 15 of the periodic table, and representative examples include: Phosphorus, arsenic, antimony, etc. Also, the impurity elements that act as acceptors are It is an element that belongs to group 13 in the table, and a representative example is boron. The first semiconductor layer 411 to which the impurity element acting as a donor is added is A method for manufacturing a microcrystalline semiconductor layer to which phosphorus is added will be described.

[0206] The source gas for the first semiconductor layer 411 to which an impurity element that imparts one conductivity type is added is A semiconductor layer is formed by mixing a gas containing an impurity element that imparts a plasma. In the reaction chamber of the CVD apparatus, a deposition gas containing silicon or germanium and water are mixed. It is formed by mixing silicon and phosphine and using glow discharge plasma. or a deposition gas containing germanium, hydrogen, phosphine, helium, neon, It is mixed with rare gases such as krypton and formed by glow discharge plasma. The first semiconductor layer 411 to which the impurity element is added is microcrystalline silicon containing phosphorus. Microcrystalline silicon germanium containing phosphorus, microcrystalline germanium containing phosphorus, etc. are formed.

[0207] Alternatively, a gas containing an impurity element that imparts one conductivity type to the surface of the first gate insulating layer 309 is After the exposure, a microcrystalline semiconductor layer is formed, and an impurity element that imparts one conductivity type is incorporated. Typically, the surface of the first gate insulating layer 309 is By exposing the first gate insulating layer 309 to phosphine, phosphorus is adsorbed on the surface of the first gate insulating layer 309. After that, a microcrystalline semiconductor layer is formed by the same method as that for the first semiconductor layer 311 shown in the above "Method 1". By forming the above, it is possible to obtain microcrystalline silicon containing phosphorus, microcrystalline silicon germanium containing phosphorus, It is possible to form microcrystalline germanium containing phosphorus, etc.

[0208] Alternatively, a microcrystalline semiconductor layer is formed over the first gate insulating layer 309, and then a gate insulating layer having one conductivity type is formed. Plasma is generated in a gas atmosphere containing an impurity element to give one conductivity type to the microcrystalline semiconductor layer. By exposing the semiconductor to plasma containing an impurity element that gives one conductivity type, the impurity element that gives one conductivity type is added. The first semiconductor layer 411 can be formed by the method shown in the above "Method 1". After forming a microcrystalline semiconductor layer by a method similar to that for forming the first semiconductor layer 311, phosphorus plasma is applied. By exposing the microcrystalline semiconductor layer, the microcrystalline silicon containing phosphorus and the microcrystalline silicon gate containing phosphorus are formed. It is possible to form microcrystalline germanium containing ruthenium or phosphorus.

[0209] Next, a second semiconductor layer 413, a third semiconductor layer 415, and After the impurity semiconductor layer 417 is formed, a resist mask 419 is formed on the impurity semiconductor layer 417. 420 is formed (see FIG. 21(B)).

[0210] Here, the second semiconductor layer 313, the third semiconductor layer 315, and the impurity The second semiconductor layer 413 and the third semiconductor layer 415 are formed in the same manner as the semiconductor layer 317. An impurity semiconductor layer 417 is formed.

[0211] The impurity semiconductor layer 417 is a fourth semiconductor layer 431, a fifth semiconductor layer 433, and a fourth semiconductor layer 434. The thickness of the semiconductor layer 435 and the impurity semiconductor layer 437 is reduced by the etching process of the sixth embodiment. Therefore, it is preferable to make the film thicker, typically about 30 to 150 nm. .

[0212] The resist masks 419 and 420 are used to form the TFT 401a and the switch 402 of the logic circuit section 391. The pixel electrode 393 is formed in a region that will become the TFT 401c of the portion 393.

[0213] Next, the first semiconductor layer 411 and the second semiconductor layer 420 are formed using resist masks 419 and 420. The semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor layer 417 are etched. As a result, the first semiconductor layer 411, the second semiconductor layer 413, the third semiconductor layer 415, and the non- The pure semiconductor layer 417 is separated into elements, and the first semiconductor layers 427a, 428a, and the second semiconductor layers 427b, 428c are separated into elements. the third semiconductor layers 425 and 426, and the impurity semiconductor layer 423; After that, the resist masks 419 and 420 are removed (see FIG. 21(C)). reference).

[0214] Next, as shown in FIG. 22(A), the fourth semiconductor layer 431, the fifth semiconductor layer 433, and the sixth semiconductor layer 434 are The impurity semiconductor layer 435 and the impurity semiconductor layer 437 are formed. Then, the stop masks 439 and 440 are formed.

[0215] A fourth semiconductor layer 431, a fifth semiconductor layer 433, a sixth semiconductor layer 435, and an impurity semiconductor The semiconductor layer 437 is the first semiconductor layer 311 and the second semiconductor layer 436 shown in the above "Method 1". The third semiconductor layer 313, the third semiconductor layer 315, and the impurity semiconductor layer 317 can be formed in the same manner. do.

[0216] The resist masks 439 and 440 are formed on the TFT 401b of the logic circuit section 391 and the pixel section 3 The TFT 401d is formed in an area corresponding to the TFT 401d of No. 95.

[0217] Next, the fourth semiconductor layer 431 and the fifth semiconductor layer 440 are formed using resist masks 439 and 440. The semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are etched. As a result, the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the non- The pure semiconductor layer 437 is separated into elements, and the fourth semiconductor layers 454a to 456a and the fifth semiconductor layers The semiconductor layers 454b to 456b, the sixth semiconductor layers 454c to 456c, and the impurity semiconductor layer 44 4, 446, and 447 are formed. Note that in this etching, the impurity semiconductor layer 423 , 424 are also etched, so that impurity semiconductor layers 443, 445 with reduced thickness are formed. This is a fourth semiconductor layer 431, a fifth semiconductor layer 433, a sixth semiconductor layer 43 5, and the impurity semiconductor layer 437 is sufficiently etched so that no etching residue is left. Therefore, even after the etching of the fourth semiconductor layer 431 is completed, over-etching occurs. As a result, the impurity semiconductor layers 423 and 424 are also etched in the overetching. (See FIG. 22(B). After that, the resist masks 439 and 440 are removed.

[0218] Next, as shown in FIG. 22(C), a conductive layer 319 is formed.

[0219] Next, a resist mask is formed over the conductive layer 319. Next, the above As in "Method 1," the conductive layer 319 is etched to form the wirings 451-458.

[0220] Next, using the resist mask, the third semiconductor layers 469 to In step 473, each of the impurity semiconductor layers 443 to 447 is partially etched. , the third semiconductor layers 469 to 473 functioning as buffer layers, and the impurity semiconductor layers 459 to 4 67 is formed. After that, the resist mask is removed.

[0221] After removing the resist mask, dry etching may be performed. The surface of No. 69 to No. 473 may be irradiated with water plasma, ammonia plasma, nitrogen plasma, etc. stomach.

[0222] Next, in the same manner as in the above-mentioned "Method 1," a second gate insulating layer 371 and an insulating layer 372 are formed. (See Figure 23(A)).

[0223] Through the above steps, a thin film transistor can be manufactured.

[0224] Next, the second gate insulating layer 371 and the insulating layer 372 are partially etched to form the logic circuit section 3 The wiring 452 and the gate electrode 303 of the TFT 401a of 91, and the wiring 457 of the pixel portion 395 An opening is formed to expose the insulating film. The opening may be formed by a photolithography method. After that, a logic circuit section is formed on the insulating layer 372 so as to be connected through the opening. A wiring 384 connecting the wiring 452 and the gate electrode 303 of the TFT 401a of 391, A pixel electrode 383 is formed to be connected to the wiring 457 of the portion 395 (the wiring 384 and the gate electrode For the connection of 303, see Figure 11(A). See Figure 23(B).

[0225] The wiring 384 connects the wiring 452 and the gate electrode 303 of the TFT 401a in the logic circuit section 391. By connecting them together, an EDMOS circuit consisting of TFT401a and TFT401b is formed. It is possible.

[0226] (Embodiment 5) In this embodiment, a protection circuit provided in a display device according to one embodiment of the present invention will be described with reference to drawings. The protection circuits 134 to 136 in the first embodiment shown in FIG. A specific example of the circuit configuration of the protection circuit will be described with reference to FIG. Although only the case where a type transistor is provided will be described, the present invention is not limited to this.

[0227] The protection circuit shown in FIG. 24A includes a protection diode 501 using a plurality of thin film transistors. The protection diode 501 has n-type thin film transistors 5 The n-type thin film transistor 501a and the n-type thin film transistor 501b are The source electrode and the drain electrode of the n-type thin film transistor 501a and the n-type thin film transistor It is connected to the gate electrode of the transistor 501b and has a potential V ss The n-type thin film is kept at The other of the source electrode and drain electrode of the transistor 501a is connected to an n-type thin film transistor 5 The n-type thin film transistor 5 is connected to one of the source electrode and drain electrode of the n-type thin film transistor 5. The other of the source electrode and drain electrode of 01b is connected to a protection diode 502. Similarly to the protective diode 501, the other protective diodes 502 to 504 are also A semiconductor device having a plurality of thin film transistors connected in series, and a semiconductor device having a plurality of thin film transistors connected in series One end of the transistor is connected to the gate electrodes of the plurality of thin film transistors.

[0228] In the present invention, the thin film transistors of the protection diodes 501 to 504 are The number and polarity of the diodes are not limited to the configuration shown in FIG. 501 may be composed of three thin film transistors connected in series.

[0229] The protection diodes 501 to 504 are connected in series in order. The connection between the protection diode 502 and the protection diode 503 is made with a wiring 505. The wiring 50 is electrically connected to the semiconductor element to be protected. The wiring connecting to 5 is limited to the wiring between the protection diode 502 and the protection diode 503. That is, the wiring 505 is not connected between the protection diode 501 and the protection diode 502. Alternatively, the protection diode 502 may be connected between the protection diode 503 and the protection diode 504. It may be possible.

[0230] One end of the protection diode 504 is connected to the power supply potential V dd In addition, the protection diode 5 Each of 01 to 504 is connected so that a reverse bias voltage is applied thereto.

[0231] The protection circuit shown in FIG. 24(A) includes a protection diode 50 as shown in FIG. 24(B). 1, 502 are replaced with a protection diode 506, and the protection diodes 503, 504 are replaced with protection diodes It is also possible to replace it with Ord 507.

[0232] The protection circuit shown in FIG. 24C includes a protection diode 510, a protection diode 511, a capacitance element The resistor element 514 is a two-terminal resistor. One end of the wire 515 is connected to a potential V in is supplied to the other end, and the potential V ss Supplied by The resistor element 514 is connected to the potential V in When the supply of power is stopped, the potential of the wiring 515 is V ss The resistance value is sufficiently larger than the wiring resistance of the wiring 515. The protection diode 510 and the protection diode 511 are diodes The device uses a gate-connected n-type thin-film transistor.

[0233] The protection diode shown in FIG. 24(C) further comprises a plurality of thin film transistors connected in series. It may also be something that has been

[0234] The protection circuit shown in FIG. 24D includes a protection diode 510 and a protection diode 511. Each of these is replaced by two n-type thin-film transistors.

[0235] The protection circuits shown in FIG. 24(C) and FIG. 24(D) use diodes as protection diodes. However, this embodiment is not limited to this configuration. do not have.

[0236] The protection circuit shown in FIG. 24(E) includes protection diodes 520 to 527 and a resistance element 52 8. The resistor element 528 is connected in series between the wiring 529A and the wiring 529B. Each of the protection diodes 520 to 527 is a diode-connected n-type thin film transistor. A transistor is used.

[0237] The protection diode 520 and the protection diode 521 are connected in series, and one end is connected to a potential V s s and the other end is held at potential V in The protection diode 52 is connected to the wiring 529A. 2 and a protection diode 523 are connected in series, and one end is connected to a potential V dd The other end is held is the potential V in The protection diode 524 and the protection diode 529 are connected to the wiring 529A. 525 are connected in series, with one end at potential V ss and the other end is held at potential V out Distribution The protection diode 526 and the protection diode 527 are connected in series. One end is connected to a potential V dd and the other end is held at potential V out Connect to wire 529B It has been done.

[0238] The protection circuit shown in FIG. 24(F) includes a resistance element 530, a resistance element 531, and a protection diode. In FIG. 24(F), a diode is used as the protection diode 532. However, this embodiment is not limited to this configuration. A plurality of diode-connected thin film transistors may be used. The resistive element 531 and the protective diode 532 are connected in series to a wiring 533 .

[0239] The resistor element 530 and the resistor element 531 reduce abrupt changes in the potential of the wiring 533. The deterioration or destruction of the semiconductor element can be prevented. This prevents a reverse bias current from flowing through the wiring 533 due to a change in potential. can be done.

[0240] In addition, when only a resistance element is connected in series to the wiring, it is necessary to reduce the sudden fluctuation of the wiring potential. In addition, the semiconductor element can be prevented from being deteriorated or destroyed. When connecting in series to wiring, it is necessary to prevent reverse current from flowing in the wiring due to fluctuations in potential. This can be done.

[0241] Let us now consider the case where the protection circuit shown in FIG. 24 operates. The source electrodes of the electrodes 501, 502, 506, 511, 520, 521, 524, and 525 At the drain electrode, the potential V ss The side that is held by the resistor is the drain electrode. The protection diodes 503, 504, 507, 510, 522, 523, and 5 At the source and drain electrodes of 26, 527, the potential V dd The side that is held by the saw The other electrode is the source electrode, and the other electrode is the drain electrode. The threshold voltage of the transistor is V th This indicates that.

[0242] In addition, the protection diodes 501, 502, 506, 511, 520, 521, 524, and 52 5 is the potential V in is the potential V ss When the voltage is higher, a reverse bias voltage is applied and current flows more slowly. On the other hand, the protection diodes 503, 504, 507, 510, 522, 523, 526, 527 is the potential V in is the potential V dd When the voltage is lower than the reverse bias voltage, the current is less likely to flow.

[0243] Here, the potential V out is approximately the potential V ss and potential V dd The protection provided between The operation of the circuit will now be described.

[0244] First, the potential V in is the potential V dd Consider the case where the potential is higher than V in is the potential V dd than If high, protection diodes 503, 504, 507, 510, 522, 523, 526, The potential difference between the gate and source electrodes of 527 is V gs =V in -V dd >V th At the time, The n-type thin film transistor is turned on. Here, V in Assume that the case is abnormally high. Therefore, the n-type thin film transistor is turned on. 2, 506, 511, 520, 521, 524, and 525 have n-type thin film transistors. Then, the protection diodes 503, 504, 507, 510, 522, and 5 23, 526, and 527, the power supply of the wiring 505, 508, 515, 529A, and 529B is The runner up is V dd Therefore, the potential V in is the potential V dd abnormally higher than Even if the potential of the wiring 505, 508, 515, 529A, and 529B is V dd It will never be higher than that.

[0245] On the other hand, the potential V in is the potential V ss If the voltage is lower than the threshold voltage, the protection diodes 501, 502, Potential difference between the gate and source electrodes of 506, 511, 520, 521, 524, and 525 V gs =V ss -V in >V th At this time, the n-type thin film transistor is turned on. So, V. in Since it is assumed that the potential is abnormally low, the n-type thin film transistor turns on. At this time, the protection diodes 503, 504, 507, 510, 522, 523, 526, The n-type thin film transistor 527 is turned off. Then, the protection diode 501, 502, 506, 511, 520, 521, 524, 525, and wiring 505, 50 8, 515, 529A, and 529B are V ss Therefore, due to noise, etc., the potential V in is the potential V ss Even if the wiring 505, 508, 515, 52 The potential of 9A and 529B is V ss Furthermore, the capacitance element 51 2, 513 is the input potential V inIt reduces the pulse noise of the It acts to mitigate sudden changes.

[0246] In addition, the potential V in But, V ss -V th From V dd +V th In the case of The n-type thin film transistor in the diode is turned off, and the potential V in is the potential V out year is output.

[0247] By disposing the protection circuits as described above, the wirings 505, 508, 515, and 529A , the potential of 529B is approximately V ss and potential V dd Therefore, The wirings 505, 508, 515, 529A, and 529B are at potentials far outside this range. In other words, the wirings 505, 508, 515, 529A, and 52 9B from becoming abnormally high or low potential, and This makes it possible to prevent the circuit from being destroyed or deteriorated, and to protect the subsequent circuits.

[0248] Furthermore, as shown in FIG. 24C, a protection circuit having a resistor element 514 is provided at the input terminal. By doing so, when no signal is being input, the potential of all wiring to which a signal is applied is kept constant. (Here, the potential V ss ) when no signal is being input. It also functions as a short ring that can short the wires together. It is possible to prevent electrostatic destruction caused by a potential difference occurring between wirings. Since the resistance of 4 is sufficiently large compared to the wiring resistance, the signal applied to the wiring when the signal is input is The number is the potential V ss It is possible to prevent the temperature from dropping to the level below the threshold.

[0249] As an example, the protective diodes 510 and 511 in FIG. Threshold voltage V th A case where an n-type thin film transistor with a capacitance of 0 is used will be described.

[0250] First, V in >V dd In this case, the protection diode 510 is connected to V gs =V in -V dd >0 The protective diode 511 turns off. Therefore, the potential of the wiring 515 becomes V d d And V out =V dd It becomes.

[0251] On the other hand, V in <V ss In this case, the protection diode 510 is turned off. 511 is V gs =V ss -V in >0, and the line 515 is turned on. Therefore, the potential of the line 515 is V ss And V out =V ss It becomes.

[0252] In this way, V in <V ss or V dd <V in Even if V ss <V o ut <V dd Therefore, V in If too high or too low Even in such cases, Vout It is possible to prevent the value from becoming too large or too small. Therefore, for example, if noise or other factors cause the potential V in is the potential V ss Even if it is lower The potential of the wiring 515 is V ss Furthermore, the capacitance element 512 and the capacitance element 513 are connected to the input potential V in It reduces the pulse noise of the potential This serves to mitigate the sudden changes in

[0253] As described above, by disposing the protective circuit, the potential of the wiring 515 is reduced to the potential V ss and electric potential V dd Therefore, if the wiring 515 is far from this range, This prevents the circuit downstream of the protection circuit (the input section is V out In addition, the input (circuits electrically connected to the By providing a protection circuit to the terminal, when no signal is input, all signals The potential of the wiring is kept constant (here, potential V ss ), that is, the signal can be kept at the input When not in use, it functions as a shorting ring that can short wires together. Therefore, it is possible to prevent electrostatic damage caused by the potential difference between wiring. In addition, since the resistance value of the resistor element 514 is sufficiently large, when a signal is input, the wiring 515 This can prevent a decrease in the potential of the signal applied to the

[0254] The protection circuit used in the present invention is not limited to the configuration shown in FIG. As long as the circuit configuration functions as described above, the design can be modified as appropriate.

[0255] The protection diode of the protection circuit of the present invention is a diode-connected thin film transistor. By using the thin film transistor of the present invention in the protection circuit, The area occupied by the protection circuit can be reduced, and the display device can be made narrower in frame, more compact, and with higher performance. It is possible to achieve this.

[0256] (Embodiment 6) In this embodiment mode, a terminal portion of a display device of the present invention will be described with reference to FIG.

[0257] 25(A) and 25(B) are a cross-sectional view and a top view, respectively, of a gate line terminal portion. FIG. 25(A) corresponds to a cross-sectional view taken along line X1-X2 in FIG. 25(B). In FIG. 5(A), a transparent conductive layer 545 on a protective insulating layer 544 is formed by lamination. In FIG. 25(A), the terminal portion is a gate electrode. A first terminal 540 formed of the same material as the source wiring, and a second terminal 541 formed of the same material as the source wiring The connection electrode 543 overlaps with the gate insulating layer 542, and these are connected with each other through the transparent conductive layer 545. The gate insulating layer 542 and the connection electrode 54 are connected (at least electrically). Between the first and second electrodes 541 and 542 is a semiconductor layer 546 (an intrinsic semiconductor layer and a semiconductor layer containing an impurity element of one conductivity type). It is provided.

[0258] 25(C) and 25(D) are a cross-sectional view and a top view, respectively, of a source wiring terminal portion. FIG. 25(C) corresponds to a cross-sectional view taken along line Y1-Y2 in FIG. 25(D). In FIG. 5(C), the transparent conductive layer 545 on the protective insulating layer 544 is In FIG. 25(C), the terminal portion is a gate electrode. An electrode 547 made of the same material as the source wiring is connected (at least electrically) to the source wiring. The electrode 547 overlaps the second terminal 541 via the gate insulating layer 542. The electrode 547 is not directly or electrically connected to the first terminal 541. Setting different potentials, such as floating, GND, or 0V, can be used to reduce noise. A capacitance or a capacitance for electrostatic protection can be formed. The second terminal 541 is , and is (at least electrically) connected to the transparent conductive layer 545. Also, the gate insulating layer 54 Between the second terminal 541 and the second terminal 542 is a semiconductor layer 546 (an intrinsic semiconductor layer and an impurity element of one conductivity type). A semiconductor layer including:

[0259] The gate wiring, source wiring, and capacitance wiring are provided in multiple numbers according to the pixel density. In the terminal section, a first terminal has the same potential as the gate line, a second terminal has the same potential as the source line, A second terminal, a third terminal having the same potential as the capacitance wiring, etc. are arranged in a row. The number of these terminals may be any number and may be determined by the implementer as appropriate.

[0260] The terminal portion and the FPC terminal portion described in this embodiment are connected via anisotropic conductive paste or the like. This allows the supply of signals and power from outside.

[0261] In addition, FIG. 25 shows the terminal part when it is manufactured using a half-tone mask. The present invention is not limited to the above-described embodiment. Figure 26 shows the terminal part when it is manufactured without the use of a solder paste.

[0262] 26(A) and 26(B) show gates fabricated without using a half-tone mask. 26(A) shows a cross-sectional view and a top view of the wiring terminal part. 26A corresponds to a cross-sectional view taken along line X3-X4. The transparent conductive layer 545 is a terminal electrode that functions as an input terminal. In the terminal section, a first terminal 540 formed of the same material as the gate wiring and a source wiring A connection electrode 543 made of the same material as the gate insulating layer 542 is overlapped with the gate insulating layer 542. are (at least electrically) connected via a transparent conductive layer 545. A connection electrode 543 is provided on the layer 542. In this embodiment, no semiconductor layer is provided.

[0263] 26(C) and 26(D) show the source produced without using a halftone mask. 26(C) shows a cross-sectional view and a top view of the wiring terminal portion, respectively. 26(C), the protective insulating layer 544 is The transparent conductive layer 545 is a terminal electrode that functions as an input terminal. In the terminal portion, an electrode 547 made of the same material as the gate wiring is connected to the source wiring ( A second terminal 541 is connected (at least electrically) to the gate insulating layer 542. The electrode 547 is not connected to the second terminal 541. If you set it to a different potential than 41, such as floating, GND, or 0V, it will be possible to reduce noise. A capacitance for preventing the occurrence of static electricity or a capacitance for preventing static electricity can be formed. The second insulating layer 542 is connected to the transparent conductive layer 545. 26(C) and 26(D) show a semiconductor layer provided That is, the terminal portion shown in FIG. 26 does not have a semiconductor layer. It is as follows.

[0264] (Embodiment 7) Next, a display panel mounted on the liquid crystal display device and the light-emitting display device described in the above embodiment will be described. Another embodiment of a light-emitting panel will be described with reference to drawings (cross-sectional views).

[0265] FIG. 27 and FIG. 28 show appearances of a liquid crystal display device and a light-emitting device which are embodiments of the present invention. FIG. 27A shows a semiconductor device having a microcrystalline semiconductor layer formed over a first substrate 601. A thin film transistor 610 and a liquid crystal element 613 are disposed between the second substrate 606 and a sealing material. FIG. 27(B) shows a top view of the liquid crystal display panel sealed with 605. ) corresponds to a cross-sectional view at KL.

[0266] A liquid crystal display device has a liquid crystal element in each pixel. It is an element that controls the transmission or non-transmission of light by using a pair of electrodes and liquid crystal. The optical modulation of liquid crystals is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field, etc.). The liquid crystal element and its driving mode are These include nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, discotic liquid crystals, Thermotropic liquid crystals, lyotropic liquid crystals (also called lyotropic liquid crystals), low molecular weight Liquid crystal, polymer liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma PALC (Panel Address Liquid Crystal), Banana-type Liquid Crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In -Plane-Switching mode, FFS (Fringe Field Switching) mode itching) mode, MVA (Multi-domain Vertical Alignment ignment) mode, PVA (Patterned Vertical Alignment) mode, ment), ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optical Compensated Birefringence) mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) mode, PDLC (Polymer Dispersed Liquid Crystal tal mode, guest host mode, etc. can be used. However, this is not limited to these. In addition, various types of liquid crystal elements can be used.

[0267] The liquid crystal layer may be formed using liquid crystal that exhibits a blue phase without using an alignment film. When the temperature of cholesteric liquid crystal is increased, the liquid crystal changes from the cholesteric phase to the isotropic phase. The blue phase appears just before the transition to the blue phase. In order to improve the temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a high response speed. It is short, at 10μs to 100μs, and is optically isotropic, so alignment processing is not required. The dependency is small.

[0268] A pixel portion 602 and a scanning line driver circuit 604 are provided on a first substrate 601. A second insulating material 605 is provided on the pixel portion 602 and the scanning line driver circuit 604. Therefore, the pixel portion 602 and the scanning line driver circuit 604 are The first substrate 601, the sealant 605, and the second substrate 606 are sealed together with the liquid crystal layer 608. In addition, in the area surrounded by the sealant 605 on the first substrate 601, A signal line driver circuit 603 is also provided in the display panel 601. The signal line driver circuit 603 is not provided separately. The thin film transistor has a polycrystalline semiconductor layer on a substrate. Note that a signal line driver circuit may be formed using transistors using a single crystal semiconductor, and the transistors may be bonded to each other. This may be allowed.

[0269] A pixel portion 602 provided on a first substrate 601 has a plurality of thin film transistors. FIG. 27B illustrates a thin film transistor 610 included in the pixel portion 602. The scanning line driver circuit 604 also has a plurality of thin film transistors. 6 shows a thin film transistor 609 included in the signal line driver circuit 603. The transistor 610 corresponds to a thin film transistor using a microcrystalline semiconductor layer.

[0270] The pixel electrode 612 of the liquid crystal element 613 is connected to the thin film transistor 610 and the wiring 618. Furthermore, the wiring 618 is electrically connected to the lead wiring 614 via the The counter electrode 617 of the liquid crystal element 613 is provided on the second substrate 606. The overlapping portions of the pixel electrode 612, the counter electrode 617, and the liquid crystal layer 608 are liquid crystal layers. This corresponds to the crystal element 613.

[0271] The first substrate 601 and the second substrate 606 may be made of glass, metal (typically The material used may be stainless steel, ceramics, or plastic. The materials used are FRP (Fiberglass-Reinforced Plastics). ) plate, PVF (polyvinyl fluoride) film, polyester film, or acrylic A PVF film or the like can be used. Alternatively, a sheet having a structure sandwiched between two films of polyester may be used.

[0272] The spacer 611 is a bead spacer and is disposed between the pixel electrode 612 and the counter electrode 617. The spacer 611 is provided to keep the distance (cell gap) constant. Instead of the bead spacer of , a spacer obtained by selectively etching an insulating layer ( Post spacers) may be used.

[0273] In addition, the signal line driver circuit 603, the scanning line driver circuit 604, and each of the signals provided to the pixel portion 602 The signal (electric potential) of each type is transmitted through FPC607 (Flexible Printed Circuit t) via lead wiring 614.

[0274] In this embodiment, the connection terminal 616 has the same conductor as the pixel electrode 612 of the liquid crystal element 613. The lead wiring 614 is formed from the same conductive layer as the wiring 618. It has been done.

[0275] The connection terminal 616 and the terminal of the FPC 607 are electrically connected via an anisotropic conductive layer 619. This is being continued.

[0276] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. The display device may further include a color filter, a light-shielding layer, and the like.

[0277] In addition, a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate) Optical films such as polarizing plates, λ / 2 plates, and color filters may be provided as appropriate. Alternatively, the circular polarizing plate may be provided with an antireflection layer.

[0278] 28 illustrates an example of a light-emitting device according to one embodiment of the present invention. As for the light-emitting device, the one using electroluminescence is The light-emitting element that uses electroluminescence uses an organic light-emitting material. They are classified according to whether they are chemical compounds or inorganic compounds. Generally, the former are organic electroluminescence (EL) elements, The latter is called an inorganic EL element.

[0279] In organic EL elements, carriers (electrons and holes) are condensed by applying a voltage to the light-emitting element. A current flows through the pair of electrodes, which are then injected into the layers containing the light-emitting organic compound. The recombination of these carriers (electrons and holes) excites the light-emitting organic compound. When the carriers return from the excited state to the ground state, light is emitted. Due to its mechanism, the optical element is called a current-excited light-emitting element.

[0280] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor recombination that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers, which are then It is sandwiched between a pair of electrodes, and its light-emitting mechanism utilizes the inner-shell electron transition of metal ions. This is localized emission.

[0281] In this embodiment, an organic EL element is used as the light-emitting element. The manufacturing method described in the above embodiment is applied to a thin film transistor for controlling An explanation will be given using a thin film transistor.

[0282] First, thin film transistors 621 and 622 are formed on a substrate. An insulating layer that functions as a protective layer is formed on 622. The insulating layer is made of an inorganic material. The insulating layer 623 made of a metal and the insulating layer 624 made of an organic material are preferably laminated to form the insulating layer 623 . In this case, the upper surface of the insulating layer may be planarized by using an insulating layer made of an organic material. For example, silicon oxide, silicon nitride, silicon oxynitride, etc. may be used. The material is an organic resin such as acrylic, polyimide or polyamide, or siloxane. It is recommended to use:

[0283] A conductive layer is provided on the insulating layer 624 made of an organic material. The first conductive layer functions as a pixel electrode. In the case of an n-type thin film transistor, it is preferable to form a cathode as the pixel electrode. In the case of a p-type thin film transistor, it is preferable to form an anode. In the case of forming a ferroelectric film, a material with a small work function, such as Ca, Al, MgAg, or AlLi, is used. etc. can be used.

[0284] Next, the side (end) of the first conductive layer 625 and the insulating layer 624 formed of an organic material are A partition wall 626 is formed on the first conductive layer 621. The partition wall 626 has an opening. 25 is exposed. The partition wall 626 is an organic resin layer, an inorganic insulating layer, or an organic polysiloxane layer. It is particularly preferable to form the partition wall using a photosensitive material, and the first conductive layer is formed using a photosensitive material. By exposing the partition wall 626 on the conductive layer 625 to light to form an opening, the side wall of the opening becomes continuous. It is preferable to form the inclined surface so as to have a certain curvature.

[0285] Next, a light emitting layer 627 is formed so as to be in contact with the first conductive layer 625 in the opening of the partition wall 626. The light-emitting layer 627 may be formed of a single layer or a plurality of layers. It may be possible.

[0286] Then, a second conductive layer 628 is formed so as to cover the light emitting layer 627. When the first conductive layer 625 is made of a cathode material, the anode The second conductive layer 628 is formed of a material. The second conductive layer 628 is a conductive material having a light-transmitting property. The second conductive layer 628 can be formed of a transparent conductive layer using a nitride material. A titanium layer or a titanium layer may be used. Here, the second conductive layer 628 is made of indium. In the opening of the partition, the first conductive layer 625 and the light emitting layer 6 The light emitting element 630 is formed by overlapping the second conductive layer 628 with the second conductive layer 27. A partition 626 is provided to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light emitting element 630. It is preferable to form a protective layer on the second conductive layer 627. A silicon layer, a silicon oxynitride layer, a DLC layer, etc. can be used. More preferably, A protective film (UV-cured resin film) that is highly airtight and has little degassing so as not to be exposed to the outside air. Further packaging (enclosure) is performed using a film or cover material.

[0287] The light emitting element 630 has at least one of the anode and cathode made transparent in order to extract light. Then, thin film transistors 621 and 622 and a light emitting element 630 are formed on the substrate. The top emission structure emits light from the surface opposite the substrate, while the bottom emission structure emits light from the surface facing the substrate. Bottom emission structure and double-sided emission structure that emits light from both the substrate side and the side opposite the substrate In the light-emitting device according to one embodiment of the present invention, any of the above-described emission structures is applicable. It can be used.

[0288] In the light emitting element 630 having a top emission structure, a light emitting layer and an anode are laminated in this order on a cathode. The cathode is made of a conductive material that has a low work function and reflects light (e.g., Ca, Al, Mg The light-emitting layer may be made of a material such as Ag, AlLi, etc. In this case, for example, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer or a hole transport layer is provided on the cathode. The anode is formed by laminating the first layer, the second layer, and the third layer in that order. It is not necessary to provide all of these layers. The insulating layer is formed using a light-transmitting conductive material, for example, an insulating layer containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium Tin Oxide, Indium Tin Oxide with Titanium Oxide, Indium Tin Oxide (ITO), Indium Translucent materials such as indium zinc oxide or indium tin oxide doped with silicon oxide The light emitted from the light emitting layer is emitted to the anode side.

[0289] In the bottom emission light emitting element 630, a light emitting layer and an anode are laminated in this order on a cathode. In the case where the anode is transparent, a light-shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode is preferably made of a material having a small work function, as in the case of the top emission structure. Any conductive layer formed by a known material may be used. However, the thickness of the conductive layer must be The thickness is set to a level that allows light to pass through (preferably, 5 nm to 30 nm). For example, 20 nm The cathode may be made of aluminum having a thickness of 1.0 m. The light-emitting layer may be made of As with top-injection structures, the structure may consist of a single layer or multiple layers stacked together. The anode does not need to be light-transmitting, but as in the case of a top-emission structure, it may be The light-shielding layer may be formed of a photoconductive material. A metal layer or a resin containing a black pigment may be used. is emitted toward the cathode side.

[0290] The pixel electrode of the light emitting element 630 is a source electrode of the thin film transistor 622 or The drain electrode is electrically connected to the drain electrode via a wiring. The common electrode of the optical element 630 is electrically connected to a light-transmitting conductive material layer.

[0291] The configuration of the light-emitting element 630 is not limited to that shown in this embodiment. The configuration of 30 is determined by the direction of light extracted from the light emitting element 630 and the polarity of the thin film transistor 622. It can be modified appropriately according to the above.

[0292] In addition, when the light emitting element 630 has a top emission structure, The second substrate, which is the substrate on which the light is placed, must be a light-transmitting substrate. In this case, the glass A light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film. A substrate made of a material that can be used.

[0293] The filler 631 disposed between the two substrates may be an inert gas such as nitrogen or argon. UV-curable resin or heat-curable resin can be used, and PVC (polyvinyl chloride) ), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) ) or EVA (ethylene vinyl acetate), etc. can be used. Nitrogen may be used.

[0294] In this embodiment, a thin film transistor 622 (driver) that controls the driving of the light emitting element 630 In the above example, the driving thin film transistor and the light emitting element are directly connected. A current controlling thin film transistor may be connected between the transistor and the light emitting element.

[0295] The light emitting device described in this embodiment is not limited to the configuration shown in the drawings. Various modifications based on technical ideas are possible.

[0296] This embodiment mode can be implemented in combination with the configurations described in the other embodiment modes.

[0297] (Embodiment 8) The semiconductor device having the thin film transistor according to the present invention can be used in various electronic devices (including gaming machines). The electronic device can be applied to, for example, a television device (television, or television receivers), computer monitors, electronic paper, digital digital cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, (also called mobile telephone devices), portable game machines, portable information terminals, audio playback devices, pachinko machines, etc. Examples include large game consoles.

[0298] The semiconductor device having the thin film transistor according to the present invention can be applied to electronic paper. Electronic paper can be used in all types of electronic devices that display information. For example, electronic paper can be used for electronic books, posters, Applies to in-car advertisements on trains and other vehicles, and to displays on various cards such as credit cards. An example of the electronic device is shown in FIG.

[0299] FIG. 29(A) shows an example of an electronic book. The electronic book shown in FIG. 29(A) has a housing 7 The device is made up of two housings, housing 700 and housing 701. Housings 700 and 701 are connected by a hinge. 704, and can perform opening and closing operations. It is possible to operate like a paper book.

[0300] A display unit 702 is incorporated in the housing 700, and a display unit 703 is incorporated in the housing 701. The display units 702 and 703 may be configured to display a continuous screen, or may display different images. By displaying different screens, for example, A text is displayed on the display unit on the left side (display unit 702 in FIG. 29(A)) and In A), an image can be displayed on the display unit 703).

[0301] FIG. 29A shows an example in which the housing 700 is provided with an operation unit and the like. The device 700 includes a power input terminal 705, operation keys 706, a speaker 707, etc. The page can be turned by pressing the key 706. A pointing device or the like may be provided. Terminal for connecting the device (connects to various cables such as earphone terminal, USB terminal, and USB cable) The configuration may include a terminal for inserting a recording medium, etc. The electronic book shown in FIG. 2 may also have a function as an electronic dictionary.

[0302] The electronic book shown in FIG. 29(A) may be configured to transmit and receive information wirelessly. By wireless communication, users can purchase and download the desired book data from the electronic book server. It is also possible to adopt a configuration in which

[0303] FIG. 29(B) shows an example of a digital photo frame. For example, FIG. 29(B) The digital photo frame shown in FIG. 7 has a display unit 712 built into a housing 711. The display unit 712 is capable of displaying various images, such as images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0304] The digital photo frame shown in FIG. 29(B) has an operation unit, an external connection terminal (USB terminals that can be connected to various cables such as USB cables, etc.), and a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a display on the surface of a digital photo frame to improve the design. Insert a memory that stores image data taken with a digital camera into the recording media insertion section to record images. Data can be imported and the imported image data can be displayed on the display unit 712.

[0305] The digital photo frame shown in FIG. 29(B) is configured to be able to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data. Cut.

[0306] FIG. 29(C) shows an example of a television device. The mobile phone device has a display unit 722 built into a housing 721. In addition, the housing 721 is supported by a stand 723. The display device described in the seventh embodiment can be used for the display unit 722. can.

[0307] The television device shown in FIG. 29C can be operated using an operation switch provided on the housing 721 or a separate This can be done by using a remote control unit. The channel and volume can be controlled, and the image displayed on the display unit 722 can be controlled. Also, the information output from the remote control device can be displayed on the remote control device. A display unit may be provided.

[0308] The television device shown in FIG. 29C includes a receiver, a modem, and the like. The receiver can receive general television broadcasts, and can also receive wired or By connecting to a wireless communication network, It is also possible to communicate information in both directions (between sender and receiver, or between receivers, etc.) be.

[0309] FIG. 29(D) shows an example of a mobile phone. The mobile phone shown in FIG. 29(D) has a case. In addition to the display unit 732 incorporated in the body 731, the operation button 733, the operation button 737, the external It is equipped with a connection port 734, a speaker 735, a microphone 736, etc.

[0310] In the mobile phone shown in FIG. 29D, the display portion 732 is a touch panel. By touching the screen, the user can operate the display contents of the display unit 732. An e-mail can be created by touching the display portion 732 with a finger or the like.

[0311] The screen of the display unit 732 has three main modes. The first is a display mode that mainly displays images. The first is a display mode, the second is an input mode for inputting information such as characters, and the third is a display mode. This is a display + input mode that combines two modes: display and input mode.

[0312] For example, when making a call or composing an email, the display unit 732 is used mainly for inputting characters. In this case, the user can enter the character input mode and input the characters displayed on the screen. In this case, most of the screen of the display unit 732 is used to display a keyboard or number buttons. is preferred.

[0313] In addition, the mobile phone shown in FIG. 29(D) includes a gyro sensor, an acceleration sensor, etc., for detecting the inclination. By providing a detection device equipped with a sensor that detects the orientation (portrait or landscape) of the mobile phone, In this way, the display information on the display unit 732 can be automatically switched.

[0314] The screen mode can be switched by touching the display unit 732 or by operating the operation button on the housing 731. The operation is performed by the operation of 737. Also, the type of image displayed on the display unit 732 can be changed. For example, if the image signal to be displayed on the display unit is video data, If the data is text, the mode can be switched to input mode.

[0315] In the input mode, the signal detected by the optical sensor of the display unit 732 is detected. If there is no input from the touch of the 732 for a certain period of time, the screen mode will be changed from input mode to The display mode may be switched to the display mode.

[0316] The display unit 732 can also function as an image sensor. The user touches the screen with their palm or fingers and the image sensor captures their palm print or fingerprint to authenticate the user. In addition, the display unit may include a backlight that emits near-infrared light or a display that emits near-infrared light. By using a sensing light source, it is also possible to capture images of finger veins, palm veins, etc.

[0317] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

Claims

1. The semiconductor device includes first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor; the second conductive layer has a region that intersects with a fifth conductive layer having a region that functions as a gate electrode of the sixth transistor; In a plan view, the channel length directions of the first to fourth transistors are aligned in the same direction.

2. The semiconductor device includes first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor in a region extending in a first direction; the second conductive layer has a region extending in the first direction and intersecting with a fifth conductive layer having a region functioning as a gate electrode of the sixth transistor; In a plan view, a channel length direction of the first to fourth transistors is a direction along the first direction.

3. The first to seventh transistors are included. one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor; the second conductive layer has a region that intersects with a fifth conductive layer having a region that functions as a gate electrode of the sixth transistor; a sixth conductive layer having a region functioning as one of a source electrode or a drain electrode of the third transistor is always electrically connected to an eighth conductive layer having a region functioning as the second power supply line and provided in the same layer as the sixth conductive layer, via a seventh conductive layer provided in the same layer as the fourth conductive layer; In a plan view, the channel length directions of the first to fourth transistors are aligned in the same direction.

4. The semiconductor device includes first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor in a region extending in a first direction; the second conductive layer has a region extending in the first direction and intersecting with a fifth conductive layer having a region functioning as a gate electrode of the sixth transistor; a sixth conductive layer having a region functioning as one of a source electrode or a drain electrode of the third transistor is always electrically connected to an eighth conductive layer having a region functioning as the second power supply line and provided in the same layer as the sixth conductive layer, via a seventh conductive layer provided in the same layer as the fourth conductive layer; In a plan view, a channel length direction of the first to fourth transistors is a direction along the first direction.

5. The semiconductor device includes first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor; the second conductive layer has a region that intersects with a fifth conductive layer having a region that functions as a gate electrode of the sixth transistor; a sixth conductive layer having a region functioning as one of a source electrode or a drain electrode of the third transistor is always electrically connected to an eighth conductive layer having a region functioning as the second power supply line and provided in the same layer as the sixth conductive layer, via a seventh conductive layer provided in the same layer as the fourth conductive layer; the seventh conductive layer has a region intersecting with a ninth conductive layer provided in the same layer as the sixth conductive layer, the ninth conductive layer has a region located between a semiconductor layer having a channel formation region of the seventh transistor and the eighth conductive layer in a plan view, In a plan view, the channel length directions of the first to fourth transistors are aligned in the same direction.

6. The semiconductor device includes first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a second power supply line; a gate electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the first power supply line; a gate electrode of the fourth transistor is always electrically connected to the first signal line; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the first power supply line; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the second power supply line; when the second power supply line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, a potential of the second power supply line is input to the gate electrode of the first transistor and the gate electrode of the sixth transistor through at least a channel formation region of the third transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off and a potential at which the sixth transistor is turned off are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor at least via the channel formation region of the fifth transistor, a first conductive layer having a region functioning as a gate electrode of the second transistor is always electrically connected to a third conductive layer having a region functioning as a gate electrode of the fifth transistor via a second conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor, a region functioning as one of a source electrode or a drain electrode of the sixth transistor, and a region functioning as one of a source electrode or a drain electrode of the seventh transistor; the second conductive layer has a region that intersects with a fourth conductive layer having a region that functions as a gate electrode of the third transistor and a region that functions as a gate electrode of the fourth transistor in a region extending in a first direction; the second conductive layer has a region extending in the first direction and intersecting with a fifth conductive layer having a region functioning as a gate electrode of the sixth transistor; a sixth conductive layer having a region functioning as one of a source electrode or a drain electrode of the third transistor is always electrically connected to an eighth conductive layer having a region functioning as the second power supply line and provided in the same layer as the sixth conductive layer, via a seventh conductive layer provided in the same layer as the fourth conductive layer; the seventh conductive layer has a region intersecting with a ninth conductive layer provided in the same layer as the sixth conductive layer, the ninth conductive layer has a region located between a semiconductor layer having a channel formation region of the seventh transistor and the eighth conductive layer in a plan view, In a plan view, a channel length direction of the first to fourth transistors is a direction along the first direction.

Images