Multilayer ceramic capacitor

Abstract

To provide multilayer ceramic capacitors in each of which an increase in ESL is suppressed even in a high-frequency region, such that an increase in frequency is able to be handled.SOLUTION: A multilayer ceramic capacitor comprises a multilayer body 11 and a pair of external electrodes 20. The multilayer body includes a plurality of dielectric ceramic layers 15 laminated in a lamination direction T, and further has a first main surface 12a and a second main surface 12b defining a pair of main surfaces 12 opposed in the lamination direction T, a first lateral surface 13a and a second lateral surface 13b defining a pair of lateral surfaces 13 opposed in a width direction W, and a first end surface 14a and a second end surface 14b defining a pair of end surfaces 14 opposed in a length direction L. The dielectric ceramic layers 15 each include at least one of Ca, Zr, or Ti. The pair of external electrodes 20 include a first external electrode 20a disposed on the first lateral surface 13a and a second external electrode 20b disposed on the second lateral surface 13b. The length direction L is longer than the lamination direction T and the width direction W.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, multilayer ceramic capacitors have been known that include dielectric ceramic layers containing CaZrO3 (calcium zirconate) as a main component and internal electrodes containing a base metal such as Cu (see, for example, Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-153778 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, as signal transmission speeds have increased, there has been a demand for multilayer ceramic capacitors mounted on AC circuits to support high frequencies, for example, from several hundred MHz to several GHz. However, conventional multilayer ceramic capacitors have a characteristic that their ESL (equivalent series inductance) increases when transmitting signals in the high-frequency range.

[0005] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor capable of supporting higher frequencies by suppressing an increase in ESL even in a high-frequency region. [Means for solving the problem]

[0006] The multilayer ceramic capacitor according to the present invention comprises a laminate having a substantially rectangular parallelepiped shape, the laminate including a plurality of dielectric ceramic layers stacked in a stacking direction T, a first main surface and a second main surface as a pair of main surfaces opposing each other in the stacking direction T, a first side surface and a second side surface as a pair of side surfaces opposing each other in a width direction W perpendicular to the stacking direction T, and a first end surface and a second end surface as a pair of end surfaces opposing each other in a length direction L perpendicular to the stacking direction T and the width direction W, and a pair of external electrodes, the dielectric ceramic layers including at least one of Ca, Zr and Ti, the pair of external electrodes including a first external electrode arranged on the first side surface and a second external electrode arranged on the second side surface, and the length direction L has a dimension longer than the stacking direction T and the width direction W. Effect of the Invention

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of supporting higher frequencies by preventing the ESL from increasing even in a high-frequency region. [Brief description of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor in accordance with a first embodiment; [Diagram 2] FIG. 2 is a cross-sectional view (LT cross-section) taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view (WT cross-section) taken along line III-III in FIG. [Figure 4] FIG. 3 is a cross-sectional view (LW cross-section) taken along line IV-IV in FIG. [Diagram 5] 2 is a partial cross-sectional view showing an example of a structure in which the multilayer ceramic capacitor according to the first embodiment is mounted on a substrate. FIG. [Figure 6] FIG. 6 is a WT cross-sectional view of the multilayer ceramic capacitor in accordance with a second embodiment. [Figure 7] FIG. 11 is a WT cross-sectional view of the multilayer ceramic capacitor in accordance with a third embodiment. [Figure 8]FIG. 11 is a WT cross-sectional view of the multilayer ceramic capacitor in accordance with a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments will be described with reference to the drawings. (First embodiment) Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 10 in accordance with a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV shown in Fig. 2.

[0010] 1, the multilayer ceramic capacitor 10 of the first embodiment has a generally rectangular parallelepiped shape as a whole. The multilayer ceramic capacitor 10 includes a laminate 11 having a generally rectangular parallelepiped shape and a pair of external electrodes 20.

[0011] 1 to 3, arrow T indicates the stacking direction of the multilayer ceramic capacitor 10 and the laminate 11. In Figs. 1, 2 and 4, arrow L indicates the length direction of the multilayer ceramic capacitor 10 and the laminate 11, which is perpendicular to the stacking direction T. In Figs. 1, 3 and 4, arrow W indicates the width direction of the multilayer ceramic capacitor 10 and the laminate 11, which is perpendicular to the stacking direction T and the length direction L. In the multilayer ceramic capacitor 10 of the first embodiment, the length direction L is the longest, and the width direction W is longer than the stacking direction T. FIG. 2 shows the LT cross section, FIG. 3 shows the WT cross section, and FIG. 4 shows the LW cross section.

[0012] The laminate 11 has a first main surface 12a and a second main surface 12b as a pair of main surfaces 12 facing each other in the stacking direction T, a first side surface 13a and a second side surface 13b as a pair of side surfaces 13 facing each other in a width direction W perpendicular to the stacking direction T, and a first end surface 14a and a second end surface 14b as a pair of end surfaces 14 facing each other in a length direction L perpendicular to the stacking direction T and the width direction W.

[0013] 1 and 3, the pair of external electrodes 20 are spaced apart from each other so as to cover the outer surfaces of both ends of the laminate 11 in the width direction W. Each of the pair of external electrodes 20 is formed of a conductive film. The pair of external electrodes 20 includes a first external electrode 20a disposed on the first side surface 13a and a second external electrode 20b disposed on the second side surface 13b.

[0014] 3 and 4 , the external electrode 20 includes a portion 21 covering the side surface 13, and a portion 22 that extends from the portion 21 covering the side surface 13 around the main surface 12 and the end surface 14 to cover these main surface 12 and end surface 14. Hereinafter, the portion 21 covering the side surface 13 may be referred to as the side surface covering portion 21, and the portion 22 covering the main surface 12 and the end surface 14 may be referred to as the end surface covering portion 22.

[0015] Each of the first external electrode 20a and the second external electrode 20b is formed, for example, by a laminated film of a sintered metal layer and a plating layer. The sintered metal layer is formed, for example, by baking a paste of Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, or the like. The plating layer is formed, for example, by a Ni plating layer and a Sn plating layer covering the Ni plating layer. The plating layer may be a Cu plating layer or an Au plating layer instead. Each of the first external electrode 20a and the second external electrode 20b may be formed only by a plating layer, or may use a conductive resin paste.

[0016] As shown in FIGS. 2 to 4, the laminate 11 includes a plurality of dielectric ceramic layers 15 and a plurality of internal electrode layers 16 stacked in a stacking direction T.

[0017] 2 and 3, the dielectric ceramic layer 15 includes a plurality of first dielectric ceramic layers 15a sandwiched between the internal electrode layers 16, a pair of second dielectric ceramic layers 15b arranged at both ends in the stacking direction T and thicker than the first dielectric ceramic layers 15a, and a pair of third dielectric ceramic layers 15c arranged at both ends in the longitudinal direction L and sandwiching the internal electrode layers 16 in the longitudinal direction L. In Fig. 2, a dashed line G indicates a virtual boundary between the third dielectric ceramic layer 15c and the first dielectric ceramic layer 15a or the second dielectric ceramic layer 15b.

[0018] The dielectric ceramic layer 15 of the first embodiment is mainly composed of a ceramic material containing at least one of Ca, Zr, and Ti. Specifically, for example, the main component is a ceramic material having a perovskite structure represented by a general formula ABO3 containing Ca and Zr. Examples of ceramic materials having such a perovskite structure include, but are not limited to, CaZrO3 (calcium zirconate) and TiO2 (titanium oxide). In addition, the main component of the ceramic material forming the dielectric ceramic layer 15 may include all of Ca, Zr, and Ti. In addition, Ca(Zr0.9Ti0.1)O3, in which ZrO3 or part of Zr is replaced with Ti in CaZrO3, may be used.

[0019] The ceramic material for forming the dielectric ceramic layer 15 is (Ca 1-x-y , Sr x , B.A. y ) m (Zr 1-z-α , Ti z , Hf α )O3 (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less), etc. may also be used.

[0020] Depending on the purpose, additives are added to the ceramic material forming the dielectric ceramic layer 15. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, and Cr, V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Y, oxides of Co, Ni, Li, B, Na, K, and Si, and glass.

[0021] The internal electrode layers 16 are conductive thin films containing metals such as Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au. In order to improve the frequency characteristics of the multilayer ceramic capacitor 10, it is preferable to use Cu for the internal electrode layers 16. The internal electrode layers 16 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric ceramic layers 15.

[0022] 2 and 3, the laminate 11 of the first embodiment has three internal electrode layers 16 arranged at equal intervals in the lamination direction T. The laminate 11 has an inner layer portion 11A in which the three internal electrode layers 16 face each other with a first dielectric ceramic layer 15a interposed therebetween, and a pair of outer layer portions 11B arranged to sandwich the inner layer portion 11A in the lamination direction T. In the inner layer portion 11A, the three internal electrode layers 16 are alternately laminated with the first dielectric ceramic layer 15a interposed therebetween.

[0023] As shown in FIG. 3, the three internal electrode layers 16 include one first internal electrode layer 16a and two second internal electrode layers 16b. The one first internal electrode layer 16a is disposed in the center of the stacking direction T. The first internal electrode layer 16a is drawn out to a first side surface 13a of the side surfaces 13 of the laminate 11 and is electrically connected to the first external electrode 20a. The two second internal electrode layers 16b are disposed on both sides of the first internal electrode layer 16a in the stacking direction T. Each second internal electrode layer 16b is drawn out to the second side surface 13b and is electrically connected to the second external electrode 20b. That is, in the inner layer portion 11A, one first internal electrode layer 16a connected to the first external electrode 20a and two second internal electrode layers 16b connected to the second external electrode 20b are alternately stacked in the stacking direction T via the first dielectric ceramic layer 15a. This results in a structure in which two capacitor elements are electrically connected in parallel between the first external electrode 20a and the second external electrode 20b.

[0024] As shown in Fig. 4, the laminate 11 has four first ridges 17a extending in the stacking direction T (the front-to-back direction of the paper in Fig. 4) between the end face 14 and the side face 13. As shown in Fig. 3, the laminate 11 has four second ridges 17b extending in the length direction L (the front-to-back direction of the paper in Fig. 3) between the main surface 12 and the side face 13. As shown in Fig. 2, the laminate 11 has four third ridges 17c extending in the width direction W (the front-to-back direction of the paper in Fig. 2) between the main surface 12 and the end face 14.

[0025] In the multilayer ceramic capacitor 10 of the first embodiment, for example, a laminate 11 is formed by laminating ceramic materials such as ceramic green sheets that form the dielectric ceramic layers 15 and conductive materials such as conductive paste that form the internal electrode layers 16. The laminate 11 is then fired, and thereafter the external electrodes 20 are formed by baking, plating, or the like to manufacture the multilayer ceramic capacitor 10. Note that the external electrodes 20 may be formed by baking a part or all of them at the same time as the firing of the laminate 11, except for the plating.

[0026] As shown in Figures 2 and 3, the thickness ET in the stacking direction T of each of the two dielectric ceramic layers 15 of the inner layer portion 11A, i.e., the two first dielectric ceramic layers 15a sandwiched in the stacking direction T between the internal electrode layers 16, is preferably 2 μm or more and 40 μm or less.

[0027] The thickness of each of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably not less than 0.5 μm and not more than 2.5 μm.

[0028] As shown in Figures 2 and 3, the distances DT in the stacking direction T between the main surface 12 and the internal electrode layer 16 closest to the main surface 12 in the stacking direction T, i.e., between the first main surface 12a and the second internal electrode layer 16b on the first main surface 12a side, and between the second main surface 12b and the second internal electrode layer 16b on the second main surface 12b side, are preferably 10 µm or more and 300 µm or less.

[0029] As shown in Figures 2 and 4, the distance DL in the length direction L between the end face 14 and the internal electrode layer 16, i.e., between the first end face 14a and the first internal electrode layer 16a and the second internal electrode layer 16b, and between the second end face 14b and the first internal electrode layer 16a and the second internal electrode layer 16b, is preferably 5 µm or more and 100 µm or less, and more preferably 5 µm or more and 40 µm or less.

[0030] The radius of curvature of each of the first ridges 17a shown in Fig. 4 is preferably 10 to 25 µm. The radius of curvature of each of the second ridges 17b shown in Fig. 3 is preferably 10 to 25 µm. The radius of curvature of each of the third ridges 17c shown in Fig. 2 is preferably 10 to 25 µm.

[0031] FIG. 5 shows an example of a state in which the multilayer ceramic capacitor 10 of the first embodiment is mounted on a substrate 30. In the multilayer ceramic capacitor 10, a pair of external electrodes 20 are soldered to a pair of lands 31 arranged on the substrate 30 at a distance in the X direction. A surface 30a of the substrate 30 is covered with an insulating film 32 made of solder resist, leaving a predetermined mounting area. A wiring 33 is formed on the surface 30a of the substrate 30. The wiring 33 is discontinuous with a separation portion 34 therebetween, and a pair of lands 31, which are portions of the wiring 33 not covered with the insulating film 32, are exposed on both sides of the separation portion 34. The pair of lands 31 are arranged on the surface 30a of the substrate 30 at a distance from each other in the X direction.

[0032] The multilayer ceramic capacitor 10 has a width direction W substantially parallel to the X direction, and a stacking direction T substantially aligned with a vertical direction Z perpendicular to a surface 30a of the substrate 30. As a result, a second main surface 12b of the main surfaces 12 of the laminate 11 faces the surface 30a of the substrate 30 substantially parallel to the surface 30a of the substrate 30. In the multilayer ceramic capacitor 10, one external electrode 20 (first external electrode 20a) is connected to one land 31 via solder 35, and the other external electrode 20 (second external electrode 20b) is connected to the other land 31 via solder 35.

[0033] The multilayer ceramic capacitor 10 according to the first embodiment described above includes a plurality of dielectric ceramic layers 15 stacked in a stacking direction T, and includes a laminate 11 having a substantially rectangular parallelepiped shape, the laminate 11 having a first main surface 12a and a second main surface 12b as a pair of main surfaces 12 opposing each other in the stacking direction T, a first side surface 13a and a second side surface 13b as a pair of side surfaces 13 opposing each other in a width direction W perpendicular to the stacking direction T, and a first end surface 14a and a second end surface 14b as a pair of end surfaces 14 opposing each other in a length direction L perpendicular to the stacking direction T and the width direction W, and a pair of external electrodes 20, the dielectric ceramic layers 15 including at least one of Ca, Zr, and Ti, the pair of external electrodes 20 including a first external electrode 20a arranged on the first side surface 13a and a second external electrode 20b arranged on the second side surface 13b, and the length direction L has a dimension longer than the stacking direction T and the width direction W.

[0034] As a result, the length direction L is longer than the width direction W, so the width direction length of the internal electrode layer is shortened, and the distance between the pair of external electrodes on both sides of the internal electrode layer is shortened. As a result, the path of the current flowing through the internal electrode layer 16 is shortened, so that it is possible to realize low capacitance and suppress ESL, and as a result, it becomes possible to handle high frequency signals.

[0035] In the multilayer ceramic capacitor 10 according to the first embodiment, the laminate 11 has a plurality of internal electrode layers 16, and the plurality of internal electrode layers 16 preferably include a first internal electrode layer 16a extended to the first side surface 13a and connected to the first external electrode 20a, and a second internal electrode layer 16b extended to the second side surface 13b and connected to the second external electrode 20b.

[0036] This allows the internal electrode layers 16 connected to the first side surface 13a and the second side surface 13b of the laminate 11 to be appropriately arranged, thereby forming a laminated ceramic capacitor that can withstand higher frequencies.

[0037] In the multilayer ceramic capacitor 10 in accordance with the first embodiment, the thickness of the dielectric ceramic layers 15 is preferably not less than 2 μm and not more than 40 μm.

[0038] Since the thickness of the dielectric ceramic layers 15 is relatively large, at not less than 2 μm and not more than 40 μm, the multilayer ceramic capacitor 10 in accordance with the first embodiment achieves a low capacitance. Therefore, the multilayer ceramic capacitor 10 in accordance with the first embodiment prevents the ESL from increasing even in a high frequency range, making it more suitable for use in high frequency circuits that require a low capacitance capacitor.

[0039] In the multilayer ceramic capacitor 10 in accordance with the first embodiment, the thickness of the internal electrode layers 16 is preferably not less than 0.5 μm and not more than 2.5 μm.

[0040] Since the thickness of the internal electrode layer 16 is relatively large, not less than 0.5 μm and not more than 2.5 μm, the ESR can be reduced.

[0041] In the multilayer ceramic capacitor 10 according to the first embodiment, the distance DT in the stacking direction T between the main surface 12 of the laminate 11 and the internal electrode layer 16 closest to this main surface 12 in the stacking direction T is preferably 10 μm or more and 300 μm or less.

[0042] As a result, the thickness of the dielectric ceramic layers on the outer side of the internal electrode layers in the stacking direction becomes relatively large, resulting in low capacitance and preventing the ESL from becoming high even in the high frequency range, making it possible to support higher frequencies.

[0043] In the multilayer ceramic capacitor 10 according to the first embodiment, the distance DL in the length direction L between the end face 14 of the laminate 11 and the internal electrode layer 16 is preferably 5 μm or more and 100 μm or less, and more preferably 5 μm or more and 40 μm or less.

[0044] This allows the ESL and ESR to be reduced by appropriately adjusting the size of the length direction L of the internal electrode layer 16, and also allows for compatibility with higher frequencies. In addition, the end faces 14 can be protected by the dielectric ceramic layer 15, and the size of the length direction L of the internal electrode layer 16 can be adjusted and maximized, thereby realizing low capacitance, suppressing ESL, and enabling compatibility with high frequency signals.

[0045] In the multilayer ceramic capacitor 10 according to the first embodiment, the laminate 11 has four first ridge portions 17a extending in the stacking direction T between the end faces 14 and the side faces 13, four second ridge portions 17b extending in the length direction L between the main face 12 and the side faces 13, and four third ridge portions 17c extending in the width direction W between the main face 12 and the end faces 14, and it is preferable that the radius of curvature of the first ridge portions 17a is 10 to 25 μm, the radius of curvature of the second ridge portions 17b is 10 to 25 μm, and the radius of curvature of the third ridge portions 17c is 10 to 25 μm.

[0046] 5, when mounting the multilayer ceramic capacitor 10 on the substrate 30 by soldering, the balance of tension acting from the solder 35 to the pair of external electrodes 20 may be lost, causing one of the external electrodes 20 to separate from the land 31, resulting in the multilayer ceramic capacitor 10 standing up, a phenomenon known as tombstone phenomenon. However, according to the multilayer ceramic capacitor 10 of the first embodiment, the above-mentioned radius of curvature of each ridge line portion makes it possible to suppress the occurrence of the tombstone phenomenon. In addition, each ridge line portion is appropriately chamfered, making it less likely to chip.

[0047] Next, a second embodiment, a third embodiment, and a fourth embodiment, which are partial modifications of the first embodiment, will be described with reference to Figures 6 to 8. These embodiments are different from the first embodiment in the form of the internal electrode layer 16, but the other configurations are the same. Therefore, the same reference numerals are used to designate components common to the first embodiment, and descriptions are omitted, and differences will be mainly described. 6 to 8, similarly to the first embodiment, the arrow W indicates the width direction, and the arrow T indicates the stacking direction.

[0048] Second embodiment 6 shows a WT cross section of the multilayer ceramic capacitor 10 according to the second embodiment. The multilayer ceramic capacitor 10 has one first internal electrode layer 16a connected to the first external electrode 20a and one second internal electrode layer 16b connected to the second external electrode 20b. The first internal electrode layer 16a and the second internal electrode layer 16b each have a width shorter than half the width of the laminate 11, and are arranged in parallel in approximately the same plane (in the LW cross section) along the length direction L and width direction W. The length direction L is the front-to-back direction of the paper in FIG. 6. The first internal electrode layer 16a and the second internal electrode layer 16b are arranged in approximately the center of the stacking direction T, and there is a gap between them in the width direction.

[0049] In the multilayer ceramic capacitor 10 in accordance with the second embodiment, the first internal electrode layer 16a and the second internal electrode layer 16b are arranged in parallel in approximately the same plane along the length direction L and width direction W.

[0050] This allows the internal electrode layers 16 to not overlap in the lamination direction T, thereby realizing a reduction in capacitance of the multilayer ceramic capacitor 10 in accordance with the second embodiment. Therefore, the multilayer ceramic capacitor 10 in accordance with the second embodiment can be more easily adapted to high-frequency circuits that require a low-capacitance capacitor.

[0051] Third embodiment 7 shows a WT cross section of the multilayer ceramic capacitor 10 according to the third embodiment. This multilayer ceramic capacitor 10 includes three each of the first internal electrode layers 16a and the second internal electrode layers 16b similar to those of the second embodiment. That is, the internal electrode layers 16 of the third embodiment include a first internal electrode layer group 16F1 in which three first internal electrode layers 16a are stacked in the stacking direction T, and a second internal electrode layer group F2 in which three second internal electrode layers 16b are stacked in the stacking direction T.

[0052] The three first internal electrode layers 16a of the first internal electrode layer group 16F1 and the three internal electrode layers 16b of the second internal electrode layer group F2 are disposed at equal intervals in the stacking direction T. Each pair of the first internal electrode layers 16a and the second internal electrode layers 16b adjacent to each other in the width direction W, disposed in the upper, middle and lower three layers, are disposed in parallel in approximately the same plane (in the LW cross section) along the length direction L and the width direction W.

[0053] In addition, the number of first internal electrode layers 16a in the first internal electrode layer group 16F1 and the number of second internal electrode layers 16b in the second internal electrode layer group F2 are not limited to three as long as they are the same number, and may be, for example, a number greater than or equal to 1 and less than or equal to 50.

[0054] In the multilayer ceramic capacitor 10 of the third embodiment, the multiple internal electrode layers 16 include a first internal electrode layer group 16F1 in which a multiple number of first internal electrode layers 16a are stacked in a stacking direction T, and a second internal electrode layer group F2 in which a multiple number of second internal electrode layers 16b are stacked in the stacking direction T.

[0055] As a result, the laminated internal electrode layers 16 ensure a required capacitance and also reduce the ESR.

[0056] (Fourth embodiment) FIG. 8 shows a WT cross section of the multilayer ceramic capacitor 10 according to the fourth embodiment. This multilayer ceramic capacitor 10 has three first internal electrode layers 16a and second internal electrode layers 16b in the stacking direction T as in the third embodiment, but the first internal electrode layer 16a and the second internal electrode layer 16b in the middle layer are shorter in the width direction than those in the upper and lower layers. Then, one third internal electrode layer 16c is disposed between the first internal electrode layer 16a and the second internal electrode layer 16b in the middle layer, which has a shorter width. That is, in the middle layer, the first internal electrode layer 16a, the second internal electrode layer 16b, and the third internal electrode layer 16c are arranged in parallel in approximately the same LW cross section. The third internal electrode layer 16c is disposed approximately at the center in the width direction W, and there is a gap in the width direction between the third internal electrode layer 16c and the first internal electrode layer 16a and the second internal electrode layer 16b. The third internal electrode layer 16c is connected to neither the first external electrode 20a nor the second external electrode 20b.

[0057] In addition, the number of third internal electrode layers 16c that are not connected to the external electrode 20 and are arranged between the first internal electrode layer 16a and the second internal electrode layer 16b in the width direction is not limited to one, and may be multiple, approximately 1 to 50.

[0058] In the multilayer ceramic capacitor 10 according to the fourth embodiment, the multiple internal electrode layers 16 are arranged in parallel between the first internal electrode layer 16a and the second internal electrode layer 16b in approximately the same plane as the first internal electrode layer 16a and the second internal electrode layer 16b in the width direction W, and have at least one third internal electrode layer 16c that is not connected to either the first external electrode 20a or the second external electrode 20b.

[0059] This allows a plurality of capacitor elements to be connected in series via the third internal electrode layers 16c, thereby realizing a reduction in capacitance of the multilayer ceramic capacitor 10 in accordance with the fourth embodiment. Therefore, the multilayer ceramic capacitor 10 in accordance with the fourth embodiment has an improved ability to reduce capacitance and is more compatible with high-frequency circuit signals that require a low-capacitance capacitor.

[0060] Examples of dimensions of the multilayer ceramic capacitor 10 according to the embodiment are presented below, but the dimensions are not limited to these. The overall dimensions of the multilayer ceramic capacitor 10 are, for example, but not limited to, 0.3 mm to 0.6 mm in the width direction W, 0.6 mm to 1 mm in the length direction L, and 0.2 mm to 0.9 mm in the stacking direction T.

[0061] Table 1 shows more specific dimensions of Samples 1 to 12. In Table 1, "capacitor dimensions" are the external dimensions of the multilayer ceramic capacitor including the external electrodes 20, "laminated dimensions" are the external dimensions of the laminate 11 excluding the external electrodes 20, and with regard to the thickness of the external electrodes, "side" is the thickness of the side covering portion 21, "end" is the thickness of the end covering portion 22, "DL" is the distance in the length direction L between the end faces 14 and the internal electrode layers 16, and "length of internal electrode layer" is the dimension in the length direction L of the internal electrode layers 16. The material of the dielectric ceramic layers 15 of Samples 1 to 12 is CaZrO3 (calcium zirconate). The dimensional tolerance includes ±10%.

[0062] [Table 1]

[0063] Although the embodiment has been described above, the present invention is not limited to the above embodiment, and the present invention includes modifications and improvements within the scope of achieving the object of the present invention. For example, when a capacitor with a lower capacitance is desired, the internal electrode layers 16 may be omitted from the laminate 11, and the capacitor may be formed between a pair of external electrodes 20 via the dielectric ceramic layers 15. In this case, the laminate 11 includes a plurality of dielectric ceramic layers 15 stacked in the stacking direction T, and the plurality of dielectric ceramic layers 15 are in direct contact with each other in the stacking direction T. [Explanation of symbols]

[0064] 10 Multilayer ceramic capacitors 11 Laminate 12 Pair of main surfaces 12a First main surface 12b Second main surface 13 Side 13a First aspect 13b The second aspect 14 End face 14a First end face 14b Second end face 15 Dielectric ceramic layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 16c Third internal electrode layer 16F1 First internal electrode layer group 16F2 Second internal electrode layer group 17a First Ridge 17b Second Ridge 17c Third Ridge 20 External electrode 20a First external electrode 20b Second external electrode L Length direction W Width direction T Stacking direction

Claims

1. a laminate including dielectric ceramic layers and internal electrodes alternately stacked in a stacking direction, the laminate having a first main surface and a second main surface as a pair of main surfaces opposing each other in the stacking direction T, a first side surface and a second side surface as a pair of side surfaces opposing each other in a width direction W perpendicular to the stacking direction T, and a first end surface and a second end surface as a pair of end surfaces opposing each other in a length direction L perpendicular to the stacking direction T and the width direction W; A pair of external electrodes; The laminate has a plurality of internal electrode layers, The dielectric ceramic layer contains at least one of Ca and Zr, The dielectric ceramic layer is (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ , Hf α ) O ３ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less), and the thickness in the stacking direction T is 2.0 μm or more and 40 μm or less, the pair of external electrodes includes a first external electrode disposed on the first side surface and a second external electrode disposed on the second side surface, The first external electrode is The first side surface is arranged so as to wrap around the first main surface, the second main surface, the first end surface, and the second end surface, The second external electrode is the second side surface is disposed so as to wrap around the first main surface, the second main surface, the first end surface, and the second end surface; The plurality of internal electrode layers are a first internal electrode layer extending to the first side surface and connected to the first external electrode; a second internal electrode layer extending to the second side surface and connected to the second external electrode; Contains only the first internal electrode layer and the second internal electrode layer are made of Cu; The first internal electrode layer overlaps only the first internal electrode layer in the stacking direction T, The second internal electrode layer overlaps only the second internal electrode layer in the stacking direction T, The length direction L has a dimension longer than the stacking direction T and the width direction W, The dimension of the laminate in the longitudinal direction L is 360 μm or more and 1078 μm or less, The dimension of the laminate in the width direction W is 162 μm or more and 528 μm or less.

2. 2 . The multilayer ceramic capacitor according to claim 1 , wherein the first internal electrode layer and the second internal electrode layer are arranged in parallel in substantially the same plane along the length direction L and the width direction W.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layers include a first internal electrode layer group in which a plurality of the first internal electrode layers are stacked in the stacking direction T, and a second internal electrode layer group in which a plurality of the second internal electrode layers are stacked in the stacking direction T.

4. a laminate including dielectric ceramic layers and internal electrodes alternately stacked in a stacking direction, the laminate having a first main surface and a second main surface as a pair of main surfaces opposing each other in the stacking direction T, a first side surface and a second side surface as a pair of side surfaces opposing each other in a width direction W perpendicular to the stacking direction T, and a first end surface and a second end surface as a pair of end surfaces opposing each other in a length direction L perpendicular to the stacking direction T and the width direction W; A pair of external electrodes; The laminate has a plurality of internal electrode layers, The dielectric ceramic layer contains at least one of Ca and Zr, The dielectric ceramic layer is (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ , Hf α ) O ３ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less), and the thickness in the stacking direction T is 2.0 μm or more and 40 μm or less, the pair of external electrodes includes a first external electrode disposed on the first side surface and a second external electrode disposed on the second side surface, The first external electrode is The first side surface is arranged so as to wrap around the first main surface, the second main surface, the first end surface, and the second end surface, The second external electrode is the second side surface is disposed so as to wrap around the first main surface, the second main surface, the first end surface, and the second end surface; The plurality of internal electrode layers are a first internal electrode layer extending to the first side surface and connected to the first external electrode; a second internal electrode layer extending to the second side surface and connected to the second external electrode; a third internal electrode layer disposed in the stacking direction between the first internal electrode layer and the first internal electrode layer adjacent to each other in the stacking direction, and between the second internal electrode layer and the second internal electrode layer adjacent to each other in the stacking direction, the first internal electrode layer and the second internal electrode layer are made of Cu; The length direction L has a dimension longer than the stacking direction T and the width direction W, The dimension of the laminate in the longitudinal direction L is 360 μm or more and 1078 μm or less, The dimension of the laminate in the width direction W is 162 μm or more and 528 μm or less.

5. 5. The multilayer ceramic capacitor according to claim 4, wherein the plurality of internal electrode layers include at least one third internal electrode layer that is arranged in parallel in approximately the same plane as the first internal electrode layer and the second internal electrode layer between the first internal electrode layer and the second internal electrode layer in the width direction and is not connected to either the first external electrode or the second external electrode.

6. 5. The multilayer ceramic capacitor according to claim 1, wherein the dielectric ceramic layers have a thickness of 2 μm or more and 40 μm or less.

7. 5. The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layers have a thickness of 0.5 μm or more and 2.5 μm or less.

8. 5. The multilayer ceramic capacitor according to claim 1, wherein a distance DT in the stacking direction T between said main surface and said internal electrode layer closest to said main surface in said stacking direction T is 10 μm or more and 300 μm or less.

9. 5. The multilayer ceramic capacitor according to claim 1, wherein a distance DL in the length direction L between the end face and the internal electrode layer is 5 μm or more and 100 μm or less.

10. The laminate comprises: four first ridge portions extending in the stacking direction T between the end faces and the side faces; four second ridge portions extending in the longitudinal direction L between the main surface and the side surfaces; four third ridge portions extending in the width direction W between the main surface and the end surface, The radius of curvature of the first ridge line is 10 to 25 μm; The radius of curvature of the second ridge line is 10 to 25 μm; 5. The multilayer ceramic capacitor according to claim 1, wherein the third edge portion has a radius of curvature of 10 to 25 μm.

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