Semiconductor device

Abstract

To provide a technique relating to a semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate that comprises an oxide semiconductor, and that has, when viewed from above, a rectangular shape defined by a pair of first sides extending along a first direction and a pair of second sides extending along a second direction orthogonal to the first direction; an upper electrode; and a lower electrode. The semiconductor substrate has, when the semiconductor substrate is viewed from above, an element region where a semiconductor element is formed and an outer peripheral region located around the element region. In the outer peripheral region, there is provided, on an upper face of the semiconductor substrate, a heat dissipation layer that comprises a material having a conductivity higher than that of the semiconductor substrate, and that is located to circulate around the element region. When La is a length of the first side, Lb is a length of the second side, κa is a thermal conductivity of the oxide semiconductor in the first direction, and κb is a thermal conductivity of the oxide semiconductor in the second direction, the relationship of κa<κb and κa / La<κb / Lb is satisfied.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate made of a Ga2O3-based semiconductor, an anode electrode provided on an upper surface of the semiconductor substrate, and a cathode electrode provided on a lower surface of the semiconductor substrate, in which a recess is provided on the lower surface of the semiconductor substrate.

[0003] Ga2O3-based semiconductors have excellent voltage resistance, but have a problem of poor heat dissipation. Patent Document 1 describes that since the thickness of the semiconductor substrate is thin in the area where the recess is formed, heat generated in the semiconductor substrate can be easily dissipated, and since the thickness of the semiconductor substrate is thick in the area where the recess is not formed, the mechanical strength of the semiconductor substrate can be maintained. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-106191 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device of Patent Document 1, the thickness of the semiconductor substrate varies greatly depending on the position, and stress is easily applied locally due to the thermal cycle when the semiconductor device is operated. As a result, cracks may occur in the semiconductor substrate. This specification provides a technology that can improve heat dissipation while suppressing unintended stress applied to the semiconductor substrate. [Means for solving the problem]

[0006] The semiconductor device (10) disclosed in this specification is made of an oxide semiconductor and includes a semiconductor substrate (12) having a rectangular shape defined by a pair of first sides (14) extending along a first direction when viewed from above and a pair of second sides (16) extending along a second direction perpendicular to the first direction, an upper electrode (70), and a lower electrode (72). When viewed from above, the semiconductor substrate has an element region (60) in which a semiconductor element is formed, and an outer periphery region (62) arranged around the element region. The upper electrode is in contact with an upper surface (12a) of the semiconductor substrate within the element region. The lower electrode is in contact with a lower surface (12b) of the semiconductor substrate. In the outer periphery region, a heat dissipation layer (28) made of a material having a higher thermal conductivity than the semiconductor substrate and arranged to surround the element region is provided on the upper surface of the semiconductor substrate. The length of the first side is defined as L. a , the length of the second side is L b The thermal conductivity of the oxide semiconductor in the first direction is κ a , the thermal conductivity of the oxide semiconductor in the second direction is κ b Then, κ a <κ b , and κ a / L a <κ b / L b The relationship is satisfied.

[0007] When the semiconductor device operates, a current flows between the upper electrode and the lower electrode, and the semiconductor substrate in the element region generates heat. Since oxide semiconductors have anisotropy in thermal conductivity, heat generated in the semiconductor substrate is likely to be conducted in the direction with higher thermal conductance. In the semiconductor device, the thermal conductance in the first direction and the second direction is κ a / L a <κ b / L bTherefore, the heat generated in the element region is first conducted along the second direction in which the thermal conductance is higher. Since the peripheral region is provided with a heat dissipation layer having a higher thermal conductivity than the semiconductor substrate, the heat conducted from the element region to the peripheral region along the second direction is dissipated to the outside of the semiconductor substrate via the heat dissipation layer. In this way, in the above-mentioned semiconductor device, by adjusting the thermal conductance of the semiconductor substrate and providing a heat dissipation layer in the peripheral region, it is possible to improve the heat dissipation while suppressing unintended stress applied to the semiconductor substrate. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a plan view of the semiconductor device according to the embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the embodiment; [Figure 4] 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the embodiment; [Diagram 5] 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the embodiment; [Figure 6] 3 is a cross-sectional view of a semiconductor device according to a modified example, which corresponds to FIG. 2. [Figure 7] FIG. 11 is a plan view of a semiconductor device according to another modified example, the plan view corresponding to FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In one example of a semiconductor device disclosed in this specification, L a >L b may be satisfied.

[0010] In this configuration, the second side along the second direction in which thermal conductance is high is shorter than the first side, and heat generated in the element region is easily conducted along the second direction, which is a short distance to the peripheral region, thereby improving heat dissipation.

[0011] In one example of a semiconductor device disclosed in this specification, Lb may be 6 mm or less.

[0012] In a semiconductor device, when one side of a semiconductor substrate is 6 mm or less, the thermal resistance increases significantly and the heat dissipation performance deteriorates. For this reason, the technology disclosed in this specification is more effective in the above configuration.

[0013] In the semiconductor device disclosed in this specification, the heat dissipation layer may have a higher breakdown field than the semiconductor substrate.

[0014] In this configuration, a high breakdown voltage can be maintained in the outer periphery region.

[0015] An example semiconductor device disclosed in this specification may further include an insulating film covering the upper surface of the semiconductor substrate and the heat dissipation layer within the peripheral region, and a metal layer provided on the upper surface of the insulating film and connected to the upper electrode.

[0016] In such a configuration, the metal layer can maintain the mechanical strength of the outer peripheral region, and heat conducted to the heat dissipation layer is dissipated via the metal layer, thereby further improving heat dissipation.

[0017] In one example semiconductor device disclosed in the present specification, a first type of semiconductor element and a second type of semiconductor element different from the first type of semiconductor element may be formed in the element region of the semiconductor substrate, and the first type of semiconductor element and the second type of semiconductor element may be arranged along the second direction.

[0018] In such a configuration, heat tends to build up near the boundary between the first type semiconductor element and the second type semiconductor element, so by arranging the first type semiconductor element and the second type semiconductor element along the second direction, heat can be dissipated efficiently.

[0019] In the semiconductor device disclosed in the present specification, the oxide semiconductor may be β-Ga2O3.

[0020] (Example) The semiconductor device 10 of the embodiment shown in Figures 1 and 2 is a Schottky barrier diode. The semiconductor device 10 includes a semiconductor substrate 12, an upper electrode 70, a lower electrode 72, etc. In Figure 1, for ease of viewing, some members on an upper surface 12a of the semiconductor substrate 12 are omitted.

[0021] The semiconductor substrate 12 is made of an oxide semiconductor. Specifically, the semiconductor substrate 12 is made of β-Ga2O3. However, the material of the semiconductor substrate 12 is not limited to β-Ga2O3, and may be, for example, a gallium oxide-based semiconductor such as (Ga,Rh)2O3, (Ga,Ir)2O3, (Ga,Bi)2O3, or ZnGa2O4, or another oxide semiconductor.

[0022] As shown in FIG. 1, the semiconductor substrate 12 has a rectangular shape defined by a pair of sides 14 extending along the x direction and a pair of sides 16 extending along the y direction when viewed from above. In FIG. 1, the surface along the x direction and the z direction is the (010) surface of β-Ga2O3, the surface along the y direction and the z direction is the (100) surface of β-Ga2O3, and the surface along the x direction and the y direction is the (001) surface of β-Ga2O3. That is, the x direction is the

[0100] direction, the y direction is the

[0010] direction, and the z direction is the

[0001] direction. In addition, β-Ga2O3 has anisotropy in thermal conductivity. Specifically, the thermal conductivity in the

[0100] direction is 13.6 W / mk, and the thermal conductivity in the

[0010] direction is 22.8 W / mk. That is, the thermal conductivity in the

[0100] direction is lower than that in the

[0010] direction. Also, in this embodiment, the first side 14 is longer than the second side 16. For example, the first side 14 is 10 mm, and the second side 16 is 6 mm. That is, the thermal conductance in the

[0100] direction (the thermal conductivity divided by the length of the side) is lower than that in the

[0010] direction.

[0023] The semiconductor substrate 12 has an element region 60 and a peripheral region 62. As shown in Fig. 1, the element region 60 is disposed in the center of the semiconductor substrate when the semiconductor substrate 12 is viewed from above. The element region 60 is a region in which a semiconductor element (a diode structure in this embodiment) is formed. The peripheral region 62 is disposed around the element region 60, which is the peripheral portion of the semiconductor substrate 12 when the semiconductor substrate 12 is viewed from above.

[0024] As shown in FIG. 2, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12 in the element region 60. Each trench 22 extends linearly in the x direction. The trenches 22 are arranged at intervals in the y direction. The inner surface of each trench 22 is covered with an oxide film 24. The upper electrode 70 is arranged in the element region 60 so as to straddle the inside of each trench 22 to the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is also arranged so as to straddle the element region 60 to a part of the peripheral region 62. Inside each trench 22, the upper electrode 70 is insulated from the semiconductor substrate 12 by the oxide film 24. The upper electrode 70 is in Schottky contact with the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 functions as an anode electrode.

[0025] As shown in FIG. 2, in the peripheral region 62, a mesa portion 26 is provided on the upper surface 12a of the semiconductor substrate 12. The depth of the mesa portion 26 is slightly deeper than the depth of the trench 22 in the element region 60. In the peripheral region 62, a plurality of heat dissipation layers 28 are formed on the upper surface 12a of the semiconductor substrate 12 (the bottom surface of the mesa portion 26). As shown in FIG. 1, each heat dissipation layer 28 is concentrically arranged so as to go around the element region 60. The heat dissipation layer 28 is made of a material having a higher thermal conductivity than the semiconductor substrate 12 and a higher dielectric breakdown field than the semiconductor substrate 12. The heat dissipation layer 28 is made of, for example, AlN (i.e., aluminum nitride). The thermal conductivity of AlN is 230 W / mK, and the dielectric breakdown field of AlN is 12 MV / cm (β-Ga2O3 is 8 MV / cm). The heat dissipation layer 28 and the upper surface 12a of the semiconductor substrate 12 (including the inner surface of the mesa portion 26) are covered with an insulating film 29. The oxide film 24 in the element region 60 and the insulating film 29 in the peripheral region 62 are connected at the boundary between the element region 60 and the peripheral region 62 .

[0026] 2, the upper surface of the upper electrode 70 in the element region 60 and the upper surface of the insulating film 29 in the peripheral region 62 are covered with a passivation film 30. The passivation film 30 has an opening at a position not shown, where the upper electrode 70 is connected to the outside (e.g., a bonding pad).

[0027] The lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is formed on substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in ohmic contact with the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 functions as a cathode electrode.

[0028] As shown in FIG. 2, the semiconductor substrate 12 includes n + n-type semiconductor layer 40, n-type semiconductor layer 42, - A type semiconductor layer 44 is provided. + The n-type semiconductor layer 40 is provided in a position in contact with the lower electrode 72 across the element region 60 and the peripheral region 62. +The n-type semiconductor layer 42 is provided on the upper side of the n-type semiconductor layer 40. + The n-type semiconductor layer 42 has a lower n-type impurity concentration than the n-type semiconductor layer 40. The n-type semiconductor layer 42 is provided across the element region 60 and the peripheral region 62. In the element region 60, the n-type semiconductor layer 42 has + The n-type semiconductor layer 42 extends from the upper end of the n-type semiconductor layer 40 to a position that reaches the upper surface 12a of the semiconductor substrate 12. - A type semiconductor layer 44 is provided. - The n-type semiconductor layer 44 has a lower n-type impurity concentration than the n-type semiconductor layer 42. - The n-type semiconductor layer 44 extends from the upper end of the n-type semiconductor layer 42 to a position reaching the upper surface 12a of the semiconductor substrate 12 (the bottom surface of the mesa portion 26).

[0029] In the semiconductor device 10 of this embodiment, when a forward bias is applied between the upper electrode 70 and the lower electrode 72, the Schottky barrier at the interface between the upper electrode 70 and the semiconductor substrate 12 (n-type semiconductor layer 42) is lowered, and a current flows from the upper electrode 70 to the lower electrode 72. On the other hand, when a reverse bias is applied between the upper electrode 70 and the lower electrode 72, the Schottky barrier at the interface between the upper electrode 70 and the semiconductor substrate 12 (n-type semiconductor layer 42) is raised, and the current stops.

[0030] When the semiconductor device 10 operates in this manner, a current flows between the upper electrode 70 and the lower electrode 72, and the semiconductor substrate 12 in the element region 60 generates heat. As described above, β-Ga2O3 has anisotropy in thermal conductivity, so that heat generated in the semiconductor substrate 12 is easily conducted in a direction with high thermal conductance. In the semiconductor device 10 of this embodiment, the first side 14 (side along the

[0100] direction) is longer than the second side 16 (side along the

[0010] direction), and the thermal conductance in the

[0100] direction is lower than that in the

[0010] direction. Therefore, the heat generated in the element region 60 is conducted along the

[0010] direction, which has a higher thermal conductance. Since the distance to the peripheral region 62 in the

[0010] direction is short, the heat in the element region 60 can be rapidly conducted to the peripheral region 62. In addition, since the peripheral region 62 is provided with the heat dissipation layer 28 having a higher thermal conductivity than the semiconductor substrate 12, the heat conducted from the element region 60 to the peripheral region 62 along the

[0010] direction is dissipated to the outside of the semiconductor substrate 12 via the heat dissipation layer 28. In this manner, in the semiconductor device 10 of this embodiment, by adjusting the thermal conductance of the semiconductor substrate 12 and providing the heat dissipation layer 28 in the peripheral region 62, it is possible to improve the heat dissipation performance while suppressing unintended stress applied to the semiconductor substrate 12.

[0031] In the semiconductor device 10 of this embodiment, the second side 16 is 6 mm. In the semiconductor device 10, if one side of the semiconductor substrate 12 is 6 mm or less, the thermal resistance becomes significantly high and the heat dissipation performance deteriorates. For this reason, the above-mentioned technology is more effective when the size of the semiconductor substrate 12 is relatively small, as in this embodiment.

[0032] In this embodiment, the dielectric breakdown field of the heat dissipation layer 28 is higher than the dielectric breakdown field of the semiconductor substrate 12. Therefore, a high breakdown voltage can be maintained in the peripheral region 62.

[0033] Next, a method for manufacturing the semiconductor device 10 will be described. First, as shown in FIG. +A semiconductor substrate 12 having an n-type semiconductor layer 40 and an n-type semiconductor layer 42 made of β-Ga2O3 is prepared, and a plurality of trenches 22 and mesa portions 26 are formed on the upper surface 12a of the semiconductor substrate 12. The semiconductor substrate 12 before processing is, for example, an n-type + The n-type semiconductor layer 42 can be formed by epitaxial growth on the upper surface of the n-type semiconductor layer 40. In this process, the trenches 22 are formed in the element region 60, and the mesa portion 26 is formed in the peripheral region 62 so as to surround the periphery of the element region 60.

[0034] Next, as shown in FIG. 4, p-type impurities (e.g., Fe ions, N ions, Mg ions, etc.) are implanted into the peripheral region 62 in the range exposed to the upper surface 12a of the semiconductor substrate 12 and the bottom surface of the mesa portion 26, forming an n-type semiconductor layer 42 having a lower n-type impurity concentration than the n-type semiconductor layer 42. - A type semiconductor layer 44 is then formed. Then, a plurality of heat dissipation layers 28 made of AlN are formed on the upper surface 12a of the semiconductor substrate 12 in the peripheral region 62. The heat dissipation layers 28 are formed concentrically so as to go around the periphery of the element region 60. The heat dissipation layers 28 can be formed, for example, by forming an AlN film over the entire upper surface 12a of the semiconductor substrate 12 by a CVD (chemical vapor deposition) method or the like, and then selectively etching the AlN.

[0035] 5, an oxide film 24 is formed in the element region 60 to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22, and an insulating film 29 is formed in the outer periphery region 62 to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the mesa portion 26, and then an annealing process is performed on the semiconductor substrate 12. Thereafter, the oxide film 24 in the portion covering the upper surface 12a of the semiconductor substrate 12 in the element region 60 is selectively removed by etching, and then an upper electrode 70, a lower electrode 72, and a passivation film 30 are formed, thereby completing the semiconductor device 10 shown in FIG.

[0036] 6, the embodiment described above may further include a metal layer 74 provided on the upper surface of the insulating film 29 and connected to the upper electrode 70 in the outer circumferential region 62. In such a configuration, the mechanical strength of the outer circumferential region 62 can be maintained by the metal layer 74, and the heat conducted to the heat dissipation layer 28 is dissipated via the metal layer 74, thereby further improving the heat dissipation performance.

[0037] In the above embodiment, the example in which a Schottky barrier diode is formed as a semiconductor element in the element region 60 has been described, but the semiconductor element formed in the element region 60 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). As shown in FIG. 7, two types of semiconductor elements 80 and 82 (for example, a diode and a MOSFET) may be formed in the element region 60 of a single semiconductor substrate 12. In this case, as shown in FIG. 7, the semiconductor elements 80 and 82 may be arranged along the

[0010] direction in which the thermal conductance is higher. With this configuration, heat that tends to be trapped near the boundary between the semiconductor elements 80 and 82 can be efficiently dissipated.

[0038] In the above embodiment, the first side 14 is longer than the second side 16, but the relationship in length between the first side 14 and the second side 16 is not limited to this. If the thermal conductance in the

[0100] direction is lower than the thermal conductance in the

[0010] direction, the first side 14 may be shorter than the second side 16, or the first side 14 and the second side 16 may be of equal length.

[0039] The configurations disclosed in this specification are listed below. (Configuration 1) A semiconductor device comprising: a semiconductor substrate made of an oxide semiconductor and having a rectangular shape defined by a pair of first sides extending along a first direction when viewed from above and a pair of second sides extending along a second direction perpendicular to the first direction; An upper electrode; A lower electrode; Equipped with the semiconductor substrate has, when viewed from above, an element region in which a semiconductor element is formed, and a peripheral region disposed around the element region; the upper electrode is in contact with an upper surface of the semiconductor substrate in the element region, the lower electrode is in contact with a lower surface of the semiconductor substrate, a heat dissipation layer is provided on the upper surface of the semiconductor substrate in the peripheral region, the heat dissipation layer being made of a material having a higher thermal conductivity than the semiconductor substrate and arranged so as to surround the element region; The length of the first side is L a , the length of the second side is L b The thermal conductivity of the oxide semiconductor in the first direction is κ a , the thermal conductivity of the oxide semiconductor in the second direction is κ b Then, κ a <κ b , and κ a / L a <κ b / L b The relationship is satisfied, Semiconductor device. (Configuration 2) L a >L b The semiconductor device according to configuration 1, wherein the following relationship is satisfied. (Configuration 3) L b 3. The semiconductor device according to claim 1, wherein the width of the semiconductor device is 6 mm or less. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the heat dissipation layer has a higher dielectric breakdown field than the semiconductor substrate. (Configuration 5) an insulating film covering the upper surface of the semiconductor substrate and the heat dissipation layer in the peripheral region; a metal layer provided on an upper surface of the insulating film and connected to the upper electrode; 5. The semiconductor device according to any one of configurations 1 to 4, further comprising: (Configuration 6) a first type of semiconductor element and a second type of semiconductor element different from the first type of semiconductor element are formed in the element region of the semiconductor substrate; 6. The semiconductor device according to any one of configurations 1 to 5, wherein the first type semiconductor element and the second type semiconductor element are arranged along the second direction. (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the oxide semiconductor is β-Ga2O3.

[0040] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0041] 10: semiconductor device, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 14: first side, 16: second side, 28: heat dissipation layer, 29: insulating film, 60: element region, 62: peripheral region, 70: upper electrode, 72: lower electrode, 74: metal layer

Claims

1. A semiconductor device (10), A semiconductor substrate (12) made of an oxide semiconductor and having a rectangular shape defined by a pair of first sides (14) extending along a first direction when viewed from above and a pair of second sides (16) extending along a second direction perpendicular to the first direction; An upper electrode (70); A lower electrode (72); Equipped with When viewed from above, the semiconductor substrate has an element region (60) in which a semiconductor element is formed, and a peripheral region (62) disposed around the element region, the upper electrode is in contact with an upper surface (12a) of the semiconductor substrate in the element region, The lower electrode is in contact with a lower surface (12b) of the semiconductor substrate, In the peripheral region, a heat dissipation layer (28) is provided on the upper surface of the semiconductor substrate, the heat dissipation layer (28) being made of a material having a higher thermal conductivity than the semiconductor substrate and being arranged so as to surround the element region; The length of the first side is L ａ , the length of the second side is L ｂ , the thermal conductivity of the oxide semiconductor in the first direction is κ ａ , the thermal conductivity of the oxide semiconductor in the second direction is κ ｂ Then, κ ａ <κ ｂ , and κ ａ / L ａ <κ ｂ / L ｂ The relationship is satisfied, Semiconductor device.

2. L ａ >L ｂ The semiconductor device according to claim 1 , wherein the following relationship is satisfied:

3. L ｂ The semiconductor device according to claim 1 , wherein the distance between the first and second electrodes is 6 mm or less.

4. The semiconductor device according to claim 1 , wherein the heat dissipation layer has a higher dielectric breakdown field than the semiconductor substrate.

5. an insulating film (29) covering the upper surface of the semiconductor substrate in the peripheral region and the heat dissipation layer; a metal layer (74) provided on an upper surface of the insulating film and connected to the upper electrode; The semiconductor device according to claim 1 , further comprising:

6. A first type of semiconductor element (80) and a second type of semiconductor element (82) different from the first type of semiconductor element are formed in the element region of the semiconductor substrate, The semiconductor device according to claim 1 , wherein the first type semiconductor element and the second type semiconductor element are arranged along the second direction.

7. The oxide semiconductor is β-Ga ２ O ３ The semiconductor device according to claim 1 ,

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