System-on-chip and manufacturing method therefor

Abstract

To provide a novel transistor with better structure and comprehensive performance to be used in a peripheral standard cell and an embedded memory cell of a system-on-chip that is desired in the industry.SOLUTION: A system-on-chip according to the present invention includes: an embedded memory module; and a peripheral digital module thereof. The embedded memory module includes at least one embed memory cell. The digital module includes: a first MOS transistor; and at least one standard cell. The standard cell includes a second MOS transistor. The embedded memory cell includes a third MOS transistor. Each of the first, the second, and the third MOS transistors includes one gate and gate oxide material layers below the gate. The second MOS transistor and the third MOS transistor have same thickness, are thinner than the gate oxide layer of the first MOS transistor. A transistor of an intermediate thickness data oxide layer in the peripheral standard cell and the memory cell in the system-on-chip of the present invention has: a smaller area; a lower operation voltage; and a smaller power consumption.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to a system on chip and a manufacturing method thereof, and in particular to a system on chip including a digital module and an embedded storage module and a manufacturing method thereof. [Background technology]

[0002] A system on chip (SOC) includes a storage module and a peripheral digital module. The storage module includes an embedded storage module and a non-embedded storage module. The embedded storage module includes an embedded storage cell, which includes a storage transistor. The peripheral digital module includes a logic transistor (also called a peripheral logic transistor) and a standard cell, which also includes a logic transistor (also called a peripheral logic transistor).

[0003] The peripheral logic transistors and storage transistors include different types of thick and thin gate oxide layers. The thick gate oxide transistors are typically 5v devices, and the thin gate oxide transistors are typically 1.5v or 1.8v devices. The thick gate oxide transistor elements may be referred to as high voltage transistor elements, and the thin gate oxide transistor elements may be referred to as low voltage transistor elements.

[0004] Peripheral standard cells and embedded memory cells usually choose high voltage transistors, e.g., 5v transistors, or low voltage transistors, e.g., 1.5v transistors, which respectively have the following disadvantages: high voltage transistors have thick gate oxide layers, high threshold voltages, large areas, small unit capacitances, and are not applicable to low voltages, e.g., voltages below 5v, while low voltage transistors have low voltage resistance and are not applicable to high voltages, e.g., voltages above 1.5v. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need in the industry for new transistors with better structure and integration for use in peripheral standard cells and embedded storage cells of systems-on-chip. [Means for solving the problem]

[0006] A system on chip according to a first aspect of the present invention includes a digital module including at least one first MOS transistor and at least one standard cell, and an embedded storage module including at least one embedded storage cell, the standard cell including at least one second MOS transistor, the embedded storage cell including at least one third MOS transistor, the first MOS transistor, the second MOS transistor and the third MOS transistor each including a gate and an underlying gate oxide layer, the gate oxide layers of the second MOS transistor and the third MOS transistor having the same thickness and each thinner than the gate oxide layer of the first MOS transistor.

[0007] In one preferred embodiment, the thickness of the gate oxide layer of the second and third MOS transistors is at least 10 Angstroms less than that of the first MOS transistor, more preferably at least 20 Angstroms less.

[0008] In another preferred embodiment, the gate oxide layers of the second MOS transistor and the third MOS transistor are formed in the same step in the same manufacturing process platform.

[0009] In another preferred embodiment, the digital module further comprises a fourth MOS transistor including a gate and an underlying gate oxide layer, the thickness of the gate oxide layer of the second MOS transistor being greater than the thickness of the gate oxide layer of the fourth MOS transistor, more preferably the thickness of the gate oxide layer of the second MOS transistor being at least 5 Angstroms greater than the thickness of the gate oxide layer of the fourth MOS transistor.

[0010] In yet another preferred embodiment, the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is 30 to 190 angstroms.

[0011] In yet another preferred embodiment, said embedded memory cells are embedded non-volatile memory cells, more preferably embedded multiple-times programmable and erasable memory cells or embedded flash memory cells.

[0012] In yet another preferred embodiment, the standard cell is an inverter, a NAND gate, a NOR gate, a three-state buffer, a latch, a flip-flop, a register, a selector, or a full adder.

[0013] According to another aspect of the present invention, a method for manufacturing the above-mentioned system-on-chip of the present invention includes a step of forming a gate oxide layer of a first MOS transistor, and then thinning the formed gate oxide layer in an area where a second MOS transistor and a third MOS transistor are to be formed, while simultaneously forming gate oxide layers of the second MOS transistor and the third MOS transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The system on chip includes multiple modules, each of which includes multiple semiconductor elements, such as transistors. A module further includes several cells that are made up of semiconductor elements (such as transistors).

[0015] The system on chip of the present invention includes an embedded memory module and a peripheral digital module. The first MOS transistor and the fourth MOS transistor included in the digital module and the second MOS transistor included in the standard cell may be called thick gate oxide layer and thin gate oxide layer peripheral logic transistors and medium thickness gate oxide layer peripheral logic transistors, respectively. The third MOS transistor included in the memory cell in the embedded memory module may be called medium thickness gate oxide layer memory transistor.

[0016] The first MOS transistor and the fourth MOS transistor in the digital module are preferably not included within a standard cell in the digital module.

[0017] In the system-on-chip of the present invention, the gate oxide layer thickness of the peripheral logic transistor with the intermediate gate oxide layer is the same as the gate oxide layer thickness of the storage transistor with the intermediate gate oxide layer, but is thinner than the gate oxide layer thickness of the peripheral logic transistor with the thick gate oxide layer. If the digital module further includes a peripheral logic transistor with the intermediate gate oxide layer, the gate oxide layer thickness of the peripheral logic transistor with the intermediate gate oxide layer is not only thinner than the gate oxide layer thickness of the peripheral logic transistor with the thick gate oxide layer, but also thicker than the gate oxide layer thickness of the peripheral logic transistor with the thin gate oxide layer, i.e., between the gate oxide layer thickness of the first MOS transistor and the gate oxide layer thickness of the fourth MOS transistor in the digital module.

[0018] The intermediate gate oxide peripheral logic transistor of the present invention has a gate oxide thickness that is thinner than that of the thick gate oxide peripheral logic transistor in the digital module, and thus has higher performance, i.e., can tolerate a smaller gate line width (channel length of transistor), reduce area, has a lower threshold voltage, can meet the requirements of medium or low operating voltage, and has higher device characteristics, such as a larger driving capability (driving current) and a higher unit capacitance, compared with the thick gate oxide peripheral logic transistor (i.e., the high voltage transistor commonly used in the normal peripheral standard cell).

[0019] In addition, the intermediate gate oxide peripheral logic transistor has a gate oxide thickness greater than that of the thin gate oxide peripheral logic transistor in the digital module, and thus has a higher voltage resistance than the thin gate oxide peripheral logic transistor (i.e., the low voltage transistor commonly used in the ordinary peripheral standard cells), and can meet the requirements of a slightly higher or medium operating voltage.

[0020] Similarly, the medium-thickness gate oxide layer memory transistor of the present invention can reduce the operating voltage, reduce the area, and reduce the power consumption compared to the thick gate oxide layer memory transistor, and has a higher voltage resistance compared to the thin gate oxide layer memory transistor, and can meet the requirements of slightly higher or medium operating voltage.

[0021] In the present invention, the thickness of the gate oxide layer of the peripheral logic transistor (second MOS transistor) with the intermediate thickness gate oxide layer is preferably at least 10 angstroms less than the thickness of the gate oxide layer of the peripheral logic transistor (first MOS transistor) with the thick gate oxide layer, more preferably at least 20 angstroms less, and even more preferably at least 30 angstroms less.

[0022] When the digital module further includes a peripheral logic transistor (fourth MOS transistor) with a medium thickness gate oxide layer, the thickness of the gate oxide layer of the peripheral logic transistor with a medium thickness gate oxide layer is preferably at least 5 angstroms more than the thickness of the gate oxide layer of the peripheral logic transistor with a thin gate oxide layer, more preferably at least 10 angstroms more, even more preferably at least 20 angstroms more, even more preferably at least 30 angstroms more, and most preferably at least 50 angstroms more.

[0023] The intermediate thickness gate oxide storage transistors have the same gate oxide thickness preference as the intermediate thickness gate oxide peripheral logic transistors.

[0024] In the present invention, the thickness of the gate oxide layer of the peripheral logic transistor and the memory transistor is not particularly limited to a specific dimension, and is set according to a specific application. Preferably, the thickness has the following dimensions:

[0025] The thickness of the gate oxide layer of the peripheral logic transistor (first MOS transistor) with a thick gate oxide layer is >60 angstroms, preferably 70-300 angstroms, more preferably 80-260 angstroms, even more preferably 90-220 angstroms, and most preferably 100-180 angstroms.

[0026] The thickness of the gate oxide layer of the peripheral logic transistor (second MOS transistor) of the intermediate thickness gate oxide layer and the memory transistor (third MOS transistor) of the intermediate thickness gate oxide layer is preferably 30 to 190 angstroms, more preferably 40 to 150 angstroms, more preferably 50 to 110 angstroms, even more preferably 55 to 100 angstroms, and most preferably 60 to 90 angstroms.

[0027] The thickness of the thin gate oxide layer of the peripheral logic transistor (fourth MOS transistor) is preferably 10 to 40 angstroms, more preferably 12 to 38 angstroms, even more preferably 15 to 35 angstroms, and most preferably 18 to 32 angstroms.

[0028] In the present invention, the gate line width (channel length) of the peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer is preferably smaller than the gate line width (channel length) of the peripheral logic transistor of the thick gate oxide layer. When the digital module includes two types of peripheral logic transistors of the thick gate oxide layer and the thin gate oxide layer, the gate line width (channel length) of the peripheral logic transistor of the intermediate thickness gate oxide layer is preferably not only smaller than the gate line width (channel length) of the peripheral logic transistor of the thick gate oxide layer, but also larger than the gate line width (channel length) of the peripheral logic transistor of the thin gate oxide layer, and is between them.

[0029] In the present invention, the gate line width (channel length) of the peripheral logic transistor and memory transistor is not particularly limited in terms of specific dimensions, and is set according to a specific application, and preferably has the following dimensions.

[0030] The gate line width (channel length) of the peripheral logic transistor of the thick gate oxide layer is preferably 0.11 to 12.00 μm, more preferably 0.15 to 7.00 μm, even more preferably 0.20 to 2.00 μm, and most preferably 0.30 to 0.8 μm.

[0031] The gate line width (channel length) of the peripheral logic transistor of the medium-thickness gate oxide layer and the memory transistor of the medium-thickness gate oxide layer is preferably 0.05 to 10.00 μm, more preferably 0.08 to 5.00 μm, even more preferably 0.11 to 1.00 μm, and most preferably 0.13 to 0.60 μm.

[0032] The gate line width (channel length) of the peripheral logic transistor of the thin gate oxide layer is preferably 0.01 to 5.00 μm, more preferably 0.03 to 1.00 μm, even more preferably 0.05 to 0.5 μm, and most preferably 0.07 to 0.20 μm.

[0033] In the system-on-chip of the present invention, the peripheral logic transistors in the digital module and the storage transistors in the storage module are manufactured and formed in the same manufacturing process platform. That is, the peripheral logic transistors in the thick gate oxide layer, the peripheral logic transistors in the medium thickness gate oxide layer, and the storage transistors in the medium thickness gate oxide layer are manufactured and formed in the same manufacturing process platform. If the digital module further includes a peripheral logic transistor in the thin gate oxide layer, the peripheral logic transistor in the thin gate oxide layer is also manufactured and formed in the same manufacturing process platform. For the peripheral logic transistors in the medium thickness gate oxide layer and the storage transistors in the medium thickness gate oxide layer, their gate oxide layers are formed together in the same manufacturing process and in the same steps, and their well implantation, gate formation, and lightly and heavily doped source and drain doping steps are respectively performed together with the corresponding steps of the peripheral logic transistors in the thick gate oxide layer. However, when the types of these transistors are different, the well implantation and the types of ions doped in the source and drain are different. Such a manufacturing method is very convenient and can not only improve efficiency but also reduce costs. Since the formation of new transistor elements in chips known in the industry usually requires an additional gate oxide layer formation step, an additional well implantation and a source-drain doping step, the technical means of the present invention reduces the process complexity and eliminates the photomask level.

[0034] That is, for an embedded memory module platform based on logic process, the present invention utilizes the tunnel oxide in the memory cell as the gate oxide layer of the logic transistor around the intermediate gate oxide layer, and shares well implantation process, source-drain light doping and heavy doping process, etc. with the standard logic element with thick gate oxide layer in the process platform to form a novel transistor or transistor capacitor. The novel transistor has a thinner gate oxide layer, a lower threshold voltage, and can operate at a lower operating voltage, the element has a smaller design rule, and the standard cell based on the process platform has a smaller area when using the novel element, which can greatly reduce the product cost for customers.

[0035] The system on chip of the present invention can be manufactured using a variety of standard logic process platforms common in the industry, such as 180nm, 150nm, 130nm, 110nm, 90nm, 55nm, or 40nm process platforms. The 180nm process can manufacture 5v or 3.3v transistor elements, or can manufacture 1.8v and 5v transistor elements simultaneously, or can manufacture 1.8v and 3.3v transistor elements simultaneously. The 110nm process can manufacture 5v transistor elements, or can manufacture 1.5v and 5v transistor elements simultaneously.

[0036] These processes generally include the following standard steps in sequence: forming a shallow trench isolation region; successively forming a well in which the thick gate oxide transistor and the thin gate oxide transistor are located; forming a thick gate oxide layer; forming a thin gate oxide layer (specifically, covering the thin gate oxide transistor region other than the thin gate oxide transistor region with a mask, and then thinning the formed thick gate oxide layer in the thin gate oxide transistor region not covered by the mask to form a thin gate oxide layer); forming a gate; successively forming lightly doped regions of the thin gate oxide transistor and the thick gate oxide transistor; forming a gate sidewall protection layer; forming heavily doped regions of the thin gate oxide transistor and the thick gate oxide transistor; forming a metal silicide; and forming a rear metal wiring layer.

[0037] If the digital module does not include thin gate oxide peripheral logic transistors, the above steps do not include steps related to thin gate oxide transistors.

[0038] More specifically, when the digital module in the system on chip does not include peripheral logic transistors with thin gate oxide layers, the steps of forming peripheral logic transistors with medium thickness gate oxide layers and memory transistors with medium thickness gate oxide layers in the present invention are as follows:

[0039] In the process of manufacturing the system-on-chip of the present invention, the wells, gates and source-drain regions of the mid-thickness gate oxide peripheral logic transistor and the mid-thickness gate oxide storage transistor are formed in the same step as the formation of the wells, gates and source-drain regions of the thick gate oxide peripheral logic transistor, respectively, except that the mid-thickness gate oxide peripheral logic transistor is of a different type from the mid-thickness gate oxide storage transistor or the thick gate oxide peripheral logic transistor, in which case the type of ions implanted in its well and the type of ions implanted in its source-drain doped region are different from those of the latter.

[0040] The gate oxide layer of the peripheral logic transistor of the intermediate thickness gate oxide layer is the same as the gate oxide layer of the storage transistor of the intermediate thickness gate oxide layer, and is formed in the same step. However, it is different from the gate oxide layer of the peripheral logic transistor of the thick gate oxide layer, and there is a sequence of formation. That is, in the gate oxide layer formation step between the well formation step and the gate formation step, after forming the gate oxide layer of the peripheral logic transistor of the thick gate oxide layer, the area other than the area where the peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer are to be formed is covered with a mask, and then, in the area of ​​the peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer that is not covered with the mask, the formed thick gate oxide layer is thinned until a desired thickness is obtained, to form a new thin intermediate thickness gate oxide layer.

[0041] A specific manner of thinning the thick gate oxide layer formed in the area not covered by the mask and forming a new intermediate thickness gate oxide layer includes irradiating the area not covered by the mask with optical radiation and etching to reach a desired thickness of the new gate oxide layer, completely stripping the formed gate oxide layer, and then thermally oxidizing the area to generate a new gate oxide layer. Alternatively, the specific manner includes irradiating the area not covered by the mask with optical radiation and etching to partially strip the formed gate oxide layer, so that the remaining gate oxide layer reaches a desired thickness of the new gate oxide layer. The first manner is preferred because in the second manner, by partially stripping the gate oxide layer, etching materials are left in the remaining gate oxide layer, which affects the performance of the new gate oxide layer.

[0042] When the digital module of the system-on-chip further includes a peripheral logic transistor with a thin gate oxide layer, in the manufacturing process, the well, gate oxide layer, gate, and source-drain doped regions of the peripheral logic transistor with an intermediate thickness gate oxide layer and the storage transistor with an intermediate thickness gate oxide layer are formed as described above. The gate oxide layer of the peripheral logic transistor with a thin gate oxide layer is formed by forming the gate oxide layers of the peripheral logic transistor with a thick gate oxide layer and the peripheral logic transistor with an intermediate thickness gate oxide layer in the gate oxide layer forming step, covering the regions other than the region where the peripheral logic transistor with a thin gate oxide layer is to be formed with a mask, and then thinning the gate oxide layer formed in the region of the peripheral logic transistor with a thin gate oxide layer that is not covered with the mask to obtain a desired gate oxide layer thickness of the new peripheral logic transistor with a thin gate oxide layer. Then, a gate is formed.

[0043] The specific manner in which the formed gate oxide layer is thinned and a new gate oxide layer is formed in the areas not covered by the mask is as described above.

[0044] The embedded memory cells of the present invention are preferably embedded non-volatile memory cells, and more preferably embedded multiple-times programmable and erasable memory cells or embedded flash memory cells.

[0045] The standard cell in the digital module of the present invention is preferably an inverter, a NAND gate, a NOR gate, a three-state buffer, a latch, a flip-flop, a register, a selector or a full adder.

[0046] The system-on-chip and the manufacturing method thereof, as well as the manufacturing method, structure and performance of the peripheral logic transistor and the memory transistor of the medium-thickness gate oxide layer of the system-on-chip of the present invention will be described in detail below by way of examples.

[0047] A 110 nm logic process is used to manufacture a system on chip, which includes an embedded multiple programmable and erasable memory module and its peripheral digital module. The memory module includes at least one embedded multiple programmable and erasable memory cell, which includes one medium thickness gate oxide memory transistor. The digital module includes at least one thick gate oxide peripheral logic transistor, at least one thin gate oxide peripheral logic transistor, and at least one standard cell. The at least one standard cell is an inverter. The inverter includes two medium thickness gate oxide peripheral logic transistors that are basically the same in structure and components but only opposite in type, namely one NMOS medium thickness gate oxide peripheral logic transistor and one PMOS medium thickness gate oxide peripheral logic transistor.

[0048] The thick gate oxide peripheral logic transistor, the thin gate oxide peripheral logic transistor, the NMOS medium thickness gate oxide peripheral logic transistor in the inverter, and the medium thickness gate oxide memory transistor are all NMOS transistors located in a P well, each having an N-type source and drain, each source and drain including one lightly N-doped region and one heavily N-doped region, and the thicknesses of these gate oxide layers are 139±5 Å, 25±5 Å, 85±5 Å, and 85±5 Å, respectively, and are applicable to 5v, 1.5v, 3.3v, and 3.3v operating voltages, respectively, and may also be referred to as 5v transistor element, 1.5v transistor element, 3.3v transistor element, and 3.3v transistor element. The PMOS intermediate-thickness gate oxide peripheral logic transistor in the inverter is located in an N-well and has a P-type source and drain, each of which contains one lightly P-doped region and one heavily P-doped region. The thickness of its gate oxide layer is the same as that of the NMOS gate oxide layer, which is 85±5 Å.

[0049] In contrast to the thick / thin gate oxide peripheral logic transistors (e.g., 5V / 1.5V transistor elements) commonly used in typical peripheral standard cells, the gate oxide layer thickness of the NMOS and PMOS intermediate-thickness gate oxide peripheral logic transistors in this embodiment is thinner than that of the thick gate oxide peripheral logic transistors, and has a lower threshold voltage, which can be used for an operating voltage of 3.3V lower than 5V, thereby meeting the requirements for low operating voltage; and at the same time, the gate oxide layer thickness is thicker than that of the thin gate oxide peripheral logic transistors, which improves the voltage resistance and can be applied to an operating voltage of 3.3V higher than 1.5V.

[0050] The gate line widths (channel lengths) of the thick gate oxide peripheral logic transistor, the thin gate oxide peripheral logic transistor, the NMOS and PMOS medium thickness gate oxide peripheral logic transistor, and the medium thickness gate oxide storage transistor in this embodiment are 0.6 μm, 0.11 μm, 0.35 μm, and 0.35 μm, respectively. The gate line width of the NMOS medium thickness gate oxide peripheral logic transistor is the same as the gate line width of the PMOS medium thickness gate oxide peripheral logic transistor. The gate line width (channel length) of the medium thickness gate oxide peripheral logic transistor is smaller than the gate line width (channel length) of the thick gate oxide peripheral logic transistor. Compared to the thick gate oxide peripheral logic transistor commonly used in a normal peripheral standard cell, the medium thickness gate oxide peripheral logic transistor of this embodiment can reduce the area size. The medium thickness gate oxide storage transistor can also reduce the area size of the storage cell.

[0051] In addition, in this embodiment, the channel saturation currents of the thick gate oxide peripheral logic transistor, the thin gate oxide peripheral logic transistor, the NMOS and PMOS medium thickness gate oxide peripheral logic transistor, and the medium thickness gate oxide storage transistor are 570 μA / μm, 425 μA / μm, 530 μA / μm, −260 μA / μm, and 530 μA / μm, respectively. The channel saturation current of the medium thickness gate oxide peripheral logic transistor is greater than the channel saturation current of the thin gate oxide peripheral logic transistor. Compared to the thin gate oxide peripheral logic transistor commonly used in a normal peripheral standard cell, the medium thickness gate oxide peripheral logic transistor of this embodiment has a greater driving capability (driving current) under the same operating voltage.

[0052] The system-on-chip of this embodiment is fabricated using a conventional 110 nm logic process platform, and includes the steps of forming shallow trench isolation regions, forming N-wells in which peripheral logic transistors of PMOS medium thickness gate oxide layers are located, forming P-wells in which peripheral logic transistors of thick gate oxide layers, peripheral logic transistors of NMOS medium thickness gate oxide layers, and storage transistors of medium thickness gate oxide layers are located, forming P-wells in which peripheral logic transistors of thin gate oxide layers are located, and forming gate oxide layers (gate oxide layers of peripheral logic transistors of thick gate oxide layers, gate oxide layers of peripheral logic transistors of PMOS and NMOS medium thickness gate oxide layers, and storage transistors of medium thickness gate oxide layers, and gate oxide layers of peripheral logic transistors of thin gate oxide layers). forming a gate sidewall protection layer on the first and second logic transistors (including successively forming the first and second oxide layers on the first and second logic transistors), forming gates of the four above-mentioned transistors, forming lightly doped N-type source / drain regions of the peripheral logic transistors in the thin gate oxide layer, forming lightly doped N-type source / drain regions of the peripheral logic transistors in the thick gate oxide layer, the peripheral logic transistors in the NMOS medium thickness gate oxide layer, and the memory transistor in the medium thickness gate oxide layer, and forming lightly doped P-type source / drain regions of the peripheral logic transistors in the PMOS medium thickness gate oxide layer, forming a gate sidewall protection layer, forming heavily doped source / drain regions of the four above-mentioned transistors, forming a metal silicide, and forming a rear metal wiring layer.

[0053] The intermediate thickness gate oxide peripheral logic transistor and the intermediate thickness gate oxide storage transistor are basically formed together with the thick gate oxide peripheral logic transistor (high voltage transistor). The well, gate, and source / drain of the NMOS intermediate thickness gate oxide peripheral logic transistor and the intermediate thickness gate oxide storage transistor are formed in the same step together with the well, gate, and source / drain of the thick gate oxide peripheral logic transistor. The N well of the PMOS intermediate thickness gate oxide peripheral logic transistor is formed in preference to the P well of the thick gate oxide peripheral logic transistor, and its gate and source / drain are also formed in the same step together with the thick gate oxide peripheral logic transistor.

[0054] However, the formation of the gate oxide layer of the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide storage transistor is different from the formation of the gate oxide layer of the thick-gate oxide peripheral logic transistor. The steps of forming the gate oxide layer of each transistor are specifically as follows:

[0055] Between the well forming step and the gate forming step, in the gate oxide layer forming step, first, a gate oxide layer having a thickness of 139±5 angstroms is formed for the peripheral logic transistor of the thick gate oxide layer. Next, the regions other than the region where the peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer are to be formed are covered with a mask, then, in the region of the peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer that is not covered with the mask, irradiation with light radiation is performed and etching is performed to completely peel off the formed thick gate oxide layer, and then, thermal oxidation is performed on the region to generate a gate oxide layer of the new peripheral logic transistor of the intermediate thickness gate oxide layer and the storage transistor of the intermediate thickness gate oxide layer having a thickness of 85±5 angstroms. Then, the gate oxide layer of the peripheral logic transistor of the thin gate oxide layer is directly formed. That is, the areas of the thin gate oxide layer other than the area where the peripheral logic transistor area is to be formed are covered with a mask, and then the areas of the peripheral logic transistor of the thin gate oxide layer that are not covered with the mask are irradiated with optical radiation and etched to completely peel off the gate oxide layer formed in those areas, and then thermal oxidation is performed on those areas to generate a gate oxide layer of the peripheral logic transistor of a new thin gate oxide layer having a thickness of 25±5 angstroms.

[0056] The present invention uses a simple, efficient and low-cost method to simultaneously fabricate novel higher performance medium-thickness gate oxide peripheral logic transistors and medium-thickness gate oxide memory transistors, which are applied to peripheral digital modules and embedded memory modules of system-on-chip, respectively.

Claims

1. a digital module including at least one first MOS transistor and at least one standard cell; and an embedded memory module including at least one embedded memory cell; a gate oxide layer disposed beneath the gate of the first MOS transistor and an underlying gate oxide layer disposed beneath the gate of the second MOS transistor and an underlying gate oxide layer disposed beneath the gate of the third MOS transistor;

2. 2. The system on a chip of claim 1, wherein the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is at least 10 Angstroms less than the thickness of the first MOS transistor.

3. The system-on-chip of claim 1 , wherein the gate oxide layers of the second MOS transistor and the third MOS transistor are formed in a same step in a same manufacturing process platform.

4. 4. The system on chip of claim 1, wherein the digital module further comprises a fourth MOS transistor including a gate and an underlying gate oxide layer, and the thickness of the gate oxide layer of the second MOS transistor is greater than the thickness of the gate oxide layer of the fourth MOS transistor.

5. 5. The system on a chip of claim 4, wherein the thickness of the gate oxide layer of the second MOS transistor is at least 5 Angstroms thicker than that of the fourth MOS transistor.

6. The system-on-chip according to any one of claims 1 to 3, wherein the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is between 30 and 190 Angstroms.

7. The system-on-chip according to any one of claims 1 to 3, wherein the embedded storage cells are embedded non-volatile storage cells.

8. The system-on-chip of claim 7 , wherein the embedded non-volatile storage cells are embedded multiple-times programmable and erasable storage cells or embedded flash storage cells.

9. 4. The system-on-chip according to claim 1, wherein the standard cell is an inverter, a NAND gate, a NOR gate, a three-state buffer, a latch, a flip-flop, a register, a selector, or a full adder.

10. 2. The method for manufacturing a system on a chip according to claim 1, further comprising the step of: after forming a gate oxide layer of a first MOS transistor, thinning the formed gate oxide layer in areas where a second MOS transistor and a third MOS transistor are to be formed, and simultaneously forming gate oxide layers of the second MOS transistor and a third MOS transistor.