CXL memory device and method for utilizing the same

Abstract

To provide a CXL memory device and a method for utilizing it.SOLUTION: The method includes a step for collecting deterioration factors of a memory device of a CXL memory device, receiving a memory allocation request from a host device connected to the memory device by using a CXL, and performing memory allocation of the memory device for the host device, and at least a portion of the memory allocation request and the memory allocation is performed on the basis of a deterioration state of the memory device by a deterioration factor of the memory device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The following embodiments relate to a CXL memory device and a method using the same. [Background technology]

[0002] CXL (Compute Express Link) is an open standard interface for high-speed communication and can provide a comprehensive interface environment that connects multiple components such as a central processing unit (CPU), memory, accelerators, and other peripheral devices. Through the extensibility of CXL, a pool of components of various systems can be configured. For example, through CXL memory pooling, a memory pool formed through various systems can be provided for any host. In addition, through CXL memory sharing, various hosts may access the same memory address of any system. Through such CXL, a computing environment suitable for technologies that require high computing resources such as artificial intelligence (AI) can be stably and easily configured. Summary of the Invention [Problem to be solved by the invention]

[0003] The objective of the following embodiments is to provide a CXL memory device and a method using the same. [Means for solving the problem]

[0004] According to one embodiment, a Compute Express Link (CXL) memory device includes a memory cell group for storing data, one or more sensors for measuring a deterioration factor of the memory cell group, and a control element for receiving a memory allocation request from a host device connected to the memory device using CXL and performing memory allocation of the memory cell group to the host device based on a deterioration state of the memory cell group due to the deterioration factor of the memory cell group.

[0005] In one embodiment, a host device includes one or more processors that receive wear factors of memory elements of a CXL memory device from a CXL memory device connected to the host device using a Compute Express Link (CXL), estimate a wear state of the memory elements based on the wear factors of the memory elements, determine a memory usage schedule for wear leveling of the memory elements based on the wear state of the memory elements, and make a memory allocation request to the CXL memory device based on the memory usage schedule.

[0006] According to one embodiment, a CXL (Compute Express Link) memory box includes a CXL memory device including a memory cell group for storing data and a sub-control element for controlling the memory cell group, one or more sensors for measuring deterioration factors of the CXL memory device, and a control element for receiving a memory allocation request from a host device connected to the CXL memory box using CXL and allocating memory of the CXL memory device to the host device based on a deterioration state of the CXL memory device due to the deterioration factors of the CXL memory device.

[0007] According to one embodiment, a CXL (Compute Express Link) memory system includes a host device that generates a memory allocation request, a CXL memory box that includes a CXL memory device that stores data and a sub-control element that controls the CXL memory device, and a control element that allocates memory of the CXL memory box to the host device based on a degradation state of the CXL memory box due to a degradation factor of the CXL memory box.

[0008] According to one embodiment, a method for managing memory in a Compute Express Link (CXL) memory device includes collecting degradation factors of memory elements of the CXL memory device, receiving a memory allocation request from a host device connected to the memory device using CXL, and allocating memory of the memory elements to the host device, wherein the memory allocation request and the memory allocation are at least partially based on a degradation state of the memory elements due to the degradation factors of the memory elements. Effect of the Invention

[0009] According to the following embodiment, a 3CXL memory device and a method using the same can be provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram showing a schematic configuration of a host device and a CXL memory device according to an embodiment. [Diagram 2] 1 is a diagram illustrating an example of a wear leveling process taking into account a deterioration factor according to an embodiment; [Diagram 3] 10A and 10B are diagrams illustrating an example of an address management operation and a degradation management operation according to an embodiment. [Figure 4] 1 is a diagram illustrating an example of a static section and a transition section of a memory element according to an embodiment; [Figure 5A] FIG. 2 is an exemplary diagram of a configuration for a CXL memory device according to one embodiment. [Figure 5B]FIG. 2 is an exemplary diagram of a configuration for a CXL memory device according to one embodiment. [Figure 6A] FIG. 1 is an exemplary diagram of a configuration related to a CXL memory box according to an embodiment. [Figure 6B] FIG. 1 is an exemplary diagram of a configuration related to a CXL memory box according to an embodiment. [Figure 6C] FIG. 1 is an exemplary diagram of a configuration related to a CXL memory box according to an embodiment. [Figure 7A] 1 is a diagram illustrating a configuration of a CXL memory system according to an embodiment; [Figure 7B] FIG. 2 is a diagram illustrating a configuration related to wear leveling of a host device according to an embodiment. [Figure 8] 1 is a diagram illustrating an example of a management unit used in work processing and deterioration management according to an embodiment. [Figure 9] 1 is a flowchart illustrating an example of a memory management method based on a deterioration factor in a CXL memory device according to an embodiment. [Figure 10] 1 is a flowchart illustrating a memory management method based on a deterioration factor by a host device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The specific structural or functional description of the embodiments is disclosed for the purpose of illustration only, and may be modified in various forms. Therefore, the embodiments are not limited to the specific disclosed forms, and the scope of the present specification includes modifications, equivalents, or alternatives within the technical spirit.

[0012] Although terms such as first or second may be used to describe multiple components, such terms should be construed only for the purpose of distinguishing one component from the other components. For example, a first component may be named a second component, and similarly, a second component may be named a first component.

[0013] When any component is referred to as being "connected" to another component, it is directly connected or connected to the other component, but it should be understood that there may be other components in between.

[0014] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, the terms "comprise" or "have" and the like indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should be understood as not precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0015] As used herein, phrases such as "at least one of A or B" and "at least one of A, B, or C" may include any one or all possible combinations of the items listed with that phrase.

[0016] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Commonly used predefined terms should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as ideal or overly formal unless expressly defined in this specification.

[0017] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the drawings, the same components are given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

[0018] FIG. 1 is a diagram showing a schematic configuration of a host device and a CXL memory device according to an embodiment. CXL (Compute Express Link) is a connecting technology that supports cache coherency for processors, memory expansion, and accelerators. If a processor and an additional component are connected using CXL, memory coherency is maintained between the memory space of the processor and the memory space of the additional component by the CXL technology, and performance can be improved through resource sharing, the complexity of the software stack can be reduced, and the cost of the entire system can be reduced. Users can focus only on the workload instead of memory management of the accelerator. As the role of accelerators to complement processors increases to support new applications such as artificial intelligence and machine learning, CXL can be provided as an open standard interface for high-speed communication. CXL can provide a comprehensive interface environment that connects multiple components such as a central processing unit (CPU), memory, accelerators, and other peripheral devices. For example, a memory pool formed through various systems for any host may be provided through CXL memory pooling based on the scalability of CXL. Additionally, through CXL memory sharing, various hosts can access the same memory addresses on any system.

[0019] 1, a host device 110 can use a CXL interface to access and use a memory element 122 in a CXL memory device 120. The CXL memory device 120 includes a control element 121 and a memory element 122. The control element 121 provides connectivity between the host device 110 and the CXL memory device 120 and can manage memory usage of the memory element 122. The memory element 122 may store data. The connection between the host device 110 and the CXL memory device 120 and / or the connection between the control element 121 and the memory element 122 uses CXL technology.

[0020] Memory element 122 refers to various levels of memory configurations. For example, memory element 122 corresponds to memory cell groups or memory devices. Memory cell group refers to a group including a plurality of memory cells (e.g., a memory chip). Memory device refers to a device including one or more memory modules. Each memory module may include a plurality of memory groups. A memory device is a device having a larger capacity than a memory cell group. When memory element 122 corresponds to a memory cell group, CXL memory device 120 corresponds to a memory device. When memory element 122 corresponds to a memory device, CXL memory device 120 corresponds to a memory box. A memory box corresponds to a large-capacity memory storage having a larger capacity than a memory device. However, the description of memory cell group, memory module, memory device, and memory box is merely one example, and CXL memory device 120 and memory element 122 may be other levels of memory not illustrated here.

[0021] The memory cell group and the memory device may be composed of dynamic random access memories (DRAM), static random access memories (SRAM), magnetic random access memories (MRAM), PRAM, self-selecting memories using Ovonic Threshold Switching (OTS) materials, etc. However, the configuration of the memory cell group and the memory device is not limited thereto.

[0022] The control element 121 includes various control means such as a controller and a CXL switch (not shown). Here, the CXL switch (not shown) and the CXL switch 130 represent separate devices. The control element 121 includes control means appropriate to the level of the memory element 122. For example, if the memory element 122 corresponds to a memory cell group, the control element 121 includes a memory controller. If the memory element 122 corresponds to a memory device, the control element 121 includes at least one of a server controller (e.g., a BMC (Baseboard Management Controller)) and a CXL switch (not shown).

[0023] The host device 110 and the CXL memory device 120 correspond to devices physically separate from each other. The CXL memory device 120 corresponds to a device independent of the host device 110 that provides storage space to the host device 110. For example, as described in detail below, the CXL memory device 120 may perform at least a part of a degradation management function including degradation data management and / or degradation scheduling, and an address management function including address conversion and address allocation. Although FIG. 1 illustrates an example in which the host device 110 and the CXL memory device 120 are connected one-to-one, multiple host devices and multiple CXL memory devices may be connected. When multiple host devices and multiple CXL memory devices are connected, the CXL memory device 120 can provide storage space to not only the host device 110 but also other host devices other than the host device 110 through memory pooling and / or memory sharing. Furthermore, the host device 110 can use storage space of not only the CXL memory device 120 but also other CXL memory devices through memory pooling and / or memory sharing.

[0024] Any of the memory elements of the memory elements 122 may have different characteristics from the other memory elements. The characteristics include performance, expected life, or a combination thereof. For example, the memory elements 122 include a first memory element and a second memory element. The first memory element and the second memory element may have different characteristics from each other in terms of performance and / or expected life. Such a difference may be caused by a difference in design specifications of the first memory element and the second memory element, or may be caused by an operational difference between the first memory element and the second memory element. For example, the performance of the first memory element may be higher than that of the second memory element because the first memory element is a model designed to exhibit higher performance than the second memory element, or the expected life of the first memory element may be longer than that of the second memory element because the usage period of the second memory element is longer than that of the first memory element.

[0025] If memory elements 122 degrade in different ways, the performance and life expectancy of memory elements 122 will suffer. Wear-leveling can keep the degradation levels of memory elements 122 similar to each other and improve the overall performance and life expectancy of memory elements 122. CXL memory device 120 can wear-level memory elements 122 based on degradation factors (degradation factors 124) to optimize the performance and life expectancy of memory elements 122.

[0026] The control element 121 collects the deterioration factor 124 of the memory element 122 and performs wear leveling of the memory element 122 using the deterioration factor 124. The sensor 123 may be used to collect the deterioration factor 124. The sensor 123 may be arranged on the memory element 122 to have a certain distribution. The deterioration factor 124 may include an operating voltage, an operating temperature, an operating time, an operating count, or a combination thereof of the memory element 122. The sensor 123 may include a detection device capable of measuring the operating voltage, the operating temperature, the operating time, the operating count, or a combination thereof.

[0027] The deterioration factor 124 provides a cause for degrading the performance of the memory element 122 and shortening the expected lifespan. For example, the deterioration factor 124 may include the operating voltage, operating temperature, operating time, operation count, or a combination thereof of the memory element 122. The operation count means the operating clock and / or the number of operations. As the operating voltage and / or operating temperature increase and the operating time increases, the deterioration of the memory element 122 may be accelerated.

[0028] The host device 110 requests memory allocation from the CXL memory device 120. The CXL memory device 120 may perform memory allocation for the host device 110. According to one embodiment, the control element 121 includes a CXL switch (not shown) that provides a CXL environment (e.g., a CXL interface) between the host device 110 and the CXL memory device 120. If necessary, a CXL switch 130 may be disposed in the host device 110 and the CXL memory device 120. The CXL switch 130 is separate from the CXL switch (not shown) of the control element 121. Memory allocation requests and memory allocations may be performed via the CXL switch 130 and / or the CXL switch (not shown) of the control element 121.

[0029] At least a portion of the memory allocation requests of the host device 110 and the memory allocation of the CXL memory device 120 may be based on the deterioration state of the memory elements 122 according to the deterioration factor 124. The deterioration state indicates the degree of deterioration. A deterioration parameter value is determined based on the deterioration factor 124, and the deterioration state may be estimated based on the deterioration parameter value. As part of wear leveling, a memory usage schedule is determined such that the distribution of the deterioration parameter values ​​of the memory elements 122 is uniform. The process of deriving the deterioration parameter value will be described with reference to FIG. 4, etc.

[0030] According to an embodiment, the CXL memory device 120 (e.g., the control element 121) can estimate the deterioration state of the memory element 122 based on the deterioration factor 124, and determine a memory usage schedule for wear leveling of the memory element 122 based on the deterioration state. Memory usage (e.g., memory allocation, data migration) may be performed based on the memory usage schedule. For example, memory allocation is performed in response to a memory allocation request from the host device 110 based on the memory usage schedule. The memory usage schedule may include a usage order regarding which memory space of the memory element 122 is used preferentially when memory usage is required, such as when the host device 110 is performing an operation. For example, when the memory usage schedule schedules the first memory space, the second memory space, and the third memory space of the memory element 122 in that order, the first memory space, the second memory space, and the third memory space may be used sequentially by the operation of the host device 110.

[0031] According to one embodiment, CXL memory device 120 (e.g., control element 121) provides wear factor 124 to host device 110. Host device 110 may estimate a wear state of memory element 122 based on wear factor 124, and determine a memory usage schedule for wear leveling of memory element 122 based on the wear state. Memory usage (e.g., memory allocation, data migration) is performed based on the memory usage schedule. For example, a memory allocation request for memory element 122 may be made based on the memory usage schedule.

[0032] The memory elements 122 may be divided into management groups according to a unit of deterioration management, which may be a page unit, a bank unit, or a rank unit. The control element 121 collects the deterioration factor 124 for each management group. The deterioration management unit may be larger than the work processing unit. The deterioration management unit corresponds to a multiple (e.g., 4 times, 8 times, 16 times, etc.) of the work processing unit. For example, a 64-bit work processing unit may be used for the work processing process (e.g., data load, data processing, data storage, etc.) of the kernel or operating system of the host device 110, and a page unit (e.g., 512 Kb (kilobyte), 1 Mb (megabyte), 2 Mb) may be used for the deterioration management process (e.g., collection of the deterioration factor 124, storage of the deterioration factor 124, estimation of the deterioration state based on the deterioration factor 124, memory allocation based on the deterioration state, data migration based on the deterioration state, etc.).

[0033] 2 is a diagram illustrating an example of a wear leveling process taking into account a deterioration factor according to an embodiment. Referring to FIG. 2, in step 210, a deterioration state of each management group is checked. Memory elements may be divided into management groups according to a deterioration management unit (e.g., a page unit, etc.). For example, a first management group G1 and a second management group G2 are illustrated in FIG. 2. For example, as shown in FIG. 2, a deterioration state check may confirm that the deterioration level of the first management group G1 is higher than that of the second management group G2.

[0034] In step 220, memory allocation is performed based on the deterioration state. A deterioration parameter value is determined based on the deterioration factor, and a deterioration state is estimated based on the deterioration parameter value. Memory allocation is performed so that the distribution of the deterioration parameter value is uniform. Although an example of memory allocation is illustrated in FIG. 2, data migration is performed instead of memory allocation. For wear leveling, memory allocation may be performed based on a second management group G2 that is in a relatively lower deterioration state than the first management group G1, and data D1 may be stored in the memory space of the second management group G2 by memory allocation.

[0035] Wear leveling maintains a wear balance between the first management group G1 and the second management group G2. The description of the management groups G1 and G2 in FIG. 2 may be applied to the entire management group of memory elements of a CXL memory device. Wear leveling of the entire management group maintains a wear balance, and the performance and life expectancy of the memory elements may be optimized.

[0036] 3 is a diagram illustrating an exemplary address management operation and degradation management operation according to an embodiment. Referring to FIG. 3, address management 301 includes address translation 302 and address allocation 303, and degradation management 305 includes degradation data management 306 and degradation scheduling 307.

[0037] The deterioration data management 306 includes operations of collecting data on deterioration factors, estimating a deterioration state from the deterioration factors, and storing / managing data on the deterioration factors and / or the deterioration state. The deterioration scheduling 307 includes operations of determining a memory usage schedule that enables wear leveling. For example, the deterioration scheduling 307 includes operations of determining a deterioration parameter value based on the deterioration factor, and determining a memory usage schedule such that the distribution of the deterioration parameter value is uniform.

[0038] Address translation 302 includes a conversion operation between a virtual memory address used by the host device and a physical memory address of a memory element. The address translation 302 may convert a virtual memory address to a physical memory address or vice versa. Address allocation 303 includes an operation of allocating an address of a memory space in response to a memory allocation request of the host device. Address allocation 303 is performed based on a memory usage schedule for wear leveling.

[0039] As described with reference to Fig. 1, CXL memory device 120 includes control element 121 and memory element 122, and control element 121 includes various control means such as a controller (e.g., a memory controller, a server controller) and a CXL switch (not shown). Also, CXL switch 130 may be disposed between host device 110 and CXL memory device 120. Address management 301 and degradation management 305 shown in Fig. 3 may be performed by control element 121 and / or CXL switch 130.

[0040] For example, both address management 301 and degradation management 305 are performed by either one of the control element 121 and the CXL switch 130. Alternatively, a part of either address management 301 or degradation management 305 is performed by the control element 121, and the remaining part is performed by the CXL switch 130. When the control element 121 includes multiple control elements (e.g., a first control element and a second control element) and at least a part of the address management 301 and degradation management 305 is performed by the control element 121, a part of the at least a part is performed by one of the multiple control elements (e.g., the first control element), and the remaining part of the at least a part is performed by the remaining part (e.g., the second control element).

[0041] 4 is a diagram illustrating an example of a static section and a transition section of a memory element according to an embodiment. As mentioned above, a deterioration parameter value is determined based on a deterioration factor of a memory element (e.g., a management group of memory elements), and a deterioration state of the memory element (e.g., a management group of memory elements) is estimated based on the deterioration parameter value. As part of wear leveling, a memory usage schedule can be determined such that the distribution of the deterioration parameter value of the memory element (e.g., a management group of memory elements) is uniform.

[0042] According to one embodiment, the degradation parameter value may be determined based on bias temperature instability (BTI), hot carrier injection (HCI), or a combination thereof, of the memory elements (e.g., memory elements of a managed group). BTI and HCI indicate stress on the semiconductor element.

[0043] BTI refers to the degradation of semiconductor devices due to electrical stress and high temperature environment. Electrical stress and high temperature environment may cause changes in the charge transfer path inside the semiconductor device, changing the electrical characteristics of the semiconductor device. BTI includes NBTI (Negative Bias Temperature Instability) and PBTI (Positive Bias Temperature Instability). NBTI refers to the degradation of pMOSFET (Positive Metal-Oxide-Semiconductor Field-Effect Transistor), which is a semiconductor device that turns on when a negative bias is applied to the gate of the semiconductor device, and PBTI refers to the degradation of nMOSFET (Negative MOSFET), which is a semiconductor device that turns on when a positive bias is applied to the gate. In the case of NBTI, holes formed in the PMOS channel are trapped in the gate oxide film, causing an increase in the threshold voltage, and in the case of PBTI, electrons formed in the NMOS channel are trapped in the gate oxide film, causing an increase in the threshold voltage. BTI may affect the performance of semiconductor devices by shortening their lifespan.

[0044] HCI is a phenomenon that occurs when carriers move to a high energy state due to electrical stress and high temperature environments. HCI occurs when carriers are accelerated by a stronger electric field as the dimensions of semiconductor devices become smaller. HCI can occur when high energy carriers collide with each other on the charge transfer path, causing defects in the semiconductor device and changing the electrical characteristics of the semiconductor device. EHPs (electron-hole pairs) generated when hot carriers accelerated by a strong electric field collide between the drain and source of a semiconductor device can be trapped in the gate oxide film, or the hot carriers can be directly trapped in the gate oxide film, increasing the threshold voltage. HCI can shorten the lifespan of semiconductor devices and affect their performance.

[0045] The operation of a memory element (e.g., a memory cell of a memory element) includes a static operation in a saturation status and a transition operation in a non-saturation status. The graph shown in FIG. 4 shows the input voltage V in and the output voltage V out 4, a static section 401 corresponds to the static operation of the memory element, and a transition section 402 corresponds to the transition operation of the memory element.

[0046] According to one embodiment, an degradation parameter value is determined using BTI in a static period 401 where the memory element is saturated, and the degradation parameter value is determined using HCI in a transition period 402 where the memory element is non-saturated. Equation (1) below shows the degradation parameter using BTI, and Equation (2) below shows the degradation parameter using HCI.

[0047]

number

[0048] In formula (1), ~ΔV th indicates a change in threshold voltage of a memory element due to BTI, V indicates an operating voltage of the memory element, T indicates an operating temperature of the memory element, and t indicates an operating time and / or an operating count of the memory element. V, T, and t correspond to deterioration factors. A change in threshold voltage due to BTI may be estimated based on the deterioration factor, and the change in threshold voltage may be used as a deterioration parameter value. For example, in the static section 401, a memory usage schedule may be determined such that deterioration parameter values ​​corresponding to changes in threshold voltage values ​​of memory elements become uniform. For example, a memory usage schedule may be determined such that memory usage of a memory space where a large change in threshold voltage is indicated decreases and memory usage of a memory space where a small change in threshold voltage is indicated increases.

number

[0049] In formula (2), ~ΔI on indicates a current change in a turn-on state of a memory element due to HCI, V indicates an operating voltage of the memory element, T indicates an operating temperature of the memory element, and t indicates an operating time and / or an operating count of the memory element. V, T, and t correspond to deterioration factors. A change in current in a turn-on state due to HCI may be estimated based on the deterioration factor, and the change in current may be used as a deterioration parameter value. For example, in the transition section 402, a memory usage schedule is determined such that deterioration parameter values ​​corresponding to changes in current change values ​​of the memory elements become uniform. For example, a memory usage schedule may be determined such that memory usage in a memory space where a large change in current is indicated decreases, and memory usage in a memory space where a small change in current is indicated increases.

[0050] 5A and 5B are diagrams illustrating a configuration of a CXL memory device according to an embodiment. Referring to FIG. 5A, a CXL memory device 520 includes a memory cell group 522 for storing data, a sensor 523 for measuring a deterioration factor of the memory cell group, and a control element 521 for receiving a memory allocation request from a host device connected to the memory device using CXL and allocating memory of the memory cell group to the host device based on a deterioration state of the memory cell group due to the deterioration factor of the memory cell group. According to an embodiment, the control element 521 corresponds to a memory controller.

[0051] The control element 521 performs address management and wear management, which can achieve wear leveling of the memory cell group 522. CXL may be used for the connection between the host device 510 and the CXL memory device 520, and for the connection between the control element 521 and the memory cell group 522.

[0052] The control element 521 performs degradation data management and degradation scheduling for degradation management. The control element 521 collects degradation factors of the memory cell group 522. According to an embodiment, the control element 521 may perform degradation management using a fabric manager. The fabric manager is an application logic responsible for system configuration and resource allocation. The fabric manager may play a role in understanding and managing the topology of components connected using CXL. The control element 521 collects degradation factors using a sensor 523. The sensor 523 generates sensor data regarding the memory cell group 522. A degradation factor is determined based on the sensor data. FIG. 5A illustrates an example in which the sensor 523 is arranged one-to-one with the memory cell group 522, but the number of the memory cell group 522 and the sensor 523 may be different. For example, one sensor may be arranged for multiple memory cell groups, or multiple sensors may be arranged for one memory cell group. In order to improve the accuracy of estimating a degradation factor for a degradation state of the memory cell group 522, processing of the sensor data may be performed.

[0053] The CXL memory device 520 may further include a management memory (not shown) for storing the deterioration factors. The control element 521 manages the history of the deterioration factors using the management memory (not shown). The management memory (not shown) corresponds to a non-volatile memory. In this case, the history of the deterioration factors is stably managed regardless of the power supply of the CXL memory device 520. However, the memory type of the management memory (not shown) is not limited thereto. The history of the deterioration factors contributes to improving the estimation accuracy of the deterioration state. The deterioration state estimated using the history of the deterioration factors accumulated over a long period of time can more accurately reflect the actual deterioration state of the memory cell group 522 compared to the deterioration state estimated using the deterioration factors at one time point. The higher the estimation accuracy of the deterioration state, the better the effect of wear leveling.

[0054] The control element 521 can estimate the deterioration state based on the deterioration factor, and determine a memory usage schedule based on the deterioration state. The memory usage schedule includes an allocation schedule and a migration schedule. The control element 521 can determine the memory usage schedule so that the deterioration states of the memory cell groups 522 (e.g., the management group of the memory cell groups 522) are uniform.

[0055] The control element 521 receives memory allocation requests from the host device 510 and performs memory allocation of the memory device 513 for the host device 510. The control element 521 may perform address translation and address allocation for address management.

[0056] The CXL memory device 520 and the host device 510 may use other address systems. The memory space of the memory cell group 522 may be assigned physical memory addresses. The physical memory addresses correspond to actual addresses. The CXL memory device 520 may use physical memory addresses. The host device 510 may use virtual memory addresses. The memory allocation request of the host device 510 includes a virtual memory address. When there is a memory allocation request of the host device 510, the address converter 5111 can map an appropriate physical memory address to the virtual memory address of the memory allocation request.

[0057] The control element 521 maps the physical memory address to the virtual memory address based on the memory usage schedule for wear leveling. The address converter 5111 may sequentially map the physical memory address according to the memory usage schedule to the memory allocation request of the host device 510. The address converter 5111 may select a physical memory address from the memory addresses of the memory cell group 522 based on the memory usage schedule, and map the selected physical memory address to the virtual memory address according to the memory allocation request of the host device 510 to determine address conversion information. The address conversion information between the virtual memory address and the physical memory address may be managed in an address conversion table.

[0058] The control element 521 may perform memory allocation by referring to the address conversion information and may perform deallocation of the allocated physical memory address. The control element 521 may map a physical memory address to a virtual memory address by referring to a memory usage schedule and perform memory allocation according to the corresponding physical memory address. If the same data remains in the same memory space and causes deterioration of the corresponding memory space, the corresponding data stored in the memory space of the memory cell group 522 in a high deterioration state may be migrated to the memory space of the memory cell group 522 in a low deterioration state based on the memory usage schedule. Whether or not to perform data migration may be determined by the control element 521. If a physical memory address of the memory space requiring data migration is identified, a new physical memory address for the data of the corresponding physical memory address is selected by referring to the memory usage schedule. Data of the previous physical memory address may be migrated to the memory space of the new physical memory address.

[0059] 5B, the CXL memory device 540 includes a control element 541, a memory cell group 542, and a sensor 543. Unlike FIG. 5A, in FIG. 5B, a CXL switch 530 may be disposed between the host device 510 and the CXL memory device 540. In this case, both address management and degradation management are performed by one of the control element 541 and the CXL switch 530. Alternatively, the control element 541 performs part of the address management and degradation management, and the CXL switch 530 performs the remaining part. For example, the control element 541 performs degradation management, and the CXL switch 530 performs address management. As a different example, the control element 541 performs degradation data management, which is a part of the degradation management, and the CXL switch 530 performs address management and degradation scheduling, which is the remaining part of the degradation management. In addition, the description of the CXL memory device 520 may be applied to the CXL memory device 540.

[0060] 6A, 6B, and 6C are diagrams illustrating an example of a configuration of a CXL memory box according to an embodiment. Referring to FIG. 6A, a CXL memory box 630 includes a CXL memory device 632 including a memory cell group for storing data and a sub-control element for controlling the memory cell group (e.g., control element 521 in FIG. 5A, control element 541 in FIG. 5B), a sensor 633 for measuring a deterioration factor of the CXL memory device 632, and a control element 631 for receiving a memory allocation request from a host device 610 connected to the CXL memory box 630 using CXL, and allocating memory of the CXL memory device 632 to the host device 610 based on the deterioration state of the CXL memory device 632 according to the deterioration factor of the CXL memory device 632. According to an embodiment, the control element 631 corresponds to a server controller (e.g., BMC) or a CXL switch. Each CXL memory device of the CXL memory device 632 corresponds to the CXL memory device 520 in FIG. 5A and the CXL memory device 540 in FIG. 5B.

[0061] The control element 631 performs address management and wear management, which achieves wear leveling of the CXL memory device 632. CXL is used for the connection between the host device 610 and the CXL memory box 630, and for the connection between the control element 631 and the CXL memory device 632.

[0062] The control element 631 collects deterioration factors of the CXL memory device 632. According to an embodiment, the control element 631 may perform deterioration management using a fabric manager. The control element 631 may collect deterioration factors using a sensor 633. The CXL memory box 630 may further include a management memory (not shown) that stores the deterioration factors. The control element 631 may manage the history of the deterioration factors using the management memory (not shown). The management memory (not shown) corresponds to a non-volatile memory.

[0063] The control element 631 estimates a deterioration state of the CXL memory device 632 based on the deterioration factor of the CXL memory device 632, and determines a memory usage schedule for wear leveling of the CXL memory device 632 based on the deterioration state of the CXL memory device 632. The control element 631 can determine the memory usage schedule such that the distribution of the deterioration parameter values ​​indicating the deterioration state of the CXL memory device 632 becomes uniform. The control element 631 can select a physical memory address from the memory addresses of the CXL memory device 632 based on the memory usage schedule, and determine address conversion information by mapping the physical memory address to a virtual memory address according to a memory allocation request of the host device 610.

[0064] 6B, a CXL memory box 640 includes a first control element 641, a second control element 642, a CXL memory device 643, and a sensor 644. Unlike the CXL memory box 630 of FIG. 6A, the CXL memory box 640 of FIG. 6B includes multiple control elements, a first control element 641 and a second control element 642. According to one embodiment, the first control element 641 corresponds to a CXL switch, and the second control element 642 corresponds to a server controller (e.g., a BMC).

[0065] Both address management and degradation management are performed by one of the first control element 641 and the second control element 642. Alternatively, some of the address management and degradation management are performed by the first control element 641, and the remaining part is performed by the second control element 642. For example, degradation management is performed by the second control element 642, and address management is performed by the first control element 641. As a different example, degradation data management, which is a part of degradation management, is performed by the second control element 642, and degradation scheduling, which is the remaining part of degradation management, as well as address management, is performed by the first control element 641. In addition, the description of the CXL memory box 630 shown in FIG. 6A may be applied to the CXL memory box 640.

[0066] Referring to FIG. 6C, a CXL memory box 650 includes a first control element 651, a CXL memory device 652, and a sensor 653. Unlike FIG. 6A and FIG. 6B, in FIG. 6C, a CXL switch 660 may be disposed between the host device 610 and the CXL memory box 650. In this case, both address management and degradation management are performed by one of the control element 651 and the CXL switch 660. Alternatively, the control element 651 performs a part of the address management and degradation management, and the CXL switch 660 performs the remaining part. For example, the control element 651 performs degradation management, and the CXL switch 660 performs address management. As a different example, the control element 651 performs degradation data management, which is a part of the degradation management, and the CXL switch 660 performs address management and degradation scheduling, which is the remaining part of the degradation management. In addition, the description of the CXL memory box 630 may be applied to the CXL memory box 650.

[0067] Referring to FIG. 7A, the CXL memory system 700 includes a host device 710 that generates a memory allocation request, a CXL memory device that stores data, and a CXL memory box 730 that includes sub-control elements (e.g., control element 631 in FIG. 6A, first control element 641, second control element 642 in FIG. 6B, control element 651 in FIG. 6C) that control the CXL memory device, and a control element 720 that performs memory allocation of the CXL memory box 730 to the host device 710 based on the deterioration state of the CXL memory box 730 due to the deterioration factor of the CXL memory box 730. The CXL memory device includes a memory cell group that stores data and a sub-control element that controls the memory cell group (e.g., control element 521 in FIG. 5A, control element 541 in FIG. 5B). According to one embodiment, the control element 720 corresponds to a server controller (e.g., BMC) or a CXL switch. Each memory box of CXL memory box 730 corresponds to CXL memory box 630 of FIG. 6A, CXL memory box 640 of FIG. 6B, and CXL memory box 650 of FIG. 6C.

[0068] The control element 720 performs address management and deterioration management. Wear leveling of the CXL memory box 730 is achieved by the address management and deterioration management. CXL may be used for the connection between the host device 710 and the control element 720 and the connection between the control element 720 and the CXL memory box 730. The control element 720 collects deterioration factors of the CXL memory box 730. According to an embodiment, the control element 720 may perform deterioration management using a fabric manager. The control element 720 can collect the deterioration factors using sensors of the CXL memory box 730. The control element 720 may include a management memory (not shown) that stores the deterioration factors. The control element 720 manages the history of the deterioration factors using the management memory (not shown). The management memory (not shown) corresponds to a non-volatile memory.

[0069] The control element 720 estimates a deterioration state of the CXL memory box 730 based on the deterioration factor of the CXL memory box 730, and determines a memory usage schedule for wear leveling of the CXL memory box 730 based on the deterioration state of the CXL memory box 730. The control element 720 may determine the memory usage schedule such that the distribution of the deterioration parameter values ​​indicating the deterioration state of the CXL memory box 730 is uniform. The control element 720 may select a physical memory address from the memory addresses of the CXL memory box 730 based on the memory usage schedule, and map the physical memory address to a virtual memory address according to a memory allocation request of the host device to determine address conversion information.

[0070] 7B, a host device 750 can use a CXL interface to access and use a memory element 772 in a CXL memory device 770. The CXL memory device 770 includes a control element 771 and a memory element 772. The control element 771 provides connectivity between the host device 750 and the CXL memory device 770 and can manage memory usage of the memory element 772. The memory element 772 stores data. CXL technology may be used for the connection between the host device 750 and the CXL memory device 770 and / or the connection between the control element 771 and the memory element 772.

[0071] The host device 750 includes one or more processors 751. The host device 750 can execute a kernel or an operating system using the one or more processors 751. The one or more processors 751 may perform at least a portion of address management and deterioration management for memory usage associated with the execution of the kernel or operating system. The one or more processors 751 can receive deterioration factors of memory elements 772 of a CXL memory device 770 from a CXL memory device 770 connected to the host device 750 using CXL, estimate a deterioration state of the memory element 772 based on the deterioration factor of the memory element 772, determine a memory usage schedule for wear leveling of the memory element 772 based on the deterioration state of the memory element 772, and make a memory allocation request to the CXL memory device 770 based on the memory usage schedule.

[0072] The control element 771 provides the wear factor to the host device 750 (e.g., one or more processors 751, a kernel, an operating system). The host device 750 may estimate a wear state of the memory element 772 based on the wear factor, and determine a memory usage schedule for wear leveling of the memory element 772 based on the wear state. Memory usage (e.g., memory allocation, data migration) is performed based on the memory usage schedule.

[0073] Optionally, a CXL switch 760 may be disposed between the host device 750 and the CXL memory device 770. Address management and wear management are performed by one or more of the processor 751, the CXL switch 760, and the control element 771. Wear leveling of the memory element 772 may be achieved by the address management and wear management.

[0074] According to an embodiment, the control element 771 may perform deterioration data management of the deterioration management. The control element 771 may collect deterioration factors of the memory element 772. The control element 771 may collect deterioration factors using a sensor 773. The deterioration factor may be determined based on sensor data of the sensor 773. The CXL memory device 770 may further include a management memory (not shown), and the control element 771 may manage data of the deterioration factors using the management memory (not shown). The control element 771 may provide the host device 750 with deterioration factors corresponding to the deterioration information.

[0075] The one or more processors 751 may perform deterioration scheduling based on the deterioration factor. The one or more processors 751 may estimate a deterioration state of the memory element 772 based on the deterioration factor, and determine a memory usage schedule for wear leveling of the memory element 772 based on the deterioration state. The memory usage schedule includes an allocation schedule and a migration schedule. The one or more processors 751 may determine the memory usage schedule such that the deterioration states of the memory elements 772 (e.g., a management group of memory elements 772) are equalized. The one or more processors 751 may generate a memory allocation request and / or a data migration request based on the memory usage schedule, and the memory allocation and / or data migration are performed via the switch 760 or the control element 771.

[0076] According to one embodiment, a degradation query application program interface (API) may be provided to the host device 750. One or more processors 751 may use the degradation query API to request degradation information from the control element 771. The control element 771 may provide the degradation information to the host device 750 using the degradation query API.

[0077] FIG. 8 is an exemplary diagram of a management unit used for work processing and deterioration management according to an embodiment. As described above, a memory device is divided into management groups according to a deterioration management unit such as one of a page unit, a bank unit, and a rank unit, and memory management based on a deterioration factor can be performed for each management group. Referring to FIG. 8, the management groups 811 are distributed across various memory regions (e.g., memory cell groups). For example, each memory region can use a K1-bit bandwidth, and each memory module 810 can use a K2-bit bandwidth. In the example of FIG. 8, K2=K1×8 holds. For example, K1=8 and K2=64 may be used. 64-bit corresponds to a work processing unit. For example, when the management group 811 uses a page-based deterioration management unit of 512 Kb, the management group 811 is formed across 8 memory modules. However, the numerical values ​​mentioned here correspond to one example, and various different numerical values ​​may be used.

[0078] Deterioration management and wear leveling are performed based on the management groups thus formed across the multiple memory modules. Referring to Fig. 8, the control element 820 of the CXL memory device can collect deterioration factors for each of the multiple management groups. The control element 820 of the CXL memory device or the host device 830 estimates the deterioration state of each of the multiple management groups based on the deterioration factors. The control element 820 or the host device 830 can generate a memory usage schedule for wear leveling based on the deterioration state of each of the multiple management groups.

[0079] 9 is a flow chart illustrating an example of a memory management method based on a deterioration factor by a CXL memory device according to an embodiment. Referring to FIG. 9, the CXL memory device collects deterioration factors of a memory device of the CXL memory device in step 910, receives a memory allocation request from a host device connected to the memory device using CXL in step 920, and allocates memory of the memory device to the host device in step 930. At least a part of the memory allocation request and memory allocation is based on a deterioration state of the memory device due to the deterioration factors of the memory device.

[0080] The CXL memory device estimates a deterioration state of the memory device based on a deterioration factor of the memory device, and determines a memory usage schedule for wear leveling of the memory device based on the deterioration state of the memory device. Memory allocation is performed based on the memory usage schedule.

[0081] When determining a memory usage schedule, the CXL memory device can determine the memory usage schedule such that a distribution of a deterioration parameter value indicating a deterioration state of the memory device is uniform. The deterioration parameter value may be determined based on a BTI, an HCI, or a combination thereof of the memory device. The operation of the memory device includes a static operation in a saturated state and a variable operation in a non-saturated state. The deterioration parameter value is determined using the BTI when the memory device is in a saturated state, and the deterioration parameter value is determined using the HCI when the memory device is in a non-saturated state.

[0082] When the CXL memory device performs memory allocation in step 930, it can select a device memory address from the memory addresses of the memory device based on the memory usage schedule, and map the device memory address to a virtual memory address according to the memory allocation request of the host device to determine address conversion information.

[0083] The CXL memory device migrates data stored in a memory space in a high degradation state of the memory device to a memory space in a low degradation state of the memory device based on a memory usage schedule.

[0084] The CXL memory device may provide a wear factor of the memory device to the host device, and memory allocation requests may be made based on a wear state of the memory device estimated by the host device using the wear factor of the memory device.

[0085] The degradation factors include the operating voltage, operating temperature, operating time, operation count, or a combination thereof of the memory device.

[0086] A first memory device of the memory device may have different characteristics than a second memory device of the memory device, which may include performance, life expectancy, or a combination thereof.

[0087] The memory device may be divided into management groups by deterioration management units, which may be any one of a page unit, a bank unit, and a rank unit. For each management group, a deterioration factor may be collected and a deterioration state may be estimated.

[0088] Additionally, the explanations of FIGS. 1 to 8 and 10 may be applied to the memory management method of FIG.

[0089] 10 is a flow chart illustrating an example of a memory management method based on a wear factor by a host device according to an embodiment. Referring to FIG. 10, the host device receives a wear factor of a memory device of a CXL memory device from a CXL memory device connected to the host device via CXL in step 1010, estimates a wear state of the memory device based on the wear factor of the memory device in step 1020, determines a memory usage schedule for wear leveling of the memory device based on the wear state of the memory device in step 1030, and makes a memory allocation request to the CXL memory device based on the memory usage schedule in step 1040.

[0090] When the host device determines the memory usage schedule in step 1030, the host device determines the memory usage schedule so that the distribution of the deterioration parameter values ​​indicating the deterioration state of the memory device becomes uniform.

[0091] The degradation parameter value may be determined based on the BTI, HCI, or a combination thereof of the memory device. The operation of the memory device includes static operation in a saturated state and transient operation in a non-saturated state. The degradation parameter value may be determined using the BTI when the memory device is in a saturated state, and the degradation parameter value may be determined using the HCI when the memory device is in a non-saturated state.

[0092] Additionally, the description of FIGS. 1 to 9 may be applied to the memory management method of FIG.

[0093] The embodiments described above may be implemented using hardware components, software components, or a combination of hardware and software components. For example, the devices and components described herein may be implemented using one or more general-purpose or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or other devices that execute and respond to instructions. The processing device executes an operating system (OS) and one or more software applications that run on the operating system. The processing device also accesses, stores, manipulates, processes, and generates data in response to the execution of the software. For ease of understanding, the processing device may be described as being one in which only one processing device is used, but one skilled in the art will appreciate that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0094] The software may include computer programs, codes, instructions, or any combination of one or more thereof, capable of configuring or instructing a processing device to operate as desired, either independently or in combination. The software and / or data may be embodied in any type of machine, component, physical device, virtual device, computer storage medium or device, or transmitted signal wave, either permanently or temporarily, to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed across computer systems coupled to a network, and may be stored and executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

[0095] The method according to the present invention may be embodied in the form of program instructions to be executed by various computer means and recorded on a computer-readable recording medium. The recording medium may include program instructions, data files, data structures, and the like, alone or in combination, and the recording medium and program instructions may be specially designed and constructed for the purposes of the present invention, or may be known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, flash memories, and the like. Examples of program instructions include not only machine language code, such as that generated by a compiler, but also high-level language code executed by a computer using an interpreter, etc.

[0096] The hardware devices described above may be configured to operate as one or more software modules to perform the operations illustrated in the present invention, and vice versa.

[0097] Although the embodiments have been described above with reference to limited drawings, those skilled in the art may apply various technical modifications and variations based on the above description. For example, the described techniques may be performed in a different order than described, and / or the components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than described, and may be replaced or substituted with other components or equivalents to achieve appropriate results.

[0098] Accordingly, other implementations, embodiments, and equivalents of the claims are intended to be within the scope of the following claims.

Claims

1. A Compute Express Link (CXL) memory device, comprising: A group of memory cells for storing data; one or more sensors for measuring a degradation factor of the memory cell group; a control element that receives a memory allocation request from a host device connected to the memory device using a CXL and performs memory allocation of the memory cell group to the host device based on a deterioration state of the memory cell group due to the deterioration factor of the memory cell group; A CXL memory device comprising:

2. The CXL memory device of claim 1 , wherein the control element estimates the deterioration state of the memory cell group based on the deterioration factor of the memory cell group to perform the memory allocation, and determines a memory usage schedule for wear leveling of the memory cell group based on the deterioration state of the memory cell group.

3. The CXL memory device of claim 2 , wherein the control element determines the memory usage schedule such that a distribution of deterioration parameter values ​​indicating the deterioration state of the memory cell group is uniform.

4. 4. The CXL memory device of claim 3, wherein the control element determines the degradation parameter value based on bias temperature instability (BTI), hot carrier injection (HCI), or a combination thereof of the memory cell group.

5. The operation of the memory cell group includes a static operation in a saturated state and a transition operation in a non-saturated state, 5. The CXL memory device of claim 4, wherein the control element determines the degradation parameter value using the BTI when the memory cell group is in a saturated state and determines the degradation parameter value using the HCI when the memory cell group is in a non-saturated state.

6. The control element, in order to perform the memory allocation, 3. The CXL memory device of claim 2, further comprising: a memory address conversion unit for converting a physical memory address from the memory addresses of the memory cell group based on the memory usage schedule; and a memory address conversion unit for converting the physical memory address to a virtual memory address based on the memory allocation request of the host device.

7. 3. The CXL memory device of claim 2, wherein the control element migrates data stored in a memory space of a high deterioration state of the memory cell group to a memory space of a low deterioration state of the memory cell group based on the memory usage schedule.

8. The CXL memory device of claim 1 , wherein the degradation factors include an operating voltage, an operating temperature, an operating time, an operating count, or a combination thereof, of the group of memory cells.

9. a first group of memory cells of the memory cell group having different characteristics than a second group of memory cells of the memory cell group; The CXL memory device of claim 1 , wherein the characteristics include performance, life expectancy, or a combination thereof.

10. The memory cell group is divided into management groups by any one of deterioration management units, which are a page unit, a bank unit, and a rank unit; The CXL memory device according to claim 1 , wherein the deterioration factors are collected and the deterioration state is estimated for each of the management groups.

11. 10. A CXL memory system comprising the CXL memory device of claim 1 and said host device.

12. A host device, receiving a deterioration factor of a memory element of the CXL memory device from a CXL memory device connected to the host device using a CXL (Compute Express Link); estimating a degradation state of the memory element based on the degradation factor of the memory element; determining a memory usage schedule for wear leveling of the memory element based on the deterioration state of the memory element; one or more processors that make memory allocation requests to the CXL memory device based on the memory usage schedule; A host device comprising:

13. The host device according to claim 12 , wherein the one or more processors determine the memory usage schedule to perform the memory allocation such that a distribution of deterioration parameter values ​​indicating the deterioration states of the memory elements is uniform.

14. The degradation parameter value is determined based on bias temperature instability (BTI), hot carrier injection (HCI), or a combination thereof of the memory element; The operation of the memory element includes a saturated static operation and a non-saturated transient operation, 14. The host device of claim 13, wherein the one or more processors determine the degradation parameter value using the BTI when the memory element is in a saturated state and determine the degradation parameter value using the HCI when the memory element is in a non-saturated state.

15. A CXL (Compute Express Link) memory box, a CXL memory device including a memory cell group for storing data and a sub-control element for controlling the memory cell group; one or more sensors for measuring degradation factors of the CXL memory device; a control element that receives a memory allocation request from a host device connected to the CXL memory box using a CXL, and allocates memory of the CXL memory device to the host device based on a degradation state of the CXL memory device due to the degradation factor of the CXL memory device; A CXL memory box including:

16. The CXL memory box of claim 15, wherein the control element estimates the deterioration state of the CXL memory device based on the deterioration factor of the CXL memory device to perform the memory allocation, and determines a memory usage schedule for wear leveling of the CXL memory device based on the deterioration state of the CXL memory device.

17. 17. The CXL memory box of claim 16, wherein the control element determines the memory usage schedule such that a distribution of degradation parameter values ​​indicating the degradation state of the CXL memory device is uniform.

18. 17. The CXL memory box of claim 16, wherein the control element, to perform the memory allocation, selects a physical memory address from the memory addresses of the CXL memory device based on the memory usage schedule, and determines address conversion information by mapping the physical memory address to a virtual memory address according to the memory allocation request of the host device.

19. 16. The CXL memory box of claim 15, comprising said memory device and said host device.

20. A Compute Express Link (CXL) memory system, comprising: a host device generating a memory allocation request; a CXL memory box including a CXL memory device for storing data and a sub-control element for controlling the CXL memory device; a control element that performs memory allocation of the CXL memory box to the host device based on a deterioration state of the CXL memory box due to a deterioration factor of the CXL memory box; A CXL memory system comprising:

21. 21. The CXL memory system of claim 20, wherein the CXL memory device includes memory cell groups for storing data and sub-control elements for controlling the memory cell groups.

22. The CXL memory system of claim 20, wherein the control element estimates the deterioration state of the CXL memory box based on the deterioration factor of the CXL memory box to perform the memory allocation, and determines a memory usage schedule for wear leveling of the CXL memory box based on the deterioration state of the CXL memory box.

23. 23. The CXL memory system of claim 22, wherein the control element determines the memory usage schedule such that a distribution of deterioration parameter values ​​indicating the deterioration state of the CXL memory box is uniform.

24. 23. The CXL memory system of claim 22, wherein the control element, to perform the memory allocation, selects a physical memory address from the memory addresses of the CXL memory box based on the memory usage schedule, and determines address conversion information by mapping the physical memory address to a virtual memory address according to the memory allocation request of the host device.

25. A memory management method for a CXL (Compute Express Link) memory device, comprising: collecting degradation factors of memory elements of the CXL memory device; receiving a memory allocation request from a host device connected to the memory device using CXL; performing a memory allocation of the memory element for the host device; Including, 11. A method of managing memory, comprising: at least a portion of the memory allocation request and the memory allocation being based on a deterioration state of the memory element according to the deterioration factor of the memory element.

26. The step of allocating memory includes: estimating the degradation state of the memory element based on the degradation factor of the memory element; determining a memory usage schedule for wear leveling of the memory element based on the degradation state of the memory element; 26. The memory management method of claim 25, wherein the memory allocation is based on the memory usage schedule.

27. 27. The memory management method according to claim 26, wherein the step of determining the memory usage schedule includes the step of determining the memory usage schedule such that a distribution of the deterioration parameter values ​​indicating the deterioration states of the memory elements is uniform.

28. The step of allocating memory includes: selecting a physical memory address from the memory addresses of the memory elements based on the memory usage schedule; determining address translation information by mapping the physical memory addresses to virtual memory addresses according to the memory allocation request of the host device; 27. The memory management method of claim 26, comprising:

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