Power electronics device having improved electric performance

Abstract

To reduce a snappy behavior caused by sudden reconnection of a minority charge carrier in a boundary surface between a drift layer and a drain layer.SOLUTION: An electronics device 10 contains: a semiconductor main body 15 of SiC that includes an upper surface 15a and a lower surface 15b that face each other along a first shaft (Z), and the semiconductor main body contains: a drain substrate 16 that extends into the semiconductor main body starting from a bottom surface, and has a first conductive type; a drift layer 17 that extends into the semiconductor main body starting from the upper surface 15a, and has a first conductive type and a second dopant concentration; a main body region 19 that is housed in the drift layer; a source region 20 that is housed in the main body region; and a gate structure 23 on the upper surface. The semiconductor main body is embedded into the drift layer, includes a second conductive type, and further comprises at least one dope pocket region 25 that is aligned with the source region and / or the gate structure along the first shaft.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to power electronic devices having improved electrical performance. In particular, the present disclosure relates to silicon carbide electronic devices including one or more power MOSFETs having improved electrical operation and reliability. Additionally, the present disclosure relates to apparatus including the power electronic devices. [Background technology]

[0002] 2. Description of Related Art As known, power devices are electronic devices for operating at high voltages and / or currents, for example voltages up to 1700V in inhibited state, and currents up to tens / hundreds of amperes, and are used in several application fields. For example, they are commonly used in audio amplifiers, motor control devices, power supplies or power switches, and include power diodes, power transistors, thyristors, Insulated Gate Bipolar Transistors (IGBT), Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET).

[0003] In power devices, a wide bandgap (e.g., having a bandgap energy value E greater than 1.1 eV), low on-state resistance (R ON Semiconductor materials having high thermal conductivity, high operating frequencies, and high saturation velocities of charge carriers are commonly used. A material that has these properties and is designed to be used in the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is preferred over silicon with respect to the properties listed above.

[0004] Electronic devices formed starting from silicon carbide substrates have many advantages over similar devices built on silicon substrates, such as lower output resistance during conduction, lower leakage current, higher operating temperatures and higher operating frequencies.

[0005] In particular, SiC MOSFETs have demonstrated higher switching performance, making these SiC power devices especially desirable for high frequency applications.

[0006] In particular, power MOSFETs have a gate-source voltage V GS It is sometimes used in saturation mode (operation in the active region) as a constant current source that is regulated by varying the value of I. In fact, in saturation mode, the drain-source current I DS is the drain-source voltage V DS It is almost independent of the gate-source voltage V GS Varies as a function of .

[0007] In different applications, power MOSFETs operate in a linear mode (also called the ohmic or triode region) of switching from an on state to an off state and vice versa. The linear mode is when the current I DS and voltage V DS and hence the linear relationship between the drain-source on-resistance R DSon (Hereinafter, on-resistance R Dson In this mode of operation, the switching speed between the OFF and ON states affects the characteristics of the power MOSFET device. In fact, the slower the transition from the ON to the OFF state, the higher the power dissipation during switching, which in turn affects the threshold voltage V TH The probability of thermal drift increases.

[0008] Therefore, SiC power MOSFETs are designed to minimize the switching time, thus reducing the probability of these drawbacks. However, reducing the switching time causes, in the dynamic and transient regime, the known phenomenon of "ringing" of the MOSFET current and voltage during the switching phase (i.e., the phenomenon of substantially sinusoidal oscillations in the current and voltage that begin at the switching moment and decrease in amplitude over time until they end after a transient period starting from the switching moment). The ringing phenomenon causes current and voltage "overshoots" (i.e., current and voltage oscillation peaks with significant amplitudes) that are often larger than what the MOSFET is designed to safely withstand. The overshoots can therefore damage the MOSFET, increase power losses, and introduce noise and electromagnetic interference of non-negligible importance.

[0009] Moreover, a general trend in SiC power MOSFETs is to continuously miniaturize them, thereby allowing a higher density of MOSFETs in the same unit area, and thus increasing the computational performance of devices that have MOSFETs, without the need to correspondingly increase their size. In particular, in vertical structure MOSFETs, this is done by reducing the distance between the body region of each MOSFET cell that is under the gate structure. This miniaturizes the MOSFET, but also causes a reduction in the gate-drain capacitance, since the contact surface between the MOSFET's drift layer and the gate structure is reduced. The reduction in gate-drain capacitance makes the drain region less dynamically capacitively coupled to the gate structure, and therefore more exposed to sudden variations in the drain voltage. This negative consequence is therefore the cause of MOSFET overshoots, and more generally, ringing phenomena.

[0010] The reduction of the gate-drain capacitance reduces the "parasitic turn-on" (PTO) phenomenon of the MOSFET, i.e., the turn-on of the conducting channel of the MOSFET when the MOSFET is controlled to operate in the inverse mode but there are oscillations in the drain voltage that generate corresponding oscillations in the gate voltage that activate the MOSFET conduction in any case due to dynamic capacitive coupling between the gate structure and the drain region. Although PTO is generally undesirable since it reduces the reliability of the MOSFET and makes it more prone to malfunction, it also has the positive effect of reducing the ringing phenomenon since it reduces the maximum amplitude of the MOSFET overshoot. However, since the PTO becomes smaller when the MOSFET is miniaturized, this phenomenon cannot be effectively utilized to reduce the ringing phenomenon in miniaturized MOSFETs.

[0011] There are several known solutions to the MOSFET ringing problem.

[0012] It is known to increase the gate resistance by adding an additional series resistor to the gate structure, for example a resistor integrated in the MOSFET or external to the MOSFET. This has been found to reduce the risk of ringing in the MOSFET. However, it is generally very difficult to select the resistor added to the gate structure appropriately without excessively degrading the electrical characteristics of the MOSFET. In fact, an increase in the gate resistance usually causes a significant increase in the switching time of the MOSFET and therefore a deterioration of its operation when used in linear mode.

[0013] Furthermore, it is known to use external electronic circuits (e.g., "snubber" or "damping" circuits based on RC circuits) to improve the electrical control of the gate structure and thus reduce the overshoot of the MOSFET. However, the presence of these electronic circuits external to the MOSFET complicates the design of devices that include the MOSFET and increases their cost and power consumption.

[0014] Furthermore, another commonly occurring problem, especially in high power MOSFETs (ie, MOSFETs configured to operate with drain-source voltages greater than about 1200V), is that of the "snappy" behavior of the MOSFET.

[0015] In particular, this behavior is evident when, for example, a high-power MOSFET has an operating voltage of about 1200 V, a drain-source voltage equal to about 850 V, o C / 200 o This is identified by a sudden change in slope in the drain-source voltage and drain-source current curves when the device is operated at a temperature of 100° C. and at a value of the rate of change of the recovery current di / dt greater than about 2.5 A / ns. This causes the occurrence of an overshoot in the drain-source voltage, which can lead to instability and malfunction of the MOSFET, degradation of the electrical performance of the MOSFET, and ringing phenomena with resulting noise and electromagnetic interference disturbances. In extreme cases, the amplitude of this overshoot can reach or even exceed the avalanche breakdown voltage, causing an avalanche breakdown of the MOSFET.

[0016] The snappy behavior has been determined to result from the sudden recombination of minority charge carriers at the interface between the drift and drain layers.

[0017] In fact, to ensure proper electrical operation, high-power MOSFETs require low dopant concentrations (e.g., about 1×10) in the drift layer. 16 at / cm 3lower) and therefore have a large number of minority carriers in the depletion region of the drift layer. If the MOSFET operates at high temperatures (for example, higher than about 170° C.), the lifetime of these minority carriers, which, as is known, is proportional to the temperature of the MOSFET, may increase to such an extent that they make complete recombination impossible before reaching the drain region. In this case, a part of the minority carriers does not recombine in the drift layer, but only disappears at the interface between the drift layer and the drain layer. For a certain time interval starting from the moment the minority carriers start to recombine at the interface between the drift layer and the drain layer, this recombination is carried out by the output parasitic capacitance C of the MOSFET oss (equal to the sum of the drain-source capacitance and the gate-source capacitance), which is constant and thus causes the snappy behavior of the MOSFET during this time interval.

[0018] This problem is instead secondary in low power MOSFETs (i.e. MOSFETs configured to operate at drain-source voltages lower than about 1200 V, for example equal to about 650 V, which have a higher dopant concentration in the drift layer and therefore a higher recombination rate of minority carriers, reducing their average lifetime), as well as in MOSFETs that do not operate at high temperatures (e.g. MOSFETs operating at temperatures lower than about 170° C., for example equal to about 30-100° C., which therefore have a shorter average lifetime of minority carriers).

[0019] Known solutions to this problem are similar to those previously presented to combat MOSFET ringing and therefore include increasing the resistance of the gate structure or using external electronic circuitry coupled to the MOSFET, therefore the same drawbacks as mentioned above apply to these solutions.

[0020] It is an object of the present disclosure to provide a power electronic device and corresponding apparatus that overcomes the shortcomings of the prior art. Summary of the Invention

[0021] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure provide power electronic devices and corresponding apparatus that at least partially overcome shortcomings of conventional solutions.

[0022] In one embodiment, an electronic device includes a semiconductor body of silicon carbide having top and bottom surfaces opposed to one another along a first axis. The semiconductor body includes a drain substrate beginning at the bottom surface of the semiconductor body and extending into the semiconductor body, the drain substrate having a first conductivity type and a first dopant concentration. The semiconductor body includes a drift layer beginning at the top surface of the semiconductor body and extending into the semiconductor body to the drain substrate, the drift layer having a second conductivity type lower than the first dopant concentration. The semiconductor body includes at least one first body region beginning at the top surface of the semiconductor body, extending into the semiconductor body away from the drain substrate, contained within the drift layer, and having a second conductivity type opposite the first conductivity type. The semiconductor body includes at least one first source region beginning at the top surface of the semiconductor body, extending into the semiconductor body, contained within the first body region spaced apart from the drift layer, and having a first conductivity type. The electronic device includes at least one first gate structure extending over a top surface of the semiconductor body and superimposed on the first body region along a first axis to form a first MOSFET portion of a first MOSFET together with the first source region, the first body region, the drift layer, and the drain substrate, The semiconductor body further includes at least one first doped pocket region embedded in the drift layer, having a second conductivity type, and at least partially aligned with the first source region and / or the first gate structure along the first axis.

[0023] In one embodiment, the electronic device includes a semiconductor body of silicon carbide. The semiconductor body includes a drain substrate of a first conductivity type and a first dopant concentration, a drift layer overlying the drain substrate and having the first conductivity type and a second dopant concentration lower than the first dopant concentration, and a body region having a second conductivity type opposite the first conductivity type, the body region having a top surface coplanar with a top surface of the drift layer and separated from the drain substrate by the drift layer. The semiconductor body includes a source region having the first conductivity type embedded in the body region and separated from the drift layer by the body region, and a first doped pocket region of the second conductivity type embedded in the drift layer and having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate. The electronic device includes a gate structure at least in part directly over the first body region and at least a portion of the first doped pocket region. The source region, the body region, the drift layer, and the drain substrate form a MOSFET.

[0024] In one embodiment, a method includes forming a semiconductor body of silicon carbide, forming a drain substrate of a MOSFET of a first conductivity type and a first dopant concentration in the semiconductor body, and forming a drift layer of the MOSFET having a second dopant concentration lower than the first dopant concentration in the semiconductor body above the drain substrate. The method includes forming a body region of the MOSFET having a second conductivity type opposite the first conductivity type, the body region having a top surface coplanar with a top surface of the drift layer and separated from the drain substrate by the drift layer in the semiconductor body. The method includes forming a source region of the MOSFET having the first conductivity type embedded in the body region and separated from the drift layer by the body region, the source region of the MOSFET having the first conductivity type, forming a first doped pocket region of the second conductivity type embedded in the drift layer, the first doped pocket region having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate, and forming a gate structure of the MOSFET directly above at least a portion of the first body region and at least a portion of the first doped pocket region. [Brief description of the drawings]

[0025] For a better understanding of the present disclosure, preferred embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Figure 1] 1A-1D are cross-sectional views of respective embodiments of an electronic device. [Diagram 2] 1A-1D are cross-sectional views of respective embodiments of an electronic device. [Diagram 3] 1A-1D are cross-sectional views of respective embodiments of an electronic device. [Figure 4] 1A-1D are cross-sectional views of respective embodiments of an electronic device. [Diagram 5] 1A-1D are cross-sectional views of respective embodiments of an electronic device. [Figure 6A] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 6B] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 6C] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 6D] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 6E] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 6F] 6 is a cross-sectional view illustrating the change in the depletion region of a portion of a MOSFET of the electronic device of FIGS. 1 to 5 as the electrical control conditions of the MOSFET change. FIG. [Figure 7A] FIG. 6 is a diagram showing electrical signals in each of the electronic devices of FIGS. 1 to 5. [Figure 7B] FIG. 6 is a diagram showing electrical signals in each of the electronic devices of FIGS. 1 to 5. [Figure 8] 11A-11C are cross-sectional views of further respective embodiments of an electronic device. [Figure 9] 11A-11C are cross-sectional views of further respective embodiments of an electronic device. [Figure 10A] 1A-1C are top views with hidden portions of respective embodiments of electronic devices. [Figure 10B] 1A-1C are top views with hidden portions of respective embodiments of electronic devices. [Figure 11] 1 is a cross-sectional view of a further embodiment of an electronic device.

[0026] In particular, the drawings are illustrated with reference to a three-axis Cartesian system defined by mutually orthogonal axes X, Y and Z.

[0027] In the following description, elements common to different embodiments are designated with the same reference numbers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] FIG. 1 illustrates a cross-sectional view of one embodiment of a power electronic device 10 .

[0029] In particular, a power electronic device 10 (hereinafter also referred to as electronic device 10 or more simply device 10) is shown in Fig. 1 in a plane XZ defined by axes X and Z. The device 10 has a main extension parallel to axis Y, and Fig. 1 shows a cross section perpendicular to this main extension.

[0030] The device 10 is, for example, in an apparatus (not shown, an electrical / electronic type apparatus such as a notebook, a mobile phone, a server, a TV, a car, a car charging station, or a conversion system for a photovoltaic panel).

[0031] The device 10 has an active area (not shown) in which one or more MOSFETs 10', in particular vertical structure MOSFETs (e.g. of the enhancement type), are accommodated. In the exemplary and non-limiting embodiment of Fig. 1, three MOSFETs 10' are shown arranged laterally relative to one another along axis X to form a MOSFET array. However, the number of MOSFETs 10' may vary in a manner which is clear per se, for example being more (e.g. 10 or 100) or less (e.g. only one MOSFET).

[0032] Device 10 includes a silicon carbide, SiC (eg, 4H-SiC) substrate (or drain substrate) 16. Substrate 16 forms the drain region of MOSFET 10'.

[0033] The substrate 16 is of a first conductivity type (hereinafter, N-type conductivity is considered) and has a thickness of, for example, 10 18 at / cm 3 and a first dopant concentration (or first conductivity value) of about 100 nm.

[0034] Substrate 16 has an upper surface 16a and a lower surface 16b opposed to each other along axis Z. For example, substrate 16 has a thickness along axis Z between surfaces 16a and 16b that is between about 50 μm and about 350 μm, more specifically between about 160 μm and about 200 μm, e.g., equal to about 180 μm.

[0035] Device 10 includes a drift layer 17 of SiC (such as 4H—SiC) extending over a substrate 16. In particular, drift layer 17 is epitaxially grown on substrate 16.

[0036] The drift layer 17 has a first conductivity type (here, N-type) and a second dopant concentration lower than the first dopant concentration (for example, about 2.5×10 16 at / cm 3 (lower than

[0037] The drift layer 17 has an upper surface 17a and a lower surface 17b facing each other along the axis Z, and the lower surface 17b of the drift layer 17 is in contact with the upper surface 16a of the substrate 16.

[0038] For example, the drift layer 17 has a thickness along the axis Z between the surfaces 17a and 17b that is between about 4 μm and about 15 μm, for example equal to about 6.5 μm.

[0039] Device 10 also includes a drain ohmic contact region or layer (not shown, e.g. nickel silicide) that extends to form an ohmic contact on the bottom surface 16b of substrate 16. For example, in a manner known per se, the drain ohmic contact region may extend onto the lower surface 16b of substrate 16, or may extend into substrate 16 so as to be exposed by substrate 16 at its lower surface 16b.

[0040] The device 10 also includes a drain metallization 18 that extends over the drain ohmic contact region so as to make direct electrical contact with the substrate 16 to form a drain electrical terminal. The drain metallization 18 is made of a conductive material and is formed, for example, by a stack of metal layers such as Ti / NiV / Ag or Ti / NiV / Au.

[0041] Device 10 also includes a number of body regions 19 contained within drift layer 17 and originating from a top surface 17a of drift layer 17 and extending toward substrate 16 (but not reaching substrate 16).

[0042] In particular, each body region 19 has a respective top surface 19a exposed by drift layer 17 and substantially aligned with top surface 17a of drift layer 17 along axis Z.

[0043] The body regions 19 are spaced apart from one another along the axis X via the drift layer 17 and are disposed laterally from one another along the axis X. The body regions 19 each have a main extension parallel to the axis Y.

[0044] The body region 19 has a second conductivity type (here, P type) opposite to the first conductivity type. 17 at / cm 3 and about 3 × 10 18 at / cm 3 and a third dopant concentration between

[0045] In particular, two body regions 19 are predefined for each MOSFET 10', and each body region 19 is shared between two adjacent MOSFETs 10' in a MOSFET array, as will be described in more detail below.

[0046] Device 10 also includes, for each body region 19, two respective source regions 20 contained within body region 19 and originating from a top surface 19a of body region 19 and extending toward drift layer 17 (without reaching drift layer 17).

[0047] In particular, each source region 20 has a respective upper surface 20a exposed by body region 19 and substantially aligned with upper surface 19a of body region 19 along axis Z.

[0048] The source regions 20 are spaced apart from one another along an axis X that passes through the body region 19. The source regions 20 each have a main extension parallel to an axis Y.

[0049] The source region 20 has a first conductivity type (here, N-type) and a fourth dopant concentration higher than the first dopant concentration (e.g., about 1×10 19 at / cm 3 ~Approx. 1×10 21 at / cm 3 , for example, about 1 × 10 20 at / cm 3 (equal to

[0050] In particular, for each body region 19 there are two source regions 20, each of which belongs to a respective one of the two MOSFETs 10' that share the body region 19 under consideration.

[0051] The portion of each body region 19 interposed along axis X between source region 20 and drift layer 17 defines a respective channel region 19′ of MOSFET 10′, through which electrical conduction occurs when MOSFET 10′ is properly biased.

[0052] The substrate 16, drift layer 17, body region 19 and source region 20 together form a SiC semiconductor body 15 of device 10, which has an upper surface 15a (defined by upper surfaces 17a, 19a and 20a of the drift layer 17, body region 19 and source region 20) and a lower surface 15b (defined by lower surface 16b of substrate 16) opposite each other along axis Z.

[0053] Device 10 also includes a respective gate structure 21 for each MOSFET 10'.

[0054] Each gate structure 21 extends across two respective channel regions 19′ that are opposite each other via the drift layer 17 and that are part of two body structures 19 that are consecutive to each other along the axis X. In other words, each gate structure 21 extends across the channel region 19′ of a respective MOSFET 10′. The gate structures 21 also have a main extension parallel to the axis Y.

[0055] In particular, each gate structure 21 extends over a respective channel region 19 ′, over a portion of the drift layer 17 interposed between these channel regions 19 ′ along axis X, and possibly over a portion of a respective source region 20 .

[0056] Each gate structure 21 includes a gate insulating layer 22 on the top surface 15a of the semiconductor body 15 and a gate region 23 surrounded by the gate insulating layer 22 in the plane XZ.

[0057] The gate insulating layer 22 is made of an insulating material such as silicon dioxide (SiO2), and the gate region 23 is made of a conductive material such as metal or doped polysilicon. In this way, the gate region 23 is physically and electrically insulated by the gate insulating layer 22 from the semiconductor body 15 (and in particular from the channel region 19' on which it overlies).

[0058] The gate region 23 is also electrically connected to a gate metallization (not shown) of the device 10, in a manner known per se to those skilled in the art. The gate metallization defines a gate terminal of the device 10.

[0059] As shown in FIG. 1, each MOSFET 10' having a vertical structure includes first and second MOSFET portions 10'. a and 10' b The first MOSFET portion 10' a is defined by a gate structure 21, a source region 20 on the left side of the drift layer 17, a respective body region 19 on the left side of the drift layer 17 (in particular, a channel region 19′ on the left side of the drift layer 17), the drift layer 17, and the substrate 16, forming a second MOSFET portion 10′. b is defined by the gate structure 21 , the source region 20 to the right of the drift layer 17 , the respective body region 19 to the right of the drift layer 17 (in particular the channel region 19 ′ to the right of the drift layer 17 ), the drift layer 17 and the substrate 16 .

[0060] Furthermore, device 10 includes a respective source ohmic contact region or layer (not shown, e.g. nickel silicide) for each source region 20. The source ohmic contact region extends onto an upper surface 20a of the respective source region 20 and forms a respective ohmic contact. For example, in a manner known per se, each source ohmic contact region may extend onto an upper surface 20a of the source region 20 or may extend into the source region 20 so as to be exposed by the source region 20 at the upper surface 20a.

[0061] Device 10 also includes a source metallization 24 that extends over the source ohmic contact region so as to make direct electrical contact with source region 20, thus forming a source electrical terminal. In practice, source metallization 24 extends over gate structure 21 and over regions of top surface 15a of semiconductor body 15 that are not covered by gate structure 21, so as to make direct electrical contact with source region 20. Source metallization 24 is made of a conductive material and is formed, for example, by a stack of metal layers, such as Ti / AlSiCu or Ni / AlSiCu.

[0062] Device 10 may also include a passivation layer (not shown) extending over source metallization 24 to protect it.

[0063] For example, in a manner not shown but known per se, the active area of ​​device 10 is defined externally in a plane XY defined by axes X and Y and substantially parallel to top surface 15a of semiconductor body 15 by an edge termination region or guard ring which completely surrounds MOSFET 10' in plane XY. For example, the edge termination region is a P-type implanted region. Optionally, device 10 may also include an edge insulating layer (not shown) which is superimposed on the edge termination region along axis Z and extends over top surface 15a of semiconductor body 15 so as to completely surround MOSFET 10' and laterally define source metallization 24.

[0064] In addition, the device 10 includes one or more doped pocket regions 25 .

[0065] In the exemplary and non-limiting embodiment of FIG. 1, there are two doped pocket regions 25 for each MOSFET portion 10'. In particular, a and 10' bThere is a respective doped pocket region 25 for each MOSFET 10'. Nevertheless, as better explained below, the number of doped pocket regions 25 may vary, e.g., may be more or less than those described above (e.g., there may be only one doped pocket region 25 for each MOSFET 10').

[0066] 1, the doped pocket region 25 has a substantially rectangular (e.g., rectangular with rounded corners) cross section in the XZ plane. However, other closed polygonal shapes of the cross section in the XZ plane of the doped pocket region 25 may be considered as well, such as a trapezoidal shape, a T-shape, a mushroom shape, etc.

[0067] The doped pocket regions 25 are embedded within the drift layer 17 and are aligned at least partially along axis Z with the source regions 20 and / or gate structures 21 of the respective MOSFETs 10′. In particular, the doped pocket regions 25 extend a distance from the body region 19 and the top surface 15a of the semiconductor body 15.

[0068] In particular, the doped pocket regions 25 are spaced apart from one another along an axis X that extends through the drift layer 17 .

[0069] The doped pocket region 25 may have a main extension parallel to the axis Y. For example, the doped pocket region 25 may have the shape of a strip parallel to the axis Y, as better shown in FIG. 10A. For example, the doped pocket region 25 has a length measured parallel to the axis Y that is approximately equal to the length of the body region 19 measured parallel to the axis Y.

[0070] The doped pocket regions 25 have a second conductivity type (here P type) and a doped pocket dopant concentration higher than the second dopant concentration of the drift layer 17. For example, the doped pocket regions 25 are doped with boron or aluminum.

[0071] In particular, the doped pocket dopant concentration is about 1×10 17at / cm 3 ~Approx. 5×10 17 at / cm 3 (i.e., about 10 to about 50 times the second dopant concentration of the drift layer 17), for example, about 3×10 17 at / cm 3 so that doped pocket region 25 is depleted at the breakdown voltage of MOSFET 10'.

[0072] According to one embodiment, the doped pocket regions 25 are arranged at substantially the same height along the axis Z and laterally relative to one another along the axis X. In other words, the doped pocket regions 25 are arranged adjacent to one another along the axis X at the same height relative to the substrate 16.

[0073] Each body region 19 has a minimum distance (or minimum body distance) D from the substrate 16. b and each doped pocket region 25 has a minimum distance (or minimum doped pocket distance) D from the substrate 16. s Considering that we have the minimum distance D s is the minimum distance D b Less than.

[0074] In particular, as will be better explained below, the minimum distance D s and the minimum distance D b The ratio (or the first ratio) between s / D b is between 0% and approximately 70% (including the boundary value).

[0075] Each MOSFET 10′ has an average width (or average MOSFET width) L along axis X. m and each doped pocket region 25 has a maximum width (or maximum doped pocket width) L along axis X. s Considering that the maximum width L s is the average width L m Smaller than the maximum width L s and average width L m The ratio (or second ratio) between L s / L mis about 15% to about 30% (including the boundary value). For example, m is measured between respective central axes, parallel to axis Z, of the two body regions 19 of the MOSFET 10′ under consideration. In other words, it is measured parallel to axis X between two points on the top surface 19a of each body region 19 that are equidistant from the two source regions 20 present in each body region 19.

[0076] Further, each of the doped pocket regions 25 has a maximum thickness (or maximum doped pocket thickness) S along the axis Z. s Considering that the maximum thickness S s and the minimum distance D b The ratio (or third ratio) between s / D b can be about 10% to about 30% (boundary values ​​included).

[0077] More specifically, each body region 19 has a lower surface 19b opposite the upper surface 19a along axis Z. Additionally, each doped pocket region 25 has an upper surface 25a and a lower surface 25b opposed to each other along axis Z, and a first side surface 25c and a second side surface 25d opposed to each other along axis X and joined to and transverse to the surfaces 25a and 25b. b is defined along axis Z between the lower surface 19b of each body region 19 and the upper surface 16a of the substrate 16. s is defined along axis Z between the lower surface 25b of each doped pocket region 25 and the upper surface 16a of the substrate 16. s is defined along an axis X between the first side 25c and the second side 25d of each doped pocket region 25. s is defined along axis Z between the upper and lower surfaces 25a, 25b of each doped pocket region 25.

[0078] According to an exemplary and non-limiting embodiment, the minimum distance D b is about 5.2 μm to about 5.7 μm, and the minimum distance D s is about 0 μm to about 0.5 μm, and the average width L mis about 4.5 μm to about 5 μm, and the maximum width L s is about 0.9 μm to about 1.5 μm, and the maximum thickness S s is about 0.5 μm to about 1.2 μm.

[0079] According to one embodiment of device 10 (e.g., as shown in FIG. 1 , where two doped pocket regions 25 are predefined for each MOSFET 10′), each source region 20 is at least partially vertically aligned (i.e., parallel to axis Z) with a respective one of the doped pocket regions 25. In turn, the doped pocket regions 25 may also be vertically aligned with the gate structure 21 of the respective MOSFET 10′, or may be vertically offset therefrom (i.e., not vertically aligned therewith).

[0080] According to different embodiments of device 10 (e.g., as shown in FIG. 2 where there is only one doped pocket region 25 for each MOSFET 10′), each gate structure 21 is at least partially vertically aligned with a respective one of the doped pocket regions 25, and the doped pocket regions 25 may be vertically offset relative to the source regions 20.

[0081] These embodiments may be combined with each other. For example, according to a further embodiment of device 10 (e.g., as shown in FIG. 3, where there are three doped pocket regions 25 for each MOSFET 10′), gate structure 21 is at least partially vertically aligned with some of the doped pocket regions 25, some of the doped pocket regions 25 are vertically offset with respect to source regions 20, and source regions 20 are at least partially vertically aligned with other doped pocket regions 25.

[0082] As an alternative to the above, for example as shown in FIG. 4, the doped pocket regions 25 may be arranged laterally to one another along the axis X, but at different heights to one another along the axis Z. In other words, the doped pocket regions 25 may be arranged contiguous to one another along the axis X, but at different heights to one another relative to the substrate 16. In this case, different minimum distances D s (In the example of FIG. 4, the first and second minimum distances D s1 and D. s2 ), each of which has a ratio D s / D b The above-mentioned conditions are met.

[0083] 5, it is also possible to have a plurality of doped pocket regions 25 that are overlapped with one another and spaced apart from one another in a direction parallel to the axis Z. In other words, the doped pocket regions 25 may be aligned at least partially perpendicular to one another. For example, it is possible to have a plurality of groups of doped pocket regions 25 laterally aligned with one another along the axis X, each group including two or more respective doped pocket regions 25 that are overlapped with one another parallel to the axis Z. For example, the doped pocket regions 25 that are overlapped with one another parallel to the axis Z may be spaced apart from one another by a respective mutual distance D parallel to the axis Z that may be, for example, greater than about 0.5 μm. r This embodiment can be combined with any of the embodiments described herein.

[0084] In known manner, during use, the device 10 is driven by a source voltage V S (e.g., a ground reference voltage GND, i.e., 0V) to the source metallization 24 and thus to the source region 20, while the drain voltage V D (e.g., 30 V to 1700 V) is applied to drain metallization 18 and thus to substrate 16. That is, a drain-source voltage V DS is applied.

[0085] Furthermore, when the gate region 23 is biased to a gate voltage V G,th greater than the gate threshold voltage V G and generates each flow of charge carriers (here electrons) through the channel region 19' of the MOSFET 10', the device 10 is in the conducting state. Conversely, when the gate voltage V G applied to the gate region 23 is lower than the gate threshold voltage V G,th and suppresses the generation of charge carriers flowing through the channel region 19' of the MOSFET 10', the device 10 is in the inhibited state.

[0086] Thus, the overall conduction of the device 10 is a function of all the MOSFETs 10', and in particular, of the electron flows in both of each MOSFET 10' (each corresponding to its respective MOSFET portion 10' a 、10' b ). As a result, when properly biased, the device 10 generates a drain-source current I DS between the source and drain terminals of the MOSFET 10'.

[0087] The doped pocket region 25 reduces the ringing phenomenon of the device 10 compared to a known case where the doped pocket region 25 does not exist. For example, it has been confirmed that the amplitude of the overshoot of the drain-source voltage V DS and the drain-source current I DS during the switching of the MOSFET 10' is also reduced by 70 - 80%. It has been confirmed that this beneficial effect is not due to the establishment of PTO in the MOSFET 10' and is unrelated to this phenomenon.

[0088] In fact, the doped pocket region 25 increases the dynamic capacitive coupling between the source and drain terminals, and thus enables a reduction in the oscillation of the drain-source voltage V DS during the switching of the MOSFET 10'.

[0089] In particular, FIGS. 6A - 6F show the drain-source voltage V DS6A-6F show the behavior of the depletion region 27 of one of the MOSFETs 10′ during a dynamic phase as the potential V V increases. a Although only one MOSFET portion 10' is shown, similar considerations apply to the second MOSFET portion 10'. b And the same is true for all MOSFETs 10'.

[0090] As can be seen in Figures 6A to 6F, the drain-source voltage V DS As the drain-source voltage V DS , and Figure 6F shows the case where the drain-source voltage V DS ), the depletion region 27 also expands, starting from the source region 20 and progressing towards the substrate 16. In other words, the depletion region 27 expands as the drain-source voltage V DS , has a lower interface 27′ (corresponding to the lower limit along axis Z of depletion region 27 and thus to the lower limit of the region of drift layer 17 where minority charge carriers, here holes, are larger than majority charge carriers, here electrons) that extends further into substrate 16.

[0091] 6A and 6B, the lower boundary surface 27' of the depletion region 27 does not yet reach the underlying doped pocket region 25 and therefore does not play any role in the distribution of the electric field and therefore the distribution of holes in the considered MOSFET 10'. In other words, the lower boundary surface 27' of the depletion region 27 extends above the doped pocket region 25.

[0092] 6C, the depletion region 27 just reaches and contacts the doped pocket region 25. In this case, the lower boundary surface 27′ of the depletion region 27 moves along the axis Z to just below the doped pocket region 25. In other words, the depletion region 27 extends through both the portion of the drift layer 17 disposed above the doped pocket region 25 and through the doped pocket region 25. In this case, it is confirmed that a flow of holes having a substantially vertical direction is established between the source region 20 and the doped pocket region 25.

[0093] 6D-6F, the depletion region 27 gradually expands under the doped pocket region 25 toward the substrate 16. In other words, the lower interface 27′ of the depletion region 27, which is interposed along the axis Z between the doped pocket region 25 and the substrate 16, moves increasingly away from the doped pocket region 25 toward the substrate 16. At the same time, the flow of holes between the source region 20 and the doped pocket region 25 becomes stronger, and the electrical coupling between the source region 20 and the doped pocket region 25 increases.

[0094] When the depletion region 27 extends through the doped pocket region 25, the drain-source voltage V DS and the drain-source current I DS It has been determined that the rate of change of these voltages over time is reduced by the same other electrical and physical parameters of the MOSFET 10'. This reduces the drain-source voltage V DS and the drain-source current I DS oscillates over time with a smaller maximum amplitude than in the absence of the doped pocket region 25, thus reducing the ringing effect.

[0095] 7A and 7B show the drain-source voltage V for one of the MOSFETs 10′ when the MOSFET 10′ switches from an on state to an off state. DS and the drain-source current I DS 1 shows the time trends of each of MOSFETs 10' and MOSFET 10', respectively, (shown below approximately t=t*=0.1 μs). In particular, this is shown for both one of MOSFETs 10' and a known MOSFET that does not have doped pocket region 25 present, in order to compare their respective electrical characteristics.

[0096] After switching at t=t*=0.1μs, there is a transient time interval during which the drain-source voltage V DS and the drain-source current I DS oscillate in a damped manner around their respective average values ​​before converging towards them (approximately 400 V and 0 A in the examples of FIGS. 7A and 7B, respectively).

[0097] During this transition time interval, the drain-source voltage V DS and the drain-source current I DS The amplitude of the oscillations is smaller in the presence of the doped pocket region 25 than in the known case where the doped pocket region 25 is not present.

[0098] Moreover, it has been determined that the presence of doped pocket regions 25 does not significantly alter other electrical and operating characteristics of device 10 (eg, breakdown voltage, drain-source on-resistance, body diode current of MOSFET 10').

[0099] The effectiveness of ringing reduction generally depends on the minimum distance D of the doped pocket region 25 from the substrate 16. s is 0 (ie, Ds=0 μm), and thus is at a maximum when the doped pocket region 25 is in contact with the top surface 16 a of the substrate 16 .

[0100] Moreover, in general, the vertical position of the doped pocket regions 25 in the drift layer 17 depends on the rate of change of the recovery current of the MOSFET 10' at which the MOSFET 10' is designed and electrically controlled to operate. In particular, the recovery current is the reverse drain-source current flowing through the MOSFET 10' during the transient time interval during the rising phase of the drain-source voltage where the drain-source current changes sign after the direct current flows. The rate of change of the recovery current di / dt also indicates the static or dynamic regime of the MOSFET 10' (e.g., static regime if di / dt<1 A / ns, dynamic regime if greater than di / dt).

[0101] In other words, the minimum distance D s and the minimum distance D b The first ratio with D s / D bThe range of variation (especially its upper limit) depends on the rate of change of the recovery current di / dt of the MOSFET10'. This is due to the fact that as the rate of change of the recovery current di / dt increases, the dynamic capacitive coupling between the source region 20 and the substrate 16 continues to ensure that it is sufficient to have a highly damped ringing. This is because the doped pocket region 25 gets closer to the substrate 16.

[0102] According to one embodiment, when the MOSFET10' is configured to operate at 0 A / ns < di / dt ≦ 1 A / ns, the first ratio D s / D b is from 0% to about 70% (in particular, from about 50% to about 70%).

[0103] According to one embodiment, when the MOSFET10' is configured to operate at 1 A / ns < di / dt ≦ 2 A / ns, the first ratio D s / D b is from 0% to about 60% (in particular, from about 40% to about 60%).

[0104] According to one embodiment, when the MOSFET10' is configured to operate at 2 A / ns < di / dt ≦ 3 A / ns, the first ratio D s / D b is from 0% to about 50% (in particular, from about 30% to about 50%).

[0105] According to one embodiment, when the MOSFET10' is configured to operate at 3 A / ns < di / dt ≦ 4 A / ns, the first ratio D s / D b is from 0% to about 40% (in particular, from about 20% to about 40%).

[0106] According to one embodiment, when the MOSFET10' is configured to operate at 4 A / ns < di / dt ≦ 5 A / ns, the first ratio D s / D b is from 0% to about 30% (in particular, from about 10% to about 30%).

[0107] According to one embodiment, when the MOSFET 10’ is configured to operate with 5 A / ns < di / dt ≦ 6 A / ns, the first ratio D s / D b is from 0% to about 20%.

[0108] According to one embodiment, when the MOSFET 10’ is configured to operate with 6 A / ns < di / dt ≦ 7 A / ns, the first ratio D s / D b is from 0% to about 10%.

[0109] According to one embodiment, when the MOSFET 10’ is configured to operate with di / dt > 7 A / ns, the first ratio D s / D b is equal to about 0%.

[0110] FIG. 8 shows a further embodiment of the device 10. In particular, the device 10 of FIG. 8 is a high-power device (i.e., designed and configured to operate, for example, with a drain-source voltage V higher than about 1200 V). DS ).

[0111] In the example of FIG. 8, the device 10 is similar to the embodiment of FIG. 1, and two doped pocket regions 25 are present for each MOSFET 10’ laterally with respect to each other along the axis X and at the same height along the axis Z. Nevertheless, the device 10 can be based on any of the foregoing embodiments, and thus the following considerations apply equally to other embodiments.

[0112] In particular, unlike FIG. 1 in which the entire drift layer 17 has the second dopant concentration, in FIG. 8 the drift layer 17 includes a main drift region 17' having a first conductivity type (here, N-type) and a second dopant concentration, and a drift buffer region 17'' having the first conductivity type (here, N-type) and a buffer dopant concentration higher than the second dopant concentration. In other words, in FIG. 1 the drift layer 17 is formed by only the drift main region 17', whereas in FIG. 8 the drift layer 17 is formed by the drift main region 17' and the drift buffer region 17''.

[0113] In particular, the buffer dopant concentration of the drift buffer region 17'' is about 25% greater than the second dopant concentration (i.e., the sum of the second dopant concentration and about 25% of the second dopant concentration) and about 3×10 16 at / cm 3 For example, between about 1.3 x 10 16 at / cm 3 As a result, the buffer dopant concentration is at least about 25% greater than the second dopant concentration.

[0114] The drift buffer region 17'' extends over the substrate 16, and the drift primary region 17' extends over the drift buffer region 17''. The drift buffer region 17'' is thus interposed along the axis Z between the substrate 16 and the drift primary region 17'.

[0115] More specifically, the drift buffer region 17'' has an upper surface 17''a and a lower surface 17''b (which contact the upper surface 16a of the substrate 16 and define the lower surface 17b of the drift layer 17) that are opposite to each other along the axis Z, and the drift main region 17' has an upper surface 17'a (which defines the upper surface 17a of the drift layer 17) and a lower surface 17'b (which contacts the upper surface 17''a of the drift buffer region 17'') that are opposite to each other along the axis Z.

[0116] The drift buffer region 17'' has a maximum thickness S along the axis Z. b and the drift primary region 17′ has a minimum thickness S along the axis Z.d which is the maximum thickness S of the drift buffer region 17″ b In particular, the drift buffer region 17'' and the drift main region 17' have a substantially constant thickness S b and S d For example, the maximum thickness S of the drift buffer region 17 ″ b is measured along axis Z between upper surface 17''a and lower surface 17''b of drift buffer region 17'', and is the minimum thickness S of drift primary region 17' d is measured along axis Z between the body region 19 (specifically, the lower surface 19b of one body region 19) and the lower surface 17'b of the drift primary region 17'.

[0117] According to one embodiment, the maximum thickness S of the drift buffer region 17″ b and the minimum distance D of the body region 19 from the substrate 16 b The ratio (or fourth ratio) between b / D b is between about 30% and about 50% (boundaries included), for example, equal to about 40%.

[0118] The doped pocket region 25 may extend completely into the drift buffer region 17'', completely into the drift main region 17', or partially into the drift buffer region 17'' and partially into the drift main region 17'.

[0119] In particular, it has been determined that the presence of drift buffer region 17'' having a higher doping than drift main region 17' prevents snappy behavior of MOSFET 10'.

[0120] In fact, the drift buffer region 17'' increases the recombination rate of the minority charge carriers (here holes) due to its higher doping. In other words, the average lifetime of the holes in the drift layer 17 is reduced, and thus, even when the device 10 operates at high temperatures (e.g., higher than about 170° C.), the holes are forced to recombine before reaching the substrate 16, thus preventing the holes from suddenly recombining upon contact with the upper surface 16a of the substrate 16. In particular, the drift buffer region 17'' prevents, in the static regime, the lower boundary surface 27' of the depletion region 27 from reaching the upper surface 16a of the substrate 16. This therefore avoids the snappy behavior of the MOSFET 10'.

[0121] Moreover, it has been determined that the presence of drift buffer region 17'' in drift layer 17 does not significantly alter the operation and other electrical parameters of device 10 (e.g., on-resistance and breakdown voltage of MOSFET 10'). In particular, the buffer dopant concentration and maximum thickness S of drift buffer region 17'' are b The value of is selected within the ranges given above so as not to substantially change the on-resistance of MOSFET 10'.

[0122] The advantages offered by the present disclosure are apparent from a review of the features of the present disclosure made in accordance with the present disclosure.

[0123] The presence of doped pocket region 25 allows the ringing phenomenon in MOSFET 10' of device 10 to be effectively reduced during the "recovery" phase of MOSFET 10', without negatively altering other electrical and physical characteristics of device 10.

[0124] Moreover, this advantage is achieved without slowing down the switching speed of MOSFET 10 ′, without increasing the area of ​​device 10 , and without adding complex electronic circuitry external to device 10 .

[0125] Furthermore, the doped pocket regions 25 may be formed in the drift layer 17 by implantation or "channeling" of doping species. This allows the device 10 to be manufactured in a simple manner and ensures precise control of the size of the doped pocket regions 25 and therefore precise control of the electrical properties of the device 10, particularly with respect to the channeling technique.

[0126] Furthermore, the use of the drift layer 17, including the drift buffer region 17'' and the drift main region 17', prevents the MOSFET 10' of the device 10 from exhibiting snappy behavior, thereby improving the electrical characteristics, operation and reliability of the device 10.

[0127] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure, as defined in the appended claims, For example, different embodiments described may be combined with one another to provide further solutions.

[0128] The shape, number and location of the doped pocket regions 25 may vary as previously described and within the ranges previously described.

[0129] Moreover, the foregoing indicates that the device 10 is a single part 10' a or 10' b (eg, having only a first MOSFET portion 10'a).

[0130] Furthermore, in a manner known per se, the drift layer 17 of the device 10 may include a current spreading layer (CSL) 40, as shown in FIG.

[0131] In particular, Figure 9 shows, by way of example, an embodiment of device 10 similar to that of Figure 1. Nevertheless, CSL 40 may be present in each of the embodiments described herein as well.

[0132] CSL 40 extends from top surface 15a of semiconductor body 15 towards substrate 16 and into drift layer 17 (in particular, into drift primary region 17') without reaching substrate 16, such that body region 19 is contained (e.g., completely contained) within CSL 40. In particular, CSL 40 is at a distance along axis Z from substrate 16 and from drift buffer region 17'', if present.

[0133] For example, below body region 19 along axis Z, CSL 40 has a thickness equal to about 0.1 μm or 0.2 μm. In other words, CSL 40 has an upper surface 40a (forming upper surface 17a of drift layer 17) and a lower surface 40b opposite each other along axis Z. Lower surface 40b of CSL 40 extends below body region 19 along axis Z and is spaced apart from lower surface 19b of body region 19 along axis Z by about 0.1 μm to 0.2 μm.

[0134] The CSL 40 has a first conductivity type (here N-type) and a CSL dopant concentration that is higher than the second dopant concentration (e.g., about 1×10 17 at / cm 3 degree).

[0135] As is known, the CSL 40 increases and homogenizes the spreading of the charge flow flowing beneath the gate structure 21 in the drift layer 17 .

[0136] Furthermore, as shown in Figures 10A and 10B, the shape of the doped pocket region 25 in the plane XY may vary.

[0137] In particular, Figures 10A and 10B show a top view (i.e., a view parallel to plane XY) of device 10. For ease of viewing, Figures 10A and 10B show only top surface 15a of semiconductor body 15, and show doped pocket regions 25 embedded in semiconductor body 15 in dashed lines. In other words, other elements of device 10 previously described (e.g., body region 19, source region 20, gate structure 21, etc.) are not shown here so as not to obscure understanding of the figures, although they are clearly present.

[0138] 10A shows an embodiment of the device 10 previously described, in which the doped pocket region 25 has the shape of a strip having a main extension parallel to the axis Y and a length along the axis Y that is substantially equal to the length of the body region 19 along the axis Y. For example, in this figure, the doped pocket region 25 has a rectangular shape.

[0139] Nevertheless, the shape of the doped pocket region 25 parallel to the axis Y may be different, for example as shown in FIG. 10B.

[0140] For example, the doped pocket region 25 may be discontinuous parallel to the axis Y.

[0141] In particular, Fig. 10B shows the case where the doped pocket regions 25 are arranged in a matrix or checkerboard pattern parallel to the plane XY. In the matrix, the doped pocket regions 25 may be aligned in columns parallel to the axis Y (as shown in Fig. 10A) or may not be aligned with each other parallel to the axis Y (for example, the doped pocket regions 25 of a row may be laterally offset with respect to the doped pocket regions 25 of the two first adjacent rows adjacent to the row in the matrix, and may be aligned parallel to the axis Y with the doped pocket regions 25 of the two rows adjacent to these two first adjacent rows in the matrix).

[0142] Parallel to the plane XY, these doped pocket regions 25 may have a rectangular shape (as shown in FIG. 10B), a square shape, a circular shape, a hexagonal shape, etc.

[0143] 11, device 10 may have drift layer 17 including drift buffer region 17'' and drift main region 17', and may instead not have doped pocket region 25. In this embodiment, where doped pocket region 25 is absent, device 10 does not have snappy behavior and therefore can operate in an optimized manner at high power.

[0144] The electronic device (10) includes a semiconductor body (15) of silicon carbide (SiC) having an upper surface (15a) and a lower surface (15b) opposed to one another along a first axis (Z), the semiconductor body (15) including a drain substrate (16) extending into the semiconductor body (15) beginning at the lower surface (15b) of the semiconductor body (15) and having a first conductivity type and a first dopant concentration, and a semiconductor substrate (16) extending from the upper surface (15a) of the semiconductor body (15) to the drain substrate (16). a drift layer (17) extending into the body (15) and having a first conductivity type and a second dopant concentration lower than the first dopant concentration; at least one first body region (19) originating from a top surface (15a) of the semiconductor body (15) and extending into the semiconductor body (15) away from the drain substrate (16) and contained within the drift layer (17) and having a second conductivity type opposite to the first conductivity type; and at least one first source region (20) having a first conductivity type, the first source region (20) being received within the first body region (19) so as to extend and be spaced apart from the drift layer (17). The electronic device (10) includes a semiconductor body (15) having a top surface (15a) of the semiconductor body (15) so as to form, together with the first source region (20), the first body region (19), the drift layer (17) and the drain substrate (16), a first MOSFET portion (10'a) of the first MOSFET (10'). and further including at least one first gate structure (21) overlaid on the first body region (19) along a first axis (Z), the semiconductor body (15) being embedded within the drift layer (17), having a second conductivity type and further including at least one first doped pocket region (25) at least partially aligned with the first source region (20) and / or the first gate structure (21) along the first axis (Z).

[0145] The first doped pocket region (25) has a minimum doped pocket distance (D) from the drain substrate (16) along a first axis (Z). s ), the first body region (19) may have a minimum body distance (D) from the drain substrate (16) along a first axis (Z). b) and the minimum doped pocket distance (D s ) and minimum body distance (D b ) the first ratio (D s / D b ) can be between 0% and 70% or equal to 0% or 70%.

[0146] When the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 0 A / ns and 1 A / ns or equal to 1 A / ns, the first ratio (D s / D b ) may be between 0% and 70%, or may be equal to 0% or 70%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 1 A / ns and 2 A / ns or equal to 2 A / ns, the first ratio (D s / D b ) may be between 0% and 60%, or may be equal to 0% or 60%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 2 A / ns and 3 A / ns or equal to 3 A / ns, the first ratio (D s / D b ) may be between 0% and 50%, or may be equal to 0% or 50%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 3 A / ns and 4 A / ns or equal to 4 A / ns, the first ratio (D s / D b ) may be between 0% and 40%, or may be equal to 0% or 40%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 4 A / ns and 5 A / ns or equal to 5 A / ns, the first ratio (D s / D b ) may be between 0% and 30%, or may be equal to 0% or 30%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 5 A / ns and 6 A / ns or equal to 6 A / ns, the first ratio (D s / D b) may be between 0% and 20%, or may be equal to 0% or 20%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) between 6 A / ns and 7 A / ns or equal to 7 A / ns, the first ratio (D s / D b ) may be between 0% and 10%, or may be equal to 0% or 10%. If the first MOSFET (10') is configured to operate with a recovery current rate of change (di / dt) of 7 A / ns or greater, the first doped pocket region (25) may be in contact with the drain substrate (16).

[0147] The first doped pocket region (25) has a maximum doped pocket width (L) along a second axis (X) perpendicular to the first axis (Z). s ), and the first MOSFET (10') may have an average MOSFET width (L m ), and a maximum doped pocket width (L s ) and average MOSFET width (L m ) the second ratio (L s / L m ) may be between 15% and 30% or equal to 15% or 30%.

[0148] The first doped pocket region (25) has a maximum doped pocket thickness (S s ), and a maximum doped pocket thickness (S s ) and minimum body distance (D b ) the third ratio (S s / D b ) may be between 10% and 30% or equal to 10% or 30%.

[0149] The first doped pocket (25) can have a doped pocket dopant concentration that is higher than the second dopant concentration of the drift layer (17), and in particular, can be greater than 1×10 17 at / cm 3 ~5×10 17 at / cm 3 or 1 x 1017 at / cm 3 Or 5 x 10 17 at / cm 3 may be equal to

[0150] The first doped pocket region (25) may be aligned with the first source region (20) and offset with respect to the first gate structure (21) along the first axis (Z), or may be aligned with the first gate structure (21) and offset with respect to the first source region (20), or may be partially aligned with the first source region (20) and partially aligned with the first gate structure (21).

[0151] The semiconductor body (15) includes at least one second body region (19) having a second conductivity type, the second body region (19) being located to the side of the first body region (19) perpendicular to the first axis (Z) and spaced from the first body region (19) perpendicular to the first axis (Z), and contained within the drift layer (17). and at least one second source region (20) having the first conductivity type, the second source region (20) extending into the semiconductor body (15) and contained within the second body region (19) so as to be spaced apart from the drift layer (17), the first gate structure (21) also defining a second MOSFET portion (10') of the first MOSFET (10') together with the second source region (20), the second body region (19), the drift layer (17) and the drain substrate (16). b ), and the semiconductor body (15) may further include at least one second doped pocket region (25) embedded in the drift layer (17), having a second conductivity type, and at least partially aligned with the second source region (20) and / or the first gate structure (21) parallel to the first axis (Z).

[0152] The first doped pocket region (25) and the second doped pocket region (25) may be at least partially aligned with each other perpendicular to the first axis (Z) or may be offset relative to each other perpendicular to the first axis (Z).

[0153] The semiconductor body (15) may further include at least one third source region (20) having a first conductivity type, the third source region (20) extending into the semiconductor body (15) starting from the top surface (15a) of the semiconductor body (15) and contained within the second body region (19) to a side of the second source region (20) and spaced apart from the drift layer (17) and the second source region (20), and the electronic device (10) together with the third source region (20), the second body region (19), the drift layer (17) and the drain substrate (16) form a first MOSFET portion (10') of each of the second MOSFETs (10'). a The semiconductor body (15) may further include at least one second gate structure (21) extending above the top surface (15a) of the semiconductor body (15), laterally of the first gate structure (21) and superimposed parallel to the first axis (Z) on the second body region (19) so as to form a third source region (20) and / or a second gate structure (21), and the semiconductor body (15) may further include at least one third doped pocket region (25) embedded in the drift layer (17), having the second conductivity type and at least partially aligned parallel to the first axis (Z) with the third source region (20) and / or the second gate structure (21).

[0154] The semiconductor body (15) may further include at least one further doped pocket region (25) embedded in the drift layer (17), having a second conductivity type and at least partially aligned with the first doped pocket region (25) along the first axis (Z).

[0155] The drift layer (17) may include a drift primary region (17') and a drift buffer region (17''), the drift buffer region (17'') being interposed along a first axis (Z) between the drift primary region (17') and the drain substrate (16), the drift primary region (17') may have a first conductivity type and a second dopant concentration, and the drift buffer region (17'') may have a buffer dopant concentration higher than the first conductivity type and the second dopant concentration.

[0156] The buffer dopant concentration in the drift buffer region (17'') is 25% higher than the second dopant concentration to 3×10 16 at / cm 3 or between 25% higher than the first dopant concentration or 3×10 16 at / cm 3 may be equal to

[0157] The drift buffer region (17'') has a maximum thickness (S b ), and may have a maximum thickness (S b ) and minimum body distance (D b ) the fourth ratio (S b / D b ) may be between 30% and 50% or equal to 30% or 50%.

[0158] The apparatus can be summarized as including an electronic device (10).

[0159] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned herein and / or listed in the Application Data Sheets are incorporated herein by reference in their entirety. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0160] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. An electronic device comprising: a silicon carbide semiconductor body having upper and lower surfaces opposed along a first axis; The semiconductor body comprises: a drain substrate beginning at the lower surface of the semiconductor body and extending into the semiconductor body, the drain substrate having a first conductivity type and a first dopant concentration; a drift layer beginning at the top surface of the semiconductor body and extending into the semiconductor body to the drain substrate, the drift layer having the first conductivity type and a second dopant concentration less than the first dopant concentration; at least one first body region beginning at the top surface of the semiconductor body and extending into the semiconductor body away from the drain substrate and contained within the drift layer, the first body region having a second conductivity type opposite to the first conductivity type; at least one first source region having the first conductivity type, the first source region extending into the semiconductor body from the top surface of the semiconductor body and contained within the first body region so as to be spaced apart from the drift layer; Including, The electronic device comprises: at least one first gate structure extending on the top surface of the semiconductor body and superimposed on the first body region along the first axis to form, together with the first source region, the first body region, the drift layer, and the drain substrate, a first MOSFET portion of a first MOSFET; the semiconductor body further comprises at least one first doped pocket region embedded in the drift layer, having the second conductivity type, and at least partially aligned with the first source region and / or the first gate structure along the first axis.

2. the first doped pocket region has a minimum doped pocket distance from the drain substrate along the first axis, and the first body region has a minimum body distance from the drain substrate along the first axis; The electronic device of claim 1 , wherein a first ratio between the minimum doped pocket distance and the minimum body distance is between 0% and 70% or is equal to 0% or 70%.

3. when the first MOSFET is configured to operate with a rate of change of the recovery current of 1 A / ns or less, the first ratio is greater than or equal to 0% and less than or equal to 70%; when the first MOSFET is configured to operate with the rate of change of the recovery current between 1 A / ns and 2 A / ns or equal to 2 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 60%; when the first MOSFET is configured to operate with the rate of change of the recovery current between 2 A / ns and 3 A / ns or equal to 3 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 50%; when the first MOSFET is configured to operate at the rate of change of the recovery current between 3 A / ns and 4 A / ns or equal to 4 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 40%; when the first MOSFET is configured to operate at the rate of change of the recovery current between 4 A / ns and 5 A / ns or equal to 5 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 30%; when the first MOSFET is configured to operate at the rate of change of the recovery current between 5 A / ns and 6 A / ns or equal to 6 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 20%; when the first MOSFET is configured to operate at the rate of change of the recovery current between 6 A / ns and 7 A / ns or equal to 7 A / ns, the first ratio is greater than or equal to 0% and less than or equal to 10%; 3. The electronic device of claim 2, wherein the first doped pocket region is in contact with the drain substrate when the first MOSFET is configured to operate at the rate of change of the recovery current of 7 A / ns or greater.

4. the first doped pocket region has a maximum doped pocket width along a second axis orthogonal to the first axis, and the first MOSFET has an average MOSFET width along the second axis; The electronic device of claim 1 , wherein a second ratio between the maximum doped pocket width and the average MOSFET width is between 15% and 30% or is equal to 15% or 30%.

5. the first doped pocket region has a maximum doped pocket thickness along the first axis; The electronic device of claim 2 , wherein a third ratio between the maximum doped pocket thickness and the minimum body distance is between 10% and 30% or is equal to 10% or 30%.

6. The first doped pocket region has a doped pocket dopant concentration that is higher than the second dopant concentration of the drift layer, and in particular, is greater than or equal to 1×10 １７ at / cm ３ ~5×10 １７ at / cm ３ or 1×10 １７ at / cm ３ Or 5 x 10 １７ at / cm ３ The electronic device of claim 1 , wherein

7. The first doped pocket region has a width along the first axis: aligned with the first source region and offset with respect to the first gate structure; or aligned with the first gate structure and offset with respect to the first source region; or 10. The electronic device of claim 1, partially aligned with said first source region and partially aligned with said first gate structure.

8. the semiconductor body being at least one second body region originating from the top surface of the semiconductor body and extending into the semiconductor body away from the drain substrate, to the side of the first body region perpendicular to the first axis and spaced apart from the first body region perpendicular to the first axis, contained within the drift layer, and having the second conductivity type; at least one second source region originating from the top surface of the semiconductor body and extending into the semiconductor body and contained within the second body region so as to be spaced apart from the drift layer, the second source region having the first conductivity type; Further comprising: the first gate structure is also superimposed parallel to the first axis on the second body region to form, together with the second source region, the second body region, the drift layer, and the drain substrate, a second MOSFET portion of the first MOSFET; 2. The electronics device of claim 1, wherein the semiconductor body further comprises at least one second doped pocket region embedded in the drift layer, having the second conductivity type, and at least partially aligned with the second source region and / or the first gate structure parallel to the first axis.

9. 9. The electronic device of claim 8, wherein the first doped pocket region and the second doped pocket region are at least partially aligned with each other perpendicular to the first axis or are offset relative to each other perpendicular to the first axis.

10. the semiconductor body further includes at least one third source region having the first conductivity type, the third source region extending into the semiconductor body starting from the top surface of the semiconductor body and contained within the second body region to be spaced apart from the drift layer and the second source region to the side of the second source region; the electronic device further comprises at least one second gate structure extending above the top surface of the semiconductor body, to the side of the first gate structure and superimposed on the second body region parallel to the first axis to form, together with the third source region, the second body region, the drift layer and the drain substrate, a first MOSFET portion of each of the second MOSFETs; 9. The electronics device of claim 8, wherein the semiconductor body further comprises at least one third doped pocket region embedded in the drift layer, having the second conductivity type, and at least partially aligned with the third source region and / or the second gate structure parallel to the first axis.

11. 2. The electronics device of claim 1 , wherein the semiconductor body further comprises at least one additional doped pocket region embedded in the drift layer, having the second conductivity type, and at least partially aligned with the first doped pocket region along the first axis.

12. the drift layer includes a drift main region and a drift buffer region interposed between the drift main region and the drain substrate along the first axis; 2. The electronics device of claim 1, wherein the drift primary region has the first conductivity type and the second dopant concentration, and the drift buffer region has a buffer dopant concentration higher than the first conductivity type and the second dopant concentration.

13. The buffer dopant concentration of the drift buffer region is between 25% higher than the second dopant concentration and 3×10 １６ at / cm ３ or a concentration 25% higher than the second dopant concentration or 3×10 １６ at / cm ３ The electronic device of claim 12 , wherein

14. the drift buffer region has a maximum thickness along the first axis; The electronic device of claim 2 , wherein a fourth ratio between the maximum thickness and the minimum body distance is between 30% and 50% or is equal to 30% or 50%.

15. An electronic device comprising: a semiconductor body of silicon carbide; The semiconductor body comprises: a drain substrate of a first conductivity type and a first dopant concentration; a drift layer located above the drain substrate, the drift layer having the first conductivity type and a second dopant concentration lower than the first dopant concentration; a body region having a top surface coplanar with a top surface of the drift layer and separated from the drain substrate by the drift layer, the body region having a second conductivity type opposite to the first conductivity type; a source region having the first conductivity type embedded in the body region and separated from the drift layer by the body region; a first doped pocket region of the second conductivity type embedded in the drift layer and having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate; Including, The electronic device comprises: a gate structure overlying at least a portion of the first body region and at least a portion of the first doped pocket region; the source region, the body region, the drift layer and the drain substrate form a MOSFET.

16. The electronic device of claim 15 , wherein the first doped pocket region and the gate structure are aligned on the same vertical axis.

17. 17. The electronics device of claim 16, wherein the semiconductor body includes a second doped pocket region of the second conductivity type embedded in the drift layer and having a top surface lower than the bottom surface of the body region and a bottom surface higher than the top surface of the drain substrate, the second doped pocket region being directly the body region.

18. 1. A method of manufacturing an electronic device, comprising: forming a semiconductor body of silicon carbide; forming a drain substrate of a MOSFET of a first conductivity type and a first dopant concentration in the semiconductor body; forming a drift layer of the MOSFET in the semiconductor body above the drain substrate, the drift layer having the first conductivity type and a second dopant concentration less than the first dopant concentration; forming a body region of the MOSFET in the semiconductor body, the body region having a top surface coplanar with a top surface of the drift layer and separated from the drain substrate by the drift layer, the body region having a second conductivity type opposite to the first conductivity type; forming a source region of the MOSFET having the first conductivity type embedded in the body region and separated from the drift layer by the body region; forming a first doped pocket region of the second conductivity type embedded in the drift layer and having an upper surface lower than a bottom surface of the body region and a bottom surface higher than an upper surface of the drain substrate; forming a gate structure of the MOSFET overlying at least a portion of the first body region and at least a portion of the first doped pocket region; A method comprising:

19. 20. The method of claim 18, wherein the first doped pocket region and the gate structure are aligned on the same vertical axis.

20. 20. The method of claim 19, comprising forming a second doped pocket region of the second conductivity type embedded in the drift layer and having a top surface lower than the bottom surface of the body region and a bottom surface higher than the top surface of the drain substrate, the second doped pocket region being directly the body region.

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