Imaging device

Abstract

To provide an imaging device capable of reducing image quality degradation resulting from voltage change at a counter electrode.SOLUTION: An imaging device includes: a photoelectric conversion part 11 including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, for generating signal charge; a charge accumulation part (FD) connected to the first electrode, for accumulating the signal charge; a first voltage supply circuit 30 connected to the second electrode, for selectively supplying one voltage from a plurality of voltages including a first voltage and a third voltage higher than the first voltage; and a second voltage supply circuit 21 connected to the charge accumulation part through a capacitor, for selectively supplying one voltage from a plurality of voltages including a second voltage and a fourth voltage lower than the second voltage. The first voltage supply circuit 30 supplies the first voltage during at least a part of a period of an accumulation period for accumulating the signal charge in the charge accumulation part, and the second voltage supply circuit 21 supplies the second voltage during the accumulation period.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Patent Document 1 discloses an imaging element in which a photosensitive layer (photoelectric conversion layer) is laminated on a substrate. In the technology described in Patent Document 1, the photosensitive layer is sandwiched between a pixel electrode layer and a counter electrode layer. The sensitivity of the photosensitive layer is controlled by adjusting the pulse width of a pulse voltage applied between the pixel electrode layer and the counter electrode layer.

[0003] Patent Document 2 discloses an imaging device capable of implementing a global shutter function. In the technology described in Patent Document 2, sensitivity is controlled by a voltage applied between a pixel electrode and a counter electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-104114 A [Patent Document 2] JP 2017-216743 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides an imaging device that reduces image quality degradation caused by potential changes in a counter electrode. [Means for solving the problem]

[0006] An imaging device according to one embodiment of the present disclosure includes a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and generates signal charges; a charge accumulation unit connected to the first electrode and accumulating the signal charges; a first voltage supply circuit connected to the second electrode and selectively supplying one of a plurality of voltages including a first voltage and a third voltage greater than the first voltage; and a second voltage supply circuit connected to the charge accumulation unit via a capacitance and selectively supplying one of a plurality of voltages including a second voltage and a fourth voltage less than the second voltage, wherein the first voltage supply circuit supplies the first voltage during at least a portion of an accumulation period for accumulating the signal charges in the charge accumulation unit, and the second voltage supply circuit supplies the second voltage during the accumulation period.

[0007] The present disclosure also relates to a method for driving an imaging device including a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode and generating signal charges, a charge accumulation unit connected to the first electrode and accumulating the signal charges, a first voltage supply circuit connected to the second electrode and selectively supplying one of a plurality of voltages including a first voltage and a third voltage greater than the first voltage, and a second voltage supply circuit connected to the charge accumulation unit via a capacitance and selectively supplying one of a plurality of voltages including a second voltage and a fourth voltage less than the second voltage, wherein the method may include the first voltage supply circuit supplying the first voltage during at least a portion of an accumulation period for accumulating the signal charges in the charge accumulation unit, and the second voltage supply circuit supplying the second voltage during the accumulation period. Effect of the Invention

[0008] According to the imaging device of the present disclosure, it is possible to reduce deterioration in image quality caused by changes in the potential of the counter electrode. [Brief description of the drawings]

[0009] [Figure 1A]FIG. 1A is a block diagram illustrating an example of a configuration of an imaging device according to the first embodiment. [Figure 1B] FIG. 1B is a diagram showing an equivalent circuit of the photoelectric conversion unit 11 in FIG. 1A. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of the second voltage supply circuit and the pixel cell according to the first embodiment. [Diagram 3] FIG. 3 is a schematic diagram showing an example of a cross section of a pixel cell according to the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram illustrating an example of photocurrent characteristics of the photoelectric conversion unit according to the first embodiment. [Figure 5A] FIG. 5A is a time chart showing an example of a read operation of the imaging device according to the first embodiment. [Figure 5B] FIG. 5B is a time chart showing an example of the operation of the imaging device according to the first embodiment. [Figure 6] FIG. 6 is a time chart showing an example of the operation of an imaging device according to a comparative example. [Figure 7] FIG. 7 is a time chart showing an example of the operation of the imaging device according to the first embodiment. [Figure 8] FIG. 8 is a time chart showing an example of operation of the imaging device according to the first embodiment in a modified example. [Figure 9A] FIG. 9A is a diagram showing an image captured by an imaging device according to a comparative example. [Figure 9B] FIG. 9B is a diagram showing an image captured by the imaging device according to the first embodiment. [Figure 10] FIG. 10 is a time chart showing an example of the operation of the imaging device according to the second embodiment. [Figure 11] FIG. 11 is a time chart showing an example of the operation of an imaging device according to a comparative example. [Figure 12] FIG. 12 is a time chart showing an example of the operation of the imaging device according to the second embodiment. [Figure 13] FIG. 13 is a time chart showing an example of the operation of the imaging device according to the third embodiment. [Figure 14]FIG. 14 is a time chart showing an example of the operation of an imaging device according to a comparative example. [Figure 15] FIG. 15 is a time chart showing an example of the operation of the imaging device according to the third embodiment. [Figure 16] FIG. 16 is a block diagram illustrating an example of a configuration of an imaging device according to the fourth embodiment. As shown in FIG. [Figure 17A] FIG. 17A is a block diagram showing an example of an arrangement of effective pixel regions and invalid pixel regions according to the fourth embodiment. [Figure 17B] FIG. 17B is a block diagram showing another example of the arrangement of the effective pixel region and the invalid pixel region according to the fourth embodiment. [Figure 18A] FIG. 18A is an explanatory diagram showing an example of a read operation of an effective pixel region and an ineffective pixel region according to the fourth embodiment. [Figure 18B] FIG. 18B is an explanatory diagram showing another example of the readout operation of the effective pixel region and the ineffective pixel region according to the fourth embodiment. [Figure 19] FIG. 19 is a diagram showing an example of change timing of the voltage of the counter electrode according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Findings that have led to one aspect of the present disclosure) As disclosed in Patent Document 1, the sensitivity can be controlled by applying a pulse voltage between a pixel electrode and a counter electrode and controlling the duty of the voltage.

[0011] Specifically, for example, a pulse voltage is applied to the counter electrode to perform duty control. That is, a high voltage and a low voltage are applied alternately to the counter electrode, and the ratio of the length of the period during which the high voltage is applied to the period during which the low voltage is applied is changed. This allows the sensitivity to be changed. In such sensitivity control, for example, when the period during which the high voltage is applied to the counter electrode is extended to set high sensitivity, it is easier to secure the time required for reading and resetting during the period during which the high voltage is applied to the counter electrode. Conversely, when the period during which the low voltage is applied to the counter electrode is extended to set low sensitivity, it is easier to secure the time required for reading and resetting during the period during which the low voltage is applied to the counter electrode. That is, it is desirable to select for each frame whether to read and reset when the potential of the counter electrode is a high voltage or to read and reset when the potential of the counter electrode is a low voltage according to the duty of the pulse voltage.

[0012] The inventors discovered that a phenomenon occurs in which the density of the obtained image changes significantly in the frame immediately after changing whether to perform readout and resetting when the potential of the opposing electrode is a high voltage or to perform readout and resetting when the potential of the opposing electrode is a low voltage.

[0013] According to the inventors' investigation, this phenomenon is caused by the change in the potential of the pixel electrode accompanying the change in the potential of the counter electrode due to the coupling caused by the capacitance between the counter electrode and the pixel electrode. A detailed explanation will be given later.

[0014] In addition, the change in the potential of the pixel electrode caused by the change in the potential of the counter electrode changes the intensity of the electric field formed between the counter electrode and the pixel electrode during the exposure period, and therefore the change in the potential of the counter electrode can also affect the maximum sensitivity and the saturation charge amount.

[0015] Furthermore, when an impurity region for storing signal charges is provided in the semiconductor substrate, the potential change of the pixel electrode accompanying the potential change of the counter electrode changes the potential difference between the impurity region and the adjacent region, and therefore the potential change of the counter electrode can cause the signal charges stored in the impurity region to leak.

[0016] In this way, when control is performed to change the potential of the counter electrode, there is a problem that deterioration of image quality may occur.

[0017] Therefore, the present disclosure provides an imaging device and a driving method thereof that reduce image quality degradation caused by potential changes in the counter electrode.

[0018] Therefore, the imaging device according to the present disclosure includes a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and generates signal charges by photoelectric conversion, a capacitive element having a first terminal connected to the first electrode and a second terminal, a first voltage supply circuit that selectively supplies at least two different voltages to the second electrode, and a second voltage supply circuit that selectively supplies at least two different voltages to the second terminal.

[0019] This makes it possible to control the potential fluctuation of the first electrode accompanying the potential change of the second electrode, which is the opposing electrode, and to reduce image quality degradation caused by the potential change of the opposing electrode.

[0020] Here, in a predetermined period of each of a plurality of frames, the first voltage supply circuit supplies to the second electrode one of a plurality of voltages including a first voltage and a third voltage greater than the first voltage. When the first voltage supply circuit supplies the first voltage to the second electrode in the predetermined period, the second voltage supply circuit supplies a second voltage to the second terminal, and when the first voltage supply circuit supplies the third voltage to the second electrode in the predetermined period, the second voltage supply circuit may supply to the second terminal a fourth voltage smaller than the second voltage.

[0021] This makes it possible to reduce fluctuations in the potential of the first electrode caused by switching the potential of the second electrode even when each of the first voltage supply circuit and the second voltage supply circuit supplies three voltage levels.

[0022] Here, the multiple voltages may further include a fifth voltage greater than the first voltage and less than the third voltage, and when the first voltage supply circuit supplies the fifth voltage to the second electrode during the specified period, the second voltage supply circuit may supply a sixth voltage less than the second voltage and greater than the fourth voltage to the second terminal.

[0023] According to this, since the voltage of the second voltage supply circuit is in an opposite phase to the voltage of the first voltage supply circuit, it is possible to cancel or reduce the voltage fluctuation of the charge storage node caused by the voltage of the counter electrode, and as a result, it is possible to reduce the deterioration of image quality caused by the potential change of the counter electrode.

[0024] Here, the predetermined period may include a period for reading out a signal corresponding to the potential of the first electrode.

[0025] This makes it possible to reduce fluctuations in the potential of the first electrode caused by switching the potential of the second electrode, which is the opposing electrode, during a period for reading out pixel signals.

[0026] Here, the predetermined period may include a period for resetting the potential of the first electrode.

[0027] This makes it possible to reduce the fluctuation in potential of the first electrode caused by switching the potential of the second electrode (that is, the counter electrode) during the period for reading out the pixel signal and the period for reading out the reference potential.

[0028] Here, the imaging device may further include a first transistor having a gate connected to the first electrode, and the specified period may include a period during which the first transistor outputs a signal corresponding to the potential of the first electrode.

[0029] This makes it possible to reduce the fluctuation in potential of the first electrode caused by switching of the potential of the second electrode during the period in which the first signal corresponding to the signal charge is output from the first transistor.

[0030] Here, the imaging device may further include a second transistor having a source or a drain connected to one of the source and drain of the first transistor, and the specified period may include a period during which the second transistor is in an on state.

[0031] This makes it possible to reduce the fluctuation in potential of the first electrode caused by switching of the potential of the second electrode during the period in which the second transistor is in the on state.

[0032] Here, the imaging device may further include a charge accumulation section connected to the first electrode and accumulating the signal charge, and during an accumulation period in which the signal charge is accumulated in the charge accumulation section, the first voltage supply circuit may alternately supply the first voltage and the third voltage to the second electrode.

[0033] This makes it possible to set the sensitivity of the photoelectric conversion unit to incident light in accordance with the ratio between the alternately generated first voltage and the third voltage.

[0034] Here, the imaging device may further include a charge accumulation section connected to the first electrode and accumulating the signal charge, and during a period during which the first voltage supply circuit supplies the third voltage to the second electrode during an accumulation period for accumulating the signal charge in the charge accumulation section, the second voltage supply circuit may supply the fourth voltage to the second terminal.

[0035] This makes it possible to suppress a decrease in sensitivity and a decrease in saturation in a read mode in which the voltage of the counter electrode is at the first voltage, which is at a low level.

[0036] Here, the imaging device may further include a charge accumulation section connected to the first electrode and accumulating the signal charge, and during a period during which the first voltage supply circuit supplies the first voltage to the second electrode during an accumulation period for accumulating the signal charge in the charge accumulation section, the second voltage supply circuit may supply the second voltage to the second terminal.

[0037] Here, the signal charges may be holes, and the photoelectric conversion unit may have no sensitivity to incident light when the first voltage is supplied to the second electrode, i.e., the sensitivity of the photoelectric conversion unit to incident light when the first voltage is supplied to the second electrode may be substantially zero.

[0038] Here, the signal charges may be electrons, and the photoelectric conversion unit may have no sensitivity to incident light when the third voltage is supplied to the second electrode, i.e., the sensitivity of the photoelectric conversion unit to incident light when the third voltage is supplied to the second electrode may be substantially zero.

[0039] Here, the imaging device may further include a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, each of the plurality of pixels including the photoelectric conversion unit and the capacitive element, and the second voltage supply circuit may selectively supply the at least two different voltages to the second terminal for each row included in the plurality of rows.

[0040] This allows the second voltage supply circuit to supply voltage on a row-by-row basis, thereby reducing image quality degradation caused by potential changes in the opposing electrodes.

[0041] Here, the plurality of pixels may include effective pixels that output signals corresponding to an amount of incident light and ineffective pixels that output an optical black level, and the first voltage supply circuit may supply any one of the plurality of voltages including the first voltage and the third voltage to the second electrode during a period for reading out the signals of the effective pixels in each of a plurality of frames. The first voltage supply circuit may not change the voltage supplied to the second electrode during a period for reading out the signals of the effective pixels in each of a plurality of frames.

[0042] This makes it possible to suppress fluctuations in pixel signals caused by voltage fluctuations in the counter electrode (that is, the second electrode) during the readout period of the effective pixels, thereby making it possible to suppress deterioration in image quality.

[0043] Furthermore, a method of driving an imaging device according to the present disclosure is a method of driving an imaging device including a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and generating signal charges by photoelectric conversion, and a capacitive element having a first terminal connected to the first electrode and a second terminal, the method including: supplying one of a plurality of voltages including a first voltage and a third voltage greater than the first voltage to the second electrode during a predetermined period of each of a plurality of frames; supplying a second voltage to the second terminal when the first voltage is supplied to the second electrode during the predetermined period; and supplying a fourth voltage smaller than the second voltage to the second terminal when the third voltage is supplied to the second electrode during the predetermined period.

[0044] According to this, in a read mode in which the counter voltage is at a high level of the third voltage, the potential of the charge storage node during the accumulation period is increased, thereby preventing the potential of the charge storage node during the readout period from becoming equal to or lower than the reference potential, thereby suppressing degradation of image quality caused by pixel signals being crushed or distorted.

[0045] Hereinafter, the embodiments will be described with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, the arrangement and connection forms of the components, steps, and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, the realization of the present disclosure is not limited to the current independent claims, and may be expressed by other independent claims.

[0046] In addition, each drawing is a schematic diagram and is not necessarily a precise illustration. In addition, in each drawing, the same reference numerals are used for substantially the same configuration, and duplicated explanations may be omitted or simplified.

[0047] In the present disclosure, all or part of a circuit, unit, device, member or part, or all or part of a functional block in a block diagram may be implemented by one or more electronic circuits including, for example, a semiconductor device, a semiconductor integrated circuit (IC), or an LSI (large scale integration). The LSI or IC may be integrated into one chip, or may be configured by combining multiple chips. For example, functional blocks other than memory elements may be integrated into one chip. Here, although it is referred to as an LSI or IC, the name may change depending on the degree of integration, and may be referred to as a system LSI, a VLSI (very large scale integration), or the like. Ultra large scale integration, or ULSI A field programmable gate array (FPGA), which is programmed after the LSI is manufactured, or a reconfigurable logic device, which can reconfigure the connections inside the LSI or set up circuit partitions inside the LSI, can also be used for the same purpose.

[0048] Furthermore, all or part of the functions or operations of a circuit, unit, device, member, or part can be executed by software processing. In this case, the software is recorded in one or more non-transitory recording media such as ROMs, optical disks, hard disk drives, etc., and when the software is executed by a processor, the functions specified in the software are executed by the processor and peripheral devices. The system or device may include one or more non-transitory recording media on which the software is recorded, a processor, and necessary hardware devices, such as interfaces.

[0049] (Embodiment 1) [1.1 Circuit configuration of imaging device] FIG. 1A is a block diagram illustrating an example of a configuration of an imaging device according to the first embodiment.

[0050] The imaging device in the figure includes a plurality of pixel cells 10, a vertical scanning circuit 20, a first voltage supply circuit 30, a column signal processing circuit 40 for each column, and an output selection circuit 41. In addition, the figure also shows vertical signal lines 19 for each column, second voltage supply lines 25 for each row, reset control signal lines 26 for each row, selection control signal lines 27 for each row, and a first voltage supply line 35 common to all pixel cells 10.

[0051] A plurality of pixel cells 10 are arranged in a matrix to form a two-dimensional imaging area.

[0052] The pixel cell 10 includes a photoelectric conversion unit 11, a charge storage node FD, a capacitance element CA, a reset transistor 2, an amplification transistor 3, and an address transistor 4.

[0053] The photoelectric conversion section 11 includes a pixel electrode 12, a counter electrode 13, and a photoelectric conversion layer 14 between the pixel electrode 12 and the counter electrode 13. The pixel electrode 12 corresponds to the above-mentioned first electrode, and the counter electrode 13 corresponds to the above-mentioned second electrode.

[0054] The photoelectric conversion layer 14 corresponds to a portion of a photoelectric conversion film, such as an organic layer, that corresponds to the pixel cell 10 and that covers the entire imaging region.

[0055] The pixel electrode 12 has an area equivalent to the area occupied by the pixel cell 10 in a plan view of the imaging region, and is an electrode for collecting signal charges generated in the photoelectric conversion layer.

[0056] The counter electrode 13 corresponds to a portion of the transparent electrode covering the surface of the photoelectric conversion layer on which incident light is incident, which corresponds to the pixel cell 10. The counter electrode 13 is supplied with a voltage Vito from the first voltage supply circuit 30 via a first voltage supply line 35. The voltage Vito is a common voltage to all pixel cells 10 for controlling the sensitivity of the photoelectric conversion unit 11 to incident light, and is selectively supplied from at least two different voltages. In the following, the voltage Vito is selectively set to a low level or a high level. The low level voltage of the voltage Vito is referred to as voltage V1, and the high level voltage of the voltage Vito is referred to as voltage V3. The voltage V1 corresponds to the first voltage described above. The voltage V3 corresponds to the third voltage described above.

[0057] The charge storage node FD functions as a charge storage unit that stores the signal charges collected by the pixel electrode 12. The charge storage node FD may include, for example, a diffusion layer that is an impurity region provided in a semiconductor substrate, or may include a capacitor. The charge storage node FD is also called a floating diffusion node (FD node).

[0058] The capacitance element CA is a capacitance element having a first terminal 17 connected to the pixel electrode 12 and a second terminal 18, and has a function of offsetting or reducing the voltage fluctuation of the charge storage node FD caused by the voltage Vito. For this reason, a voltage VA for offsetting or reducing is supplied to the second terminal 18 from a second voltage supply circuit 21. The voltage VA is a voltage for offsetting or reducing the voltage fluctuation of the charge storage node FD caused by the voltage Vito, and selectively has two values, low level and high level, for the two-value voltage Vito. Hereinafter, the high level voltage of the voltage VA may be referred to as voltage V2, and the low level voltage of the voltage VA may be referred to as voltage V4. The voltage V2 corresponds to the second voltage described above. The voltage V4 corresponds to the fourth voltage described above.

[0059] The reset transistor 2 is a switch transistor that resets the charge storage node FD to a reference potential in accordance with a reset control signal Vrst input to a gate connected to a reset control signal line 26 .

[0060] The amplifier transistor 3 configures a source follower circuit that outputs the potential of the gate connected to the charge storage node FD from the source as a pixel signal. The amplifier transistor 3 corresponds to the above-mentioned first transistor.

[0061] The address transistor 4 is a switch transistor that is turned on and off in accordance with a selection control signal Vsel (or an address signal) input to a gate connected to a selection control signal line 27. When the address transistor 4 is on, a pixel signal from the amplification transistor 3 is output to a vertical signal line 19. The address transistor 4 corresponds to the above-mentioned second transistor.

[0062] The vertical scanning circuit 20 controls the reset and selection for each row by scanning the multiple pixel cells 10 on a row-by-row basis. Therefore, the vertical scanning circuit 20 is connected to a second voltage supply line 25, a reset control signal line 26, and a selection control signal line 27 provided for each row, and outputs a voltage VA, a reset control signal Vrst, and a selection control signal Vsel for each row. The vertical scanning circuit 20 also has a second voltage supply circuit 21.

[0063] The second voltage supply circuit 21 selectively supplies at least two different voltages to the second terminal 18 of the capacitance element CA. Fig. 2 is a block diagram showing a configuration example of the second voltage supply circuit 21 and the pixel cell 10 according to the first embodiment. As shown in Fig. 2, the second voltage supply circuit 21 is connected to second voltage supply lines 25 provided for each row, and selectively supplies a high-level voltage V2 and a low-level voltage V4 as the voltage VA on a row-by-row basis.

[0064] The first voltage supply circuit 30 selectively supplies at least two different voltages Vito to the counter electrode 13 via the first voltage supply line 35. Since the counter electrode 13 corresponds to a portion of the transparent electrode covering the surface of the photoelectric conversion layer that corresponds to the pixel cells 10, the voltage Vito supplied by the first voltage supply circuit 30 is common to all the pixel cells 10 and controls the sensitivity of the photoelectric conversion unit 11. Here, the voltage Vito is set to either the voltage V1 or the voltage V3. In this case, the sensitivity is controlled by the ratio between the time when the voltage V1 is applied and the time when the voltage V3 is applied, that is, the duty. For example, when the voltage V1 corresponds to low sensitivity, for example, zero sensitivity, and the voltage V3 corresponds to high sensitivity, the sensitivity can be set continuously or stepwise from zero sensitivity to high sensitivity according to the above duty. Also, when the voltage V1 corresponds to zero sensitivity, the state in which the voltage V1 is applied corresponds to the state in which the shutter is closed in the electronic shutter function.

[0065] A column signal processing circuit 40 is provided for each column. The column signal processing circuit 40 processes signals output from pixel cells 10 in a row selected by the vertical scanning circuit 20 via vertical signal lines 19. A pixel signal corresponding to the amount of signal charge accumulated in a charge accumulation node FD and a reference signal indicating a reference potential or a reset level are output from the pixel cells 10. The column signal processing circuit 40 performs correlated double sampling (CDS) and analog-to-digital conversion.

[0066] The output selection circuit 41 selectively outputs from an output terminal 42 signals output from the column signal processing circuits 40, the number of which is the same as the number of columns.

[0067] [1.2 Device structure of pixel cell 10] Next, the configuration of a pixel cell 10 formed as a semiconductor device will be described with reference to a cross-sectional view.

[0068] Fig. 3 is a schematic diagram showing an example of a cross section of a pixel cell 10 according to the first embodiment. In the configuration shown in Fig. 3, the above-mentioned reset transistor 2, amplifying transistor 3, and address transistor 4 are formed on a semiconductor substrate 7. The semiconductor substrate 7 is not limited to a substrate whose entirety is made of a semiconductor. The semiconductor substrate 7 may be an insulating substrate having a semiconductor layer provided on the surface on which the photosensitive region is formed. Here, an example in which a P-type silicon substrate is used as the semiconductor substrate 7 will be described.

[0069] The semiconductor substrate 7 has impurity regions (here, N-type regions) 4d, 3s, 3d, 2d, and 2s, and an element isolation region 9 for electrical isolation between pixel cells 10. Here, the element isolation region 9 is also provided between the impurity region 3s and the impurity region 2d. The element isolation region 9 is formed, for example, by ion implantation of an acceptor under predetermined implantation conditions.

[0070] The impurity regions 4d, 3s, 3d, 2d, and 2s are typically diffusion layers formed in the semiconductor substrate 7. As shown in FIG. 3, the amplifier transistor 3 includes impurity regions 3s and 3d and a gate electrode 3g. The gate electrode 3g is typically a polysilicon electrode. The impurity region 3s functions as, for example, a source region of the amplifier transistor 3. The impurity region 3d functions as, for example, a drain region of the amplifier transistor 3. A channel region of the amplifier transistor 3 is formed between the impurity regions 3s and 3d.

[0071] Similarly, the address transistor 4 includes impurity regions 4d and 3d and a gate electrode 4g connected to the selection control signal line 27. In this example, the amplification transistor 3 and the address transistor 4 are electrically connected to each other by sharing the impurity region 3d. The impurity region 4d functions as, for example, a drain region of the address transistor 4. The impurity region 4d is connected to the vertical signal line 19 shown in FIG. 1A.

[0072] The reset transistor 2 includes impurity regions 2d and 2s, and a gate electrode 2g connected to a reset control line 48. The impurity region 2s functions as, for example, a source region of the reset transistor 2. The gate electrode 2g is connected to the reset control signal line 26 shown in FIG. 1A.

[0073] An interlayer insulating layer 8 is disposed on the semiconductor substrate 7 so as to cover the amplifying transistor 3, the address transistor 4, and the reset transistor 2. As shown in the figure, a wiring layer 56 may be disposed in the interlayer insulating layer 8. The wiring layer 56 is typically formed of a metal such as copper, and may include, for example, wiring such as the above-mentioned vertical signal line 19 as a part thereof. The number of insulating layers in the interlayer insulating layer 8 and the number of layers included in the wiring layer 56 disposed in the interlayer insulating layer 8 may be set arbitrarily, and are not limited to the example shown in FIG. 3.

[0074] The above-mentioned photoelectric conversion unit 11 is disposed on the interlayer insulating layer 8. In other words, in the embodiment of the present disclosure, a plurality of pixel cells 10 constituting an imaging region are formed on a semiconductor substrate 7. A plurality of pixel cells 10 arranged two-dimensionally on the semiconductor substrate 7 form a pixel region which is a photosensitive region. The pixel pitch, which is the distance between two adjacent pixel cells 10, may be, for example, about 2 μm.

[0075] The photoelectric conversion unit 11 includes a pixel electrode 12, a counter electrode 13, and a photoelectric conversion layer 14 disposed therebetween. In this example, the counter electrode 13 and the photoelectric conversion layer 14 are formed across a plurality of pixel cells 10. On the other hand, the pixel electrode 12 is provided for each pixel cell 10, and is spatially separated from the pixel electrodes 12 of other adjacent pixel cells 10, thereby being electrically separated from the pixel electrodes 12 of the other pixel cells 10.

[0076] The counter electrode 13 is typically a transparent electrode formed of a transparent conductive material. The counter electrode 13 is disposed on the surface of the photoelectric conversion layer 14 on which light is incident. Therefore, light transmitted through the counter electrode 13 is incident on the photoelectric conversion layer 14. The light detected by the imaging device 100 is not limited to light within the wavelength range of visible light (for example, 380 nm or more and 780 nm or less). In this specification, "transparent" means that at least a part of the light in the wavelength range to be detected is transmitted, and it is not essential that light is transmitted over the entire wavelength range of visible light. In this specification, electromagnetic waves in general, including infrared and ultraviolet rays, are expressed as "light" for convenience. For the counter electrode 13, for example, a transparent conductive oxide (TCO) such as ITO, IZO, AZO, FTO, SnO2, TiO2, or ZnO2 can be used.

[0077] The photoelectric conversion layer 14 receives incident light and generates hole-electron pairs. The photoelectric conversion layer 14 is typically formed of a semiconductor material including an organic material. The photoelectric conversion layer 14 may be amorphous silicon or may be quantum dots made of an inorganic material.

[0078] As described with reference to FIG. 1A, the counter electrode 13 is connected to a first voltage supply line 35 for sensitivity control, which is connected to the first voltage supply circuit 30. Here, the counter electrode 13 is formed across a plurality of pixel cells 10. Therefore, it is possible to collectively apply the voltage Vito from the first voltage supply circuit 30 between a plurality of pixel cells 10 via the first voltage supply line 35. Note that, as long as a sensitivity control voltage of a desired magnitude can be applied from the first voltage supply circuit 30, the counter electrode 13 may be provided separately for each pixel cell 10. Similarly, the photoelectric conversion layer 14 may be provided separately for each pixel cell 10.

[0079] By controlling the potential of the counter electrode 13 relative to the potential of the pixel electrode 12, either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 14 by photoelectric conversion can be collected by the pixel electrode 12. For example, when holes are used as signal charges, it is possible to selectively collect the holes by the pixel electrode 12 by setting the potential of the counter electrode 13 higher than that of the pixel electrode 12. The following illustrates an example in which holes are used as signal charges. Of course, it is also possible to use electrons as signal charges.

[0080] The pixel electrode 12 facing the counter electrode 13 collects one of the positive and negative charges generated by photoelectric conversion in the photoelectric conversion layer 14 by applying an appropriate bias voltage between the counter electrode 13 and the pixel electrode 12. The pixel electrode 12 is made of a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to give it electrical conductivity.

[0081] The pixel electrode 12 may be a light-shielding electrode. For example, by forming a TaN electrode having a thickness of 100 nm as the pixel electrode 12, sufficient light-shielding properties can be achieved. By forming the pixel electrode 12 as a light-shielding electrode, the incidence of light passing through the photoelectric conversion layer 14 into the impurity region functioning as the channel region, source region, or drain region of the transistor formed in the semiconductor substrate 7 can be suppressed. In this embodiment, for example, the incidence of light into the amplifying transistor 3, the address transistor 4, and the reset transistor 2 is suppressed. A light-shielding film may be formed in the interlayer insulating layer 8 by utilizing the above-mentioned wiring layer 56. By suppressing the incidence of light into the channel region of the transistor formed in the semiconductor substrate 7, for example, the fluctuation of the threshold voltage of the transistor can be suppressed. In addition, by suppressing the incidence of light into the impurity region formed in the semiconductor substrate 7, the inclusion of noise due to unintended photoelectric conversion in the impurity region can be suppressed. In this way, suppressing the incidence of light into the semiconductor substrate 7 contributes to improving the reliability of the imaging device.

[0082] As shown in FIG. 3, the pixel electrode 12 is connected to the gate electrode 3g of the amplification transistor 3 through the plug 52, the wiring 53, and the contact plug 54. In other words, the gate of the amplification transistor 3 has an electrical connection with the pixel electrode 12. The plug 52 and the wiring 53 are formed of a metal such as copper. The plug 52, the wiring 53, and the contact plug 54 constitute a part of the charge storage node FD. The wiring 53 may be a part of the wiring layer 56. The pixel electrode 12 is also connected to the impurity region 2d through the plug 52, the wiring 53, and the contact plug 55. In the configuration illustrated in FIG. 3, the gate electrode 3g of the amplification transistor 3, the plug 52, the wiring 53, the contact plugs 54 and 55, and the impurity region 2d, which is one of the source region and the drain region of the reset transistor 2, function as a charge storage unit that stores the signal charge collected by the pixel electrode 12.

[0083] A voltage corresponding to the amount of signal charge collected by the pixel electrode 12 and stored in the charge storage section is applied to the gate of the amplifying transistor 3. The amplifying transistor 3 amplifies this voltage. The voltage amplified by the amplifying transistor 3 is selectively read out via the address transistor 4 as a pixel signal.

[0084] The interlayer insulating layer 8 also includes a second voltage supply line 25 connected to the second terminal 18 of the capacitance element CA. Although the capacitance element CA is not shown in FIG. 3, the specific configuration of the capacitance element CA is not particularly limited. The capacitance element CA may have, for example, a MIS (metal-insulator-semiconductor) structure disposed in the interlayer insulating layer 8, or a depletion-type MOS (D Alternatively, it may be a MIM (metal-insulator-metal) structure. If the MIM structure is used, it is easy to obtain a larger capacitance value.

[0085] [1.3 Sensitivity characteristics of photoelectric conversion unit 11] Next, the sensitivity characteristics of the photoelectric conversion section 11 will be described.

[0086] FIG. 4 is an explanatory diagram showing an example of the photocurrent characteristics of the photoelectric conversion unit 11 according to the embodiment. The horizontal axis of the figure shows the voltage Vito applied to the photoelectric conversion unit 11. In addition, in the figure, the range of the voltage Vito is divided into voltage ranges R1 to R3 for convenience. The vertical axis shows the magnitude of the photocurrent generated when a certain amount of light is incident for a certain period of time. In other words, the photocurrent on the vertical axis shows the sensitivity of the photoelectric conversion unit 11.

[0087] When the voltage Vito is within the voltage range R1, almost no photocurrent flows. In other words, the sensitivity of the photoelectric conversion unit 11 is approximately 0 in the voltage range R1. If the voltage V1, which is the low level of the voltage Vito, is set to a value within the voltage range R1, the sensitivity is approximately 0, so that it can be used as a shutter function. For example, if the voltage Vito is set to 0 V, it can be made to be in the same state as when a physical shutter is closed.

[0088] When the voltage Vito is within the voltage range R2, the higher the voltage Vito, the larger the photocurrent. By varying the voltage Vito within the voltage range R2, it is possible to vary the sensitivity of the photoelectric conversion unit 11 continuously or stepwise. In addition, there is a difference of 1V or more between the lower limit voltage and the upper limit voltage of the voltage range R2.

[0089] When the voltage Vito is within the voltage range R3, the photocurrent is nearly saturated. If the voltage V3, which is the high level of the voltage Vito, is set to a value within the voltage range R3, the photoelectric conversion unit 11 can have the highest sensitivity. When the voltage Vito is in the voltage range R3 and exposure occurs, even if the potential of the charge storage node FD increases due to the signal charge and the potential difference applied to the photoelectric conversion unit 11 becomes smaller, the sensitivity is less likely to decrease and linearity between the illuminance and the amount of signal charge generated can be ensured.

[0090] In order to make the sensitivity of the photoelectric conversion unit 11 variable, the voltage Vito can be made variable not only in an analog manner by utilizing the characteristics of the voltage range R2, but also in a digital manner. Here, the sensitivity of the photoelectric conversion unit 11 can be digitally controlled by, for example, PWM (Pulse Width Modulation). That is, it can be easily controlled by setting the ratio of the low level period and the high level period of the voltage Vito during the exposure period.

[0091] [1.4 Potential fluctuation of the charge storage node FD due to fluctuation of the voltage Vito] Here, we will explain the potential fluctuation of the charge storage node FD caused by the fluctuation of the voltage Vito applied to the counter electrode for sensitivity adjustment. Furthermore, the capacitive element CA shown in Figure 1A has the function of offsetting or reducing the voltage fluctuation of the charge storage node FD caused by the voltage Vito. This point will also be explained in detail.

[0092] 1B is a diagram showing an equivalent circuit of the photoelectric conversion unit 11 in FIG. 1A. As shown in FIG. 1B, the photoelectric conversion unit 11 is expressed as a parallel circuit of a resistance component R1, a capacitance component C1, and a diode component D1. In this equivalent circuit, under bias conditions in which the dark current of the photoelectric conversion layer 14 is small and no forward current of the diode component D1 flows, the photoelectric conversion unit 11 can be regarded as a capacitance component C1. In this case, the potential fluctuation of the charge storage node FD caused by the fluctuation of the voltage Vito is expressed by (Equation 1).

[0093] ΔVfd=(C1 / (Cfd+CA+C1))ΔVito (Formula 1)

[0094] Here, ΔVito indicates the potential fluctuation of the voltage Vito, that is, the difference (V3-V1) between the voltages V3 and V1. ΔVfd indicates the potential fluctuation of the charge storage node FD. C1 indicates the capacitance component of the photoelectric conversion unit 11, Cfd indicates the capacitance value of the parasitic capacitance of the charge storage node FD, and CA indicates the capacitance value of the capacitive element CA.

[0095] On the other hand, the potential fluctuation of the charge-storage node FD caused by the voltage VA applied to the second terminal 18 of the capacitive element CA connected to the charge-storage node FD is expressed by (Equation 2).

[0096] ΔVfd =(CA / (Cfd+CA+C1))ΔVA (Formula 2)

[0097] Here, ΔVA indicates the potential fluctuation of the capacitance element CA, that is, the difference between the voltage V2 and the voltage V4 (V2−V4).

[0098] For (Equation 1) and (Equation 2) to cancel each other out, the sum of (Equation 1) and (Equation 2) must be 0. In other words, the condition of (Equation 3) must be satisfied.

[0099] CA·ΔVA = -C1·ΔVito (Formula 3)

[0100] The first voltage supply circuit 30 and the second voltage supply circuit 21 set the voltages Vito and VA so as to satisfy (Equation 3). However, (Equation 3) does not need to be satisfied all the time, and it is sufficient that (Equation 3) is satisfied only for a predetermined period. Here, the predetermined period refers to a period during which the potential fluctuation ΔVfd in (Equation 1) affects the image quality or pixel signal. The predetermined period includes, for example, a period during which pixel signals and the like are read out from the pixel cells 10 via the vertical signal lines 19, a period during which the charge storage node FD is reset, and the like.

[0101] It should be noted that the voltage VA does not have to completely satisfy (Equation 3). For example, if the voltage Vito fluctuates to the positive side, the voltage VA may be controlled to fluctuate to the negative side, and if the voltage Vito fluctuates to the negative side, the voltage VA may be controlled to fluctuate to the positive side. Even in this case, the state of (Equation 3) can be approached, so that the effect on the image quality or pixel signal can be reduced.

[0102] [1.5 Example of operation] Next, the operation of the imaging device according to the first embodiment will be described.

[0103] FIG. 5A is a time chart showing an example of a read operation of the imaging device according to the first embodiment. The horizontal axis in the figure indicates the time axis. The selection control signal Vsel indicates the waveform of the selection control signal applied to the gate of the address transistor 4. The reset control signal Vrst indicates the waveform of the reset control signal applied to the gate of the reset transistor 2. The potential Vfd indicates a change in the voltage of the charge storage node FD. The period marked "accumulation" in FIG. 5A is a period for accumulating the signal charge generated by photoelectric conversion in the charge storage node FD. This period is also called an accumulation period or an exposure period. The period marked "read" is a period for reading out a signal from the pixel cell 10 to the column signal processing circuit 40. This period is also called a read period. The read period includes a period for resetting the potential of the charge storage node. In each figure used in the following description, the periods marked "accumulation" and "read" mean the same periods.

[0104] At time t0, the selection control signal Vsel rises, turning on the address transistor 4. The period during which the address transistor 4 is in the on state, that is, the period from time t0 to time t3, is the read period.

[0105] In the period from time t0 to time t1, a pixel signal corresponding to the amount of signal charge accumulated in the charge accumulation node FD is read out.

[0106] At time t1, the reset control signal rises, turning on the reset transistor 2. This resets the charge storage node FD to the reference potential Vref. The reference potential Vref is, for example, 0V.

[0107] At time t2, the reset control signal falls, turning off the reset transistor 2. In the period from time t2 to time t3, a reference signal corresponding to the reference potential Vref is read out. The difference between the pixel signal and the reference signal is a signal corresponding to the amount of light irradiation.

[0108] First, the cause of the above problem will be described in detail with reference to FIG. 6 and FIG. 9A.

[0109] Fig. 6 is a time chart showing an example of the operation of an imaging device according to a comparative example. The example shown in Fig. 6 assumes a pixel cell 10 that does not include a configuration for controlling the potential Vfd of the charge storage node FD. Fig. 6 shows the operation for four frames. The voltage Vito indicates the voltage of the counter electrode. For ease of understanding, the potential Vfd indicates the potential of the charge storage node FD in the dark, that is, when there is no incident light.

[0110] Moreover, Fig. 9A is a diagram showing a schematic diagram of a captured image according to a comparative example. This figure shows a case where the voltage Vito of the counter electrode when reading out pixel signals is high in the first frame, low in the second frame, and low in the third frame, as in Fig. 6. Of the images P1 to P3, the image P2 is darker overall than the images P1 and P3. In other words, the image quality of the image P2 is degraded. The cause of this will be explained using Fig. 6.

[0111] 6, the voltage Vito of the counter electrode is a high voltage in the readout period of the first frame, and is a low voltage in the readout period of the subsequent second frame. At this time, the pixel signals read out in the second frame are read out when the voltage of the counter electrode is a low voltage.

[0112] However, the pixel signal of the second frame corresponds to the amount of signal charge accumulated after the counter electrode voltage was reset when the counter electrode voltage was high in the first frame. Therefore, if the pixel signal is read out when the counter electrode voltage is high, the true pixel signal value is obtained. However, if the pixel signal is read out when the counter electrode voltage is low, the pixel signal value will be smaller than the true pixel signal value.

[0113] In this way, when the voltage of the counter electrode during the readout period is changed from a high voltage to a low voltage between frames, a phenomenon occurs in which the image becomes dark in the frame immediately after the change.

[0114] If the counter electrode voltage Vito remains at a low voltage in the third frame following the second frame, this phenomenon does not occur because the counter electrode voltage Vito is the same at the immediately preceding reset time and when the image signal is read out.

[0115] In this way, when the voltage of the counter electrode during the readout period is changed between frames from a high voltage to a low voltage, a phenomenon occurs in which the image becomes dark only in the frame immediately after the change, as shown in FIG. 9A.

[0116] Conversely, when the voltage of the counter electrode is changed from a low voltage to a high voltage between frames, a phenomenon occurs in which the image becomes bright only in the frame immediately after the change.

[0117] Next, an operation example according to the first embodiment will be described. Fig. 5B is a time chart showing an operation example of the imaging device according to the first embodiment. The horizontal axis of the figure indicates the time axis. The vertical axis indicates the voltage Vito for sensitivity control, the operation of the imaging device, and the voltage VA.

[0118] The voltage Vito shows a waveform that changes between a high level voltage V3 and a low level voltage V1, while the voltage VA shows a waveform that changes between a high level voltage V2 and a low level voltage V4.

[0119] Fig. 5B shows the operation of pixel cells 10 in a certain row among the pixel cells 10 of the imaging device. Fig. 5B shows an operation including five readout periods, that is, an operation spanning five frames.

[0120] During the readout period, there are cases where the voltage V3 is applied to the counter electrode and cases where the voltage V1 is applied.

[0121] Of the readout period from time t0 to time t2, the period from time t0 to time t1 is a period for reading out a pixel signal corresponding to the amount of signal charge accumulated in the charge storage node FD. At time t1, the reset transistor 2 resets the charge storage node FD to a reference potential. In the period from time t1 to time t2, the potential of the reset charge storage node FD, that is, a reference signal corresponding to the reference potential which is the reset level, is read out. The same applies to other readout periods such as the readout period from time t10 to time t12.

[0122] In the accumulation period, the sensitivity is adjusted by adjusting the ratio between the high-level period in which Vito is at voltage V3 and the low-level period in which Vito is at voltage V1. For example, in the accumulation period from time t2 to time t10, the low-level period in the first half and the high-level period in the second half are about half and half, and the sensitivity is about 50%. In other accumulation periods as well, the sensitivity is adjusted by adjusting the ratio between the low-level period and the high-level period.

[0123] The voltage VA is controlled as follows: in the readout period, when the first voltage supply circuit 30 supplies a low-level voltage V1 as the voltage Vito, the second voltage supply circuit 21 supplies a high-level voltage V2 as the voltage VA. In addition, in the readout period, when the first voltage supply circuit 30 supplies a high-level voltage V3 as the voltage Vito, the second voltage supply circuit 21 supplies a low-level voltage V4 as the voltage VA.

[0124] In other words, the voltage VA is controlled to be in an anti-phase relationship with the voltage Vito during the readout period. All five readout periods in FIG. 5B satisfy the anti-phase relationship. This satisfies the above-mentioned (Equation 3) or can be brought closer to the state of (Equation 3). In this way, the potential fluctuation of the charge storage node FD is offset or reduced. The readout period is an example of the above-mentioned predetermined period, that is, a period during which the potential fluctuation ΔVfd of (Equation 1) affects the image quality or pixel signal.

[0125] In order to satisfy the opposite phase relationship in each readout period, the second voltage supply circuit 21 also changes the level of the voltage VA, for example, when the voltage Vito is changed in the current readout period compared to the previous readout period one frame ago.

[0126] 5B, the voltage Vito is changed from the previous readout period, so the voltage VA is also changed to be in opposite phase to the voltage Vito. In the fourth readout period, the voltage Vito is the same as the previous readout period, so the voltage VA is not changed to maintain the opposite phase to the voltage Vito.

[0127] Next, the timing for changing the voltage VA will be described.

[0128] For example, in order to satisfy the opposite phase relationship between the voltage VA and the voltage Vito during the readout period, the voltage VA may be changed during the period from the end of the previous readout period to the start of the current readout period. This period is, for example, the accumulation period from t2 to t10.

[0129] More precisely, the voltage VA can be changed during the period from the completion of the reference signal output in the previous readout period to just before the start of the pixel signal output in the current readout period. Figure 5B shows an example in which the voltage VA is changed just before the readout period. This change can be made on a row-by-row basis.

[0130] Also, the voltage Vito may be changed multiple times during the accumulation period, whereas the voltage VA may be changed only once during the accumulation period.

[0131] Note that the high and low levels of the voltages Vito and VA indicate a relative magnitude relationship, not an absolute value. In other words, the high level of the voltage Vito may be a different value from the high level of the voltage VA, and the low level of the voltage Vito may be a different value from the low level of the voltage VA.

[0132] Next, for comparison with the first embodiment, the operation of the imaging device according to the comparative example will be described in more detail with reference to FIG. 6 described above.

[0133] 6, when the voltage Vito is changed from low to high at time t3, the potential Vfd rises due to coupling. Also, like in the accumulation period from time t12 to time t20 and the accumulation period from time t22 to time t30, the potential Vfd rises when the voltage Vito rises and falls when the voltage Vito falls.

[0134] In the readout period from time t10 to time t12, when the voltage Vito is at a high level, a pixel signal that is brighter than the actual pixel signal is read out. The reason for this is as follows. At time t1, the charge storage node FD becomes the reference potential, and then the voltage Vito of the counter electrode 13 The potential Vfd of the charge storage node FD rises due to coupling accompanying the rise. The potential Vfd read out from time t10 to time t11 is higher by the amount of this rise. On the other hand, after being reset at t11, the potential Vfd becomes the same reference potential as at time t1, regardless of the potential of the counter electrode 13. Therefore, the difference between these is a value higher by the amount of the rise in the potential Vfd of the charge storage node FD due to coupling, resulting in an image that is brighter than the actual image.

[0135] Furthermore, when the voltage Vito is at a low level at the reset timing of time t21, a large difference occurs between the signal level and the reference level of the potential Vfd indicating the signal level immediately before the reset and the potential Vfd indicating the reference level immediately after the reset, even though it is dark. This difference occurs uniformly in the pixel cells of the same row. In this case, the signal level becomes a negative value smaller than the reference level, so it goes outside the AD conversion range, and the pixel signal may be crushed or distorted.

[0136] Next, the operation of the imaging device according to the first embodiment will be described with reference to FIG.

[0137] Fig. 7 is a time chart showing an example of the operation of the imaging device according to the first embodiment. As previously described with reference to Fig. 5B, the imaging device according to the first embodiment differs from Fig. 6 in that a voltage VA is introduced. Note that Fig. 7 also shows an example of the operation in the dark.

[0138] As shown by the dotted line in the figure, the voltage VA is controlled to be in opposite phase to the voltage Vito during each readout period. This cancels out or reduces the potential fluctuation of the charge storage node FD caused by the fluctuation of the voltage Vito. As a result, the potential Vfd indicating the signal level immediately before resetting during each readout period and the potential Vfd indicating the reference level immediately after resetting maintain their original state during the dark period, that is, the same level.

[0139] In this way, the voltage VA is controlled to be in an anti-phase relationship with the voltage Vito during the readout period. The anti-phase relationship is satisfied in all four readout periods in FIG. 7. This satisfies the above-mentioned (Equation 3) or makes it possible to approach the state of (Equation 3). In this way, the potential fluctuation of the charge storage node FD is offset or reduced.

[0140] [1.6 Modifications] Next, a description will be given of a modification of the first embodiment. In this modification, an example will be described in which the voltage Vito has multiple values, that is, more than two values.

[0141] Fig. 8 is a time chart showing an example of operation of the imaging device according to the first embodiment. In the figure, the voltage Vito can take three values: high level, middle level, and low level. Fig. 8 shows "operation", the voltage Vito, the voltage VA, and the potential Vfd of the charge storage node FD. Fig. 8 also shows an example of operation in the dark.

[0142] During the readout period, the voltage VA can take three values, as shown by the dotted line frame, just like Vito. If Vito is at the middle level, the voltage VA is controlled to the middle level. In addition, the high and low levels of the voltage VA are controlled to be in opposite phase to the voltage Vito. This makes it possible to cancel or reduce the potential fluctuation of the charge storage node FD at any time during the readout period.

[0143] [1.7 Effects] Next, the effects of the imaging device according to the first embodiment will be described.

[0144] FIG. 9B is a diagram illustrating an image captured by the imaging device according to the first embodiment.

[0145] In the figure, the voltage Vito of the counter electrode when reading out pixel signals is high in the first frame, low in the second frame, and low in the third frame. In this case, the voltage VA is low in the first frame, high in the second frame, and high in the third frame during the readout period.

[0146] Compared to FIG. 9A, images P11 to P13 do not show a sudden change in brightness due to the potential fluctuation of the charge storage node FD. In other words, the image quality degradation due to the fluctuation of the voltage Vito of the counter electrode is greatly reduced. Thus, the first embodiment has the effect of reducing the image quality degradation due to the potential change of the counter electrode.

[0147] In the first embodiment, the voltage VA may be changed in synchronization with the change in the voltage Vito so as to satisfy an inverse phase relationship. The voltage VA may be changed not row by row but for all the rows simultaneously.

[0148] (Embodiment 2) In this embodiment, an operation example for suppressing the decrease in sensitivity and the decrease in saturation during the accumulation period will be described. Specifically, the second voltage supply circuit 21 supplies a voltage to the capacitive element CA during the accumulation period that is lower than that during the readout period.

[0149] [2.1 Configuration of imaging device] The configuration of the imaging device according to the second embodiment is the same as that of the first embodiment.

[0150] [2.2 Operation of the imaging device] 10 is a time chart showing an example of the operation of the imaging device according to embodiment 2. The diagram shows the operation of a certain row of pixel cells 10 of the imaging device, or the operation of a certain pixel cell 10, and shows the operation including five readout periods, that is, the operation spanning five frames.

[0151] The first voltage supply circuit 30 supplies a voltage V1 that makes the sensitivity zero except for a part of the accumulation period, and supplies a voltage V3 that is higher than the voltage V1 only for a part of the accumulation period.

[0152] The second voltage supply circuit 21 supplies a voltage V2 during the readout period, and supplies a voltage V4 lower than the voltage V2 during the accumulation period.

[0153] This operation makes it possible to suppress a decrease in sensitivity and a decrease in saturation. The reason for this will be explained below with reference to Figs. 11 and 12.

[0154] Fig. 11 is a time chart showing an example of the operation of an imaging device according to a comparative example. This figure assumes a pixel cell 10 that does not include a configuration for controlling the potential Vfd of the charge storage node FD. The potential Vfd shows the potential of the charge storage node FD in the dark, i.e., when there is no incident light, in order to emphasize the fluctuation due to the voltage Vito. Furthermore, a state in which the voltage Vito is at a low level is, for example, a state in which the sensitivity is zero and no photoelectric conversion is performed. This state corresponds to a state in which the electronic shutter is closed. A high level state is a state in which photoelectric conversion is performed.

[0155] The sensitivity of the photoelectric conversion unit 11 depends on the potential difference applied to the photoelectric conversion layer 14, that is, Vito-Vfd, and the greater this potential difference is, the higher the sensitivity is.

[0156] If the voltage Vito is set to a high level during the accumulation period, Vfd also rises due to coupling as shown in Fig. 11. Therefore, the potential difference across the photoelectric conversion layer 14 is substantially reduced, and the sensitivity is reduced. Furthermore, when Vfd rises, the saturation charge amount of the charge accumulation node FD may decrease.

[0157] In order to solve such a problem, in this embodiment, the operations shown in FIGS. 10 and 12 are performed.

[0158] Fig. 12 is a time chart showing an example of the operation of the imaging device according to embodiment 2. In Fig. 12, the preconditions are the same as in Fig. 10, and the potential Vfd shows a case in which it is dark.

[0159] 12, during the readout period, the voltage Vito of the counter electrode 13 is a low-level voltage V1. Also, as shown in the dotted frame, during the accumulation period, the voltage VA is set to a low-level voltage V4. Note that, during the readout period, the voltage VA is a high-level voltage V2 that is in phase opposite to the voltage Vito, as shown in the dotted frame.

[0160] According to the present embodiment, the potential difference applied to the photoelectric conversion layer 14 during the accumulation period, i.e., Vito-Vfd, can be made larger than that in Fig. 11. This makes it possible to suppress a decrease in the sensitivity of the photoelectric conversion unit 11. Also, it is possible to suppress a decrease in the amount of saturated charge.

[0161] (Embodiment 3) In this embodiment, an example of an operation for reducing leakage of signal charges during the accumulation period will be described. Specifically, the second voltage supply circuit 21 supplies a higher voltage to the capacitive element CA during the accumulation period than during the readout period.

[0162] [3.1 Configuration of imaging device] The configuration of the imaging device according to the third embodiment is the same as that of the first embodiment.

[0163] [3.2 Operation of the imaging device] 13 is a time chart showing an example of the operation of the imaging device according to embodiment 3. The diagram shows the operation of a certain row of pixel cells 10 of the imaging device, or the operation of a certain pixel cell 10, and shows the operation including five readout periods, that is, the operation spanning five frames.

[0164] The first voltage supply circuit 30 supplies a voltage V3 except for a part of the accumulation period, and supplies a voltage V1 lower than the voltage V3 only for a part of the accumulation period. The second voltage supply circuit 21 supplies a voltage V4 during the readout period, and supplies a voltage V2 higher than the voltage V4 during the accumulation period.

[0165] According to this embodiment, even if the voltage Vito temporarily changes to a low level during the accumulation period, leakage of signal charges can be suppressed. The reason for this will be explained below with reference to FIGS.

[0166] Fig. 14 is a time chart showing an example of the operation of an imaging device according to a comparative example. This figure assumes a pixel cell 10 that does not include a configuration for controlling the potential Vfd of the charge storage node FD. The potential Vfd shows the potential of the charge storage node FD in the dark, i.e., when there is no incident light, in order to emphasize the fluctuation due to the voltage Vito. Also, a low-level state of the voltage Vito is, for example, a state in which the sensitivity is zero and no photoelectric conversion is performed, i.e., a state in which the electronic shutter is closed. A high-level state is a state in which photoelectric conversion is performed.

[0167] When the voltage Vito of the counter electrode temporarily becomes low during the exposure period, the potential Vfd of the charge storage node FD also drops due to coupling. At this time, as shown in FIG. 14, the potential Vfd may drop below the reset level, which is the reference potential. If the reset level is low, the parasitic PN diode between the semiconductor substrate and the diffusion layer formed in the semiconductor substrate as part of the charge storage node FD may shift from a reverse bias to a forward bias state. This may cause the signal charge stored in the diffusion layer to leak. As a result, the low-level pixel signal may be crushed.

[0168] In order to solve such a problem, in this embodiment, the operations shown in FIGS. 13 and 15 are performed.

[0169] Fig. 15 is a time chart showing an example of the operation of the imaging device according to embodiment 3. In Fig. 15, the preconditions are the same as in Fig. 13, and the potential Vfd shows a case in which it is dark.

[0170] 15, during the readout period, the voltage Vito of the counter electrode 13 is a high-level voltage V3. Also, as shown in the dotted frame, during the accumulation period, the voltage VA is set to a high-level voltage V2. Note that, during the readout period, the voltage VA is a low-level voltage V4 that is in phase opposite to the voltage Vito, as shown in the dotted frame.

[0171] According to this embodiment, during the accumulation period, the possibility that the potential Vfd of the charge accumulation node FD falls below the reset level, which is the reference potential, can be reduced. This makes it possible to suppress the collapse of pixel signals. Furthermore, it is also possible to set the reset level lower.

[0172] (Embodiment 4) In this embodiment, in addition to the embodiments 1 to 3, an example of the timing of changing the voltage Vito of the counter electrode will be described. Specifically, the first voltage supply circuit 30 in the embodiment 4 changes the voltage Vito during a readout period of an ineffective pixel in one frame period. In other words, the first voltage supply circuit 30 does not change the voltage Vito during a readout period of an effective pixel in one frame period.

[0173] [4.1 Configuration of imaging device] The imaging device according to the fourth embodiment may be the same as those of the first to third embodiments, but may also have a configuration as shown in FIG. 16. FIG. 16 is a block diagram showing a configuration example of the imaging device according to the fourth embodiment. FIG. 16 differs from FIG. 1A in that the number of vertical scanning circuits 20 is increased from one to two, and that output selection circuit 41a and output selection circuit 41b are provided instead of output selection circuit 41. The following mainly describes the differences.

[0174] 1A, and supplies various control signals for each row from both the left and right sides of the imaging area 10A. This reduces the time difference caused by delays between the left and right ends of the imaging area 10A, enabling faster driving.

[0175] The output selection circuit 41a and the output selection circuit 41b are circuits obtained by dividing the output selection circuit 41 in Fig. 1A in half. For example, the output selection circuit 41a corresponds to odd-numbered columns of all columns of the pixel cells 10, and the output selection circuit 41b corresponds to even-numbered columns of all columns of the pixel cells 10. This makes it possible to make the output operation of pixel signals more than twice as fast.

[0176] The output selection circuits 41a and 41b may be assigned to other than odd-numbered columns and even-numbered columns.

[0177] Next, a configuration example of the imaging region 10A will be described.

[0178] 17A is a block diagram showing an example of the arrangement of effective pixel regions and invalid pixel regions according to Embodiment 4. In the figure, an imaging region 10A includes an invalid pixel region a0 and an effective pixel region a1.

[0179] The invalid pixel area a0 is an area where invalid pixels are arranged. The invalid pixels are formed as pixel cells 10 in which the amount of incident light is blocked by a light-shielding film, for example, and output an optical black level as a pixel signal. Note that the invalid pixel area a0 may contain both invalid pixels and valid pixels.

[0180] The effective pixel area a1 is an area in which effective pixels are arranged. The effective pixels are the pixel cells 10 shown in FIG. 1A, and output pixel signals according to the amount of incident light. There are no invalid pixels in the effective pixel area a1. In FIG. 17A, the invalid pixel areas a0 are arranged on the four sides of the imaging area 10A so as to surround the entire periphery of the effective pixel area a1.

[0181] Moreover, Fig. 17B is a block diagram showing another example of the arrangement of the effective pixel region and the invalid pixel region according to embodiment 4. In Fig. 17B, the invalid pixel regions a0 are located outside three sides of the effective pixel region a1 and are arranged on three sides of the imaging region 10A.

[0182] [4.2 Operation of the imaging device] Next, the operation of the imaging device according to the present embodiment will be described.

[0183] 18A is an explanatory diagram showing an example of a readout operation of an effective pixel region and an invalid pixel region according to embodiment 4. The diagram shows a schematic diagram of a readout period (Ri) of an invalid pixel and a readout period (Rv) of an effective pixel in one frame period.

[0184] In FIG. 18A, there are invalid pixel readout periods (Ri) at the beginning and end of one frame period, and there are a series of valid pixel readout periods (Rv) between them.

[0185] 18B is an explanatory diagram showing another example of readout operation of the valid pixel region and the invalid pixel region according to the fourth embodiment. In FIG. 18B, the invalid pixel readout period (Ri) and the valid pixel readout period (Rv) are repeated multiple times within one frame period. In this case, the imaging device, for example, interrupts readout of the valid pixels halfway, jumps to the invalid pixels, and resumes access to the valid pixels from the interrupted point.

[0186] Next, an example of the timing for changing the voltage Vito of the counter electrode will be described.

[0187] 19 is a diagram showing an example of the change timing of the voltage Vito of the counter electrode according to the fourth embodiment. As shown in the dotted frame, the first voltage supply circuit 30 changes the voltage Vito during the readout period (Ri) of the invalid pixels in one frame period. Moreover, the first voltage supply circuit 30 does not change the voltage Vito during the readout period (Rv) of the valid pixels in one frame period.

[0188] This makes it possible to suppress fluctuations in pixel signals caused by voltage fluctuations in the counter electrode 13 .

[0189] Although the imaging device according to one or more aspects of the present disclosure has been described based on the embodiment, the present disclosure is not limited to this embodiment. As long as it does not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to this embodiment and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0190] The imaging device and the driving method thereof according to the present disclosure can be used in a camera. [Explanation of symbols]

[0191] 2 Reset transistor 2s, 2d, 3s, 3d, 4d impurity region 3 Amplification transistor 4 Address transistor 7. Semiconductor Substrates 8 Interlayer Insulation Layer 9. Element isolation region 10 pixel cells 10A Imaging area 11 Photoelectric conversion section 12 Pixel electrode 13 Counter electrode 14 Photoelectric conversion layer 17 1st terminal 18 2nd terminal 19 Vertical signal line 20 Vertical scanning circuit 21 Second voltage supply circuit 25 Second voltage supply line 26 Reset control signal line 27 Selection control signal line 30 First voltage supply circuit 35 First voltage supply line 40 Column signal processing circuit 41, 41a, 41b Output selection circuit 42 Output terminal 52 Plug 54, 55 Contact plug 53 Wiring 56 wiring layer a0 Invalid pixel area a1 Effective pixel area C1 Capacitive component CA Capacitor D1 Diode component FD Charge storage node R1 Resistance component Ri Invalid pixel readout period Rv Effective pixel readout period Vrst Reset control signal Vref Reference potential Vsel selection control signal

Claims

1. a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and configured to generate signal charges; a charge accumulation section connected to the first electrode and configured to accumulate the signal charges; a first voltage supply circuit connected to the second electrode and configured to selectively supply one of a plurality of voltages including a first voltage and a third voltage higher than the first voltage; a second voltage supply circuit connected to the charge storage unit via a capacitance and configured to selectively supply one of a plurality of voltages including a second voltage and a fourth voltage smaller than the second voltage; Equipped with the first voltage supply circuit supplies the first voltage during at least a part of an accumulation period for accumulating the signal charge in the charge accumulation section; the second voltage supply circuit supplies the second voltage during the accumulation period. Imaging device.

2. a capacitance element connected between the second voltage supply circuit and the charge storage unit and functioning as the capacitance; The imaging device according to claim 1 .

3. The signal charges are holes.

3. The imaging device according to claim 1.

4. the sensitivity of the photoelectric conversion unit is substantially zero when the first voltage is supplied to the second electrode; The imaging device according to claim 1 .

5. the second voltage supply circuit supplies the fourth voltage during a reset period in which the charge storage unit is reset; The imaging device according to claim 1 .

6. the first voltage supply circuit supplies the first voltage during a portion of the accumulation period; The imaging device according to claim 1 .

7. the first voltage supply circuit supplies the third voltage during a period that is different from the part of the accumulation period. The imaging device according to claim 6.

8. a photoelectric conversion unit including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and configured to generate signal charges; a charge accumulation section connected to the first electrode and configured to accumulate the signal charges; a first voltage supply circuit connected to the second electrode and configured to selectively supply one of a plurality of voltages including a first voltage and a third voltage higher than the first voltage; a second voltage supply circuit connected to the charge storage unit via a capacitance and configured to selectively supply one of a plurality of voltages including a second voltage and a fourth voltage smaller than the second voltage; Equipped with the first voltage supply circuit supplies the third voltage during at least a portion of an accumulation period for accumulating the signal charge in the charge accumulation section; the second voltage supply circuit supplies the first voltage during the accumulation period; Imaging device.

9. a capacitance element connected between the second voltage supply circuit and the charge storage unit and functioning as the capacitance; The imaging device according to claim 8.

10. The signal charges are holes.

10. The imaging device according to claim 8.

11. the sensitivity of the photoelectric conversion unit is substantially zero when the first voltage is supplied to the second electrode; The imaging device according to claim 8 .

12. the second voltage supply circuit supplies the second voltage during a reset period in which the charge storage unit is reset; The imaging device according to claim 8 .

13. the first voltage supply circuit supplies the third voltage during a part of the accumulation period; The imaging device according to claim 8 .

14. the first voltage supply circuit supplies the first voltage during a period that is different from the part of the accumulation period. The imaging device according to claim 13.

Images