Semiconductor device

Abstract

To provide a transistor structure that can make the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor as the channel forming region positive and realize a so-called normally-off switching element.SOLUTION: An oxide semiconductor stack comprises at least of a first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps and a transistor is formed using the oxide semiconductor stack with a region that contains an excess of oxygen above the stoichiometric composition ratio.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the disclosed invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and they are used as LSIs, CPUs, and memories. The PU is a semiconductor integrated circuit (at least the transistors and A semiconductor device is an assembly of semiconductor elements having a memory and on which electrodes that serve as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards. It is mounted on a wiring board and used as one of the components in various electronic devices.

[0005] In addition, a technology for manufacturing transistors and the like by using an oxide semiconductor film in a channel formation region is gaining attention. For example, a transistor using zinc oxide (ZnO) as an oxide semiconductor film is , InGaO 3 (ZnO) m These oxide semiconductor transistors include A transistor using the insulating film is formed on a light-transmitting substrate, and is used as a switch of an image display device. Technologies for use in coupling elements and the like are disclosed in Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] The transistor applied to the semiconductor device has a gate voltage that is a positive threshold as close as possible to 0V. It is desirable for the channel to form at a high threshold voltage (Vth). If the gate voltage is negative, a current flows between the source and drain electrode layers even if the gate voltage is 0V. It tends to flow, or become what is known as normally on.

[0008] In view of this, in one embodiment of the present invention, In the transistor, a so-called normally-off switching element having a positive threshold voltage is used. It is an object of the present invention to provide a transistor structure that realizes the above-mentioned element and a manufacturing method thereof.

[0009] In addition, depending on the material and manufacturing conditions, the manufactured transistor may not be normally off. Even in this case, it is important to approach the normally-off characteristics, and the value of the threshold voltage Even if the transistor is normally on, the threshold voltage of the transistor approaches zero. It is also an object of the present invention to provide a structure and a manufacturing method thereof.

[0010] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. It is also an object of the present invention to provide a method for producing the same.

[0011] In addition, the leakage current of a transistor also affects the power consumption of a semiconductor device. It is also important to reduce the power consumption in order to realize a semiconductor device with low power consumption. The aspect is a leakage current (parasitic channel) in the source electrode layer and the drain electrode layer of a transistor. It is also an object of the present invention to provide a configuration that reduces the occurrence of

[0012] It is to be noted that one aspect of the present invention is to solve at least one of the above-mentioned problems. [Means for solving the problem]

[0013] In one aspect of the invention, the nuclei have different energy gaps and / or different electron affinities. An oxide semiconductor layer in which oxide semiconductors are stacked (hereinafter also referred to as an oxide semiconductor stack) is used. In addition, the oxide semiconductor stack has a composition ratio higher than the stoichiometric ratio. It has a region that contains an excess of oxygen (hereinafter, also referred to as an oxygen excess region).

[0014] For example, the first oxide semiconductor layer and the second oxide semiconductor layer have different energy gaps. and a second oxide semiconductor layer having an oxygen excess region. Here, the first oxide semiconductor layer and the second oxide semiconductor layer are As long as the layers have different energy gaps, the order of stacking does not matter. The energy gap of one oxide semiconductor layer is set to 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to 3 eV or more. The energy gap of the layer may be less than 3 eV.

[0015] In this specification, the term "energy gap" means "band gap." or "forbidden band width."

[0016] The oxide semiconductor stack may include three or more oxide semiconductor layers. When the conductor laminate has three or more oxide semiconductor layers, all of the oxide semiconductor layers The layers may have different energy gaps, or the layers may have the same energy gaps. An oxide semiconductor layer having a gap may be used in a stack of multiple oxide semiconductors.

[0017] For example, a first oxide semiconductor layer and a second oxide semiconductor layer are provided on the first oxide semiconductor layer and have a first electron affinity. the electron affinity of the first oxide semiconductor layer is greater than that of the first oxide semiconductor layer, or the energy gap of the first oxide semiconductor layer is greater than that of the first oxide semiconductor layer. a second oxide semiconductor layer having an energy gap smaller than that of the oxide semiconductor layer; a third oxide semiconductor layer provided on the conductor layer so as to surround a side surface of the second oxide semiconductor layer; Note that the electron affinity and energy of the third oxide semiconductor layer can be The gap is preferably set to be equal to the electron affinity and energy gap of the first oxide semiconductor layer. Here, the electron affinity represents the energy difference between the vacuum level and the conduction band of an oxide semiconductor. The second oxide semiconductor layer with a small energy gap is By using a structure in which the first oxide semiconductor layer and the third oxide semiconductor layer are sandwiched, This provides the effect of reducing the off-current (leakage current) of the transistor.

[0018] Specifically, the energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer are The energy gap of the second oxide semiconductor layer is set to be 3 eV or more, and the energy gap of the second oxide semiconductor layer is set to be less than 3 eV. In a transistor using an oxide semiconductor layer, the energy gap of the oxide semiconductor layer is For example, in a transistor using an oxide semiconductor layer, In a semiconductor device, when the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, The current and field effect mobility are improved, while the energy gap of the oxide semiconductor layer is large. Therefore, the off-current can be reduced.

[0019] In the case of a single oxide semiconductor layer, the size of the energy gap of the oxide semiconductor layer determines the transistor Since the electrical characteristics of the transistor are almost determined, it is necessary to give the transistor the desired electrical characteristics. However, a transistor according to one embodiment of the present invention can be used at different energy levels. By using a stack of oxide semiconductor layers each having a gap, Therefore, the electrical characteristics can be controlled more precisely, and desired electrical characteristics can be imparted to the transistor. It will be possible to provide

[0020] Therefore, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, and low power consumption. It is possible.

[0021] One embodiment of the structure of the invention disclosed in this specification is a semiconductor device including a first oxide semiconductor layer and a second oxide semiconductor layer. and a second oxide semiconductor layer having an energy gap different from that of the first oxide semiconductor layer. A stacked layer is formed, a source electrode layer or a drain electrode layer is formed over the oxide semiconductor stacked layer, and a source electrode layer or a drain electrode layer is formed over the oxide semiconductor stacked layer. A gate insulating film is formed on the source electrode layer or the drain electrode layer, and a source electrode is formed on the gate insulating film. Using the electrode layer or drain electrode layer as a mask, oxygen is introduced into the oxide semiconductor stack in a self-aligned manner. a gate electrode layer overlapping the oxide semiconductor stack with a gate insulating film interposed therebetween; A method for making the device.

[0022] Another embodiment of the invention disclosed in this specification is a semiconductor device including a first oxide semiconductor layer and a second oxide semiconductor layer which are stacked in this order. a second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer; a third oxide semiconductor layer having a larger energy gap than the second oxide semiconductor layer; a source electrode layer or a drain electrode layer is formed on the oxide semiconductor stack; An electrode layer is formed, a gate insulating film is formed on the source electrode layer or the drain electrode layer, and a gate From above the insulating film, the oxide semiconductor stack is formed by using the source electrode layer or the drain electrode layer as a mask. Oxygen is introduced in a self-aligned manner, and a gate electrode overlapping the oxide semiconductor stack is formed through the gate insulating film. The present invention relates to a method for manufacturing a semiconductor device that forms a pole layer.

[0023] In the above-described method for manufacturing a semiconductor device, It is preferable to laminate a third oxide semiconductor layer so as to cover the side surfaces of the conductor layer.

[0024] A third oxide semiconductor layer is formed so as to cover the side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer. By forming the semiconductor layer, an increase in oxygen vacancies in the second oxide semiconductor layer is suppressed, and the transistor The threshold voltage of the second oxide semiconductor layer can be made close to zero. The conductor layer becomes a buried channel, which keeps the channel formation region away from the insulating film interface. This reduces the interface scattering of carriers and realizes high field effect mobility. This can be done.

[0025] In any one of the above-described methods for manufacturing a semiconductor device, after the gate electrode layer is formed, The dopant is introduced into the oxide semiconductor stack in a self-aligned manner using the gate electrode layer as a mask. preferable.

[0026] In any one of the above-mentioned methods for manufacturing a semiconductor device, an interlayer insulating film is provided on the gate electrode layer. A contact hole reaching the source electrode layer or the drain electrode layer is formed in the interlayer insulating film. A source electrode layer or a drain electrode layer is formed on the interlayer insulating film through a contact hole. Wiring layers may be formed to connect to the electrode layers, respectively.

[0027] In another embodiment of the present invention, the first oxide semiconductor layer and a second oxide semiconductor layer different from the first oxide semiconductor layer are a second oxide semiconductor layer having an energy gap; and a source electrode layer or a drain electrode layer provided on the semiconductor stack; A gate insulating film is provided on the drain electrode layer, and an oxide semiconductor stack is formed on the gate insulating film. a gate electrode layer overlapping with a source electrode layer or The region that does not overlap with the drain electrode layer is a region that overlaps with the source electrode layer or the drain electrode layer. The semiconductor device has a higher oxygen concentration than that of the semiconductor device.

[0028] Another embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer and a second oxide semiconductor layer in contact with the first oxide semiconductor layer, a second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer; The second oxide semiconductor layer is in contact with the first oxide semiconductor layer and has a larger energy gap than the second oxide semiconductor layer. a third oxide semiconductor layer having a first oxide semiconductor layer and a second oxide semiconductor layer provided over the oxide semiconductor stack; a source electrode layer or a drain electrode layer provided on the source electrode layer or the drain electrode layer; The gate insulating film is formed on the oxide semiconductor layer. The gate insulating film is formed on the oxide semiconductor layer. and a source electrode layer or a drain electrode layer in the oxide semiconductor stack. The region that does not overlap with the source electrode layer or the drain electrode layer has a higher oxygen concentration than the region that overlaps with the source electrode layer or the drain electrode layer. The semiconductor device has the following features.

[0029] In the semiconductor device having the above structure, the first oxide semiconductor layer and the second oxide semiconductor layer are formed in the same matrix. The third oxide semiconductor layer can be formed by using a mask, and the third oxide semiconductor layer can overlap the second oxide semiconductor layer. In addition, the area of ​​the second oxide semiconductor layer is larger than that of the first oxide semiconductor layer. The semiconductor device having such a configuration may be configured to wrap the conductor layer. A third oxide semiconductor layer is formed so as to cover and contact the side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer. Since the conductor layer is provided, the source electrode layer formed on and in contact with the third oxide semiconductor layer Alternatively, the drain electrode layer is not in contact with the side surface of the second oxide semiconductor layer. Prevents leakage current (parasitic channel) from the source and drain electrode layers of a transistor. This is preferable because it can reduce the

[0030] In addition, the source electrode layer or the drain electrode layer is not in contact with a side surface of the second oxide semiconductor layer. The structure is not particularly limited as long as it is the above-mentioned. For example, the side surface of the first oxide semiconductor layer is The third oxide semiconductor layer is formed on the upper surface of the first oxide semiconductor layer. It may be configured so that it comes into contact with a part of the

[0031] In any one of the above-mentioned semiconductor devices, the oxide semiconductor stack may further include a gate electrode layer. It is preferable that the region not overlapping with the oxide layer contains a dopant. The nitride semiconductor laminate has a channel forming region that overlaps with the gate electrode layer via a gate insulating film. The semiconductor device has a pair of low resistance regions sandwiching the channel formation region in the channel length direction.

[0032] An oxide semiconductor layer including a low-resistance region is formed on both sides of a channel formation region in the channel length direction. As a result, the transistor has high on-characteristics (e.g., on-current and field-effect mobility). This enables high-speed operation and high-speed response. Since the electrode layer does not overlap with the semiconductor layer, the parasitic capacitance can be reduced. This leads to a reduction in the power consumption of the entire semiconductor device.

[0033] The dopant concentration in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0034] In addition, depending on the film thickness of the source electrode layer and the drain electrode layer and the conditions for introducing the dopant, These dopants are introduced into the oxide semiconductor stack by passing through the source electrode layer or the drain electrode layer. The dopant may be added to the channel forming region. Therefore, the thicknesses of the source and drain electrode layers are set to be larger than the thickness of the gate electrode layer. The thickness is also thin.

[0035] In any one of the above semiconductor devices, a source electrode layer is provided on the gate electrode layer. Alternatively, an interlayer insulating film having a contact hole reaching the drain electrode layer, and a and connected to the source electrode layer or the drain electrode layer through the contact hole. It is preferable that the semiconductor device further includes a wiring layer. Effect of the Invention

[0036] According to one embodiment of the present invention, the on-characteristics of a transistor (e.g., on-current and field-effect mobility) can be improved. ) can be improved.

[0037] According to one embodiment of the present invention, a normally-off transistor can be realized. In addition, even if the transistor is normally on, the threshold voltage of the transistor is set close to zero. It can be attached. [Brief description of the drawings]

[0038] [Figure 1] 1A to 1C are a plan view, a cross-sectional view, and an energy band diagram illustrating a semiconductor device of one embodiment of the present invention. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 5] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] Energy band diagram. [Figure 11] TEM photograph of the sample and its schematic diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention is not limited to the description of the embodiment shown below. It is not to be interpreted.

[0040] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in different drawings, and the repeated explanations are omitted. When referring to parts having similar functions, the same hatch pattern is used and no particular reference number is given. There are cases.

[0041] In each figure described in this specification, the size, thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0042] In this specification, the ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name for the purpose of reference.

[0043] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. In this embodiment, a transistor having an oxide semiconductor stack will be described as an example of a semiconductor device. A transistor is shown.

[0044] The transistor 510 shown in FIG. 1A, FIG. 1B, and FIG. 1C has a top-gate structure. FIG. 1(A) is a top view, and the dashed line XY in FIG. 1(A) is an example of a transistor having such a structure. The cut cross section corresponds to FIG. 1(B), and the cross section cut along the dashed line VW in FIG. 1(A) corresponds to FIG. 1(C). 1B and 1C, the oxide semiconductor stack 403 includes The interfaces of the oxide semiconductor layers are shown by dotted lines. Depending on the film formation conditions, the interfaces between the oxide semiconductor layers may become unclear. When the interface becomes unclear, it is called a mixed region or a mixed layer of different oxide semiconductor layers. There may also be areas where this can occur.

[0045] As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, a transistor 510 is formed by A first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are formed on a substrate 400 having an insulating surface on which an insulating film 436 is provided. The oxide semiconductor stack 403 includes a second oxide semiconductor layer and a third oxide semiconductor layer. a source electrode layer 405a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer In the transistor 510, the first oxide semiconductor layer is an oxide insulating The second oxide semiconductor layer is formed on and in contact with the film 436. In the transistor 510, the oxide semiconductor stack is formed by stacking a third oxide semiconductor a third oxide semiconductor layer is disposed between a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer; The third oxide semiconductor layer is provided so as to cover the side surface of the oxide insulating layer. It contacts the velum.

[0046] The oxide semiconductor stack 403 overlaps with the gate electrode layer 401 via the gate insulating film 402. The overlapping channel formation regions are formed in three layers, a first channel formation region 121c, a second channel formation region 121d, and a A channel formation region 122c and a third channel formation region 123c are stacked.

[0047] In addition, the first low resistance region 12 is disposed on either side of the first channel formation region 121c in the channel length direction. 1a and 121b. A second channel forming region 122c is sandwiched between the first and second channel forming regions 122a and 122b in the channel length direction. The second low resistance regions 122a and 122b are formed in the channel length direction. The third low resistance regions 123a and 123b sandwich a panel formation region 123c.

[0048] In addition, the first region 121d overlapping with the source electrode layer 405a or the drain electrode layer 405b , 121e, second regions 122d, 122e, and third regions 123d, 123e.

[0049] In the transistor 510 illustrated in FIG. 1, the oxide semiconductor stack 403 includes a first low-resistance region 121a, 121b, the first channel forming region 121c, and the first region 121d, 12 The first oxide semiconductor layer including 1e, the second low-resistance regions 122a and 122b, and the second channel a second oxide semiconductor layer including a panel formation region 122c and second regions 122d and 122e; the third low-resistance regions 123a and 123b, the third channel formation region 123c, and the third and a third oxide semiconductor layer including the regions 123d and 123e. .

[0050] In the transistor 510, the second oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer. The third oxide semiconductor layer has a smaller energy gap than the second oxide semiconductor layer. In addition, the first oxide semiconductor layer and the third oxide semiconductor layer have a larger energy gap than the first oxide semiconductor layer. It is preferable that the semiconductor layer has a similar energy gap.

[0051] FIG. 1B is a cross-sectional view in the channel length direction, showing an end portion of the second oxide semiconductor layer, that is, the first The side surfaces of the second regions 122d and 122e are the ends of the third oxide semiconductor layer, that is, the third region 1 It is preferable that the structure be covered with 23d and 123e. The leakage current (parasitic current) of the source electrode layer 405a and the drain electrode layer 405b of the transistor The occurrence of dust particles can be reduced.

[0052] FIG. 1C is a cross-sectional view in the channel width direction, and similarly to FIG. 1B, the second oxide semiconductor The end of the third oxide semiconductor layer, that is, the side surface of the second channel formation region 122c, is That is, it is preferable to have a structure covered with the third channel formation region 123c.

[0053] FIG. 1(D) is an energy band diagram in the film thickness direction (between D-D') in FIG. 1(B). In this embodiment, the energy band diagram shown in FIG. Then, materials for the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are selected. However, since a sufficient effect can be obtained if a buried channel is formed in the conduction band, As shown in the energy band diagram in Figure 1(D), the material must have a depression in both the conduction band and the valence band. For example, the energy band diagram may have a concave portion only in the conduction band. The configuration may be such that an energy band diagram can be obtained.

[0054] FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show an example of a method for manufacturing a transistor. Shows.

[0055] First, an oxide insulating film 436 and a first oxide semiconductor layer 10 are formed on a substrate 400 having an insulating surface. 1. A second oxide semiconductor layer 102 is formed.

[0056] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. In addition, a silicon substrate, a silicon carbide substrate, etc. can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A semiconductor device having a semiconductor element on a substrate such as a silicon-on-insulator (SOI) substrate can also be used. may be used as the substrate 400.

[0057] A semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device having such a structure, a transistor including an oxide semiconductor stack is formed over a flexible substrate. Alternatively, a transistor including an oxide semiconductor stack may be formed on another substrate. The substrate may be peeled off and then transferred to a flexible substrate. In order to place the transistor having the oxide semiconductor stack on the substrate, a separation layer is provided between the formation substrate and the transistor having the oxide semiconductor stack. It is good.

[0058] The oxide insulating film 436 is formed by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide , gallium oxide, silicon nitride oxide, aluminum nitride oxide, or a mixture of these materials. The oxide insulating film 436 may be a single layer or a stacked layer. In this embodiment, a silicon oxide film formed by a sputtering method is used as the oxide insulating film 436. There are.

[0059] In the transistor 510, the oxide insulating film 436 is a bottom layer and a top layer of an oxide semiconductor stack. In order to contact with the upper layer, the amount of oxygen in the film (bulk) must exceed at least the stoichiometric composition ratio. For example, a silicon oxide film is used as the oxide insulating film 436. In the case of SiO 2+α (where α>0). By using the oxide semiconductor layer, oxygen can be supplied to the oxide semiconductor stack formed above, and the characteristics of the oxide semiconductor stack can be improved. By supplying oxygen to the oxide semiconductor stack, oxygen vacancies in the film can be eliminated. It can be compensated for.

[0060] In the step of forming an oxide semiconductor stack over the oxide insulating film 436, The conductor layer 101 and the second oxide semiconductor layer 102 are preferably formed so that hydrogen or water is not contained therein. In order to achieve this, before the formation of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102, As a treatment, the substrate on which the oxide insulating film 436 is formed is heated in a preheating chamber of a sputtering apparatus. Impurities such as hydrogen and moisture adsorbed on the substrate and the oxide insulating film 436 are desorbed and discharged by preheating. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. .

[0061] The oxide semiconductor layer used in the oxide semiconductor stack is at least indium (In) or It is preferable that the alloy contains zinc (Zn). It is particularly preferable that the alloy contains In and Zn. As a stabilizer to reduce the variation in electrical characteristics of oxide-based transistors In addition, it is preferable to have gallium (Ga) in addition to them. It is preferable to use tin (Sn) as a stabilizer. It is preferable that the stabilizer is aluminum (Al). It is preferred.

[0062] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0063] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0064] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. It should be noted that the energy gap of the same material may be different between single crystal and non-single crystal. Therefore, it is important to select the appropriate crystal state. As shown in the diagram, the materials of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are Select .

[0065] In addition, as the oxide semiconductor stack, an oxide semiconductor film that contains crystals and has crystallinity (a crystalline oxide The crystalline state of the crystalline oxide semiconductor film is The directions of the axes may be random or may have a certain orientation.

[0066] For example, the crystalline oxide semiconductor film may be an oxide semiconductor film having crystals with a c-axis approximately perpendicular to the surface. A nitride semiconductor film can be used.

[0067] The oxide semiconductor film including crystals having a c-axis approximately perpendicular to the surface does not have a single crystal structure. CAAC-OS (C Axis Al ignited Crystalline Oxide Semiconductor film be.

[0068] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure having crystalline and amorphous parts in the amorphous phase. The crystal part must be small enough to fit within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0069] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0070] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0071] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0072] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0073] The thickness of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is 5 nm or more and 10 nm or less. nm or less (preferably 5 nm to 30 nm) and sputtering method, MBE (Mo crystalline beam epitaxy, CVD, pulsed laser deposition, AL D (Atomic Layer Deposition) method, etc. can be used as appropriate. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed by sputtering. This is a process in which multiple substrate surfaces are set approximately perpendicular to the target surface and then film formation is performed. The film may be formed using a sputtering device.

[0074] Note that the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed in a low temperature range due to the presence of oxygen. For example, a sputtering method is used under conditions where oxygen is abundant (100% oxygen atmosphere). The oxide semiconductor is preferably in a crystalline state. The film contains a region in which the oxygen content is excessive with respect to the stoichiometric composition ratio. preferable.

[0075] Note that in this embodiment, the first oxide semiconductor layer 101 is formed by a sputtering method. For example, the composition ratio of the target for this purpose is In. 2 O 3 :Ga 2 O 3 :Zn Using a metal oxide target with a molar ratio of O = 1:1:2, In-Ga-Zn oxide The material and composition of the target are not limited, and may be, for example, In 2 O 3 :Ga 2 O 3 A metal oxide target having a ZnO molar ratio of 1:1:1 may also be used. .

[0076] The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed by a sintering machine. The sputtering gas is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is preferable to use:

[0077] The oxide insulating film 436 and the stack of oxide semiconductor layers can be successively formed without exposure to air. It is preferable that the oxide insulating film 436 and the oxide semiconductor stack be formed in succession without exposure to air. This prevents impurities such as hydrogen and moisture from being adsorbed onto the surface of the oxide insulating film 436. It is possible.

[0078] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0079] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0080] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0081] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0082] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0083] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0084] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. Then, it is heated at a temperature between 1000℃ and 1500℃ to produce polycrystalline In-G The target is a-Zn-O compound. X, Y, and Z are any positive numbers. The specified mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo The powder types and their mixing ratios depend on the sputtering process to be produced. The thickness may be appropriately changed depending on the target.

[0085] In this embodiment, as shown in FIG. 2A, the formed oxide semiconductor stack is a first photoresist. The island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 are formed by a lithography process. The island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 are processed into a conductor layer 102. A resist mask for forming the compound semiconductor layer 102 may be formed by an ink-jet method. When the resist mask is formed by the inkjet method, no photomask is used, so the manufacturing process is This reduces manufacturing costs.

[0086] Note that the etching of the oxide semiconductor stack can be either dry etching or wet etching. For example, an etchant used for wet etching of an oxide semiconductor film may be used. The mixing solution may be a mixture of phosphoric acid, acetic acid, and nitric acid. TO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0087] Next, the island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 are covered with In this way, an oxide semiconductor stack 403 is formed. The third oxide semiconductor layer 103 is formed from the same target as the first oxide semiconductor layer 101. The third oxide semiconductor layer 103 is formed under the same deposition conditions as the first oxide semiconductor layer. Since this is the same as 101, the explanation will be omitted here. The second oxide semiconductor layer 102 is overlapped with the second oxide semiconductor layer 102 by the above-mentioned process. The third oxide semiconductor layer 103 is formed so as to have a top shape larger than its surface area.

[0088] Next, excess hydrogen (including water and a hydroxyl group) is removed from the oxide semiconductor stack 403 (dehydration or The temperature for the heat treatment is 300°C or higher for 7 The temperature must be below 00°C or below the distortion point of the substrate. Heat treatment must be performed under reduced pressure or in a nitrogen atmosphere. For example, a substrate is introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor is The conductor laminate 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0089] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0090] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0091] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0092] After the oxide semiconductor stack 403 is heated by the heat treatment, the heating temperature is maintained or increased. While slowly cooling from the heat temperature, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra pure oxygen gas are added to the same furnace. Dry air (measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter When the moisture content is measured, it should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. , more preferably air of 10 ppb or less) may be introduced. Oxygen gas or nitrous oxide It is preferable that the oxygen gas does not contain water, hydrogen, etc. The purity of the nitrogen gas or dinitrogen monoxide gas is 6N or more, preferably 7N or more (i.e., oxygen gas). Or the impurity concentration in the nitrous oxide gas is 1 ppm or less, preferably 0.1 ppm or less. It is preferable that the dehydration or dehydration is performed by the action of oxygen gas or nitrous oxide gas. The oxide semiconductor that is reduced by the process of removing impurities through the oxidation process By supplying oxygen, which is a main component of the oxide semiconductor stack 403, the oxide semiconductor stack 403 is highly purified and It can be made into type i (intrinsic).

[0093] Next, a source electrode layer and a drain electrode layer (the same layer as this The conductive film is formed to be a wiring (including wiring formed by the method described above). As a conductive film used for the source electrode layer and the drain electrode layer, for example, A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, the lower or upper side of a metal film such as Al or Cu may be used. Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film A laminated structure of a silicon nitride film, a molybdenum nitride film, and a tungsten nitride film may also be used. The conductive film used for the source electrode layer and the drain electrode layer is formed of a conductive metal oxide. Indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide (In 2 O 3 -SnO 2 ), I oxide Indium zinc oxide (In 2 O3 -ZnO) or silicon oxide on these metal oxide materials can be used.

[0094] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by etching, a resist The mask is removed. The cross section at this stage is shown in FIG. 2(B). A tungsten film having a thickness of 10 nm is formed as the electrode layer 405a and the drain electrode layer 405b. In this way, when the source electrode layer 405a and the drain electrode layer 405b are thin, In addition, the coverage of the gate insulating film 442 to be formed on the source electrode layer 405a and the drain electrode layer 405b is improved. The oxide semiconductor layer 405b passes through the source electrode layer 405a and the drain electrode layer 405b. Dopants may be introduced into the conductor stack 403 .

[0095] Next, the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405b are A gate insulating film 402 is formed to cover the substrate 401 .

[0096] The thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less. Methods such as a CVD method, a pulsed laser deposition method, and an ALD method can be used as appropriate. The insulating film 402 is formed by depositing a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that performs film formation in a set state.

[0097] The material of the gate insulating film 402 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitride oxide film. It can be formed using a silicon film.

[0098] The material of the gate insulating film 402 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and the use of high-k materials such as lanthanum oxide allows the gate Furthermore, the gate insulating film 402 may have a single layer structure or a multilayer structure. It can also be used as a structure.

[0099] Next, as shown in FIG. 2C, a source electrode layer 405a and a drain electrode layer 405b are Oxygen 431 is introduced into the oxide semiconductor stack 403 using the mask. and introducing at least a third radical, an oxygen atom, or an oxygen ion into the reaction system. Oxygen is supplied to the oxide semiconductor layer. The oxygen is introduced by ion implantation, ion doping, etc. ion implantation, plasma immersion ion implantation, plasma processing, etc. It can be used.

[0100] By introducing oxygen into the oxide semiconductor stack 403, The region that does not overlap with the source electrode layer 405a or the drain electrode layer 405b is the source electrode layer 405b. and a region overlapping with the drain electrode layer 405a or the drain electrode layer 405b. By the oxygen introduction treatment, the source electrode layer 405a or the drain electrode layer 405b The oxygen content in the non-overlapping region is set to a level exceeding the stoichiometric composition ratio. For example, the oxide semiconductor film in the region where oxygen is introduced by the oxygen introduction process is preferably The peak oxygen concentration in layer 403 is 1×10 18 / cm 3 5×10 or more 21 / cm 3 The following It is preferable to do so.

[0101] In this embodiment, oxygen 431 is introduced to make the oxygen amount larger than the stoichiometric composition ratio. As an additional region (oxygen excess region), a first oxygen excess region 111, a second oxygen excess region The second oxygen excess region 112 and the third oxygen excess region 113 are formed in a self-aligned manner. At least the third oxide semiconductor layer 103 and the gate insulating film 402 are contained in the interface. Therefore, depending on the depth to which the oxygen 431 is introduced, the first oxide semiconductor layer 101 and The oxygen concentration in the oxide semiconductor layer 102 in the second embodiment is In some cases, the area overlapping with the electrode layer 405b may be the same as the other area. The depth of oxygen introduction into the semiconductor layer 403 is determined by the injection conditions such as the acceleration voltage and the dose amount, and the amount of oxygen that is passed through the The thickness of the gate insulating film 402 can be appropriately set and controlled.

[0102] The timing of introducing oxygen 431 is limited to after the gate insulating film 402 is formed. However, if oxygen is introduced through a film stacked on the oxide semiconductor stack 403, the oxygen Since the introduction depth (introduction region) of oxygen can be easily controlled, the oxygen can be introduced into the oxide semiconductor stack 403. This has the advantage that it can be injected efficiently.

[0103] After the introduction of oxygen 431, a heat treatment may be performed. The heating conditions are a temperature of 25 The reaction is carried out at a temperature of 0°C to 700°C, preferably 300°C to 450°C, in an oxygen atmosphere. It is also preferable to carry out the heat treatment under a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air). Good too.

[0104] When at least one layer of the oxide semiconductor stack is a crystalline oxide semiconductor film, the introduction of oxygen 431 In this case, the heat treatment should be performed after the introduction of oxygen 431. By this, the crystallinity of the stacked oxide semiconductor layers can be restored.

[0105] In addition, by forming an oxygen excess region in the oxide semiconductor stack 403, oxygen vacancies can be immediately compensated for. Therefore, the charge trapping centers in the oxide semiconductor stack 403 can be reduced. In the oxide semiconductor stack 403, oxygen vacancies exist in the portions from which oxygen is released. The electron vacancy causes a donor level that causes a change in the electrical characteristics of the transistor. By introducing such oxide, oxygen vacancies in the film can be compensated for. By using semiconductor stacks in transistors, the threshold voltage of the transistors caused by oxygen vacancies can be reduced. It is possible to reduce the variation in voltage Vth and the shift in threshold voltage ΔVth. The threshold voltage can be shifted in the positive direction to make the transistor normally off.

[0106] Next, the gate electrode layer 401 is formed by plasma CVD or sputtering. The gate electrode layer 401 is formed on the insulating film 402. The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, or the like. Metallic materials such as zinc, tungsten, aluminum, copper, chromium, neodymium, and scandium The gate electrode layer can be formed using a material selected from the group consisting of fluorine, ... 401 is a semiconductor, typically a polycrystalline silicon film doped with impurity elements such as phosphorus Alternatively, a silicide film such as nickel silicide may be used. It may have a layered structure or a laminated structure.

[0107] The material of the gate electrode layer 401 is indium tin oxide or indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide A conductive material such as indium tin oxide doped with the above-mentioned conductive material can also be used. It is also possible to use a laminated structure of an electrically conductive material and the above-mentioned metal material.

[0108] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 402 is made of a metal oxide containing nitrogen. oxides, specifically, In-Ga-Zn oxide films containing nitrogen and In-Sn oxide films containing nitrogen. oxide film, an In-Ga-based oxide film containing nitrogen, an In-Zn-based oxide film containing nitrogen, Nitrogen-containing Sn-based oxide films, nitrogen-containing In-based oxide films, and metal nitride films (InN, Sn N, etc.) can be used. These films have a work energy of 5 eV, preferably 5.5 eV or more. When the gate electrode layer is used, the threshold voltage of the transistor is It is possible to make it positive, and thus to realize a so-called normally-off switching element.

[0109] Next, a process for selectively introducing dopants 421 is preferably performed. Using the gate electrode layer 401 as a mask, the first low resistance region 12 is 1a, 121b, the second low resistance region 122a, 122b, the third low resistance region 123a, In this process, the first channel forming region 121c is sandwiched in the channel length direction. The first low resistance regions 121a and 121b are formed in a self-aligned manner. The second low resistance regions 122a and 122b are arranged in the axial direction with the second channel formation region 122c interposed therebetween. The third channel forming region 123c is sandwiched between the first and second channel forming regions 123a and 123b in the channel length direction. Thus, the third low resistance regions 123a and 123b are formed in a self-aligned manner.

[0110] In the transistor 510 of the present embodiment, the first low-resistance regions 121a and 121b and the The second low resistance regions 122a, 122b and the third low resistance regions 123a, 123b are This results in a punt and an area with excess oxygen.

[0111] Furthermore, the gate insulating film 402, the source electrode layer 405a, and the drain electrode layer 405b are formed by this process. 405b, the oxide semiconductor stack 403 (at least the third oxide semiconductor layer 103) A dopant 421 is selectively introduced into the first region 121d, 121e, the second region 121c, and the 2d, 122e, and third regions 123d, 123e are formed (see FIG. 2(D)). The dopant 421 is also introduced under the source electrode layer 405a and the drain electrode layer 405b. This results in first regions 121d and 121e, second regions 122d and 122e, and a third region This allows the resistance of the regions 123d and 123e to be reduced.

[0112] A dopant 421 is introduced to form a low resistance region sandwiching a channel formation region in the channel length direction. By forming the oxide semiconductor stack 403, the on-state characteristics of the transistor 510 are improved. This allows a transistor to operate at high speed and respond at high speed. Since the gate electrode layer is formed in a self-aligned manner and does not overlap the gate electrode layer, the parasitic capacitance can be reduced. Reducing the parasitic capacitance leads to a reduction in the power consumption of the entire semiconductor device. Gar.

[0113] In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are formed as thin films. In order to achieve this, the oxide semiconductor stack 4 below the source electrode layer 405a and the drain electrode layer 405b is The dopant 421 is also introduced into the source electrode layer 405a and the drain electrode layer 403. Depending on the thickness of the dopant 421 and the thickness of the source electrode layer 405a and the dopant 421 introduction conditions, The dopant 421 is not introduced into the oxide semiconductor stack below the drain electrode layer 405b. It is also possible.

[0114] The dopant 421 introduction process is performed by controlling the implantation conditions such as the acceleration voltage and the dose amount, and the gate The thickness of the gate insulating film 402 can be appropriately set and controlled. When implanting boron ions using the boron implantation method, the dose is set to 1×10 13 ions / cm 2 Below top 5×10 16 ions / cm 2 The following would suffice.

[0115] The first low resistance regions 121a and 121b, the second low resistance regions 122a and 122b, and the third low resistance regions 121a and 121b, The concentration of the dopant 421 in the low resistance regions 123a and 123b is 5×10 18 / c m 3 More than 1×10 22 / cm 3 It is preferable that:

[0116] The dopant may be introduced while the substrate 400 is being heated.

[0117] The first low resistance regions 121a and 121b, the second low resistance regions 122a and 122b, The process of introducing the dopant 421 into the low resistance regions 123a and 123b in the third embodiment is carried out multiple times. A plurality of dopants may be used.

[0118] After the dopant 421 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0119] When at least one layer of the oxide semiconductor stack is a crystalline oxide semiconductor film, the dopant 42 The introduction of 1 may cause some amorphous structures. In this case, after the introduction of dopant 421, By performing the heat treatment, the crystallinity of the stacked oxide semiconductor layers can be restored.

[0120] In this embodiment, boron is used as the dopant. a, 121b, second low resistance regions 122a, 122b, and third low resistance region 123a, 123b contains boron and excess oxygen.

[0121] Through the above steps, the transistor 510 of this embodiment is manufactured.

[0122] Note that an insulating film 407 may be formed so as to cover the transistor (FIG. 1B and FIG. 1C). (See (C)).

[0123] The insulating film 407 may be a silicon oxide film, or may be an aluminum oxide film or a silicon oxynitride film. An inorganic insulating film such as an aluminum oxide nitride film, an aluminum oxide film, or a gallium oxide film can be used. For example, a laminate of a silicon oxide film and an aluminum oxide film can be used as the insulating film 407. It is possible.

[0124] An aluminum oxide film that can be used as the insulating film 407 is resistant to impurities such as hydrogen and moisture. The membrane has a high blocking effect, preventing both water and oxygen from passing through it.

[0125] Alternatively, a planarization insulating film may be used as the insulating film 407. Organic materials such as amide resin, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. In addition, a planarizing insulating film is formed by stacking multiple insulating films made of these materials. You may do so.

[0126] Next, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 407. Wirings are formed in the openings to electrically connect the source electrode layer 405a and the drain electrode layer 405b. This wiring layer is used to connect to other transistors and form various circuits. It is possible.

[0127] Note that the transistor described in this embodiment is made of oxide semiconductors having different energy gaps. The oxide semiconductor layer includes a conductor and a stack of the oxide semiconductor layers. The oxide semiconductor stack 4 has a region containing excess oxygen. It is not necessary to introduce impurities into 03. For example, in the manufacturing process shown in FIG. After the gate electrode layer 401 is formed, the gate insulating film 402 and the gate By forming an insulating film 407 over the second electrode layer 401, a transistor 520 shown in FIG. It can be achieved.

[0128] The transistor 520 illustrated in FIG. 3 includes a substrate having an insulating surface provided with an oxide insulating film 436. On the plate 400, a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are a source electrode layer 405a, a drain electrode layer 405b, and The gate insulating film 402 overlaps with the oxide semiconductor stack 403 with the gate insulating film 402 interposed therebetween. and a gate electrode layer 401 .

[0129] In the transistor 520, the oxide semiconductor stack 403 includes the source electrode layer 405a or The first oxygen excess region 11 is formed in a self-aligned manner using the drain electrode layer 405b as a mask. 1. The second oxygen excess region 112, the third oxygen excess region 113, and the source electrode layer 405a Alternatively, the first regions 131d and 131e and the second region 131c overlapping with the drain electrode layer 405b may be 32d, 132e and third regions 133d, 133e.

[0130] The region not overlapping with the source electrode layer 405a or the drain electrode layer 405b (the first oxygen-excess The region 111, the second oxygen excess region 112, and the third oxygen excess region 113 are The region overlapping with the drain electrode layer 405a or the drain electrode layer 405b (the first region 131d, e, the second region 132d, 132e and the third region 133d, 133e) Although the concentrations are the same in both regions, the constituent elements are the same.

[0131] The highly purified and oxygen-free semiconductor used in the transistor 510 or the transistor 520 Impurities such as hydrogen and water are sufficiently removed from the filled oxide semiconductor stack 403. The hydrogen concentration in the oxide semiconductor stack 403 is 5×10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 The hydrogen concentration in the oxide semiconductor stack 403 is determined by the secondary ion mass. Secondary Ion Mass Spectrometer (SIMS) y).

[0132] The oxide film produced by the present embodiment is highly purified and contains an excess of oxygen to compensate for the oxygen deficiency. The transistor using the stacked semiconductor layer 403 has a current value in an off state (off current value). , 100zA / μm per 1μm of channel width at room temperature (1zA (zeptoampere) is 1× 10 -21 A) or less, preferably 10zA / μm or less, more preferably 1zA / μm or less , and more preferably, can be reduced to a level of 100 yA / μm or less.

[0133] In the transistors 510 and 520 described in this embodiment, A third oxide semiconductor is formed so as to cover the side surfaces of the oxide semiconductor layer and the second oxide semiconductor layer. With this configuration, oxygen vacancies in the second oxide semiconductor layer are eliminated. Therefore, the increase in the threshold voltage of the transistor can be suppressed and the threshold voltage of the transistor can be made close to zero. Furthermore, the second oxide semiconductor layer serves as a buried channel, which reduces carrier scattering. Therefore, high field effect mobility can be achieved.

[0134] In addition, the second oxide semiconductor layer having a small energy gap is By using a structure in which the first oxide semiconductor layer and the third oxide semiconductor layer are sandwiched, This has the effect of further reducing the off-state current (leakage current) of the transistor.

[0135] By using the transistors with excellent electrical characteristics obtained in this way, high performance and high reliability semiconductors can be realized. A body device can be provided.

[0136] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0137] (Embodiment 2) In this embodiment, an example of a transistor obtained by partially modifying the process of the first embodiment is shown. 4(A) to (E). Since there are only some differences from the first embodiment, the same is used for simplicity. The same reference numerals will be used in the description, and detailed description of the same parts will be omitted here.

[0138] A transistor 530 illustrated in FIG. 4A includes a first oxide semiconductor layer and a second oxide semiconductor layer. When processing the layer into islands, the same mask is used (or the first island created by processing is used). Using the first oxide semiconductor layer and the second oxide semiconductor layer as masks, The oxide insulating film 43 in the transistor 530 is thinned by etching. The region overlapping with the island-shaped first oxide semiconductor layer and the second oxide semiconductor layer is The first oxide semiconductor layer and the second oxide semiconductor layer have a larger thickness than the first oxide semiconductor layer and the second oxide semiconductor layer. When the second oxide semiconductor layer is processed into an island shape, part of the oxide insulating film 436 is also etched. By this, etching residues such as residues of the first oxide semiconductor layer are removed, and leakage current is reduced. The occurrence of current can be reduced.

[0139] The transistor 540 shown in FIG. 4B is formed by three photolithography steps. The oxide semiconductor stack 403 is formed. The conductor stack 403 is formed by forming a first oxide semiconductor layer and then forming an island-shaped first An oxide semiconductor layer is formed, and a second oxide semiconductor layer is formed on the island-shaped first oxide semiconductor layer. Then, a second oxide semiconductor layer having an island shape is formed using a second mask, and the first and second island-shaped oxide semiconductor layers are After a third oxide semiconductor layer is formed over the oxide semiconductor layer, the third oxide semiconductor layer is It is formed by processing it into an island shape using a mask.

[0140] Note that in the transistor 540, the side surface of the first oxide semiconductor layer is in contact with the side surface of the second oxide semiconductor layer. The third oxide semiconductor layer is formed on one side of the first oxide semiconductor layer. The third region 12 corresponds to an end of the third oxide semiconductor layer. The first regions 121d and 121e correspond to the ends of the first oxide semiconductor layer. They touch and overlap with e.

[0141] In addition, in the transistor 550 illustrated in FIG. 4C, the source electrode layer is a source electrode layer 405c. The source electrode layer 405a is laminated, and the drain electrode layer 405b is laminated. The laminated structure of the in-electrode layer 405b includes a source electrode layer 405c and a drain electrode layer 405d. In this example, the wiring layers 465a and 465b are formed so as to reach the insulating film 407. The source electrode layer 405a or In some cases, a part of the drain electrode layer 405b may be removed by over-etching. In the transistor 550, the source electrode layer 405a and the drain electrode layer 405b are stacked. In this case, the lower conductive layer can function as an etching stopper.

[0142] In the transistor 550 described in this embodiment, the source electrode layer 405c and the drain A tungsten film or a tantalum nitride film is used as the electrode layer 405d, and the upper layer is thicker than the lower layer. A copper film or an aluminum film as the source electrode layer 405a and the drain electrode layer 405b The source electrode layer 405a and the drain electrode layer 405b in FIG. By setting the thickness to 5 nm or more and 15 nm or less, the coverage of the gate insulating film 402 formed thereon is improved. In the present embodiment, the wiring layer 465a and the wiring layer 4 65b is a laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film. This makes it possible to reduce the contact resistance.

[0143] In addition, a transistor 560 illustrated in FIG. 4D includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a The conductor layer and the third oxide semiconductor layer are formed in a single photolithography process using the same mask. The oxide semiconductor stack 403 is formed by the above-mentioned method. The oxide semiconductor stack 403 includes a first oxide semiconductor layer, a second oxide semiconductor layer, and The oxide semiconductor layer of 3 has the same shape as the oxide semiconductor layer of 3, and the ends of the oxide semiconductor layer are aligned. In the semiconductor stack 403, the side surfaces (edges) of the first oxide semiconductor layer and the second oxide semiconductor layer are The part is exposed.

[0144] The oxide semiconductor stack 403 is formed in one photolithography process. This allows the number of transistors to be reduced, thereby reducing the manufacturing cost of the semiconductor device. In the transistor 560, the source electrode layer 405a and the drain electrode layer 405b are formed using a third oxide. The second oxide semiconductor layer is formed so as to be in contact with only the top surface of the second oxide semiconductor layer or only the top surface and side surfaces of the third oxide semiconductor layer. By providing the source electrode layer 405a and the drain electrode layer 405b over the third oxide semiconductor layer, A structure in which 405b is not in contact with the side surface of the second oxide semiconductor layer can be used. By using this structure, the leakage current (parallel This is preferable because it can reduce the occurrence of raw channels.

[0145] The oxide semiconductor stack 403 does not necessarily have to have a three-layer structure. The transistor 570 shown in FIG. 1 has two oxide semiconductor layers, a first oxide semiconductor layer and a second oxide semiconductor layer. The transistor 570 includes an oxide semiconductor stack 403 having a layer structure. The second oxide semiconductor layer overlaps the first oxide semiconductor layer and has a surface contact with the first oxide semiconductor layer. By making the area larger than the area of ​​the first oxide semiconductor layer, the first oxide semiconductor layer can be enclosed. With such a structure, an increase in oxygen vacancies in the first oxide semiconductor layer can be suppressed, The threshold voltage of the transistor can be made close to zero. In the case of the oxide insulating film 436 in the photodiode 570, an aluminum oxide film is included. In this case, oxygen can be prevented from being released from the insulating film in contact with the first oxide semiconductor layer. I wish.

[0146] A transistor 570 illustrated in FIG. 4E has a semiconductor layer formed over and in contact with a second oxide semiconductor layer. The source electrode layer 405a or the drain electrode layer 405b is in contact with a side surface of the first oxide semiconductor layer. Since the source electrode layer 405a and the drain electrode layer 405b can be formed without the need for a gate insulating film, This is preferable because it is possible to reduce the occurrence of leakage current (parasitic channel).

[0147] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0148] (Embodiment 3) A semiconductor having a display function using the transistor described in Embodiment 1 or 2 In addition, a driver circuit including a transistor can be manufactured. A part or the whole of the above is formed integrally on the same substrate as the pixel section to form a system-on-panel. It is possible.

[0149] In FIG. 5A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the semiconductor device is sealed with a second substrate 4006. In A), a region surrounded by a sealant 4005 on a first substrate 4001 and The semiconductor layer is formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate in a different region. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are also mounted. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a signal line driver circuit 4005 are provided to the pixel portion 4002. Various signals and potentials are transmitted through the FPC (Flexible Printed Circuit). )Powered by 4018a and 4018b.

[0150] In FIG. 5B and FIG. 5C, a pixel portion 400 provided on a first substrate 4001 A sealant 4005 is provided so as to surround the gate electrode 2 and the scanning line driver circuit 4004. A second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed on the first substrate 4001. The display element is sealed by a sealant 4005 and a second substrate 4006. In FIG. 5(B) and FIG. 5(C), the first substrate 4001 is surrounded by a sealant 4005. A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region where the semiconductor device is mounted. A signal line driver circuit 4003 formed of a conductor film is mounted. In the embodiment, a signal line driver circuit 4003 and a scanning line driver circuit 4004 are separately formed. Various signals and potentials applied to the pixel portion 4002 are supplied from an FPC 4018 .

[0151] In addition, in FIG. 5B and FIG. 5C, a signal line driver circuit 4003 is separately formed. In the illustrated example, the scanning line driver is mounted on a single substrate 4001, but the present invention is not limited to this configuration. Alternatively, a driving circuit may be formed separately and mounted, or a part of a signal line driving circuit or a scanning line driving circuit may be mounted. Only a part of it may be formed separately and mounted.

[0152] The method of connecting the separately formed drive circuit is not particularly limited, and may be any of the following: ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a utomated bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 5B shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 4003) is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0153] The display device includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above, are mounted.

[0154] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with printed wiring board attached The IC (integrated circuit) is directly mounted on the installed module or display element using the COG method. The display device includes all of the modules installed in the display device.

[0155] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistors described in the first embodiment or the second embodiment can be used. .

[0156] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements ( The light-emitting element can be used as a light-emitting display element. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0157] One mode of a semiconductor device will be described with reference to FIGS. 5 and 6. FIG. 6 shows the M Equivalent to the cross-sectional view at -N.

[0158] As shown in FIG. 5 and FIG. 6, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminals of the FPC 4018. and electrically connected via an anisotropic conductive film 4019 .

[0159] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is a source electrode layer and a drain electrode layer of the transistors 4040, 4010, and 4011. The conductive film is formed of the same material as the layer.

[0160] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. The pixel portion 4002 includes a plurality of transistors. 4040 and a transistor 4011 included in the scanning line driver circuit 4004. In addition, in FIG. 6B, a transistor 4010 included in a pixel portion 4002 and a scan line A transistor 4011 included in the driver circuit 4004 is illustrated in FIG. An insulating film 4020 is provided over the transistors 4040 and 4011. An insulating film 4020 and an insulating film 4021 are provided on the transistors 4010 and 4011. Note that the insulating film 4023 functions as a base film.

[0161] The transistor 4011 included in the scan line driver circuit 4004 may be any of the transistors described in Embodiment 1 or The transistor having a buried channel described in Embodiment 2 can be used. Transistors with buried channels have the following characteristics: on-state current and field-effect transition This embodiment has a high pixel shift rate, which enables high-speed operation and high-speed response of the scanning line driver circuit 4004. In this embodiment, a transistor having a structure similar to that of the transistor described in Embodiment 1 is used. Here is an example.

[0162] The transistors 4010 and 4040 provided in the pixel portion 4002 are electrically connected to the display element. The display element is not particularly limited as long as it can display a picture, and various kinds of display elements can be used. Such a display element can be used.

[0163] In addition, the transistor 4040 included in the pixel portion 4002 is, in particular, a buried channel Therefore, the transistor 40 having a single oxide semiconductor layer as a channel formation region can be used. This transistor 4040 can be manufactured without increasing the number of steps. The transistor 4040 can be manufactured in the same process as that of the transistor 011. The oxide semiconductor layer is formed in the same process as the third oxide semiconductor layer of the transistor 4011. The transistor 4040 can improve the on-state characteristic especially in the case of a display device other than a large display device. The transistor 4040 has a single oxide semiconductor layer. The off-current value can be made lower than that of the 4011 transistor, realizing a display device with low power consumption. can.

[0164] FIG. 6(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal element 4013 which is a display element, a first electrode layer 4030 and a second electrode layer 403 1, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between two layers functioning as alignment films. The second electrode layer 4031 is formed on the second substrate. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the liquid crystal layer 400 The structure is such that the layers are stacked via 8.

[0165] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. It is provided to control the thickness (cell gap) of the liquid crystal layer 4008. A pacer may be used.

[0166] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material (liquid crystal composition) can be in a cholesteric phase, a smectic phase, or a cubic phase. The phases shown are biaxial, chiral nematic, isotropic, etc.

[0167] In addition, the liquid crystal layer 4008 may be made of a liquid crystal composition that exhibits a blue phase without using an alignment film. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase is a phase that appears just before the transition from the black phase to the isotropic phase. The blue phase can be expressed by using a liquid crystal composition in which the above-mentioned liquid crystals are mixed. In order to widen the range of the blue phase, a polymerizable monomer and a polymerization initiator are added to the liquid crystal composition that exhibits the blue phase. The liquid crystal layer can be formed by adding a polymer stabilizer. The liquid crystal composition that exhibits this phase has a short response time and is optically isotropic, so no alignment treatment is required. The viewing angle dependence is small. Also, since there is no need to provide an alignment film, rubbing treatment is not required. Therefore, electrostatic damage caused by the rubbing process can be prevented, and the manufacturing process This reduces defects and damage to the liquid crystal display device during the manufacturing process. A transistor including an oxide semiconductor film can be prevented from being affected by static electricity. This can cause the electrical characteristics of the transistor to vary significantly and deviate from the design range. A liquid crystal display device having a transistor including an oxide semiconductor film and capable of exhibiting a blue phase can be provided. It is more effective to use a crystalline composition.

[0168] The specific resistance of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 11 Ω cm or more, and more preferably 1×10 12 In addition, this specification The resistivity values ​​stated herein are those measured at 20°C.

[0169] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into account factors such as the capacitance of the capacitor. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor having a semiconductor film, the liquid crystal capacitance of each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0170] The transistor 4040 including the oxide semiconductor film disclosed in this specification has a The current value (off-state current value) can be controlled to be low. This makes it possible to preserve electrical signals such as image signals. The holding time can be extended, and the writing interval can also be set longer when the power is on. This reduces the frequency of refresh operations, thereby reducing power consumption. do.

[0171] In addition, the transistor 4011 including the oxide semiconductor film disclosed in this specification has a field-effect Since the mobility can be controlled to be high, the scanning line driver circuit 4004 can be driven at high speed. According to this embodiment, the switching transistor in the pixel section and the transistor in the driving circuit section are The driver transistor can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed of a silicon wafer or the like, The number of parts in the device can be reduced.

[0172] In the pixel portion, a transistor having a stack of oxide semiconductor layers similar to that of the transistor 4011 is also used. A transistor capable of high speed operation may be used in the pixel portion. This makes it possible to provide high-quality images and large-area displays.

[0173] There are two types of LCD displays: TN (Twisted Nematic) and IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0174] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. The present invention can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to defeat molecules in a complex manner. The following method can be used.

[0175] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. Optical members (optical substrates) such as a prevention member are provided as appropriate. For example, a polarizing substrate and a retardation substrate Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0176] The display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is The color is not limited to the three colors red, green, and blue. For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but is applicable to monochrome display devices. It is also possible.

[0177] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element utilizing electroluminescence is made of a light-emitting material They are classified according to whether they are organic or inorganic compounds. Generally, the former are called organic E The latter is called an inorganic EL element.

[0178] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element. An explanation will be given using an EL element.

[0179] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission is from the top surface, the bottom emission is from the surface on the substrate side, and the bottom emission is from the surface on the substrate side and the opposite side to the substrate. There are light emitting devices with a double-sided emission structure that emits light from both sides, and light emitting devices of any emission structure can be used. It is possible.

[0180] FIG. 6B shows an example of a light-emitting device using a light-emitting element as a display element. The element 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4512. The light-emitting element 4513 has a stacked structure of two electrode layers 4031, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed appropriately according to the direction of the light to be extracted from the do.

[0181] The partition 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening is a continuous curved It is preferable to form the inclined surface so that the inclined surface is formed with a certain rate.

[0182] The electroluminescent layer 4511 may be composed of a single layer or may be composed of a plurality of layers stacked together. It doesn't matter whether it is done or not.

[0183] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective film may be formed on the insulating film 4031 and the partition wall 4510. The protective film may be made of silicon nitride. It is possible to form a silicon oxide nitride film, a DLC film, etc.

[0184] In addition, in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4513, A layer containing an organic compound that covers the electrode 4513 may be formed by evaporation.

[0185] In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4005 are sealed. The space is filled with a filler 4514 and sealed. Protective films with high airtightness and low outgassing (lamination films, UV curing resins) It is preferable to package (enclose) the product in a film or a cover material.

[0186] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, etc. Mido, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen may be used as a filler. stomach.

[0187] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0188] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display) and is similar to paper. It is possible to make it as easy to read as other display devices, consume less power, and have a thinner and lighter shape. This has the advantage that

[0189] The electrophoretic display device may have various forms, but it has a first particle having a positive charge and A microcapsule containing a negatively charged second particle and a negatively charged second particle is introduced into a solvent or solute. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and they do not migrate in the absence of an electric field. The color of the first particle and the color of the second particle are different (including colorless). )

[0190] In this way, the electrophoretic display device is a so-called This is a display that utilizes the dielectrophoretic effect.

[0191] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0192] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0193] In addition, display devices using the twist ball display method can also be used as electronic paper. The twist ball display method uses spherical particles painted in black and white on the display element. The electrode layer is disposed between the first electrode layer and the second electrode layer, which are the electrode layers to be used. This method creates a potential difference between the electrode layers to control the orientation of the spherical particles, thereby displaying information. be.

[0194] In addition, in FIG. 5 and FIG. 6, the first substrate 4001 and the second substrate 4006 are made of glass. In addition to a glass substrate, a flexible substrate can also be used. For example, a light-transmitting plastic substrate can be used. As for plastic, FRP (Fibreglass) is used. s-Reinforced Plastics) plate, PVF (Polyvinyl fluoride) A film, a polyester film or an acrylic resin film can be used. If transparency is not required, metal substrates such as aluminum and stainless steel (metal film For example, aluminum foil may be covered with a PVF film or polyester film. It is also possible to use a sheet sandwiched between two sheets.

[0195] In this embodiment, an aluminum oxide film is used as the insulating film 4020.

[0196] The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film is resistant to hydrogen, moisture, and the like. The membrane has a high blocking effect against both impurities such as urea and oxygen. stomach.

[0197] Therefore, the aluminum oxide film is free from hydrogen, which is a variable factor during and after the manufacturing process. The intrusion of impurities such as moisture into the oxide semiconductor film and the intrusion of the oxide semiconductor into the main component material The oxide semiconductor film functions as a protective film for preventing release of oxygen from the oxide semiconductor film.

[0198] The insulating film 4021 functioning as a planarizing insulating film is made of an acrylic resin, a polyimide resin, or Heat-resistant organic materials such as benzocyclobutene resins, polyamide resins, and epoxy resins In addition to the above organic materials, low-k materials, Siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. In addition, by stacking multiple insulating films made of these materials, the insulating film can be It may be formed.

[0199] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) for applying a voltage to the display element In the case of the electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the light reflecting property can be selected depending on the pattern structure of the electrode layer.

[0200] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide , indium tin oxide doped with silicon oxide, graphene, and other light-transmitting conductive materials Fees may be used.

[0201] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the following metals: Cut.

[0202] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0203] As described above, by using the transistor described in Embodiment 1 or 2, Semiconductor devices having various functions can be provided.

[0204] (Embodiment 4) Using the transistor shown in the first or second embodiment, information on an object is read. It is possible to manufacture a semiconductor device having an image sensor function.

[0205] FIG. 7A shows an example of a semiconductor device having an image sensor function. FIG. 7(B) is a cross-sectional view showing a part of the photosensor.

[0206] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode of the transistor 640 is electrically connected to the gate of the transistor 640. One of the source or drain is connected to the photosensor reference signal line 672, and the other of the source or drain is connected to the photosensor reference signal line 672. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The sensor output signal line 671 is electrically connected to the sensor output signal line 671.

[0207] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor film is not clearly shown. To make it easy to understand, the symbol for a transistor using an oxide semiconductor film is marked with “OS.” In FIG. 7A, a transistor 640 and a transistor 656 are the same as those in the first embodiment. or the transistor described in Embodiment 2 can be used. In this embodiment, a transistor having a structure similar to that of the transistor described in Embodiment 1 is used. An example of application of a transistor will be shown.

[0208] FIG. 7B shows a photodiode 602 and a transistor 640 in the photosensor. 6 is a cross-sectional view showing a TFT substrate 601 having an insulating surface, on which a TFT substrate 602 is formed. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on the board 602 and the transistor 640 using an adhesive layer 608. do.

[0209] On the transistor 640, an insulating film 631, an insulating film 632, an interlayer insulating film 633, and an interlayer insulating film The photodiode 602 is provided on the interlayer insulating film 633. An electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer 642 formed on the interlayer insulating film 634 Between the first semiconductor film 606a and the second semiconductor film 606b, a first semiconductor film 606c and a second semiconductor film 606d are formed in this order from the interlayer insulating film 633 side. 6b, and a third semiconductor film 606c.

[0210] The electrode layer 641 is electrically connected to a conductive layer 643 formed on the interlayer insulating film 634. 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is The photodiode 602 is electrically connected to the gate electrode layer of the transistor 640. It is electrically connected to the transistor 640 .

[0211] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film A high resistance semiconductor film (I-type semiconductor film) is used as 606b, and an n-type semiconductor film is used as the third semiconductor film 606c. A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0212] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous semiconductor film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed of a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g. boron (B)), plasma CVD method The semiconductor material gas is silane (SiH 4 ) can be used. Or, S i 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4 etc. may also be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is then subjected to diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using an ion implantation method or the like. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the method for forming the amorphous silicon film includes the LPCVD method, the vapor phase growth method, Alternatively, a sputtering method or the like may be used. It is preferable to form the film so that the thickness is 0 nm or less.

[0213] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A fast silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH 4 ) can be used. Or, Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , S iCl 4 , SiF 4 The second semiconductor film 606b may be formed by the LPCVD method, The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0214] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type conductivity. The third semiconductor film 606c is formed of a fast silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g. phosphorus (P)). Silane (SiH 4 ) can be used. Or, Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4 Also, impurities such as After forming an amorphous silicon film that does not contain elements, the material is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The method for forming the amorphous silicon film includes the LPCVD method, the vapor phase growth method, or the sputtering method. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that the bottom is facing downward.

[0215] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, a polycrystalline semiconductor may be used. Semiconductor Amorphous Semiconductor (SAS) It may be formed using a conductor.

[0216] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so Photodiodes exhibit better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed, the photodiode 602 This example shows how the light received by the semiconductor film is converted into an electrical signal. Since light from the semiconductor film side having the pattern becomes disturbance light, the electrode layer uses a conductive film with light blocking properties. In addition, the n-type semiconductor film side can be used as the light receiving surface.

[0217] The insulating film 632, the interlayer insulating film 633, and the interlayer insulating film 634 are made of an insulating material. Depending on the material, sputtering, plasma CVD, SOG, spin coating, and die deposition are used. Spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater It can be formed using the above.

[0218] In this embodiment, an aluminum oxide film is used as the insulating film 631. The film can be formed by a sputtering method or a plasma CVD method.

[0219] The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film is resistant to hydrogen, moisture, and the like. High blocking effect that prevents impurities and oxygen from passing through the membrane .

[0220] Therefore, the aluminum oxide film is free from hydrogen, which is a variable factor during and after the manufacturing process. The intrusion of impurities such as moisture into the oxide semiconductor film and the intrusion of the oxide semiconductor into the main component material The oxide semiconductor film functions as a protective film for preventing release of oxygen from the oxide semiconductor film.

[0221] The insulating film 632 may be made of an inorganic insulating material such as a silicon oxide layer, a silicon oxynitride layer, An oxide insulating film such as an aluminum oxide layer or an aluminum oxynitride layer, or a silicon nitride layer , a nitride such as a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer. A single layer or a stacked layer of an insulating film can be used.

[0222] The interlayer insulating films 633 and 634 function as planarizing insulating films to reduce surface irregularities. The interlayer insulating films 633 and 634 are preferably made of, for example, polyimide resin, acrylic resin, or the like. resins, benzocyclobutene resins, polyamide resins, epoxy resins, etc. In addition to the above organic insulating materials, low dielectric constant materials ( low-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron gas) A single layer such as a lath or a laminate can be used.

[0223] By detecting the light incident on the photodiode 602, information on the detected object is read. In addition, when reading the information of the detected object, a light source such as a backlight is used. It is possible.

[0224] As described above, by using a stack of oxide semiconductor layers having a buried channel, This allows for more precise control of the electrical characteristics of the transistor, making it possible to obtain the desired electrical characteristics. Therefore, by using this transistor, it is possible to achieve high performance and high reliability. It is possible to provide semiconductor devices that meet various objectives, such as high performance or low power consumption.

[0225] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0226] (Embodiment 5) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic equipment includes a television set (television or television receiver) (also called), computer monitors, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, games These electronic devices include machines (pachinko machines, slot machines, etc.) and game cabinets. An example is shown in Figure 8.

[0227] FIG. 8A shows a table 9000 having a display unit. A display portion 9003 is incorporated in a body 9001. The semiconductor device can be used in a display unit 9003, and displays an image on the display unit 9003. It is possible to show the above configuration. In addition, the housing 9001 has a power cord 9005 for power supply. .

[0228] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances and control them, improving the quality of images. The control device may be a control device that controls other home appliances by surface operations. If the semiconductor device having the image sensor function shown in the embodiment 3 is used, the display portion 9003 can be It is possible to provide a touch input function.

[0229] In addition, the screen of the display unit 9003 can be vertically supported on the floor by a hinge provided on the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrowed, but if you put it on a table, If the display unit is built in, the space in the room can be used more effectively.

[0230] FIG. 8B shows a television device 9100. The television device 9100 includes: A display portion 9103 is incorporated in a housing 9101. The semiconductor device can be used for a display portion 9103, and an image can be displayed through the display portion 9103. In this example, the housing 9101 is supported by a stand 9105. This shows the configuration.

[0231] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the display 9103 shows In addition, the remote control unit 9110 can control the image displayed on the remote control unit 9110. A display unit 9107 for displaying information output from 9110 may be provided.

[0232] A television device 9100 shown in FIG. 8(B) includes a receiver, a modem, and the like. The vision device 9100 can receive general television broadcasts using a receiver, and further By connecting to a wired or wireless communication network via a modem, (from sender to receiver) or bidirectional (between sender and receiver, or between receivers) It is also possible to carry out information communication.

[0233] By using the semiconductor device having the buried channel shown in the above embodiment, the semiconductor By using the device in the display portion 9103 of a television set, a display quality higher than that of a conventional device can be obtained. It may be a television device.

[0234] FIG. 8C shows a computer, which includes a main body 9201, a housing 9202, a display unit 9203, and a keyboard. It includes a board 9204, an external connection port 9205, a pointing device 9206, etc. The computer displays a semiconductor device manufactured according to one embodiment of the present invention on the display portion 9203. It is produced by using

[0235] In addition, by using the semiconductor device described in the above embodiment, the semiconductor device can be used as a computer. By using this in the display portion 9203, it is possible to provide a display portion with higher display quality than conventional display portions. It becomes.

[0236] FIG. 8D shows an example of a mobile phone. A mobile phone 9500 is provided in a housing 9501. In addition to the built-in display unit 9502, operation buttons 9503, external connection port 9504, The mobile phone 9500 is an embodiment of the present invention. The semiconductor device manufactured in this manner is used for the display portion 9502 .

[0237] In the mobile phone 9500 shown in FIG. 8D, information is displayed by touching the display portion 9502 with a finger or the like. You can type, make a call, or compose an email.

[0238] The screen of the display unit 9502 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. It is a mixture of two modes: display mode and input mode.

[0239] For example, when making a call or composing an e-mail, the display unit 9502 is used for inputting characters. The main input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 9502. stomach.

[0240] In addition, the mobile phone 9500 is equipped with a sensor that detects the inclination, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 9500 (portrait or landscape) can be determined. In this way, the screen display on the display unit 9502 can be automatically switched.

[0241] The screen mode can be switched by touching the display unit 9502 or by pressing the operation button on the housing 9501. The button 9503 is operated. Also, depending on the type of image displayed on the display unit 9502, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the mode switches to display mode, and if it is text data, the mode switches to input mode.

[0242] In the input mode, a signal detected by the optical sensor of the display unit 9502 is detected and displayed. If there is no input by touch operation of the part 9502 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0243] The display portion 9502 can also function as an image sensor. By touching the palm or fingers to the sensor 9502 and capturing an image of the palm print or fingerprint, the user can be authenticated. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0244] By using the semiconductor device described in the above embodiment, color bleeding, color shift, etc. in a display can be prevented. Since the semiconductor device is hardly generated, the display portion 9502 of the mobile phone can be used to It is possible to provide a mobile phone with a higher display quality than the conventional one. The pair of substrates is held together by a laser, making it extremely resistant to external forces such as shock and distortion. , can be suitably used as the mobile phone shown in FIG. 8(D).

[0245] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination. EXAMPLES

[0246] In this embodiment, a first oxide semiconductor layer is formed on the first oxide semiconductor layer. A second oxide semiconductor layer having a thickness smaller than that of the first oxide semiconductor layer is formed, and a third oxide semiconductor layer is formed on the second oxide semiconductor layer. A sample with a nitride semiconductor layer is prepared, and the ionization potential of the sample is measured. The energy band diagram was calculated based on the results. The potential value is the sum of the band gap and the electron affinity. The value is obtained by measuring a single film of the material using an ellipsometer.

[0247] The sample is a single crystal silicon substrate with a 5 nm thick IGZO film and a 5 nm thick In-Sn The deposition conditions for each layer were: The film was formed by sputtering at a substrate temperature of 300°C in an oxygen atmosphere (100% oxygen). The target used was an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. The In-Sn-Zn oxide film was formed by the following method: In:Sn:Zn= An oxide target with an atomic ratio of 2:1:3 is used.

[0248] In addition, a quartz substrate was used as the substrate, and a first film having a thickness of 5 nm was formed on the quartz substrate 1000 under the same film forming conditions. IGZO film 1001, 5 nm thick In-Sn-Zn oxide film 1002, 5 nm thick A TEM image of the cross section of sample 2 obtained by laminating the second IGZO film 1003. The true figure is shown in FIG. 11(A). A schematic diagram is shown in FIG. 11(B). In FIG. 11(B), The interface of the oxide semiconductor layer is shown by a dotted line, but is merely a schematic illustration. Depending on the conditions and heat treatment, the interface with each oxide semiconductor layer may become unclear. In sample 2 of 1(A), the interface between the In-Sn-Zn oxide film and the IGZO film can be seen. In FIG. 11A, the second IGZO film 1003 and the In-Sn-Zn oxide film 1002 is a crystalline oxide semiconductor film (CAAC-O) containing crystals and having a c-axis orientation. In FIG. 11(A), the first IGZO film 1001 In FIG. 11(A), two of the three layers have a crystalline structure. However, there is no particular limitation, and only the second IGZO film 1003 is a crystalline oxide semiconductor film. The three layers may have a crystalline structure, or all three layers may have an amorphous structure. It is also possible.

[0249] While sputtering from the surface of sample 1, ultraviolet photoelectron spectroscopy (UPS) was performed. Ionosphere by aviolet photoelectron spectroscopy The results of measuring the ionization potential are shown in FIG.

[0250] In FIG. 9, the horizontal axis represents the sputtering time from the sample surface, and the vertical axis represents the ionization potential. The potentials of the IGZO film and the In-Sn-Zn oxide film are shown in Fig. The boundary of the sample is shown assuming that the thickness is equal. It can be seen that the ionization potential is reduced in the In-Sn-Zn oxide film. The ionization potential represents the energy difference from the vacuum level to the valence band.

[0251] The conduction band is calculated by subtracting the band gap measured by ellipsometry from the ionization potential. The energy was calculated and the band structure of this laminated film was created. The band gaps of the Sn-Zn oxide films were set to 3.2 eV and 2.8 eV, respectively. The result is shown in Figure 10. In Figure 10, the energy band diagram is filled in like that shown in Figure 1(D). It can be seen that an in-between channel is formed.

[0252] In this embodiment, IGZO films are used as the first oxide semiconductor layer and the third oxide semiconductor layer. has a higher ionization potential than the first oxide semiconductor layer and the third oxide semiconductor layer. The second oxide semiconductor layer has a small energy gap and is made of In-Sn The stacked layer using the -Zn-based oxide film has the energy band diagram shown in Figure 10 or Figure 1(D). It was confirmed that the first oxide semiconductor layer, the second oxide semiconductor layer, and The combination of materials for the third oxide semiconductor layer is not particularly limited, and may be any of the materials shown in FIG. Considering the energy gap of the material used by the implementer, the energy band diagram shown in For example, the first oxide semiconductor layer and the third oxide semiconductor layer may be made of a material selected from the materials. The first oxide semiconductor layer is an IGZO film, and the second oxide semiconductor layer is an In-Sn-Z A laminated layer using an n-type oxide film may also be used. [Explanation of symbols]

[0253] 101 Oxide semiconductor layer 102 Oxide semiconductor layer 103 Oxide semiconductor layer 111 Oxygen excess region 112 Oxygen excess region 113 Oxygen excess region 121a First low resistance region 121b First low resistance region 121c Channel forming region 121d First Area 121e First Area 122a Second low resistance region 122b Second low resistance region 122c Channel formation region 122d The Second Region 122e Second Area 123a The third low resistance region 123b The third low resistance region 123c Channel forming region 123d The Third Region 123e The Third Realm 131d First Area 131e First Area 132d The Second Region 132e Second Area 133d The Third Region 400 Substrates 401 Gate electrode layer 402 Gate insulating film 403 Oxide Semiconductor Stacking 405a Source electrode layer 405b Drain electrode layer 405c Source electrode layer 405d Drain electrode layer 407 Insulating Film 421 Dopant 431 Oxygen 436 Oxide insulating film 442 Gate insulating film 465a Wiring layer 465b Wiring layer 510 Transistor 520 Transistor 530 Transistor 540 Transistor 550 Transistor 560 Transistor 570 Transistor 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating film 632 Insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 Transistor 641 Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photosensor reference signal line 1000 quartz substrate 1001 First IGZO film 1002 In-Sn-Zn oxide film 1003 Second IGZO film 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4040 Transistor 4510 Bulkhead 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling material 9000 Table 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9100 Television equipment 9101 Case 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9500 Mobile Phone 9501 Case 9502 Display section 9503 Operation button 9504 External connection port 9505 Speaker 9506 Microphone

Claims

[Claim 1] an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer having an energy gap different from that of the first oxide semiconductor layer; a source electrode layer or a drain electrode layer provided over the oxide semiconductor stack; a gate insulating film provided on the source electrode layer or the drain electrode layer; a gate electrode layer overlapping the oxide semiconductor stack with the gate insulating film interposed therebetween; a region of the oxide semiconductor stack that does not overlap with the source electrode layer or the drain electrode layer has a higher oxygen concentration than a region of the oxide semiconductor stack that overlaps with the source electrode layer or the drain electrode layer.

Images