Memory device

Abstract

To simplify a manufacturing process, reduce a size of a three-dimensional memory device, and improve a space availability of a chip in which the three-dimensional memory device is formed.SOLUTION: A memory device comprises: a substrate; a stack structure; at least one gate wire slit dividing the stack structure into at least two parts. The stack structure includes: a plurality of gate material layers and a plurality of insulation layers that are alternately arranged; and a plurality of two or more connection parts conductively connecting each gate material layer on a common one of a plurality of tiers. The plurality of tiers contains: a first tier; and a second tier that is a tier above the first tier. The two or more connection parts conductively connecting the gate material layers of the first tier contains the connection part having a length in a first direction being shorter than a length in the first direction of the two or more connection parts conductively connecting the gate material layer of the second tier.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to memory devices and methods of forming same.

[0002] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. 201710132422.8, filed on March 7, 2017, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Flash memory devices are being developed rapidly. Flash memory devices can store data for a significant amount of time without power, and have the advantages of high integration levels, fast access, easy erasure and rewriting, etc. To further improve the bit density and reduce the cost of flash memory devices, three-dimensional NAND flash memory devices have been developed.

[0004] A 3D NAND flash memory device includes a stack of gate electrodes arranged on a substrate with multiple semiconductor channels passing through word lines and crossing the word lines to the substrate. The lower / lower gate electrode acts as a lower / lower select gate. The upper / upper gate electrode acts as an upper / upper select gate. The word line / gate electrode between the upper / upper select gate electrode and the lower / lower gate electrode acts as a word line. The intersection of the word line and the semiconductor channel forms a memory cell. The upper / upper select gate is connected to a word line for row selection and the lower / lower select gate is connected to a bit line for column selection. Summary of the Invention

[0005] Accordingly, disclosed herein are embodiments of three-dimensional memory device architectures and manufacturing methods. The disclosed structures and methods provide many advantages, including, but not limited to, simplified manufacturing processes, reduced size of the three-dimensional memory devices, and improved space utilization of the chips on which the three-dimensional memory devices are formed.

[0006] In some embodiments, the three-dimensional memory device includes a substrate including a device region and a connection region adjacent to each other, and a plurality of separate stack structures in the device region and the connection region, the stack structures including a plurality of stack word lines (e.g., gate electrodes), and an isolation layer (e.g., gate line slits) on the substrate portion between the adjacent stack structures. The three-dimensional memory device also includes a connection structure on the connection region and conductively connecting the adjacent stack structures. The connection structure includes a plurality of repeating conductive connection portions, and two ends of each conductive layer each connect word lines of the same height in the adjacent stack structures. The three-dimensional memory device further includes a plurality of contact vias on the top surface of the word lines of each height. Each contact via is conductively connected to the contacting word line, other word lines of the same height as the contacting word line, and the conductive connection portion of the same height as the contacting word line.

[0007] In some embodiments, the conductive connections are made from the same material as the wordlines.

[0008] In some embodiments, the conductive connections and wordlines are made from one or more of tungsten, aluminum, and copper.

[0009] In some embodiments, the stack structure further includes a first insulating portion between adjacent gate structures, and the connection structure further includes a second insulating portion between adjacent conductive connection portions.

[0010] In some embodiments, the first insulating portion and the second insulating portion are made from silicon oxide.

[0011] In some embodiments, the substrate further comprises a channel region adjacent to one or more of the connection region and the device region. The stack structure extends to a portion of the substrate in the channel region. In some embodiments, the three-dimensional memory device further comprises a plurality of semiconductor channels above a portion of the substrate in the channel region, the semiconductor channels penetrating the stack structure.

[0012] In some embodiments, the three dimensional memory device further includes a gate dielectric layer between the word lines and the semiconductor channel.

[0013] In some embodiments, a method for forming a three-dimensional memory device includes providing a substrate, the substrate including a device region and a connection region adjacent to each other; forming a plurality of separate stack structures in the device region and the connection region, the stack structure including a plurality of stacked word lines; and forming an isolation layer (e.g., gate line slits) on a substrate portion between adjacent stack structures. The method also includes forming a connection structure over the connection region and conductively connecting adjacent stack structures. The connection structure includes a plurality of repeating conductive connection portions, and two ends of each conductive layer each connect word lines of the same height in adjacent stack structures. The method further includes forming a plurality of contact vias on a top surface of each word line of each height. Each contact via is conductively connected to a contacting word line, other word lines of the same height as the contacting word line, and a conductive connection portion of the same height as the contacting word line.

[0014] In some embodiments, the stack structure further includes an insulating portion between adjacent gate structures, and the connection structure further includes an insulating portion between adjacent conductive connection portions. In some embodiments, the act of forming the stack structure and the insulating portion includes forming a composite structure over portions of the substrate in the device region and the connection region. The composite structure includes a plurality of alternating insulating portions and a plurality of sacrificial layers. The composite structure can be patterned to remove portions of the composite structure in the device region to form vertical trenches, the vertical trenches extending through the composite structure along a direction perpendicular to the substrate. The direction in which the vertical trenches extend can be perpendicular to the boundary between the device region and the connection region. Additionally, an isolation layer (e.g., a gate line slit) can be formed in the vertical trench. After the isolation layer is formed, the sacrificial layer in the device region and the connection region can be removed, and a horizontal trench can be formed between adjacent insulating portions. A word line layer can be formed in the horizontal trench in the device region and the connection region. A portion of the word line layer in the device region and a portion of the word line layer in the connection region adjacent to the isolation layer can form a word line. The word line layer in the connection region can be connected to form a conductive connection portion.

[0015] In some embodiments, patterning the composite structure includes forming a mask layer over the composite structure, the mask layer covering a portion of the composite structure in the connection region and a portion of the composite structure in the device region, the mask layer can be used as an etch mask for etching the composite structure.

[0016] In some embodiments, etching the composite structure includes dry etching and / or wet etching.

[0017] In some embodiments, the method further includes forming a gate dielectric layer on bottoms and sidewalls of portions of the horizontal trenches in the device region and the connection region prior to forming the wordlines.

[0018] In some embodiments, the substrate further includes a channel region adjacent to one or more of the connection region and the device region. The stack structure extends to a portion of the substrate in the channel region. In some embodiments, prior to removing the sacrificial layer in the device region and the connection region, the method further includes forming a plurality of semiconductor channels on a portion of the substrate in the channel structure, the semiconductor channels penetrating the stack structure.

[0019] In some embodiments, the insulating portion comprises silicon oxide, the sacrificial layer comprises polysilicon, polygermanium, and / or silicon nitride, and the wordline layer comprises tungsten, aluminum, and / or copper.

[0020] In some embodiments, removing the sacrificial layer in the device and connection regions comprises an isotropic dry etch and / or a wet etch.

[0021] In some embodiments, forming the word lines includes chemical vapor deposition (CVD).

[0022] In some embodiments, the conductive connecting portions include tungsten, aluminum, and / or copper.

[0023] Compared with the prior art, the present disclosure includes the following advantages:

[0024] With the three-dimensional memory device provided by the present disclosure, the conductive connection portion can connect word lines at the same height in adjacent stack structures, and obtain electrical connection of word lines at the same height in adjacent stack structures. Thus, word lines at the same height in adjacent stack structures can share the same contact vias, so that these word lines can be connected to external circuits. Thus, the disclosed method can reduce the number of contact vias, simplify the manufacture of three-dimensional memory devices, reduce the size of memory devices, and improve the space utilization of chips.

[0025] Using the method for forming a three-dimensional memory device provided by the present disclosure, a connection structure can be formed on a portion of a substrate in a connection region. The connection structure can connect adjacent stack structures. An electrical connection of word lines at the same height in adjacent stack structures can be obtained through the stack structure, and word lines at the same height in adjacent stack structures can share the same contact vias, so that these word lines can be connected to an external circuit. Thus, the disclosed method can reduce the number of contact vias, simplify the manufacture of three-dimensional memory devices, reduce the size of memory devices, and improve the space utilization of chips.

[0026] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with common industry practice, various features have not been drawn to scale, and in fact, dimensions of various features may be arbitrarily expanded or reduced for clarity of illustration and description. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a diagram of a three-dimensional memory device. [Figure 2A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 2B] 2B is a cross-sectional view of the three-dimensional memory structure of FIG. 2A according to some embodiments. [Figure 3A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 3B] 3B is a cross-sectional view of the three-dimensional memory structure of FIG. 3A according to some embodiments. [Figure 4A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 4B] 4B is a cross-sectional view of the three-dimensional memory structure of FIG. 4A according to some embodiments. [Figure 5A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 5B] 5B is a cross-sectional view of the three-dimensional memory structure of FIG. 5A according to some embodiments. [Figure 6A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 6B] 6B is a cross-sectional view of the three-dimensional memory structure of FIG. 6A according to some embodiments. [Figure 7A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 7B] 7B is a cross-sectional view of the three-dimensional memory structure of FIG. 7A according to some embodiments. [Figure 7C] 7B is another cross-sectional view of the three-dimensional memory structure of FIG. 7A according to some embodiments. [Figure 8A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 8B] 8B is a cross-sectional view of the three-dimensional memory structure of FIG. 8A according to some embodiments. [Figure 9A] 1A-1D are top views of a three-dimensional memory structure at different stages of an exemplary manufacturing process, according to some embodiments. [Figure 9B] 9B is a cross-sectional view of the three-dimensional memory structure of FIG. 9A according to some embodiments. [Figure 10] FIG. 2 illustrates a top view of another three-dimensional memory structure, according to some embodiments. [Figure 11] 1 is a diagram of a manufacturing process for forming a three-dimensional memory structure, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to one skilled in the art that the present disclosure can also be used in a variety of other applications.

[0029] References herein to "one embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but it should be noted that all embodiments do not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, if a particular feature, structure, or characteristic is described in connection with one embodiment, it will be within the knowledge of one of ordinary skill in the art that such feature, structure, or characteristic also is provided in connection with other embodiments, whether or not expressly described.

[0030] Generally, terms may be understood, at least in part, from usage in context. For example, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," "the," etc. may be understood to convey singular usage or plural usage, also depending at least in part on the context.

[0031] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also means "on" something with an intervening feature or layer, and such that "above" or "on" not only means "on" something or "on" something, but also means "on" something or "on" something without an intervening feature or layer (i.e., directly on top of something).

[0032] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0033] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0034] As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers within the substrate, and / or can have one or more layers above, above, and / or below the substrate. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor layers and contact layers (contacts, interconnect lines, and / or vias are formed in the interconnect layer), and one or more dielectric layers.

[0035] As used herein, the term "nominal / nominal" refers to a desired or target value of a characteristic or parameter of a component or process operation, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may result from slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can refer to a value of a particular quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0036] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (such as NAND strings, referred to herein as "memory strings") on a landscape substrate such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the outer surface of the substrate.

[0037] Trends in the 3D NAND memory industry include shrinking device dimensions and simplifying manufacturing processes. In a 3D NAND memory device, memory cells for storing data are embedded in a stack of word lines (control gate electrodes) and a semiconductor channel formed through the stack. Each word line is separately connected to a metal contact via, which is further connected to a metal interconnect, a bit line, and / or an external circuit (e.g., a control circuit), so that writing and erasing data to the memory cells can be controlled from the external circuit. Thus, the number of metal contact vias is often equal to the number of word lines. As the demand for storage capacity increases, a large number of memory cells formed by an increased number of word lines and semiconductor channels are formed in a NAND memory device. Thus, more metal contact vias need to be formed to connect to the word lines. Meanwhile, the size of NAND memory devices continues to decrease. Thus, it is more difficult to form an increased number of metal contact vias (i.e., metal interconnects) in a reduced device space. For example, to place an increased number of metal contact vias in smaller NAND memory devices, the fabrication of word lines and metal contact vias must be adapted to the reduced dimensions of these components so that a desired number of word lines and metal contact vias can be formed in the smaller NAND memory devices. As a result, the fabrication of smaller NAND memory devices becomes more difficult and the space in the smaller NAND memory devices is not efficiently utilized.

[0038] In this disclosure, for ease of explanation, a "level" is used to refer to elements that are at substantially the same height along a vertical direction. For example, a word line and a gate dielectric layer below the word line may be referred to as a "level", a sacrificial layer and an insulating layer below the sacrificial layer may both be referred to as a "level", a word line and an insulating layer below the word line may both be referred to as a "level", word lines at substantially the same height may be referred to as a "level of word lines", etc.

[0039] 1 shows a block 100 of a three-dimensional NAND flash memory device. The flash memory device includes a substrate 101, an insulating layer 103 on the substrate 101, a level of lower select gate electrodes 104 on the insulating layer 103, and multiple levels of control gate electrodes 107 stacked on top of the bottom select gate electrodes 104. The flash memory device also includes a level of upper select gate electrodes 109 on top of the stack of control gate electrodes 107, doped source line regions 120 in portions of the substrate 101 between adjacent lower select gate electrodes 104, and a semiconductor channel 114 through the upper select gate electrodes 109, the control gate electrodes 107, the lower select gate electrodes 104, and the insulating layer 103. The semiconductor channel 114 includes a memory film 113 on an inner surface of the semiconductor channel 114, and a core fill film 115 surrounded by the memory film 113 within the semiconductor channel 114. The flash memory device further includes a plurality of bit lines 111 connected to a semiconductor channel 114 over the upper select gate electrodes 109, and a plurality of metal interconnects 119 connected to the gate electrodes through a plurality of metal contacts 117. Insulating layers between adjacent levels of gate electrodes are not shown in Figure 1. The gate electrodes include an upper select gate electrode 109, a control gate electrode 107 (e.g., also referred to as a word line), and a lower select gate electrode 104.

[0040] In FIG. 1, for illustrative purposes, three levels of control gate electrodes 107-1, 107-2, and 107-3 are shown, along with one level of upper select gate electrodes 109 and one level of lower select gate electrodes 104. Each level of gate electrodes has substantially the same height above the substrate 101. The gate electrodes of each level are separated by gate line slits 108-1 and 108-2 through the stack of gate electrodes. Each gate electrode of the same level is conductively connected to a metal interconnect 119 through a metal contact via 117. That is, the number of metal contacts formed on the gate electrodes is equal to the number of gate electrodes (i.e., the sum of all upper select gate electrodes 109, control gate electrodes 107, and lower select gate electrodes 104). Furthermore, the same number of metal interconnects are formed to connect to each metal contact via. As the dimensions of flash memory devices decrease, it becomes more difficult to form metal contact vias and metal interconnects that can fit into the reduced space of the devices.

[0041] The present disclosure describes a three-dimensional NAND memory device in which one or more word lines of the same level in a block are conductively connected together, and the connected word lines are conductively connected to a shared metal contact via to reduce the number of metal contact vias and metal interconnects. The disclosed method and structure simplify the manufacturing process for forming a three-dimensional NAND memory device. Among other things, the advantage of conductively connecting word lines of the same level is that the number of metal interconnects connecting to control signals is significantly reduced. In other words, within the same level, connected word lines can share the same metal interconnect. Thus, the formed three-dimensional NAND memory device can reduce the number of metal contact vias and metal interconnects, and the total number of metal contact vias is less than the total number of word lines. Thus, the manufacturing of the three-dimensional NAND memory device can be simplified, the dimensions of the memory device can be further reduced, and the space in the memory device can be more efficiently utilized.

[0042] For purposes of illustration, similar or identical parts of the 3D NAND device are labeled using the same reference numbers. However, the reference numbers are used only to distinguish relevant parts of the embodiment of the invention, and do not indicate any similarity or difference in function, configuration, or location. Each of the structures 200-1000 shown in Figures 2-10 is a portion of a 3D NAND memory device. Other parts of the memory device are not shown for ease of illustration. Although a 3D NAND device is used as an example, in various applications and designs, the disclosed structures can also be applied to similar or different semiconductor devices, for example, to reduce the number of metal connections or wiring. The specific application of the disclosed structures should not be limited by the embodiments of the present disclosure. For illustrative purposes, word lines and gate electrodes are used interchangeably to describe the present disclosure.

[0043] 2A and 2B show an example structure 200 for forming a three-dimensional memory structure, according to some embodiments. FIG. 2A is a top view 201 of the structure 200, and FIG. 2B is a cross-sectional view 202 of the structure 200 along the 2-2′ direction. In some embodiments, the structure 200 includes a base substrate 210 and a material layer 240 on the base substrate 210. The base substrate 210 can provide a platform for forming subsequent structures. The material layer 240 can include an alternating stack (e.g., a pair / stack of dielectric layers) having alternating first materials / elements 211′ and second materials / elements 212′. The material layer 240 can be used to form subsequent wordlines on the base substrate 210. For purposes of illustration, three layers / pairs of first material 211′ / second material 212′ are shown to illustrate the present disclosure. In various applications and designs, material layer 240 can include any suitable number of layers / pairs of first material / second material stacked together, depending on the design of the three-dimensional memory device. For example, material layer 240 can include 64 layers / pairs of first material / second material stacked together that subsequently form 64 levels of wordlines in a three-dimensional memory device.

[0044] In some embodiments, the base substrate 210 may include any suitable material for forming a three-dimensional memory device. For example, the base substrate 210 may include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, gallium nitride, gallium arsenide, and / or other suitable III-V compounds.

[0045] In some embodiments, material layer 240 includes an alternating stack of sacrificial material layers 211' (i.e., a first element or material) and insulating material layers 212' (i.e., a second element or material) arranged vertically (along the z-axis) above base substrate 210. For illustrative purposes, sacrificial material layers 211' and insulating material layers 212' below the corresponding sacrificial layers are referred to as a material pair or a material pair of the same tier. Sacrificial material layers 211' may each have the same thickness or different thicknesses. Insulating material layers 212' may each have the same thickness or different thicknesses. In some embodiments, material layer 240 includes more sacrificial material layers and / or more insulating material layers than a material pair. The additional one or more sacrificial material layers may each have the same or different thickness as sacrificial material layer 211' of the material pair, and the additional one or more insulating material layers may each have the same or different thickness as insulating material layer 212' of the material pair. In some embodiments, the sacrificial material layer 211' is subsequently removed to deposit a gate material to form the word lines. In some embodiments, the sacrificial material layer 211' comprises any suitable material different from the insulating material layer 212'. For example, in various embodiments, the sacrificial material layer 211' can comprise polycrystalline silicon, silicon nitride, polycrystalline germanium, and / or polycrystalline germanium silicon. In some embodiments, the sacrificial material layer 211' comprises silicon nitride. The insulating material layer 212' can comprise any suitable insulating material, such as, for example, silicon oxide. The material layer 240 can be formed by alternately depositing an insulating material layer 212' and a sacrificial material layer 211' on the base substrate 210. For example, the insulating material layer 212' can be deposited on the base substrate 210, the sacrificial material layer 211' can be deposited on the insulating material layer 212', and so on. Deposition of the sacrificial material layer 211' and the insulating material layer 212' may include any suitable deposition method, such as CVD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), and / or atomic layer deposition (ALD).In some embodiments, the sacrificial material layer 211' and the insulating material layer 212' are each formed by CVD.

[0046] For illustrative purposes, the structure 200 (e.g., base substrate 210) is divided into three regions, namely regions A, B, and C. In the subsequent fabrication of the three-dimensional memory structure, word lines (gate electrodes) are formed along a horizontal direction (e.g., y-axis) substantially parallel to the top surface of the base substrate 210 through regions A (e.g., device region), B (e.g., connection region), and C (e.g., array region), semiconductor channels (e.g., also known as memory strings) are formed substantially in region C, and connection portions conductively connecting the word lines are formed substantially in region B. It should be noted that regions A, B, and C are presented merely for ease of explanation and are not intended to indicate a physical division of the structure 200 or dimensions of the structure 200.

[0047] 3A and 3B show an example structure 300 for forming a three-dimensional memory device according to some embodiments. FIG. 3A is a top view 301 of the structure 300, and FIG. 3B is a cross-sectional view 302 of the structure 300 along the 3-3′ direction. The structure shown by FIG. 3A and 3B may be referred to as a “staircase structure” or a “stepped cavity structure”. The terms “staircase structure”, “stepped cavity structure”, and the like refer to a structure having a stepped surface. In this disclosure, a “stepped surface” refers to a set of surfaces including at least two horizontal planes (e.g., along the xy plane) and at least two (e.g., first and second) vertical planes (e.g., along the z axis), such that each horizontal plane is adjacent to a first vertical plane extending upward from a first side of the horizontal plane and adjacent to a second vertical plane extending downward from a second side of the horizontal plane. A “step” or “staircase” refers to a vertical shift in height of a set of adjacent surfaces.

[0048] The staircase structure can have various stepped surfaces, such that the horizontal cross-sectional shape of the staircase structure varies in steps as a function of vertical distance from the top surface of the structure 300, with reference to FIGS. 3A and 3B. In some embodiments, the structure 300 is formed from the structure 200 by repeatedly etching the sacrificial material layer 211' and the insulating material layer 212' of the material layer 240, for example along the vertical direction (i.e., z-axis) using a mask. For illustrative purposes, the structure formed by etching the material layer 240, which is on the base substrate 210, is referred to as a stack 240'. Thus, as shown in FIGS. 3A and 3B, the structure 300 can have multiple sacrificial layers (e.g., 211-1 to 211-4) and multiple insulating layers (e.g., 212-1 to 212-4). Each sacrificial layer 211 can be paired or tiered with an adjacent underlying insulating layer having substantially the same length / shape along the y-axis. For example, sacrificial layer 211-1 and insulating layer 212-1 form a first level, sacrificial layer 211-2 and insulating layer 212-2 form a second level, and so on. Etching of the sacrificial and insulating layers of each pair can be performed with one etching process or different etching processes. After formation of the stepped surface, the mask can be removed, for example, by ashing. In some embodiments, multiple photoresist layers and / or multiple etching processes are used to form the stepped surface. As shown in FIG. 3A, in structure 300, the sacrificial layers of each level (i.e., 211-1 to 211-4) are exposed along the z-axis. In various embodiments, within each pair / level, insulating layer 212 can also be above sacrificial layer 211. In this case, an additional insulating layer can be disposed between material layer 240 and base substrate 210. The manufacturing process for forming the word lines can be similar to the manufacturing process provided in the present disclosure. Metal contact vias can then be formed that conductively connect to the word lines by penetrating the insulating layers of each level and forming contacts with the underlying word lines. Details of the manufacturing process can be found in the present disclosure and will not be repeated here.

[0049] 4A and 4B show an exemplary structure 400 for forming a three-dimensional memory device according to some embodiments. FIG. 4A is a top view 401 of the structure 400, and FIG. 4B is a cross-sectional view 402 of the structure 400 along the 4-4′ direction. In some embodiments, the structure 400 includes a plurality of semiconductor channels 220 formed in region C. The semiconductor channels 220 can be distributed as an array along the x-axis, with each array separated by a suitable distance, for example, Δx. Δx can be any suitable distance depending on the design / layout of the three-dimensional memory device. Each array of semiconductor channels 220 can have the same or different numbers of semiconductor channels 220. For illustrative purposes, referring to FIG. 4A, in the present disclosure, each array includes four semiconductor channels 220, forming a 2×2 array arrangement. The semiconductor channels 220 can be formed through stacks 240 substantially along the z-axis into the base substrate 210 for subsequent formation of sources and / or drains of the three-dimensional memory device. Semiconductor channel 220 and subsequently formed word lines may form, for example, memory cells of a three dimensional memory device for storing data.

[0050] Each semiconductor channel 220 may have substantially the shape of a pillar along the z-axis and may include multiple layers surrounding each other (not shown in the figures of this disclosure). For example, the semiconductor channel 220 may include a dielectric core positioned substantially at the center of the semiconductor channel 220 along the z-axis. The dielectric core may be surrounded by a semiconductor channel film. The semiconductor channel film may be surrounded by a memory film. The dielectric core, the semiconductor channel film, and the memory film may each include one or more layers and together may fill the channel hole to form the semiconductor channel 220. In some embodiments, the channel hole may be formed by patterning the stack 240' with a mask, e.g., etching the portion of the stack 240' exposed by the patterned mask using a suitable etching process, such as dry etching and / or wet etching. The channel hole may extend through the stack 240 and substantially into the base substrate 210. The mask may be removed after the channel hole is formed.

[0051] For example, the memory film may be formed on and contact the sidewalls of the channel hole. In some embodiments, the memory film may include one or more block dielectric layers on the sidewalls of the channel hole to insulate other layers in the channel hole from the stack 240' surrounding the channel hole. The memory film may also include a storage unit layer (memory layer) on the block dielectric layer and surrounded by the block dielectric to trap charges and form multiple charge storage regions along the z-axis. The memory film may also include a tunnel layer (e.g., tunnel dielectric) on the memory layer and surrounded by the memory layer. Charge tunneling may be performed through the tunneling layer under a suitable electrical bias. In some embodiments, charge tunneling may be performed through hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the operation of the three-dimensional memory device.

[0052] The one or more blocking dielectric layers can include a first blocking layer including a dielectric metal oxide layer having a relatively high dielectric constant. The term "metal oxide" can include metallic elements as well as non-metallic elements such as oxygen, nitrogen, and other suitable elements. For example, the dielectric metal oxide layer can include aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, silicates, nitrogen-doped compounds, alloys, and the like. The first blocking layer can be deposited, for example, by CVD, ALD, pulsed laser deposition (PLD), liquid mist chemical deposition, and / or other suitable deposition methods.

[0053] The one or more block dielectric layers may also include a second block layer that includes another dielectric layer on top of the dielectric metal oxide. The other dielectric layer may be different from the dielectric metal oxide layer. The other dielectric layer may include silicon oxide, a dielectric metal oxide having a different composition than the first block layer, silicon oxynitride, silicon nitride, and / or other suitable dielectric materials. The second block layer may be deposited, for example, by low pressure chemical vapor deposition (LPCVD), ALD, CVD, and / or other suitable deposition methods. In some embodiments, the one or more block dielectric layers include silicon oxide formed by CVD.

[0054] The storage unit layer may be successively formed on one or more block dielectric layers. The storage unit layer may include a charge trapping material, such as a dielectric charge trapping material (e.g., silicon nitride) and / or a conductive material (e.g., doped polysilicon). In some embodiments, the dielectric charge trapping material includes silicon nitride and may be formed by CVD, ALD, PVD, and / or other suitable deposition methods.

[0055] The tunnel layer can be formed continuously over the memory layer. The tunnel layer can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide, dielectric metal oxynitride, dielectric metal silicate, alloy, and / or other suitable materials. The tunnel layer can be formed by CVD, ALD, PVD, and / or other suitable deposition methods. In some embodiments, the tunnel layer includes silicon oxide formed by CVD.

[0056] The semiconducting channel film can be formed continuously on the tunnel layer. The semiconducting channel film can include one or more layers of any suitable semiconductor material, such as silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and / or other suitable semiconductor materials. The semiconducting channel film can be formed by a suitable deposition method, such as metalorganic chemical vapor deposition (MOCVD), LPCVD, CVD, and / or other suitable deposition methods. In some embodiments, the semiconducting channel film is formed by depositing a layer of amorphous silicon using CVD, followed by an annealing process such that the amorphous silicon is converted to single crystal silicon. In some embodiments, other amorphous materials can be annealed and crystallized to form the semiconducting channel film.

[0057] A dielectric core can be formed on top of the semiconducting channel film, filling the space in the center of the channel hole. The dielectric core can comprise a suitable dielectric material, such as silicon oxide and / or organosilicate glass. The dielectric core can be formed by a suitable conformal deposition method (e.g., LPCVD) and / or self-planarizing deposition method (e.g., spin coating). In some embodiments, the dielectric core comprises silicon oxide and is formed by LPCVD.

[0058] In various embodiments, the number of layers, the methods of forming these layers, and the particular order of forming these layers may vary according to different designs and should not be limited by the embodiments of the present disclosure.

[0059] 5A and 5B show a structure 500 for forming a three-dimensional memory device according to some embodiments. FIG. 5A is a top view 501 of the structure 500, and FIG. 5B is a cross-sectional view 502 of the structure 500 along the 5-5′ direction. The structure 500 includes a plurality of insulating or vertical trenches, each formed between two arrays of semiconductor channels 220 substantially along the y-axis to divide the stack 240′ into a plurality of fingers, each finger extending substantially along the y-axis. In this disclosure, the term “vertical” refers to “along the z-axis” or “substantially perpendicular to the x-y plane”. Subsequently, a word line can be formed in each finger. The vertical trenches can include one or more openings along the y-axis. The openings vertically form aligned sub-openings in different levels to allow adjacent fingers of the same level to be connected through the sub-openings in the levels by material connecting portions (i.e., the openings are filled with portions of the material layer 240). The sub-openings formed from the same opening can be aligned with each other along the x-axis, y-axis, and z-axis (i.e., have the same projected area on the top surface of the base substrate 210). The vertical trenches can be subsequently filled with a suitable insulating material to form gate line slits, also referred to as insulating spacers. That is, the word lines subsequently formed in adjacent fingers are insulated at the locations filled with the insulating material and connected at the locations of the openings. In other words, two adjacent word lines of the same layer can be conductively connected through the connection parts (connection parts that are not filled with the insulating material and are filled with the gate metal material) formed by one or more openings.

[0060] For illustrative purposes, two adjacent vertical trenches 221' and 222' are shown in Figures 5A and 5B. As shown in Figure 5A, the vertical trench 221' includes an opening 223' formed through the stack 240', and the vertical trench 222' includes an opening 224' formed through the stack 240'. The openings 223' and 224' can be formed in region B and can divide the vertical trench 221' into a first portion 221'-1 and a second portion 221'-2, and the vertical trench 222' into a first portion 222'-1 and a second portion 222'-2 along the y-axis. The two adjacent vertical trenches 221' and 222' divide the structure 500 into fingers 1, 2, and 3, each of which includes an array of semiconductor channels 220. First portions 221'-1 and 222'-1 of the vertical trenches are formed in region C to divide the array of semiconductor channels 220 into different fingers along the x-axis, and second portions 221'-2 and 222'-2 are formed in region A to divide the subsequently formed word lines into different fingers. The array of semiconductor channels 220, together with the subsequently formed word lines in fingers 1, 2, and 3, can form memory cells, respectively. The sacrificial layer / insulating layer pairs of each level of the structure 500 are connected through openings. For example, FIG. 5B shows a cross-sectional view of the structure 500 between fingers 2 and 3. For fingers 2 and 3, the sacrificial layer 211-1 / insulating layer 212-1 pairs are connected through openings 224'. Similarly, the sacrificial / insulating layers of other levels (211-2 / 212-2, 211-3 / 212-3, and 211-4 / 212-4) in fingers 2 and 3 are connected through sub-openings of openings 223′ and 224′ in different levels. The sacrificial / insulating layers in fingers 1 and 2 are connected in a similar configuration. In other words, the fingers of stack 240′ are connected through region B and separated in regions A and C by vertical trenches 221′ and 222′. Thus, in a subsequent manufacturing step, word lines can be formed in each finger. Adjacent word lines of the same level can be conductively connected through region B.Also, adjacent insulating layers at the same level can be connected through openings 223' and 224' (in region B). In some embodiments, fingers 1, 2, and 3 are collectively referred to as a block, and word lines at the same level within a block are connected through region B.

[0061] The vertical trenches (e.g., 221' and 222') can be formed by forming a mask layer over the stack 240' and patterning the mask, e.g., using photolithography, to form openings in the patterned mask layer that correspond to the vertical trenches. An appropriate etching process, e.g., dry etching and / or wet etching, can be performed to remove the portions of the stack 240' exposed by the openings until the vertical trenches expose the base substrate 210. The mask layer can be removed after the vertical trenches are formed. In some embodiments, the vertical trenches pass through each tier in the stack 240' and divide the stack 240' into multiple fingers along the y-axis. The vertical trenches can include one or more openings as described above along the y-axis such that the sacrificial / insulating layers of adjacent fingers in each tier can connect through the opening(s) in the vertical trench between the fingers. In this disclosure, the term "vertical" refers to "substantially perpendicular to the x-y plane" or "substantially along the z-axis." In some embodiments, the vertical trenches are substantially perpendicular to the top surface of the base substrate 210.

[0062] In some embodiments, the vertical trench can have more than one opening to allow adjacent sacrificial / insulating layers of levels in the stack 240' to be connected in more than one location. For example, region B can include multiple sub-regions along the y-axis separated by portions of the vertical trench. That is, the subsequently formed word lines of adjacent fingers of each level can be conductively connected in more than one location. In some embodiments, the vertical trench can have more than one opening to allow sacrificial / insulating layers of some levels in the stack 240' to be connected in more than one location. For example, the vertical trench can have one or more openings distributed in region A along the y-axis. That is, the subsequently formed word lines of adjacent fingers of some levels can be conductively connected in more than one location. Details are described below.

[0063] 6A and 6B show a structure 600 for forming a three-dimensional memory device according to some embodiments. FIG. 6A is a top view 601 of the structure 600, and FIG. 6B is a cross-sectional view 602 of the structure 600 along the 6-6' direction. The structure 600 includes multiple insulating layers in a stack 240'. In some embodiments, the structure 600 is formed from the structure 500 by removing a sacrificial layer. The insulating layers of each level can be connected at a location(s) that are not separated by a vertical trench. Thus, horizontal trenches can be formed between the insulating layers of adjacent levels, i.e., at the locations / spaces where the sacrificial layers have been removed. The horizontal trenches can be divided by vertical trenches along the z-axis. In this disclosure, the term "horizontal" refers to "substantially along the x-y plane" or "substantially perpendicular to the z-axis." Similarly, the horizontal trenches of each level can be connected at a location(s) that are not separated by a vertical trench. The top surface of the insulating layer of each level and the outer sidewall portions of the semiconductor channel 220 that were previously surrounded by the sacrificial layer may be exposed.

[0064] For example, as shown in FIGS. 6A and 6B, the structure 600 includes vertical trenches 221′ and 222′ that separate fingers 1, 2, and 3 from each other at locations filled with insulating material (e.g., in regions A and C). The insulating layers 212 of each level are connected at locations not separated by the vertical trenches 221′ and 222′ (e.g., at the locations of openings 223′ and 224′). After the sacrificial layers 211 of each level are removed, horizontal trenches (e.g., 230-1, 230-2, 230-3, and 230-4) are formed. Thus, the top surfaces of the insulating layers (e.g., 212-1, 212-2, 212-3, and 212-4) of each level and the outer sidewall portions of the semiconductor channel 220 that were previously surrounded by the sacrificial layers 211 are exposed. The horizontal trenches 230 and insulating layers 212 of each level are connected in region B, respectively. In some embodiments, other support structures (e.g., dummy / auxiliary channels in stack 240') may be formed to support stack 240' during removal of sacrificial layer 211. Details of the support structures are not described herein.

[0065] The sacrificial layer 211 can be removed by a suitable etching process, for example, an isotropic dry etch or a wet etch. The etch process can have a sufficiently high etch selectivity of the material of the sacrificial layer 211 relative to the material of the other portions of the substrate 200 such that the etch process can have minimal impact on the other portions of the substrate 200. The isotropic dry etch and / or wet etch can remove the sacrificial layer 211 in various directions to expose the top and bottom surfaces of each insulating layer 212 and the outer sidewall portion of the semiconductor channel 220 that was previously surrounded by the sacrificial layer 211. Horizontal trenches 230 can then be formed in each tier. In some embodiments, the sacrificial layer 211 includes silicon nitride and the etchant for the isotropic dry etch includes one or more of CF4, CHF3, C4F8, C4F6, and CH2F2. The radio frequency (RF) power for the isotropic dry etch can be less than about 100 W and the bias can be less than about 10 V. In some embodiments, the sacrificial layer 211 includes silicon nitride and the etchant for the wet etch includes phosphoric acid.

[0066] 7A, 7B, and 7C show a structure 700 for forming a three-dimensional memory device according to some embodiments. FIG. 7A is a top view 701 of the structure 700, FIG. 7B is a cross-sectional view 702 of the structure 700 along the 7-7' direction, and FIG. 7C is a cross-sectional view 703 of the structure 700 along the 7''-7'''' direction. In the structure 700, the stack 240' includes alternating gate material layers 231' and insulating layers 212. For example, each level of the structure 700 includes a gate material layer 231' on a respective insulating layer 212. In some embodiments, the structure 700 can be formed from the structure 600 shown in FIGS. 6A and 6B by filling the horizontal trenches 230 with a suitable gate material (e.g., a conductor and / or a metal). The gate material can fill each horizontal trench along the xy plane and cover each insulating layer 212. The gate material layer 231' can provide a base material for the subsequently formed word lines (i.e., gate electrodes). After the horizontal trenches 230 are filled with gate material, a connection portion made of gate material can be formed in the opening(s) of the vertical trench in each level of the stack 240'. The connection portion refers to the portion of the gate material layer 231' deposited on the respective insulating layer 212 in the opening formed by the vertical trench. The connection portion can be formed vertically from aligned sub-openings in different levels. The sub-connection portions formed from one opening can be aligned with each other along the x-axis, y-axis, and z-axis (i.e., have the same projected area on the top surface of the base substrate 210). The connection portion can conductively connect different portions of the respective gate material layer 231' that are in the same level and connected to the connection portion (i.e., gate material deposited in fingers adjacent / connected to the connection portion or gate material deposited in adjacent fingers). For ease of explanation, the portion of the insulating layer 212 under the word line (i.e., within the fingers) is referred to as the first insulating portion 2121, and the portion of the insulating layer 212 under the connection portion (i.e., between the fingers) is referred to as the second insulating portion 2122.

[0067] For example, as shown in FIG. 7A, a gate material can be deposited in the horizontal trenches (230-1, 230-2, 230-3, and 230-4) of each level of the stack 240' to form a pair / stack of conductor / dielectric layers. The gate material (e.g., a conductor) can fill each horizontal trench 230 to form a gate material layer (231'-1, 231'-2, 231'-3, and 231'-4) of each level of the stack 240'. At least a portion of each gate material layer 231' is exposed along the x-y plane. The connecting portions 223 and 224 can be formed by portions of the gate material deposited in the openings 223' and 224'. Thus, the sub-connecting portions of the connecting portions 223 and 224 of each level can be formed by portions of the gate material deposited in the openings 223' and 224' of each level. As shown in FIG. 7B, the gate material is formed on the respective first insulating portions (2121-1, 2121-2, 2121-3, and 2121-4) in finger 2, and each first insulating portion 2121 electrically insulates adjacent gate materials on both sides of the first insulating portion 2121 along the z-axis. As shown in FIG. 7C, at the position of the opening 224', a connection portion is formed including sub-connection portions 224-1, 224-2, 224-3, and 224-4 in different layers aligned along the z-axis (in region B). Each sub-connection portion 224 is formed on a respective second insulating portion 2122, and each second insulating portion 2122 electrically insulates adjacent sub-connection portions 224 from each other along the z-axis. The sub-connection portions 224 of each layer conductively connect the respective gate materials of fingers 1 and 2. For example, sub-connection portion 224-1 conductively connects gate material deposited in fingers 1 and 2 of the first level (e.g., a subsequently formed word line). Similarly, sub-connection portions 224-2 to 224-4 conductively connect gate material deposited in fingers 1 and 2 of the second to fourth levels, respectively. Gate material layer 231′ of each level surrounds a respective outer sidewall portion of semiconductor channel 220.

[0068] The gate material may include any suitable conductive material, such as, for example, tungsten, aluminum, and / or copper, to form the wordlines (i.e., gate electrodes or conductor layers). The gate material may be deposited in the horizontal trenches 230 using a suitable deposition method, such as CVD, sputtering, MOCVD, and / or ALD. In some embodiments, the gate material includes tungsten, which is formed by CVD.

[0069] In some embodiments, a gate dielectric material layer (not shown in the figures of this disclosure) can be formed in the horizontal trench prior to deposition of the gate metal material. The gate dielectric material layer can be formed on the horizontal trench, the outer sidewall portion of the semiconductor channel 220 between the opposing surfaces, and the opposing surfaces of the adjacent insulating layers that form the respective vertical trenches. The gate dielectric material layer provides a base material for the subsequently formed gate dielectric layers. The gate dielectric layer can insulate the respective word lines from the underlying insulating layer 212. The gate dielectric material layer can include any suitable dielectric material that is electrically insulating. For example, the gate dielectric material layer can include one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the gate dielectric material layer can include a high-k dielectric material (k less than 3.9). In some embodiments, the gate dielectric material layer can include a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer. Formation of the gate dielectric material layer may include one or more of CVD, PECVD, PVD, and / or ALD.

[0070] The connection portion (e.g., 223 or 224) can conductively connect the gate material deposited on the finger adjacent / connected to the connection portion. In some embodiments, the vertical trench includes two or more openings in a tier, so that after deposition of the gate metal material, two or more connection portions are formed from the openings. In some embodiments, each tier includes two or more sub-connection portions. Two or more sub-connection portions in one tier can strengthen / improve the conductive connection between the gate material deposited on the finger adjacent / connected to the two or more sub-connection portions, so that the electrical connection between these fingers can be ensured. Thus, the word lines subsequently formed in the connected fingers can share the same metal contact vias, which are further connected to the respective metal interconnects for transmitting electrical signals from an external circuit. Thus, the number of metal contact vias can be reduced, simplifying the fabrication of the three-dimensional memory device.

[0071] 8A and 8B show a structure 800 for forming a three-dimensional memory device according to some embodiments. FIG. 8A is a top view 801 of the structure 800, and FIG. 8B is a cross-sectional view 802 of the structure 800 along the 8-8′ direction. The structure 800 includes a plurality of gate line slits substantially aligned along the y-axis. The gate line slits can be formed by filling the vertical trenches described in FIGS. 5A-7C with a suitable insulating material. The formed gate line slits electrically insulate and separate adjacent fingers and subsequently formed word lines in different levels at the locations filled with the insulating material. The gate line slits can include one or more openings along the y-axis connecting the gate material / insulating layers of adjacent fingers.

[0072] For illustrative purposes, FIG. 8A shows two gate line slits 221 and 222 formed from vertical trenches 221′ and 222′. Gate line slit 221 includes a connecting portion 223 that divides gate line slit 221 into a first portion 221-1 and a second portion 221-2, and gate line slit 222 includes a connecting portion 224 that divides gate line slit 222 into a first portion 222-1 and a second portion 222-2. Gate line slits 221 and 222 divide stack 240′ into fingers 1, 2, and 3. Each of gate line slits 221 and 222 insulates adjacent gate material layers / insulating layers of each level at locations filled with insulating material (e.g., in regions A and C). Adjacent gate material layers / insulating layers of each level at locations not filled with insulating material (e.g., region B) are connected. For example, as shown in FIG. 8B , first portion 222-1 and second portion 222-2 of gate line slit 222 insulate finger 2 from finger 3 in regions A and C through stack 240', and gate material layer / insulation layer pairs of finger 2 and finger 3 at the same level (e.g., 231'-1 / 2121-1, 231'-2 / 2121-2, 231'-3 / 2121-3, and 231'-4 / 2121-4) are connected in region B.

[0073] In some embodiments, the gate line slits (e.g., 221 and 222) can be formed by filling the vertical trenches (e.g., 221′ and 222′) with a suitable insulating material. For example, a suitable deposition method such as CVD, PVD, PECVD, and / or ALD can be utilized to deposit the insulating material in the vertical trenches. The insulating material can include any suitable material that allows electrical isolation between the fingers. For example, the insulating material can include silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the insulating material includes silicon oxide. In some embodiments, after deposition, recess etching and / or chemical mechanical planarization (CMP) is used to remove excess insulating material on the stack 240′ after deposition, so that the gate material layer 231′-1 is exposed and the top surface of the gate line slits is flush with the top surface of the gate material layer 231′-1.

[0074] In some embodiments, a doping process is performed before the formation of the gate line slits, so that the base substrate 210 is doped with an opposite dopant type to the base substrate 210 at the bottom of the vertical trenches (221' and 222'). The doped region at the bottom of the vertical trenches can form the source region. An insulating material can then be deposited on the bottom and sidewalls of the vertical trenches. A source contact via can subsequently be formed in the vertical trench by filling the center of the vertical trench with source material. Thus, the insulating material can provide electrical insulation between the source contact via and the remainder of the stack 240'. In some embodiments, the annular bottom surface of the gate line slits contacts the source region, and the source contact via is electrically connected to the source region. In some embodiments, ion implantation is utilized to dope the base substrate 210 at the bottom of the vertical trenches to form the source region, and an insulating material can be deposited to cover the sidewalls of the vertical trenches, so that a cavity is formed in the vertical trench and surrounded by the insulating material. A suitable source metal can be deposited to fill the cavity and form the source contact via. The insulating material can include silicon oxide, silicon nitride, and / or silicon oxynitride. The source metal can include tungsten and / or other suitable conductive materials. In some embodiments, a barrier layer, e.g., TiN, is formed between the gate line slit and the source contact via to prevent the source metal from penetrating into the stack 240'.

[0075] 9A and 9B show a structure 900 for forming a three-dimensional memory device according to some embodiments. FIG. 9A is a top view 901 of the structure 900, and FIG. 9B is a cross-sectional view 902 of the structure 900 along the 9-9′ direction. The structure 900 includes multiple levels of word lines stacked along the z-axis, with each level including multiple word lines, each word line aligned in a different finger. To electrically isolate the word lines of two adjacent levels, an insulating layer is formed between the word lines of the adjacent levels. One or more word lines of the same level can be conductively connected through one or more connecting portions. The connected word lines can share the same metal contact via. One or more metal contact vias can be formed on each level to electrically connect the connected word lines.

[0076] In some embodiments, structure 900 may be formed from structure 800 shown in FIGS. 8A and 8B. In some embodiments, excess gate material and gate dielectric material on the sidewalls of stack 240′ (e.g., sidewalls of insulating layer 212) may be removed using a suitable etching process (e.g., dry etching and / or wet etching). The remaining portions of the gate material layer may form the word lines of each level, and the remaining portions of the gate dielectric material layer may form the gate dielectric layers of each level. In some embodiments, each word line may be formed on a respective gate dielectric layer. Additionally, metal contact vias may be formed on each level to connect the word lines of each level to external circuitry. In some embodiments, structure 900 includes a dielectric stack (not shown) on / surrounding stack 240′ to electrically isolate subsequently formed metal contact vias from each other. In some embodiments, the metal contact vias are formed by patterning the dielectric stack to form a plurality of contact openings exposing the contact regions of each level, and filling the contact openings with a suitable conductive material to form the metal contact vias. The patterning process can include forming a mask over the dielectric stack, performing a photolithography process to define contact openings in the mask, and removing material in the contact openings until the contact areas of the stack 240' are exposed. The contact areas of each level can be on one or more wordlines. Furthermore, the contact openings can be filled with a suitable conductive material, such as, for example, tungsten, aluminum, and / or copper.

[0077] As shown in FIGS. 9A and 9B, after the excess gate material and gate dielectric material are removed from the stack 240′, the remaining gate material of each level of the stack 240′ forms word lines (231-m-wln, m=1-4, n=1-4) in different fingers substantially along the y-axis. In some embodiments, each finger (e.g., fingers 1-3) includes multiple word lines 231-m-wln stacked along the z-axis, and each word line 231-m-wln is insulated from each other along the z-axis by adjacent first insulating portion(s). The gate line slits 221 and 222 provide electrical insulation between adjacent fingers in regions A and C to separate the word lines 231-m-wln of different fingers and, respectively, separate the arrays of semiconductor channels 220 of different fingers. Adjacent word lines 231-m-wln (or word lines 231-m-wln of adjacent fingers) at the same level are conductively connected by sub-connection portions at the same level (e.g., 223-1 to 223-4 and / or 224-1 to 224-4, see FIG. 7C and FIG. 9A). That is, two or more word lines 231-m-wln at the same level can be conductively connected by one or more sub-connection portions at the same level, such that the connected word lines 231-m-wln can share the same metal contact via. In some embodiments, each word line 231-m-wln is connected to other word lines 231-m-wln at the same level through a connection portion, such that the word lines 231-m-wln at the same level can share one metal contact via.

[0078] For example, structure 900 includes fingers 1, 2, and 3. Wordlines 231-1-wl1, 231-2-wl1, 231-3-wl1, and 231-4-wl1 are stacked along the z-axis in finger 1, wordlines 231-1-wl2, 231-2-wl2, 231-3-wl2, and 231-4-wl2 are stacked along the z-axis in finger 2, and wordlines 231-1-wl3, 231-2-wl3, 231-3-wl3, and 231-4-wl3 are stacked along the z-axis in finger 3. Word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3 are in the same level 1 and are conductively connected by connecting portions 223 and 224 (e.g., or sub-connecting portions of connecting portions 223 and 224). A metal contact via 232-1 is formed on word line 231-1-wl2 to connect word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3. Similarly, word lines 231-2-wl1, 231-2-wl2, and 231-2-wl3 are in the same level 2 and are conductively connected by connecting portions 223 and 224, word lines 231-3-wl1, 231-3-wl2, and 231-3-wl3 are in the same level 3 and are conductively connected by connecting portions 223 and 224, and word lines 231-4-wl1, 231-4-wl2, and 231-4-wl3 are in the same level 4 and are conductively connected by connecting portions 223 and 224. Metal contact vias 232-2, 232-3, and 232-4 are formed on levels 2 to 4, respectively, to conductively connect to the word lines of each level. In some embodiments, two adjacent word lines 231-m-wln are conductively connected by two or more connecting portions. In some embodiments, several wordlines 231-m-wln of the same level are conductively connected, and the connected wordlines share one or more metal contact vias 232. In some embodiments, two or more metal contact vias 232 are formed to connect to the connected wordlines 231-m-wln that ensure / strengthen the electrical connection between the connected wordlines 231-m-wln and the corresponding metal interconnect(s).Metal contact vias 232 may be formed at any suitable location(s) (in the xy plane) of the hierarchy depending on the design. In some embodiments, other structures, such as drain regions, may be formed in the structure 900. For ease of explanation, details of the formation of other structures are omitted in this disclosure.

[0079] By using the disclosed methods and structures shown in Figures 2-9, the number of metal contact vias in a three-dimensional memory device can be significantly reduced. In some embodiments, each word line in the same tier can be conductively connected to other word lines by two or more connecting portions, resulting in improved electrical connection during operation and making the memory device less susceptible to connection failures of these connecting portions. In some embodiments, one metal contact via is formed to connect each tier of a block of word lines, and all the word lines are conductively connected. Assuming each tier contains N word lines, only one metal contact via needs to be formed in this tier. Compared to conventional methods and structures, the number of metal contact vias is reduced by (N-1) for each tier of word lines. In some embodiments, due to manufacturing considerations, the connecting portions of different tiers are aligned along the z-axis, as shown in Figure 7C. In various embodiments, some of the connecting portions in different tiers are misaligned along the z-axis. That is, the specific location of the connecting portions in each tier can be determined individually according to different design requirements. In some embodiments, other components of the three-dimensional memory device can be adjusted to apply electrical signals to the desired word lines during operation. For example, external circuitry can be programmed or adjusted to select the desired word lines and apply electrical signals / biases to the word lines. Other suitable means can also be applied.

[0080] 10 shows a top view 1001 of another exemplary structure 1000 of a three-dimensional memory device. Unlike the structure 900, the structure 1000 includes two or more connection portions in each level to conductively connect the word lines of each level with the shared metal contact via(s). For illustrative purposes, one metal contact via is shown for each level (232-1, 232-2, 232-3, and 232-4). Each of the gate line slits 221 and 222 includes two or more openings substantially along the y-axis, so that two or more connection portions (e.g., in regions B1, B2, B3, B4, and B5) are formed substantially along the y-axis. The stack of connection parts is formed vertically (along the z-axis) at the position of the gate line slit opening, so that in FIG. 10 , the word lines of the first level (i.e., 231-1-wln (n=1 to 3)) are conductively connected by four connection parts 223, 224, 225, and 229, and the word lines of the second level (i.e., 231-2-wln (n=1 to 3)) are conductively connected by six connection parts 223, 224, 225, 229, 226, and 230. The word lines of the third hierarchy (i.e., 231-3-wln (n=1 to 3)) are conductively connected by eight connection parts 223, 224, 225, 229, 226, 230, 227, and 231, and the word lines of the fourth hierarchy (i.e., 231-4-wln (n=1 to 3)) are conductively connected by ten connection parts 223, 224, 225, 229, 226, 230, 227, 231, 228, and 232. By increasing the number of connection parts in the hierarchy of word lines, desired word lines can be more effectively connected and the possibility of connection failure between word lines can be reduced. In various embodiments, the total number of metal contact vias is less than the total number of word lines. Thus, the number of metal contact vias can be reduced, simplifying the manufacture of the three-dimensional memory device. The space in the three-dimensional memory device can be more efficiently utilized.

[0081] For ease of illustration, the connection portions formed between different fingers are substantially aligned along the x-axis. In various other embodiments, the connection portions formed between different fingers can be offset or misaligned along the x-axis. For example, in FIG. 10, connection portions 223 and 224 may or may not be aligned with each other along the x-axis. In various designs and applications, the number and location of connection portions may vary according to different design rules and should not be limited by the embodiments of the present disclosure.

[0082] 11 is a diagram of an example method 1100 for forming a three-dimensional memory device, according to some embodiments. For purposes of explanation, the operations shown in method 1100 are described in the context of Figures 2-9. In various embodiments of the present disclosure, the operations of method 1100 may be performed in different orders and / or may be varied.

[0083] In operation 1101, a substrate may be provided. Figures 2A and 2B show an exemplary substrate in this operation. The substrate may include a base substrate and a material layer on the substrate. The base substrate may include any suitable material for forming a three-dimensional structure. For example, the base substrate may include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, gallium nitride, gallium arsenide, and / or other suitable III-V compounds. In some embodiments, the material layer may include an alternating stack of sacrificial and insulating material layers disposed along a vertical direction on the base substrate. In some embodiments, the sacrificial material layer includes silicon nitride and the insulating material layer includes silicon oxide.

[0084] In operation 1102, a plurality of word lines extending horizontally on a base substrate and at least one connecting portion conductively connecting two or more word lines can be formed. FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A-7C, 8A, 8B, 9A, and 9B show exemplary structures in this operation. Referring to FIGS. 3A and 3B, an alternating stack having a staircase structure can be formed from the substrate provided in operation 1101. A plurality of alternating sacrificial / insulating layer pairs can be formed in the stack. A portion of the top surface of each sacrificial layer can be exposed, and a respective insulating layer can be disposed below the sacrificial layer. Furthermore, as shown in FIGS. 4A and 4B, a plurality of semiconductor channels can be formed through the stack substantially into the base substrate. Each of the semiconductor channels can include at least a dielectric core, a semiconductor channel film, and a memory film. The semiconductor channels can be formed by sequentially depositing a memory film, a semiconductor channel film, and a dielectric core using an appropriate deposition method.

[0085] Further, referring to FIG. 5A, FIG. 5B, FIG. 6A, and FIG. 6B, vertical trenches can be formed along the horizontal direction through the stack to divide the stack into multiple fingers. The vertical trenches can subsequently form gate line slits. At least one of the vertical trenches includes one or more openings along the horizontal direction to connect sacrificial / insulating layer pairs of adjacent fingers of the same tier. The vertical trenches can be formed by patterning a mask over the stack and etching the portions of the stack exposed by the mask. Furthermore, the sacrificial layers in the stack can be removed using a suitable isotropic etching process so that horizontal trenches can be formed. The horizontal trenches can expose the remaining insulating layers and sidewall portions of the semiconductor channel.

[0086] Further, referring to FIGS. 7A-7C, a gate material can be deposited to fill the horizontal trenches, and a gate material layer can be formed on each insulating layer. The portions of the gate material layer deposited in the different fingers can form word lines in a subsequent step. The portions of the gate material layer at the openings of the vertical trenches can form connecting portions that conductively connect subsequently formed word lines adjacent the openings. In some embodiments, the gate material includes one or more of tungsten, aluminum, and copper, and can be deposited by any suitable deposition method, such as CVD, sputtering, and / or ALD. Further, referring to FIGS. 8A and 8B, a suitable dielectric material can be deposited in the vertical trenches to form the gate line slits. After the dielectric material is deposited, a recess etch and / or a CMP process can be used to planarize the top surface of the stack.

[0087] 9A and 9B, excess gate material on the sidewalls of the stack can be removed (e.g., by a suitable etching process) to form word lines along the horizontal direction in different fingers. In some embodiments, the stack can include multiple fingers aligned horizontally, with each finger including multiple word lines stacked vertically. One or more of the multiple word lines can be conductively connected to other word lines of the same tier through one or more connecting portions. In some embodiments, the word lines of each tier are conductively connected through one or more conductive portions.

[0088] In operation 1103, metal contact vias may be formed on the word lines. Figures 9A and 9B show an example structure for this operation. One or more metal contact vias may be formed on the connected word lines to conductively connect the connected word lines with external circuitry. In some embodiments, word lines of the same level are conductively connected and one metal contact via is formed on one of the word lines.

[0089] In various embodiments, the total number of metal contact vias formed is less than the total number of word lines. Thus, the number of metal contact vias can be reduced, simplifying the manufacture of the three-dimensional memory device. The volume of the three-dimensional memory device can be further reduced, and the space within the three-dimensional memory device can be more efficiently utilized.

[0090] The present disclosure describes various embodiments of three-dimensional NAND memory devices and methods of manufacture. In some embodiments, the three-dimensional memory device includes a substrate and a first tier of conductor layers of a first length including a first plurality of conductor layers extending along a first direction on the substrate. The first direction is substantially parallel to a top surface of the substrate. The memory device also includes at least one connecting portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by the connected conductor layers of the first tier and connected to a first metal interconnect.

[0091] In some embodiments, a method for forming a three-dimensional memory device includes providing a substrate; forming an alternating stack on the substrate, the alternating stack including multiple hierarchies of sacrificial / insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming multiple hierarchies of conductor layers extending along the first direction based on the alternating stack; forming at least one connecting portion conductively connecting two or more conductor layers of the multiple hierarchies of conductor layers; and forming at least one metal contact via conductively shared by the connected conductor layers, the at least one metal contact via being connected to at least one metal interconnect.

[0092] In some embodiments, the three-dimensional memory device includes a substrate, a plurality of semiconductor channels, one end of each of the plurality of semiconductor channels extending in a direction substantially perpendicular to the top surface of the substrate, a drain region above an end of each of the plurality of semiconductor channels, a plurality of charge storage regions, each charge storage region being surrounded by a respective one of the plurality of semiconductor channels, and a source region in the substrate. The three-dimensional memory device also includes a plurality of bit lines, each above a respective end of each of the plurality of semiconductor channels, a plurality of word lines extending along a direction substantially parallel to the top surface of the substrate and including an upper select gate, a lower select gate, and a plurality of word lines between the upper word lines and the lower select gate, a plurality of metal contact vias connecting the plurality of word lines through a plurality of metal contact vias, and a driver circuit above the plurality of bit lines. Two or more of the plurality of word lines at substantially the same height above the substrate are conductively connected through at least one connection portion at substantially the same height. Two or more of the plurality of wordlines share a metal contact via that electrically connects to a respective metal interconnect, the metal contact via being formed on one of the two or more of the plurality of wordlines.

[0093] The foregoing description of specific embodiments fully reveals the general nature of the present disclosure, so that those skilled in the art can easily modify such specific embodiments and / or adapt them to various applications without undue experimentation by applying knowledge within the skill of the art, without departing from the general concept of the present disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It should be understood that the phraseology or terminology used herein is for purposes of explanation and not limitation, and as a result, the phraseology or terminology used herein should be interpreted by those skilled in the art in light of the teaching and guidance.

[0094] The embodiments of the present disclosure have been described above using functional components that indicate the implementation of specific functions and the relationships of the implementation of specific functions. The boundaries of these functional components are arbitrarily defined in this specification for the convenience of description. Alternative boundaries may be defined as long as the specified functions and the specified relationships of the functions are appropriately performed.

[0095] The Summary and Abstract sections may describe one or more example embodiments of the present disclosure, but not all, contemplated by the inventor(s) and are therefore not intended to be in any way limiting of the scope of the disclosure and the appended claims.

[0096] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A substrate; a stack structure formed on the substrate; and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate and dividing the stack structure into at least two portions; The stack structure includes: a plurality of alternating gate material layers and a plurality of insulating layers extending along the first direction, the plurality of alternating gate material layers and a plurality of insulating layers including a plurality of tiers of pairs of the gate material layers and the insulating layers; a plurality of two or more connection parts that divide the at least one gate line slit and each of the connection parts conductively connects the gate material layer of the same level included in each of the at least two parts; the plurality of hierarchical levels includes a first hierarchical level and a second hierarchical level that is a level above the first hierarchical level, a number of the two or more connection portions that conductively connect the gate material layer of the first level included in each of the at least two portions is greater than a number of the two or more connection portions that conductively connect the gate material layer of the second level included in each of the at least two portions; the two or more connection portions that conductively connect the gate material layers of the first level included in each of the at least two portions include connection portions that have a length in the first direction that is shorter than a length in the first direction of the two or more connection portions that conductively connect the gate material layers of the second level included in each of the at least two portions; Memory device.

2. The two or more connection portions are aligned along the first direction. The memory device of claim 1 .

3. Further comprising a plurality of metal contact vias; a respective one of the plurality of metal contact vias formed on each of the plurality of gate material layers; 3. A memory device according to claim 1 or 2.

4. the plurality of two or more connecting portions and the plurality of gate material layers are made of the same material; A memory device according to any one of claims 1 to 3.

5. a source region in the substrate; a source contact via formed in the at least one gate line slit and electrically connected to the source region; the at least two portions and the source contact via are electrically insulated; A memory device according to any one of claims 1 to 4.

6. Providing a substrate; forming a stack structure on the substrate, the stack structure including alternating sacrificial layers and insulating layers extending along a first direction substantially parallel to a top surface of the substrate; Dividing the stack structure into at least two parts and forming at least one vertical trench extending along the first direction and including an opening; forming a plurality of tiers of gate material layers extending along the first direction based on the stack structure in which the at least one vertical trench is formed; forming two or more connecting portions that conductively connect the at least two portions; After forming the plurality of levels and forming the two or more connecting portions, filling the at least one vertical trench with an insulating material to form at least one gate line slit; forming the two or more connection parts includes forming a plurality of the two or more connection parts; Each of the two or more connection portions is configured to conductively connect the gate material layer of the same level included in each of the at least two portions; the plurality of hierarchical levels includes a first hierarchical level and a second hierarchical level that is a level above the first hierarchical level, a number of the two or more connection portions that conductively connect the gate material layer of the first level included in each of the at least two portions is greater than a number of the two or more connection portions that conductively connect the gate material layer of the second level included in each of the at least two portions; the two or more connection portions that conductively connect the gate material layers of the first level included in each of the at least two portions include connection portions that have a length in the first direction that is shorter than a length in the first direction of the two or more connection portions that conductively connect the gate material layers of the second level included in each of the at least two portions; A method for forming a memory device.

7. The two or more connection portions are aligned along the first direction. A method for forming the memory device of claim 6.

8. forming a respective one of a plurality of metal contact vias on each of the plurality of levels of gate material layers. A method for forming a memory device according to claim 6 or 7.

9. forming the at least one gate line slit includes depositing the insulating material on a sidewall of the at least one vertical trench; The forming method includes: forming a source region by doping the substrate at a bottom of the at least one vertical trench before forming the at least one gate line slit; and forming a source contact via in the at least one vertical trench by filling a center of the at least one vertical trench with a source material after depositing the insulating material on the sidewalls. A method for forming a memory device according to any one of claims 6 to 8.

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