Semiconductor memory device

Abstract

To provide a semiconductor memory device for improving an operation speed thereof.SOLUTION: A semiconductor memory device of the embodiment including: a first memory cell and a second memory cell adjacent to each other and connected in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit, in which the control circuit is configured to perform a plurality of program loop operations each including a program operation and a verify operation after the program operation, supply a first write voltage to the first word line and supply a first voltage less than the first write voltage to the second word line during a first period in the program operation in a first program loop operation that is included in the plurality of program loop operations and is a target for the first memory cell, and supply a second voltage less than the first voltage to the first word line during a second period after the first period and supply a third voltage higher than the second voltage to the second word line.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device capable of storing data in a nonvolatile manner. NAND flash memory employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-28958 A Summary of the Invention [Problem to be solved by the invention]

[0004] The operating speed of a semiconductor memory device is improved. [Means for solving the problem]

[0005] A semiconductor memory device of an embodiment includes a first memory cell and a second memory cell adjacent to each other and connected in series, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a control circuit, wherein the control circuit executes a plurality of program loop operations, each having a program operation and a verify operation after the program operation, and is configured to, in a first program loop operation included in the plurality of program loop operations and targeting the first memory cell, during the program operation, supply a first write voltage to the first word line during a first period while supplying a first voltage less than the first write voltage to the second word line, and during a second period after the first period while supplying a second voltage less than the first voltage to the first word line, and supply a third voltage higher than the second voltage to the second word line. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment, and a host device. [Diagram 2] FIG. 1 is a block diagram showing an example of a configuration of a semiconductor memory device according to an embodiment. [Diagram 3] 1 is a circuit diagram for explaining an example of a configuration of a memory cell array in a semiconductor memory device according to an embodiment. [Figure 4] 1 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to an embodiment; [Diagram 5] 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of a cross-sectional structure of the memory cell array in the semiconductor memory device according to the embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure of a memory pillar included in a memory cell array of the semiconductor memory device according to the embodiment. [Figure 7] 3 is a schematic diagram showing an example of a threshold voltage distribution of a memory cell transistor included in a memory cell array of the semiconductor memory device according to the embodiment. [Figure 8] 1 is a block diagram showing an example of a configuration of a memory cell array, a driver module, and a row decoder module of a semiconductor memory device according to an embodiment. [Figure 9] FIG. 2 is a block diagram showing an example of the configuration of a sense amplifier module of the semiconductor memory device according to the embodiment. [Figure 10] 4 is a timing chart showing an outline of a write operation of the semiconductor memory device according to the embodiment. [Figure 11] 11 is a timing chart showing an example of a program loop operation of the semiconductor memory device according to the embodiment. [Figure 12] 11 is a table for explaining a write operation using a semiconductor memory device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. Note that the dimensions and ratios in the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference numerals. In addition, when elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment A semiconductor memory device according to an embodiment will be described below.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the embodiment will be described.

[0010] 1.1.1 Memory System First, a configuration example of a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment, and a host device.

[0011] The memory system 3 is, for example, a solid state drive (SSD) or TM The memory system 3 is a card. The memory system 3 is connected to, for example, an external host device 4. The memory system 3 stores data from the host device 4. The memory system 3 also reads out data to the host device 4.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2. Note that the semiconductor memory device 1 and the memory controller 2 may be combined to form one semiconductor device, for example.

[0013] The semiconductor memory device 1 is, for example, a NAND type flash memory. The semiconductor memory device 1 stores data in a non-volatile manner. The semiconductor memory device 1 is connected to a memory controller 2 via a NAND bus. In the following, an example will be described in which the semiconductor memory device 1 is a NAND type flash memory.

[0014] The NAND bus transmits and receives signals DQ<7:0>, DQS, / DQS, / CE, CLE, ALE, / WE, / RE, RE, / WP, and / RB conforming to the NAND interface via individual signal lines. The signal / CE is a chip enable signal. The signal / CE is a signal for enabling the semiconductor memory device 1. The signal CLE is a command latch enable signal. While the signal CLE is at an “H (High)” level, the semiconductor memory device 1 is notified that the signal DQ<7:0> flowing through the semiconductor memory device 1 is a command. The signal ALE is an address latch enable signal. While the signal ALE is at an “H” level, the semiconductor memory device 1 is notified that the signal DQ<7:0> flowing through the semiconductor memory device 1 is an address. The signal / WE is a write enable signal. The signal / WE instructs the semiconductor memory device 1 to take in the signal DQ<7:0>. For example, the signal / WE instructs the semiconductor memory device 1 to take in the signal DQ<7:0> as a command, address, or data at the rising edge of the signal / WE in a single data rate (SDR). Also, the signal / WE instructs the semiconductor memory device 1 to take in the signal DQ<7:0> as a command or address at the rising edge of the signal / WE in a double data rate (DDR). The signal / RE is a read enable signal. The signal / RE instructs the semiconductor memory device 1 to output the signal DQ<7:0>. For example, the signal / RE instructs the semiconductor memory device 1 to output the signal DQ<7:0> as data at the falling edge of the signal / RE in a single data rate. Also, the signal / RE instructs the semiconductor memory device 1 to output the signal DQ<7:0> as data at the falling edge and rising edge of the signal / RE in a double data rate. Signal RE is the complement of signal / RE.The signal / WP is a Write Protect signal. The signal / WP instructs the semiconductor memory device 1 to prohibit writing and erasing of data. The signal / RB is a Ready Busy signal. The signal / RB indicates whether the semiconductor memory device 1 is in a ready state (a state in which an external command is accepted) or a busy state (a state in which an external command is not accepted). The signal DQ<7:0> is, for example, an 8-bit signal. The signal DQS is a Data Strobe signal. The signal DQS is used to control the operation timing of the semiconductor memory device 1 related to the signal DQ<7:0>. For example, the signal DQS instructs the semiconductor memory device 1 to take in the signal DQ<7:0> as data at the falling edge and rising edge of the signal DQS at the double data rate. Furthermore, the signal DQS is generated based on the falling edge and rising edge of the signal / RE at the double data rate. The signal DQS is output together with the signal DQ<7:0> as data from the semiconductor memory device 1. The signal / DQS is a complementary signal to the signal DQS.

[0015] The signal DQ<7:0> is transmitted and received between the semiconductor memory device 1 and the memory controller 2, and includes a command CMD, an address ADD, and data DAT. The command CMD includes, for example, a command (erase command) for causing the semiconductor memory device 1 to execute an erase operation, a command (write command) for causing the semiconductor memory device 1 to execute a write operation, and a command (read command) for causing the semiconductor memory device 1 to execute a read operation. The data DAT includes read data and write data.

[0016] The memory controller 2 receives commands from the host device 4. The memory controller 2 controls the semiconductor memory device 1 based on the received commands. Specifically, the memory controller 2 writes data that is instructed to be written to the semiconductor memory device 1 based on a write command received from the host device 4. Also, the memory controller 2 reads data that is instructed to be read by the host device 4 from the semiconductor memory device 1 based on a read command received from the host device 4, and transmits the data to the host device 4.

[0017] Examples of the host device 4 that uses the memory system 3 described above include a digital camera, a personal computer, and a server in a data center.

[0018] 1.1.2 Memory Controller The configuration of the memory controller 2 will be explained further with reference to FIG.

[0019] The memory controller 2 includes a CPU (Central Processing Unit) 20, an internal memory 21, a buffer memory 22, a NAND interface circuit (NAND I / F) 23, and a host interface circuit (host I / F) 24. The memory controller 2 is configured as, for example, a SoC (System-on-a-Chip).

[0020] The CPU 20 controls the overall operation of the memory controller 2. The CPU 20 issues commands to instruct the semiconductor memory device 1 to execute various operations such as a write operation, a read operation, and an erase operation, for example.

[0021] The built-in memory 21 is, for example, a semiconductor memory such as a DRAM. The built-in memory 21 is used as a work area for the CPU 20. The built-in memory 21 stores firmware for managing the semiconductor storage device 1, various management tables, and the like.

[0022] The buffer memory 22 temporarily stores write data received from the host device 4, read data received by the memory controller 2 from the semiconductor memory device 1, and the like.

[0023] The NAND interface circuit 23 is connected to the semiconductor memory device 1 via a NAND bus and controls communication with the semiconductor memory device 1. In response to an instruction from the CPU 20, the NAND interface circuit 23 transmits a command CMD, an address ADD, and write data to the semiconductor memory device 1. In addition, the NAND interface circuit 23 receives read data from the semiconductor memory device 1.

[0024] The host interface circuit 24 is connected to the host device 4 via a host bus, and controls communication between the memory controller 2 and the host device 4. The host interface circuit 24 transfers, for example, commands and data received from the host device 4 to the CPU 20 and the buffer memory 22, respectively.

[0025] 1.1.3 Semiconductor memory devices Next, the internal configuration of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of a semiconductor memory device according to the embodiment.

[0026] The semiconductor memory device 1 includes a memory cell array 10, an input / output circuit 11, a logic control circuit 12, an address register 13, a command register 14, a sequencer 15, a driver module 16, a row decoder module 17, and a sense amplifier module 18.

[0027] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 2). Each block BLK is a set of a plurality of memory cell transistors capable of storing data in a non-volatile manner. Each block BLK is used, for example, as a data erasure unit. That is, data stored in memory cell transistors included in the same block BLK is erased all at once. The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. The plurality of bit lines and the plurality of word lines will be described later. Each memory cell transistor is associated with one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0028] The input / output circuit 11 transmits and receives the signal DQ<7:0> to and from the memory controller 2. The input / output circuit 11 transfers the address ADD and the command CMD in the signal DQ<7:0> to the address register 13 and the command register 14, respectively. In addition, the input / output circuit 11 transmits and receives the data DAT to and from the sense amplifier module 18.

[0029] The logic control circuit 12 receives, for example, signals DQS, / DQS, / CE, CLE, ALE, / WE, / RE, RE, and / WP from the memory controller 2. The logic control circuit 12 controls the input / output circuit 11 based on the received signals. The logic control circuit 12 also generates a signal / RB and transmits it to the memory controller 2.

[0030] The address register 13 stores an address ADD transferred from the input / output circuit 11. The address ADD includes, for example, a block address, a column address, and a page address. The block address, the column address, and the page address are associated with a block BLK, a bit line, and a word line, respectively. The address register 13 transfers the stored address ADD to the row decoder module 17 and the sense amplifier module 18.

[0031] The command register 14 stores the command CMD transferred from the input / output circuit 11. The command register 14 transfers the stored command CMD to the sequencer 15.

[0032] The sequencer 15 receives a command CMD from the command register 14 and controls the entire semiconductor memory device 1 in accordance with a sequence based on the received command CMD. For example, when the sequencer 15 receives an erase command, a write command, or a read command, the sequencer 15 instructs the driver module 16 to generate a voltage to be used in the corresponding operation.

[0033] Based on instructions from the sequencer 15, the driver module 16 generates voltages used for erase operations, write operations, read operations, etc., and supplies the generated voltages to the memory cell array 10, the row decoder module 17, the sense amplifier module 18, etc.

[0034] The row decoder module 17 receives a block address in the address ADD from the address register 13, and selects one of the blocks BLK0 to BLK(k-1) based on the block address. The row decoder module 17 supplies a voltage supplied from the driver module 16 to the selected block BLK, for example.

[0035] The sense amplifier module 18 receives a column address in the address ADD from the address register 13. The sense amplifier module 18 transfers data DAT between the memory controller 2 and the memory cell array 10 based on the column address. More specifically, during a write operation, the sense amplifier module 18 receives write data from the input / output circuit 11. The sense amplifier module 18 transfers the write data to the memory cell array 10. During a read operation, the sense amplifier module 18 senses the threshold voltage of a memory cell transistor in the memory cell array 10 that is the target of the read operation to generate read data. The sense amplifier module 18 transfers the read data to the input / output circuit 11.

[0036] 1.1.4 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 10 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram for explaining an example of the configuration of the memory cell array of the semiconductor memory device according to the embodiment. Fig. 3 shows the circuit of one block BLK among a plurality of blocks BLK included in the memory cell array 10. In the example shown in Fig. 3, the block BLK includes five string units SU0, SU1, SU2, SU3, and SU4.

[0037] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BL(m-1) (m is an integer equal to or greater than 2). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage film. Each of the memory cell transistors MT0 to MT7 holds data in a non-volatile manner. The select transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, when the bit lines BL0 to BL(m-1) are not differentiated from one another, each of the bit lines BL0 to BL(m-1) is simply called a bit line BL. When the memory cell transistors MT0 to MT7 are not differentiated from one another, each of the memory cell transistors MT0 to MT7 is simply called a memory cell transistor MT. When the select transistors ST1 and ST2 are not differentiated from one another, each of the select transistors ST1 and ST2 is simply called a select transistor ST.

[0038] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. A first terminal of the selection transistor ST1 is connected to a bit line BL associated with the selection transistor ST1. A second terminal of the selection transistor ST1 is connected to one terminal of the series-connected memory cell transistors MT0 to MT7. A first terminal of the selection transistor ST2 is connected to the other terminal of the series-connected memory cell transistors MT0 to MT7. A second terminal of the selection transistor ST2 is connected to a source line SL.

[0039] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. The gates of the select transistors ST1 in the string units SU0 to SU4 are connected to the select gate lines SGD0 to SGD4, respectively. In contrast, the gates of the select transistors ST2 are commonly connected to the select gate line SGS. However, this is not limited to this, and the gates of the select transistors ST2 may be connected to different select gate lines SGS for each string unit SU. In the following description, when the word lines WL0 to WL7 are not differentiated, each of the word lines WL0 to WL7 is simply referred to as a word line WL. When the select gate lines SGD0 to SGD4 are not differentiated, each of the select gate lines SGD0 to SGD4 is simply referred to as a select gate line SGD.

[0040] A different column address is assigned to each of the bit lines BL0 to BL(m-1). Each bit line BL is shared by a NAND string NS that is assigned the same column address among multiple blocks BLK. Word lines WL0 to WL7 are provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0041] A set of multiple memory cell transistors MT connected to a common word line WL in one string unit SU is called, for example, a cell unit CU. The storage capacity of a cell unit CU including multiple memory cell transistors MT, each of which stores one bit of data, is defined as, for example, "one page of data." The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0042] The circuit configuration of the memory cell array 10 is not limited to the above-described configuration. For example, the number of string units SU included in each block BLK may be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS may be any number.

[0043] 1.1.5 Memory Cell Array Structure Next, the structure of the memory cell array 10 will be described. In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate used to form the semiconductor memory device 1. Hatching is appropriately added to the plan views to make the views easier to see. The hatching added to the plan views does not necessarily relate to the material or characteristics of the components to which the hatching is added. In the cross-sectional views, illustrations of the configuration are appropriately omitted to make the views easier to see. The configurations shown in each drawing are appropriately simplified.

[0044] 1.1.5.1 Planar structure The planar structure of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the memory cell array of the semiconductor memory device according to the embodiment. Fig. 4 shows an area corresponding to one block BLK.

[0045] The memory cell array 10 includes a stacked wiring structure, a plurality of memory pillars MP, a plurality of contacts CC, and a plurality of members SLT and SHE.

[0046] The stacked wiring structure is a structure stacked along the Z direction according to the select gate lines SGD and SGS and the word lines WL0 to WL7. The stacked wiring structure includes the select gate lines SGD and SGS and the word lines WL0 to WL7. In the following description, each of the select gate lines SGD and SGS and the word lines WL0 to WL7 is also simply referred to as a stacked wiring. Each stacked wiring extends in the X direction.

[0047] The stacked wiring structure is divided into, for example, a memory region MR and a lead-out region HR. The memory region MR and the lead-out region HR are aligned in the X direction. In the following description, the memory region MR and the lead-out region HR on the lead-out region HR side are referred to as one end side along the X direction. Also, the memory region MR and the lead-out region HR on the memory region MR side are referred to as the other end side along the X direction.

[0048] The memory region MR is an area in which data is actually stored. A plurality of memory pillars MP are provided in the memory region MR.

[0049] The lead-out region HR is a region used for connecting the stacked wiring to the row decoder module 17 etc. A plurality of contacts CC are provided in the lead-out region HR.

[0050] Each member SLT extends in the X direction. Each member SLT crosses the stacked wiring structure in the X direction across the memory region MR and the lead-out region HR. Multiple members SLT are arranged in the Y direction. Each member SLT divides adjacent stacked wirings via the member SLT. Each area separated by multiple members SLT corresponds to one block BLK. Each member SLT has a structure in which, for example, an insulator or a plate-shaped contact is embedded therein.

[0051] Each member SHE extends in the X direction. Each member SHE crosses the stacked wiring structure in the X direction across the memory region MR. The multiple members SHE are arranged in the Y direction. Each member SHE has a structure in which an insulator is embedded, for example. Each member SHE divides adjacent selection gate lines SGD, for example, via the member SHE. Each of the regions partitioned by the multiple members SLT and SHE corresponds to one string unit SU.

[0052] In the following description, the string unit SU0 side of the five string units SU in each block BLK will be referred to as one end side in the Y direction, and the string unit SU4 side of the five string units SU in each block BLK will be referred to as the other end side in the Y direction.

[0053] In the lead-out region HR, the select gate lines SGS and SGD and the word lines WL0 to WL7 have a plurality of terrace portions that do not overlap with the upper conductive layer.

[0054] A plurality of contacts CC are provided on the plurality of terrace portions. Each of the plurality of contacts CC is electrically connected to a row decoder module 17. As a result, a voltage is supplied to the selection gate lines SGS and SGD and the word lines WL0 to WL7 via the plurality of contacts CC.

[0055] In the memory region MR, each memory pillar MP functions as, for example, one NAND string NS. With such a configuration, the memory cell array 10 stores data. The block BLK includes a row of memory pillars MP aligned in the Y direction. In each row of memory pillars MP, the memory pillars MP are aligned in the X direction. In the example shown in FIG. 5, for example, 24 rows of memory pillars MP are aligned in the Y direction in each block BLK. The memory pillars MP are arranged in a staggered pattern, for example. In addition, the memory pillars MP are arranged such that the member SHE overlaps the 5th, 10th, 15th, and 20th memory pillars MP counting from one end side in the Y direction.

[0056] With the above-described configuration, in the memory region MR of each block BLK extending in the X direction, each memory pillar MP at one end along the X direction can be provided at a position physically closer to the contacts CC connected to the row decoder module 17 than the memory pillar MP provided at the other end along the X direction of the memory pillar MP. In such a configuration, in the memory region MR of each block BLK, one end side and the other end side along the X direction are called the near side and the far side, respectively. Also, in such a configuration, the memory region MR of each block BLK includes a near side region and a far side region that are adjacently arranged in this order from one end side to the other end side along the X direction, for example.

[0057] In the memory cell array 10, the above-described planar layout is repeatedly arranged in the Y direction.

[0058] The planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number depending on the number of string units SU. In addition, the number and arrangement of the memory pillars MP in each block BLK are not limited to the configuration described using FIG. 4, and can be changed as appropriate.

[0059] 1.1.5.2 Cross-sectional structure Next, the cross-sectional structure of the memory cell array 10 will be described.

[0060] The cross-sectional structure of the memory cell array 10 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view taken along line VV in Fig. 4, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the embodiment. Fig. 5 shows an example of the cross-sectional structure of the memory cell array 10 taken along the YZ plane.

[0061] The memory cell array 10 further includes a semiconductor substrate 40, conductive layers 41-45, and insulating layers 30-.

[0062] More specifically, an insulator layer 30 is provided on a semiconductor substrate 40. The insulator layer 30 includes circuits (not shown), such as a row decoder module 17 and a sense amplifier module 18. In the following description, the side of the semiconductor substrate 40 on which the memory cell array 10 is provided is referred to as the upper side.

[0063] A conductive layer 41 is provided on the insulating layer 30. The conductive layer 41 is formed in a plate shape extending along the XY plane, for example. The conductive layer 41 is used as a source line SL. The conductive layer 41 includes, for example, silicon doped with phosphorus.

[0064] An insulating layer 31 is provided on the conductive layer 41. A conductive layer 42 is provided on the insulating layer 31. The conductive layer 42 is formed in a plate shape extending along the XY plane, for example. The conductive layer 42 is used as a select gate line SGS. The conductive layer 42 includes, for example, tungsten.

[0065] A plurality of insulating layers 32 and a plurality of conductive layers 43 are stacked on the conductive layer 42. The plurality of insulating layers 32 and the plurality of conductive layers 43 are stacked in the following order from the top: insulating layer 32, conductive layer 43, insulating layer 32, ..., conductive layer 43, insulating layer 32, and conductive layer 43. The conductive layer 43 is formed, for example, in a plate shape extending along the XY plane. The stacked conductive layers 43 are used as word lines WL0 to WL7, respectively, in order from the semiconductor substrate 40 side. The conductive layer 43 contains, for example, tungsten.

[0066] An insulating layer 33 is provided on the uppermost conductive layer 43. A conductive layer 44 is provided on the insulating layer 33. The conductive layer 44 is formed in a plate shape extending along the XY plane, for example. The conductive layer 44 is used as a select gate line SGD. The conductive layer 44 includes, for example, tungsten.

[0067] An insulating layer 34 is provided on the conductive layer 44. A plurality of conductive layers 45 are provided on the insulating layer 34. Each conductive layer 45 is formed in a line shape extending in the Y direction, for example. Each conductive layer 45 is used as a bit line BL. The conductive layer 45 includes, for example, copper.

[0068] Each of the memory pillars MP is provided extending along the Z direction, and penetrates the insulating layers 31-33 and the conductive layers 42-44. The bottom of the memory pillar MP is in contact with the conductive layer 41. The portion where the memory pillar MP intersects with the conductive layer 42 functions as a select transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 43 functions as one memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 44 functions as a select transistor ST1.

[0069] Each of the memory pillars MP includes, for example, a core member 50, a semiconductor layer 51, and a laminated film 52. The core member 50 is provided by extending along the Z direction. The upper end of the core member 50 is located, for example, above the conductive layer 44. The lower end of the core member 50 is located, for example, below the conductive layer 42. The semiconductor layer 51 covers the periphery of the core member 50. At the lower part of the memory pillar MP, a part of the semiconductor layer 51 contacts the conductive layer 41. The laminated film 52 covers the side and bottom surfaces of the semiconductor layer 51 except for the part where the semiconductor layer 51 and the conductive layer 41 contact each other. The core member 50 includes, for example, an insulator such as silicon oxide. The semiconductor layer 51 includes, for example, silicon.

[0070] A columnar contact CV is provided on the upper surface of the semiconductor layer 51 in the memory pillar MP. In the illustrated region, one contact CV corresponding to one of the three memory pillars MP is shown. In the memory region MR, the contact CV is connected in a region not shown to the memory pillar MP that does not overlap with the member SHE and is not connected to the contact CV.

[0071] The upper surface of the contact CV is electrically connected to one conductive layer 45. The contacts CV are provided in each of the spaces partitioned by the members SLT and SHE such that one contact CV is connected to one conductive layer 45. That is, one memory pillar MP included in each string unit SU is electrically connected to each of the conductive layers 45.

[0072] The member SLT has a portion provided along, for example, the XZ plane, and divides the conductive layers 42 to 44. The member SLT includes a contact LI and a spacer SP. The contact LI is, for example, a conductive material having a portion provided extending in the X direction. The spacer SP is, for example, an insulator provided on the side surface of the contact LI. The contact LI and the stacked wiring adjacent to the contact LI in the Y direction are separated by the spacer SP. This electrically insulates the contact LI from the stacked wiring adjacent to the contact LI in the Y direction. The contact LI may be an insulator. In this case, the contact LI and the spacer SP may be formed integrally.

[0073] The member SHE has a portion provided along, for example, the XZ plane, and divides the conductive layer 44. The lower surface of the member SHE is located, for example, between the uppermost conductive layer 43 and the conductive layer 44. The member SHE includes an insulator such as silicon oxide.

[0074] 1.1.5.3 Memory pillar structure The structure of a memory pillar MP in the semiconductor memory device 1 according to the embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of a memory pillar included in the memory cell array of the semiconductor memory device according to the embodiment.

[0075] The laminated film 52 includes, for example, a tunnel insulating film 53, an insulating film 54, and a block insulating film 55.

[0076] In a cross section including the conductor layer 43, the core member 50 is provided in the center of the memory pillar MP. The core member 50 has, for example, a circular shape in the XY plane. The semiconductor layer 51 surrounds the side surface of the core member 50. The tunnel insulating film 53 surrounds the side surface of the semiconductor layer 51. The insulating film 54 surrounds the side surface of the tunnel insulating film 53. The block insulating film 55 surrounds the side surface of the insulating film 54. The conductor layer 43 surrounds the side surface of the block insulating film 55. Each of the tunnel insulating film 53 and the block insulating film 55 contains, for example, silicon oxide. The insulating film 54 contains, for example, silicon nitride.

[0077] With the above-described configuration, the memory pillar MP has, for example, a circular shape in the XY plane.

[0078] In the above-mentioned memory pillar MP, the semiconductor layer 51 functions as a current path for the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The insulating film 54 is used as a charge storage layer for the memory cell transistors MT. The semiconductor memory device 1 causes a current to flow through the memory pillar MP between the bit line BL and the source line SL by turning on the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2.

[0079] 1.1.6 Threshold voltage distribution of memory cell transistors The threshold voltage distribution of the memory cell transistors MT in the semiconductor memory device according to the embodiment will be described with reference to FIG. 7. FIG. 7 is a schematic diagram showing an example of the threshold voltage distribution of the memory cell transistors included in the memory cell array of the semiconductor memory device according to the embodiment. In the threshold voltage distribution shown in FIG. 7, the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT. The vertical axis corresponds to the number of memory cell transistors MT. In FIG. 7, the number of memory cell transistors MT is indicated as a value NMTs.

[0080] In the semiconductor memory device 1 according to the embodiment, eight states are formed in each block BLK, for example, depending on the threshold voltages of a plurality of memory cell transistors MT. Hereinafter, the eight states are referred to as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state, in order from the lowest threshold voltage. The numbers of memory cell transistors MT included in the "S0" state to the "S7" state are, for example, approximately equal to each other.

[0081] The "S0" state corresponds to, for example, an erased state of data. The threshold voltage of the memory cell transistor MT included in the "S0" state is less than the voltage R1.

[0082] The "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states correspond to states in which data is written. The threshold voltage of the memory cell transistor MT included in the "S1" state is equal to or greater than the voltage R1 and less than the voltage R2 (R2>R1). The threshold voltage of the memory cell transistor MT included in the "S2" state is equal to or greater than the voltage R2 and less than the voltage R3 (R3>R2). The threshold voltage of the memory cell transistor MT included in the "S3" state is equal to or greater than the voltage R3 and less than the voltage R4 (R4>R3). The threshold voltage of the memory cell transistor MT included in the "S4" state is equal to or greater than the voltage R4 and less than the voltage R5 (R5>R4). The threshold voltage of the memory cell transistor MT included in the "S5" state is equal to or greater than the voltage R5 and less than the voltage R6 (R6>R5). The threshold voltage of the memory cell transistor MT in the "S6" state is equal to or greater than voltage R6 and less than voltage R7 (R7>R6). The threshold voltage of the memory cell transistor MT in the "S7" state is equal to or greater than voltage R7 and less than voltage VREAD (VREAD>R7). When the voltage VREAD is supplied to the control gate of the memory cell transistor MT, it turns on the memory cell transistor MT regardless of whether the memory cell transistor MT is in the "S0" state to the "S7" state.

[0083] When a voltage is supplied to the control gate of the memory cell transistor MT, the memory cell transistor MT is turned on if the memory cell transistor MT has a threshold voltage less than the supplied voltage, and when a voltage is supplied to the control gate of the memory cell transistor MT, the memory cell transistor MT is turned off if the memory cell transistor MT has a threshold voltage equal to or greater than the supplied voltage.

[0084] A different 3-bit data is assigned to each of the eight types of threshold voltage distributions of the memory cell transistors MT described above. An example of data allocation to the threshold voltage distributions is listed below. In the following, the data assigned to each state is shown in the order of "upper bit, middle bit, lower bit" corresponding to the state.

[0085] “S0” state: “1, 1, 1” data, “S1” state: “1, 1, 0” data, “S2” state: “1, 0, 0” data, “S3” state: “0, 0, 0” data, “S4” state: “0, 1, 0” data, “S5” state: “0, 1, 1” data, “S6” state: “0, 0, 1” data, “S7” state: “1, 0, 1” data.

[0086] When such data allocation is applied, one page of data (lower page data) composed of lower bits is determined by a read operation using voltages R1 and R5, one page of data (middle page data) composed of middle bits is determined by a read operation using voltages R2, R4, and R6, and one page of data (upper page data) composed of upper bits is determined by a read operation using voltages R3 and R7.

[0087] Also, between adjacent states, a verify voltage is set, which is used to determine the threshold voltage of the memory cell transistor MT during a write operation. More specifically, between the "S0" state and the "S1" state, a voltage V1 is set as the verify voltage. The voltage V1 is, for example, higher than the voltage R1. Between the "S1" state and the "S2" state, a voltage V2 is set as the verify voltage. The voltage V2 is, for example, higher than the voltage R2. Between the "S2" state and the "S3" state, a voltage V3 is set as the verify voltage. The voltage V3 is, for example, higher than the voltage R3. Between the "S3" state and the "S4" state, a voltage V4 is set as the verify voltage. The voltage V4 is, for example, higher than the voltage R4. Between the "S4" state and the "S5" state, a voltage V5 is set as the verify voltage. The voltage V5 is, for example, higher than the voltage R5. Between the "S5" state and the "S6" state, a voltage V6 is set as the verify voltage. The voltage V6 is higher than the voltage R6, for example. Between the "S6" state and the "S7" state, a voltage V7 is set as a verify voltage. The voltage V7 is higher than the voltage R7, for example.

[0088] In the description of the semiconductor memory device 1 according to the embodiment, each memory cell transistor MT stores 3-bit data, but this is not limiting. The semiconductor memory device 1 may be configured such that each memory cell transistor MT stores 2-bit data, or 4-bit data or more.

[0089] 1.1.7 Configuration of memory cell array, driver module, and row decoder module Next, the connection relationship between the memory cell array 10, the driver module 16, and the row decoder module 17 will be described with reference to Fig. 8. Fig. 8 is a block diagram showing an example of the configuration of the memory cell array, the driver module, and the row decoder module of the semiconductor memory device according to the embodiment.

[0090] The row decoder module 17 includes row decoders RD0 to RD(k-1). The row decoders RD0 to RD(k-1) are used to select a block BLK. The row decoders RD0 to RD(k-1) are associated with the blocks BLK0 to BLK(k-1), respectively.

[0091] Each row decoder RD includes, for example, a block decoder BD and transistors TR0 to TR19. The transistors TR0 to TR19 are, for example, high-voltage N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The transistors TR0 and TR14 are associated with the select gate line SGS included in each block BLK. The transistors TR1 to TR8 are associated with the word lines WL0 to WL7 included in each block BLK. The transistors TR9 and TR15 are associated with the select gate line SGD0 included in each block BLK. The transistors TR10 and TR16 are associated with the select gate line SGD1 included in each block BLK. The transistors TR11 and TR17 are associated with the select gate line SGD2 included in each block BLK. The transistors TR12 and TR18 are associated with the select gate line SGD3 included in each block BLK. The transistors TR13 and TR19 are associated with the select gate line SGD4 included in each block BLK.

[0092] The block decoder BD decodes the block address in the address ADD. The block decoder BD supplies a "H" level voltage and a "L (Low)" level voltage to the transfer gate lines TG and bTG, respectively, based on, for example, the result of the decoding. The block decoder BD supplies an "L" level voltage to the transfer gate line bTG while supplying an "H" level voltage to the transfer gate line TG. In addition, the block decoder BD supplies an "H" level voltage to the transfer gate line bTG while supplying an "L" level voltage to the transfer gate line TG.

[0093] The transistors TR0 to TR19 associated with each block BLK connect the driver module 16 to the block BLK via signal lines SGSD, CG0 to CG7, SGDD0 to SGDD4, USGS, and USGD. In the following description, when the signal lines SGSD, CG0 to CG7, SGDD0 to SGDD4, USGS, and USGD are not distinguished from each other, each of the signal lines SGSD, CG0 to CG7, SGDD0 to SGDD4, USGS, and USGD is simply referred to as a signal line CG.

[0094] More specifically, in each row decoder RD, a gate of the transistor TR0 is connected to a transfer gate line TG. A first end of the transistor TR0 is connected to the driver module 16 via a signal line SGSD. A second end of the transistor TR0 is connected to a selection gate line SGS.

[0095] The gates of the transistors TR1 to TR8 are connected to a transfer gate line TG. The first terminals of the transistors TR1 to TR8 are connected to the driver module 16 via the signal lines CG0 to CG7, respectively. The second terminals of the transistors TR1 to TR8 are connected to the word lines WL0 to WL7, respectively.

[0096] The gates of the transistors TR9 to TR13 are connected to a transfer gate line TG. First terminals of the transistors TR9 to TR13 are connected to the driver module 16 via signal lines SGDD0 to SGDD4, respectively. Second terminals of the transistors TR9 to TR13 are connected to the select gate lines SGD0 to SGD4, respectively.

[0097] The gate of the transistor TR14 is connected to the transfer gate line bTG. The first end of the transistor TR14 is connected to the driver module 16 via a signal line USGS. The second end of the transistor TR14 is connected to the select gate line SGS together with the second end of the transistor TR0.

[0098] The gates of the transistors TR15 to TR19 are connected to a transfer gate line bTG. First terminals of the transistors TR15 to TR19 are connected to the driver module 16 via a signal line USGD. Second terminals of the transistors TR15 to TR19 are connected to the select gate lines SGD0 to SGD4, respectively, together with second terminals of the transistors TR9 to TR13.

[0099] When a "H" level voltage is supplied to the transfer gate line TG, the transistors TR0 to TR13 are turned on. As a result, the voltages of the signal lines SGSD, CG0 to CG7, and SGDD0 to SGDD4 are transferred to the select gate line SGS, the word lines WL0 to WL7, and the select gate lines SGD0 to SGD4 via the transistors TR0 to TR13, respectively. When a "L" level voltage is supplied to the transfer gate line TG, the transistors TR0 to TR13 are turned off.

[0100] When a voltage of the "H" level is supplied to the transfer gate line bTG (when a voltage of the "L" level is supplied to the transfer gate line TG), the transistors TR14 to TR19 are turned on. As a result, the voltage of the signal line USGS is transferred to the select gate line SGS via the transistor TR14. Also, the voltage of the signal line USGD is transferred to the select gate lines SGD0 to SGD4 via the transistors TR15 to TR19. When a voltage of the "L" level is supplied to the transfer gate line bTG (when a voltage of the "H" level is supplied to the transfer gate line TG), the transistors TR14 to TR19 are turned off. The voltage of the signal lines USGS and USGD is, for example, the voltage VSS. The voltage VSS is the ground voltage. That is, when a voltage of the "H" level is supplied to the transfer gate line bTG of the row decoder RD, the voltage VSS is supplied to the select gate lines SGS and SGD0 to SGD4 of the block BLK corresponding to the row decoder RD (the select transistors ST1 and ST2 are turned off).

[0101] For each of the select gate lines SGS, SGD0 to SGD4, and word lines WL0 to WL7 of each block BLK, the wiring length between the portion included in the near side area and the row decoder RD or driver module 16 associated with that block BLK is configured to be shorter than the wiring length between the portion included in the far side area and the row decoder RD or driver module 16.

[0102] 1.1.8 Sense Amplifier Module Next, the configuration of the sense amplifier module 18 will be described with reference to Fig. 9. Fig. 9 is a block diagram showing an example of the configuration of the sense amplifier module of the semiconductor memory device according to the embodiment.

[0103] The sense amplifier module 18 includes sense amplifier units SAU0 to SAU(m-1). The sense amplifier units SAU0 to SAU(m-1) are associated with the bit lines BL0 to BL(m-1), respectively. In the following, when the sense amplifier units SAU0 to SAU(m-1) are not distinguished from one another, each of the sense amplifier units SAU0 to SAU(m-1) is simply referred to as a sense amplifier unit SAU. Each sense amplifier unit SAU includes, for example, a sense amplifier section SA, and latch circuits SDL, ADL, BDL, CDL, and XDL.

[0104] The sense amplifier unit SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are commonly connected to a bus LBUS. The latch circuits SDL, ADL, BDL, CDL, and XDL can transmit and receive data to and from each other.

[0105] Each sense amplifier unit SA receives, for example, a strobe signal STB generated by the sequencer 15. Then, the sense amplifier unit SA senses whether the threshold voltage of the selected memory cell transistor MT is equal to or higher than a read voltage based on the timing at which the strobe signal STB is asserted. In other words, the sense amplifier unit SA is a circuit that directly controls the reading of data stored in the selected memory cell transistor MT.

[0106] Each of the latch circuits SDL, ADL, BDL, CDL, and XDL temporarily holds data. The latch circuit XDL is used for inputting and outputting data DAT between the input / output circuit of the semiconductor memory device 1 and the sense amplifier unit SAU. The latch circuit XDL can also be used as, for example, a cache memory CM of the semiconductor memory device 1.

[0107] 1.2 Operation Next, an operation of the semiconductor memory device 1 according to the embodiment will be described.

[0108] In the following description, the word line WL selected based on the address ADD is called the selected word line WLn. The word lines WL that are not selected (unselected) are called the unselected word lines WLusel. Among the unselected word lines WLusel, the word lines WLusel adjacent to the selected word line WLn in the Z direction are called the adjacent word lines WLn±1. Among the unselected word lines WLusel, all the unselected word lines WLusel except for the adjacent word lines WLn±1 are called the unselected word lines WLoth.

[0109] Moreover, the memory cell transistor MT connected to the selected word line WLn is called a selected memory cell transistor MTn.

[0110] Moreover, a signal line CG connected to a selected word line WLn is called a selected signal line CGn. Moreover, a signal line CG connected to an unselected word line WLusel is called an unselected signal line CGusel. Moreover, of the unselected signal lines CGusel, unselected signal lines CGusel connected to adjacent word lines WLn±1 are called adjacent signal lines CGn±1. Moreover, of the unselected signal lines CGusel, unselected signal lines CGusel connected to unselected word lines WLoth are called unselected signal lines CGoth.

[0111] 1.2.1 Write Operation Overview The write operation will be outlined with reference to Fig. 10. Fig. 10 is a timing chart showing the outline of the write operation of the semiconductor memory device according to the embodiment.

[0112] The semiconductor memory device 1 repeatedly executes a program loop operation (Program loop) in a write operation. FIG. 10 shows the change in voltage of the selected word line WLn with an increase in the number of times the program loop operation is executed in the write operation (hereinafter referred to as the loop number). Each program loop operation includes a program operation (Program) and a write verify operation (Verify). Hereinafter, the write verify operation is simply referred to as a verify operation. By repeating the program loop operation, the semiconductor memory device 1 increases the threshold voltage of the memory cell transistor MT to a target voltage.

[0113] In each program loop operation, the sequencer 15 executes a program operation before a verify operation.

[0114] A program operation is an operation that can increase the threshold voltage of a memory cell transistor MT. In a program operation, a plurality of selected memory cell transistors MTn are set to be programmed or to be program-prohibited based on write data stored in the associated sense amplifier unit SAU. If the threshold voltage of the selected memory cell transistor MTn has not reached a target threshold voltage, the selected memory cell transistor MTn is set to be programmed. On the other hand, if the threshold voltage of the selected memory cell transistor MTn has reached a target threshold voltage, the selected memory cell transistor MTn is set to be program-prohibited.

[0115] In a program operation, a voltage VPGM is supplied to the selected word line WLn. The voltage VPGM is a voltage capable of increasing the threshold voltage of the selected memory cell transistor MTn. For example, the voltage VPGM increases with an increase in the number of loops. In the example of FIG. 10, the voltage VPGM increases by a voltage dVP each time the number of loops increases. When the voltage VPGM is supplied to the selected word line WLn, the threshold voltage of the selected memory cell transistor MTn set to be programmed increases. On the other hand, the increase in the threshold voltage of the selected memory cell transistor MTn set to be programmed is suppressed (the threshold voltage is maintained).

[0116] Hereinafter, the operation of increasing the threshold voltage of the memory cell transistor MT is called a "0" program operation, and the operation of maintaining the threshold voltage of the memory cell transistor MT is called a "1" program operation.

[0117] Upon completing the program operation, the sequencer 15 executes a verify operation.

[0118] The verify operation is a read operation for checking whether the threshold voltage of the selected memory cell transistor MTn has reached a target threshold voltage. For example, in each program loop operation, the sequencer 15 executes a read operation using a predetermined verify voltage on the selected memory cell transistor MTn set as the program target.

[0119] In the example of FIG. 10, one verify voltage is used in each verify operation, but this is not limited to this. Multiple verify voltages may be used in each verify operation. In this case, for example, read operations using multiple verify voltages are performed in sequence.

[0120] In the verify operation, the sense amplifier unit SAU judges whether the threshold voltage of the selected memory cell transistor MTn is higher than the verify voltage supplied to the selected word line WLn based on the voltage of the bit line BL. Each sense amplifier unit SAU judges the selected memory cell transistor MTn whose threshold voltage is higher than the verify voltage as "verify pass". On the other hand, each sense amplifier unit SAU judges the selected memory cell transistor MTn whose threshold voltage is equal to or lower than the verify voltage as "verify fail". Each sense amplifier unit SAU stores the verify result described above in any of the latch circuits inside the sense amplifier unit SAU. When the verify operation is completed, the sequencer 15 sets each selected memory cell transistor MTn to be programmed or programmed prohibited based on the result of the verify operation, and starts the next program loop operation.

[0121] 1.2.2 Program Loop Operation Each program loop operation in the embodiment will be described with reference to Fig. 11. Fig. 11 is a timing chart showing an example of a program loop operation of the semiconductor memory device according to the embodiment. Fig. 11 shows voltage changes of the word line WL, the select gate lines SGS and SGD, the bit line BL, and the source line SL.

[0122] 11, the solid line corresponds to the bit line BL corresponding to the memory cell transistor MT that is the target of the “1” program operation (hereinafter, bit line BL(“1”)). The dashed and dotted line corresponds to the bit line BL corresponding to the memory cell transistor MT that is the target of the “0” program operation (hereinafter, bit line BL(“0”)).

[0123] From time t0 to time t5, a program operation is executed.

[0124] At time t0, the sense amplifier module 18 supplies a voltage VBL to the bit line BL ("1") to perform BL precharge. The voltage VBL is, for example, a voltage higher than the voltage VSS (VBL>VSS). On the other hand, the voltage VSS is supplied to the bit line BL ("0").

[0125] Moreover, the row decoder module 17 selects one of the blocks BLK. Furthermore, the row decoder module 17 selects one of the string units SU. Then, the row decoder module 17 supplies a voltage VS to the selection gate line SGD in the selected string unit SU (selected string unit SU). Furthermore, the row decoder module 17 supplies a voltage VSS to the selection gate line SGD of the unselected string unit SU. The voltage VS is a voltage that turns on the selection transistor ST1 when the voltage VSS is supplied to the bit line BL, but turns off the selection transistor ST1 when the voltage VBL is supplied to the bit line BL.

[0126] In the following description, the select gate line SGD in the selected string unit SU is called the select gate line SGDsel, and the select gate line SGD in the unselected string unit SU is called the select gate line SGDusel.

[0127] Furthermore, the row decoder module 17 supplies the voltage VSS to the select gate line SGS to turn off the select transistor ST2.

[0128] In addition, the driver module 16 supplies a voltage VSL to the source line SL. The voltage VSL is, for example, higher than the voltage VSS.

[0129] By the above process, the channel of the NAND string NS corresponding to the bit line BL ("1") becomes in a floating state in which it is electrically insulated from the bit line BL and the source line SL.

[0130] As described above, in the same program operation, a "0" program operation and a "1" program operation can be set for each bit line BL.

[0131] The row decoder module 17 selects one of the word lines WL in the selected block BLK.

[0132] At time t1, the driver module 16 starts supplying the voltage VPGM to the selected signal line CGn. Then, the row decoder module 17 starts supplying the voltage VPGM to the selected word line WLn. As a result, the voltage of the selected word line WLn rises to a voltage approximately equal to the voltage VPGM.

[0133] The driver module 16 also starts supplying the voltage VPASS to the unselected signal lines CGusel, including the adjacent signal lines CGn±1 and CGoth. The row decoder module 17 then starts supplying the voltage VPASS to the unselected word lines WLusel. This causes the voltage of the unselected word lines WLusel to rise to a voltage substantially equal to the voltage VPASS.

[0134] In the NAND string NS corresponding to the bit line BL ("0"), the select transistor ST1 is in the on state. As a result, the channel potential of the memory cell transistor MT connected to the selected word line WLn is VSS. This increases the potential difference (VPGM-VSS) between the control gate and the channel. As a result, electrons are injected into the charge storage layer, increasing the threshold voltage of the memory cell transistor MT.

[0135] On the other hand, in the NAND string NS corresponding to the bit line BL ("1"), the channel of the memory cell transistor MT connected to the selected word line WLn is in a floating state. In this case, for example, the channel potential rises due to capacitive coupling between the channel and the word line WL. This reduces the potential difference between the control gate and the channel. As a result, almost no electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT is maintained.

[0136] At time t2, the driver module 16 starts to supply, for example, a voltage VP-V to the selected signal line CGn and the unselected signal line CGoth. Then, the row decoder module 17 supplies, for example, a voltage VP-V to the selected word line WLn and the unselected word line WLoth. Also, the driver module 16 starts to supply voltages VCGn±1 to the adjacent signal lines CGn±1. Then, the row decoder module 17 supplies voltages VCGn±1 to the adjacent word lines WLn±1. The voltage VP-V is, for example, equal to or higher than the voltage VSS (VP-V≧VSS). That is, the voltage VP-V may be equal to the voltage VSS. The voltages VCGn±1 are higher than the voltage VP-V (VCGn±1>VP-V). Also, the voltages VP-V and VCGn±1 are, for example, lower than the voltages VPASS and VREAD (VCGn±1, VP-V <VPASS、VREAD)。

[0137] The voltages of the selected word line WLn and the unselected word line WLoth become approximately equal to the voltage VP-V in accordance with the voltages transferred from the selected signal line CGn and the unselected signal line CGoth, respectively.

[0138] Furthermore, the adjacent word lines WLn±1 can quickly respond to the voltage transferred from the adjacent signal lines CGn±1 in the Near-side region. As a result, the voltage of the adjacent word lines WLn±1 (WLn±1(Near)) in the Near-side region becomes, for example, substantially the same as the voltage VCGn±1 without being affected by the voltage of the selected word line WLn.

[0139] On the other hand, the adjacent word lines WLn±1 in the far side region may be significantly affected by coupling due to the voltage drop of the selected word line WLn from voltage VPGM to voltage VP-V, compared to the near side region. As a result, the voltage of the adjacent word lines WLn±1 (WLn±1(Far)) in the far side region becomes lower than, for example, voltage VCGn±1. For example, voltage VCGn±1 is set so that the voltage of the adjacent word lines WLn±1(Far) is approximately equal to or higher than voltage VP-V. Note that the example of FIG. 11 shows a case where the voltage of the adjacent word lines WLn±1(Far) becomes approximately equal to voltage VP-V.

[0140] At time t3, the row decoder module 17 supplies the voltage VSS to the select gate line SGD, the sense amplifier module 18 supplies the voltage VSS to the bit line BL, and the driver module 16 supplies the voltage VSS to the source line SL.

[0141] At time t4, the driver module 16 supplies the voltage VP-V to the adjacent signal lines CGn±1. Then, the row decoder module 17 supplies the voltage VP-V to the adjacent word lines WLn±1. As a result, the voltages of the adjacent word lines WLn±1 become substantially equal to the voltage VP-V. That is, the voltages of all the word lines WL in the selected block BLK become substantially equal to each other.

[0142] By the above operations, charges are injected into the charge storage layer of the memory cell transistor MT that is the target of the "0" program operation, and the program operation is completed.

[0143] Then, at a time after time t5, a verify operation is executed.

[0144] In the following description, the period from when the voltage VP-V starts to be supplied to the selected word line WLn in the program operation until the verify operation starts is called the period PV. In other words, the period PV is the period from time t2 to time t5.

[0145] At time t5, the row decoder module 17 supplies, for example, a voltage VS to the select gate lines SGS and SGDsel. For example, a voltage VSS is supplied to the select gate line SGDusel. Note that the voltages supplied to the select gate lines SGDsel and SGS in the verify operation may be voltages that turn on the select transistors ST1 and ST2, respectively, and may be voltages different from the voltage VS. Through the above process, the select transistors ST1 and ST2 of the selected string unit SU are turned on. Also, the select transistor ST1 of the unselected string unit SU is turned off.

[0146] Further, the driver module 16 starts supplying the voltage VREAD to the signal lines CG0 to CG7. Then, the row decoder module 17 supplies the voltage VREAD to all the word lines WL of the selected block BLK. As a result, all the word lines WL are boosted at, for example, approximately equal speeds. Then, after a predetermined period has elapsed from time t5, the voltages of all the word lines WL are boosted to a voltage approximately equal to the voltage VREAD. As a result, the memory cell transistors MT in the selected block BLK are turned on.

[0147] At time t6, the driver module 16 starts supplying the voltage VVRF to the selection signal line CGn. The row decoder module 17 also supplies the voltage VVRF to the selected word line WLn. This causes the voltage of the selected word line WLn to become equal to the voltage VVRF. The voltage VVRF is one of the voltages V1 to V7 set as a verify voltage. That is, the voltage VVRF is less than the voltage VREAD (VREAD>VVRF). The voltage VVRF is set according to the threshold voltage of the memory cell transistor MT that is the target of the read operation. If the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the voltage VVRF, the memory cell transistor MT is turned off, and if the threshold voltage is equal to or lower than the voltage VVRF, the memory cell transistor MT is turned on.

[0148] At time t7, the sense amplifier module 18 sets the voltage of the bit line BL to the voltage VBL. Note that the voltage supplied to the bit line BL at time t7 may be, for example, a voltage different from the voltage VBL and higher than the voltage VSS.

[0149] At time t8, the driver module 16 starts supplying the voltage VREAD to the selected signal line CGn. The row decoder module 17 also supplies the voltage VREAD to the selected word line WLn. This causes the voltages of all the word lines WL in the selected block BLK to become approximately equal to the voltage VREAD.

[0150] At time t9, the driver module 16 starts supplying the voltage VSS to the signal lines CG0 to CG7. The row decoder module 17 also supplies the voltage VSS to all the word lines WL in the selected block BLK. This makes the voltages of all the word lines WL in the selected block BLK approximately equal to the voltage VSS.

[0151] In addition, the sense amplifier module 18 supplies a voltage VSS to the bit line BL.

[0152] In addition, the row decoder module 17 supplies a voltage VSS to the select gate lines SGDsel and SGS.

[0153] Through the above operations, data is read from the memory cell transistor MT corresponding to the selected word line WLn of the selected string unit SU. Then, it is determined whether the read memory cell transistor MT is a “verify pass” or a “verify fail”.

[0154] Note that Figure 11 is merely an example of a timing chart of a program loop operation according to an embodiment, and the magnitude relationship of the voltages supplied to each of the word line WL, select gate lines SGS and SGD, bit line BL, and source line SL does not necessarily coincide with the magnitude relationship of the voltages shown in Figure 11.

[0155] In the above example of the program loop operation, the voltages of the non-selected signal lines CGusel are equal between times t1 and t2 and between times t6 and t8, but this is not limiting. For example, the voltages of adjacent signal lines CGn±1 of the non-selected signal line CGusel may be higher than the voltage of the non-selected signal line CGoth between times t1 and t2 and between times t6 and t9.

[0156] 1.3 Effects According to the embodiment, it is possible to improve the operating speed of the semiconductor memory device 1. The effects of the embodiment will be described below.

[0157] The semiconductor memory device 1 according to the embodiment is configured to supply a voltage VPGM as a write voltage to the selected word line WLn while supplying a voltage VPASS to the adjacent word lines WLn±1 at time t1 in a program operation. The semiconductor memory device 1 is also configured to supply, for example, a voltage VP-V to the selected word line WLn while supplying a voltage VCGn±1 higher than the voltage VP-V to the adjacent word lines WLn±1 at time t2. With the above configuration, the semiconductor memory device 1 according to the embodiment can promote boosting of the word lines WL in a verify operation. This can improve the speed of the program loop operation and the write operation. Therefore, the operating speed of the semiconductor memory device 1 can be improved.

[0158] In addition, when the voltage VP-V is supplied to all unselected signal lines during the period PV, the far side region of the adjacent word lines may excessively drop below the voltage in the near side region due to coupling caused by the voltage drop of the selected word line. That is, the voltage in the far side region of the adjacent word lines may become lower than the voltage VP-V. In this case, after the period PV has elapsed, when all the word lines of the selected block are raised to the voltage VREAD in the verify operation, the boost in the far side region of the adjacent word lines is delayed. This causes a delay in the program loop operation and the write operation due to the slowdown of the verify operation.

[0159] According to the embodiment, between time t2 and time t4, the adjacent signal lines CGn±1 are supplied with a voltage VCGn±1 higher than the voltage VP-V. This makes it possible to prevent the voltage in the far-side region of the adjacent word lines WLn±1 from being excessively reduced. That is, even if coupling occurs in the period PV, the voltage in the far-side region of the adjacent word lines WLn±1 is maintained at, for example, approximately equal to or higher than the voltage VP-V. Therefore, in the verify operation, when the voltage VREAD is supplied to all the word lines WL of the selected block BLK, a delay in boosting the voltage of the adjacent word lines WLn±1 is prevented.

[0160] In addition, when the voltage VP-V is supplied to all non-selected signal lines during the period PV, the boost of adjacent word lines may be further delayed due to coupling during the verify operation. More specifically, the boost of adjacent word lines may be delayed due to coupling during the program operation, so that when the voltage of the selected word line is reduced from the voltage VREAD to the verify voltage during the verify operation, the voltage of the adjacent word lines may not reach the voltage VREAD. In this case, the voltage of the selected word line is reduced while the voltage of the adjacent word lines is increased, so that the voltages of the selected word line and the adjacent word lines change in the opposite directions. This makes the effect of the coupling between the selected word line and the adjacent word lines more pronounced, further delaying the boost of the adjacent word lines to the voltage VREAD and also delaying the convergence of the selected word line to the voltage VVRF. This further delays the verify operation, causing delays in the program loop operation and the write operation.

[0161] According to the embodiment, as described above, excessive voltage drop in the far side region of the adjacent word lines WLn±1 in the program operation is suppressed. As a result, when the voltage VREAD is supplied to all the word lines WL of the selected block BLK at time t5, all the word lines WL can be boosted at the same speed. As a result, when the voltage of the selected word line WLn is reduced from the voltage VREAD to the voltage VVRF, the voltage of the adjacent word lines WLn±1 is made equal to, for example, the voltage VREAD. That is, the boost of the voltage of the adjacent word lines WLn±1 is suppressed, and the change in the voltage of the selected word line WLn and the adjacent word lines WLn±1 in the opposite direction is suppressed. Therefore, the influence of coupling is suppressed from becoming significant in the verify operation, and the delay in boosting the adjacent word lines WLn±1 is suppressed, and the delay in the convergence of the selected word line WLn to the voltage VVRF can also be suppressed. Therefore, the delay in the verify operation is suppressed.

[0162] 2. Variations The above-described embodiment can be modified in various ways, and semiconductor memory devices according to modifications of the embodiment will be described below.

[0163] In the above embodiment, the voltages VCGn±1 are supplied to the signal lines CGn±1 between time t2 and time t4 in each program loop operation. However, this is not limiting, and the voltages VCGn±1 supplied to the signal lines CGn±1 may be configured to increase with an increase in the number of loops and an increase in the voltage of the selected word line WLn.

[0164] The configuration of the semiconductor memory device 1 according to the modification may be equivalent to the configuration of the semiconductor memory device 1 according to the embodiment. In the following description, the operation of the semiconductor memory device 1 according to the modification will be mainly described with respect to differences from the operation of the semiconductor memory device 1 according to the embodiment.

[0165] Each program loop operation using the semiconductor memory device 1 according to the modification can be similar to each program loop operation using the semiconductor memory device 1 according to the embodiment. For this reason, in the following, a description of the timing chart of the program loop operation will be omitted, and an increase in the voltages VPGM and VCGn±1 accompanying an increase in the number of loops will be described.

[0166] The operation of the semiconductor memory device 1 according to the modified example will be described with reference to FIG. 12. FIG. 12 is a table for explaining a write operation using the semiconductor memory device according to the modified example. FIG. 12 shows, as an example, a case in which 18 program loop operations are executed in a write operation. FIG. 12 also shows voltages VPGM and VCGn±1 during program loop operations for each number of loops.

[0167] When the number of loops is a value i (in the i-th program loop operation), the voltage VPGM is a voltage VP(i), where the value i is an integer equal to or greater than 1. Moreover, the voltage VP(i) is, for example, a voltage (VP(1)+(i-1)×dVP) obtained by adding the voltage VP(1) and the voltage obtained by multiplying the voltage dVP by a value (i-1).

[0168] In the modified example, the semiconductor memory device 1 divides the write operation into a plurality of sections SecW1 to SecW3 based on, for example, the number of loops and the voltage VPGM. In the following description, when the plurality of sections SecW1 to SecW3 are not distinguished from one another, each of the plurality of sections SecW1 to SecW3 is simply referred to as a section SecW.

[0169] Section SecW1 includes program loop operations when the loop number is 1 to 6. Section SecW2 includes program loop operations when the loop number is 7 to 12. Section SecW3 includes program loop operations when the loop number is 13 to 18.

[0170] In section SecW1, during the period PV, the voltage VCGn±1 supplied to adjacent signal lines CGn±1 is set to voltage VC(1). In section SecW2, during the period PV, the voltage VCGn±1 supplied to adjacent signal lines CGn±1 is set to voltage VC(2). Voltage VC(2) is a higher voltage than voltage VC(1) (VC(2)>VC(1)). In section SecW3, during the period PV, the voltage VCGn±1 supplied to adjacent signal lines CGn±1 is set to voltage VC(3). Voltage VC(3) is a higher voltage than voltage VC(2) (VC(3)>VC(2)).

[0171] That is, in each program loop operation, for example, when the voltage VPGM supplied to the selected word line WLn is equal to or greater than the voltage VP(1) and less than the voltage VP(7), the driver module 16 supplies the voltage VC(1) to the adjacent signal lines CGn±1. Also, in each program loop operation, for example, when the voltage VPGM supplied to the selected word line WLn is equal to or greater than the voltage VP(7) and less than the voltage VP(13), the driver module 16 supplies the voltage VC(2) to the adjacent signal lines CGn±1. Also, in each program loop operation, for example, when the voltage VPGM supplied to the selected word line WLn is equal to or greater than the voltage VP(13) and less than the voltage VP(18), the driver module 16 supplies the voltage VC(3) to the adjacent signal lines CGn±1.

[0172] In the following description, the voltages VCGn±1 in the j-th section SecW are referred to as voltages VC(j), where the value j is an integer of 1 or more.

[0173] The voltage VC(j) is, for example, a voltage (VC(1)+(j-1)×dVC) obtained by adding the voltage VC(1) and the voltage dVC multiplied by the value (j-1). That is, the semiconductor memory device 1 is configured to increase the voltage by a predetermined voltage each time the section SecW transitions to a different section SecW as the number of loops increases.

[0174] In the above-described modified example, the semiconductor memory device 1 divides the write operation into three sections SecW, but this is not limited to this. The semiconductor memory device 1 may divide the write operation into two, or four or more sections SecW. In the above-described modified example, the semiconductor memory device 1 makes the number of program loop operations included in the multiple sections SecW equal to each other. However, this is not limited to this, and the number of program loop operations executed in the multiple sections SecW may be different from each other.

[0175] Furthermore, the semiconductor memory device 1 may be configured to increase the voltage VCGn±1 every time the number of loops increases in a write operation, for example.

[0176] As described above, the semiconductor memory device 1 according to the modified example is configured to increase the voltage VCGn±1 supplied to the adjacent signal lines CGn±1 in response to an increase in the number of loops and the voltage VPGM. This prevents an excessive voltage drop in the far side region of the adjacent word lines WLn±1 due to an increase in the voltage VPGM supplied to the selected word line WLn.

[0177] That is, according to the modified example, the semiconductor memory device 1 is configured to increase the voltage VCGn±1 in accordance with an increase in the number of loops and the voltage VPGM. This prevents the voltage in the far side region of the adjacent word lines WLn±1 from falling below the voltage VP-V due to the increased voltage VPGM, which makes the effect of coupling in the period PV more pronounced. This configuration also improves the operating speed of the semiconductor memory device 1.

[0178] 3. Other Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0179] 1...semiconductor memory device, 2...memory controller, 3...memory system, 4...host device, 10...memory cell array, 11...input / output circuit, 12...logic control circuit, 13...address register, 14...command register, 15...sequencer, 16...driver module, 17...row decoder module, 18...sense amplifier module, 20...CPU, 21...built-in memory, 22...buffer memory, 23...NAND interface circuit, 24...host interface circuit, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...selection transistor, BL...bit line, WL...word line, SGS, SGD...selection gate line, member...SLT, SHE, contact...CC, CV.

Claims

1. a first memory cell and a second memory cell adjacent to each other and connected in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; A control circuit; Equipped with The control circuit includes: performing a plurality of program loop operations, each having a program operation and a verify operation after the program operation; In a first program loop operation that is included in the plurality of program loop operations and targets the first memory cell, during the program operation, supplying a first voltage lower than the first write voltage to the second word line while supplying a first write voltage to the first word line during a first period; during a second period following the first period, a second voltage less than the first voltage is supplied to the first word line, while a third voltage higher than the second voltage is supplied to the second word line; It is configured as follows: Semiconductor memory device.

2. The control circuit, in the first program loop operation, at the time of the verify operation, supplying a fourth voltage higher than the second voltage and the third voltage to the first word line and the second word line during a third period; during a fourth period following the third period, supplying the fourth voltage to the second word line while supplying a first verify voltage lower than the fourth voltage to the first word line; It is configured as follows:

2. The semiconductor memory device according to claim 1.

3. The control circuit, after the second period and before the third period, supplying the second voltage to the second word line while supplying the second voltage to the first word line; It is configured as follows:

3. The semiconductor memory device according to claim 2.

4. a third memory cell adjacent to the second memory cell and connected in series to the first memory cell via the second memory cell; a third word line connected to the third memory cell; Further equipped with The control circuit includes: supplying the second voltage to the third word line during the second period; It is configured as follows:

2. The semiconductor memory device according to claim 1.

5. the plurality of program loop operations further includes a second program loop operation that is executed after the first program loop operation and targets the first memory cell; The control circuit, in the second program loop operation, during the program operation, during a fifth period, supplying the first voltage to the second word line while supplying a second write voltage higher than the first write voltage to the first word line; during a sixth period after the fifth period, the second voltage is supplied to the first word line while a fifth voltage higher than the second voltage is supplied to the second word line; 2. The semiconductor memory device according to claim 1.

6. The control circuit includes: supplying the third voltage as the fifth voltage to the second word line when the second write voltage is less than a sixth voltage; When the second write voltage is equal to or higher than the sixth voltage, the fifth voltage is set to be higher than the third voltage. It is configured as follows:

6. The semiconductor memory device according to claim 5.

7. The control circuit includes: The first program loop operation and the second program loop operation are executed consecutively. It is configured as follows: the fifth voltage is higher than the third voltage; 6. The semiconductor memory device according to claim 5.

8. the second word line includes a first region and a second region having a wiring length between the second word line and the control circuit longer than the first region; In the second period, the voltage of the second region is lower than the voltage of the first region.

4. The semiconductor memory device according to claim 3.

9. In the second period, the voltage of the second region is equal to or greater than the second voltage; The voltage of the first region is higher than the voltage of the second region.

9. The semiconductor memory device according to claim 8.

10. the third voltage is less than the first voltage; 2. The semiconductor memory device according to claim 1.

11. the third voltage is less than the fourth voltage; 3. The semiconductor memory device according to claim 2.

12. The control circuit includes a voltage generating circuit, the voltage generating circuit outputs the first write voltage, the first voltage, the second voltage, and the third voltage.

2. The semiconductor memory device according to claim 1.

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