Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an operation of a parasitic element including a field plate as constituent element.SOLUTION: A semiconductor device includes: a base body 1 of a first conductivity-type; a first well region 2 of a second conductivity-type, which is provided in the base body 1 and in which a high-side circuit 102 is formed; a first voltage blocking region 8 of the second conductivity-type, which is provided into a circular state around the first well region 2 and has a lower impurity concentration than the first well region 2; a second voltage blocking region 3 of the first conductivity-type, which is provided into a circular state in contact with the first voltage blocking region 8 on an outer circumferential side of the first voltage blocking region 8; a first level shift element 20a provided to encompass a part of the first voltage blocking region 8; a first isolation region 6a of the first conductivity-type provided to surround a circumference of the first level shift element 20a; and a field plate (10, 11, 12) provided over the first voltage blocking region 8 and the first isolation region 6a with insulating films 71, 72 interposed, the field plate having a first distance d1 from the first isolation region 6a greater than a second distance d2 from the first voltage blocking region 8.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent documents 1 and 2 disclose a high voltage integrated circuit (HVIC) that integrates a high voltage N-type MOSFET (HVNMOS) with a high voltage junction termination (HVJT) and disposes the HVNMOS in a p - This paper discloses a structure in which the HVJT is electrically isolated by surrounding the HVJT with a slit region (also called a "split RESURF structure"). - The slit region is the channel, and p - A parasitic MOS transistor (parasitic MOS) is formed with the field plate directly above the mold slit region as its gate.

[0003] Patent Document 3 discloses a configuration in which the field plate is separated on the HVJT and on the HVNMOS to prevent the formation of a parasitic MOS. Patent Document 4 discloses a configuration in which the start point of the field plate is connected to the drain potential of the HVNMOS to suppress the operation of the parasitic MOS.

[0004] Patent Document 5 states, p. - The patent document 6 discloses a structure that is resistant to surface charging by tightly covering the slit region with two layers of field plates. - Patent Document 7 discloses a configuration in which the formation of an inversion layer of a parasitic MOS is suppressed by forming a dense p-type layer in a part of a type slit region. Patent Document 7 discloses a configuration in which the operation of a parasitic MOS is suppressed by connecting the start point of a field plate to a VS potential. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6798377 [Patent Document 2] Patent No. 3917211 [Patent Document 3] Patent No. 6009341 [Patent Document 4] Patent No. 6134219 [Patent Document 5] Patent No. 6414861 [Patent Document 6] JP 2021-114527 A [Patent Document 7] Patent No. 5321768 Summary of the Invention [Problem to be solved by the invention]

[0006] In the conventional split RESURF structure, when the parasitic MOS operates, a leakage current flows between the HVJT and the HVNMOS, which interferes with the normal operation of the HVIC. There is room for improvement in the method of suppressing the operation of the parasitic MOS.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing the operation of a parasitic element having a field plate as a component. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device including: a base of a first conductivity type; a first well region of a second conductivity type provided on the base in which a high-side circuit is formed; a first voltage-withstanding region of the second conductivity type provided in an annular shape around the first well region and having a lower impurity concentration than the first well region; a second voltage-withstanding region of the first conductivity type provided in an annular shape on the outer periphery of the first voltage-withstanding region and in contact with the first voltage-withstanding region; a first level shift element provided to include a part of the first voltage-withstanding region; a first isolation region of the first conductivity type provided to surround the periphery of the first level shift element; and a field plate provided above the first voltage-withstanding region and the first isolation region via an insulating film, the first distance between the field plate and the first isolation region being greater than the second distance between the field plate and the first voltage-withstanding region. Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device capable of suppressing the operation of a parasitic element having a field plate as a component. [Brief description of the drawings]

[0010] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA′ in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line BB' in FIG. [Diagram 5] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line BB' in FIG. 5. [Figure 7] FIG. 13 is a plan view of a semiconductor device according to a third embodiment. [Figure 8] FIG. 13 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 13 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 10] FIG. 13 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 11] 11 is a cross-sectional view taken along line BB' in FIG. 10. [Figure 12] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth embodiment. [Figure 14] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the first to ninth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Moreover, the first to ninth embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0012] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field effect transistor (FET) or static induction transistor (SIT), the emitter region of an insulated gate bipolar transistor (IGBT), etc. In addition, in a diode, a static induction (SI) thyristor, or a gate turn-off (GTO) thyristor, the anode region serves as the carrier supply region. In addition, the term "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT, etc. In a diode, a SI thyristor, or a GTO thyristor, the cathode region functions as the carrier receiving region.

[0013] In addition, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0014] In addition, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Furthermore, "+" and "-" attached to "n" and "p" respectively mean that the semiconductor region has a relatively high or low impurity concentration compared to the semiconductor region without "+" and "-". However, even if the same "n" and "n" are attached to the semiconductor region, it does not mean that the impurity concentration of each semiconductor region is strictly the same. Furthermore, in the following description, the members and regions to which the limitations of "first conductivity type" and "second conductivity type" are added mean members and regions made of semiconductor materials even if there is no particular explicit limitation.

[0015] (First embodiment) <Circuits of semiconductor device> As an example of a semiconductor device according to the first embodiment, a high voltage integrated circuit (HVIC) 100 is shown in Fig. 1. The HVIC 100 drives a power conversion unit 200, which is, for example, one phase of a bridge circuit for power conversion, as a drive target. The power conversion unit 200 configures a half-bridge circuit by connecting a high potential side switching element T3 and a low potential side switching element T4 in series. In Fig. 1, IGBTs are shown as an example of the high potential side switching element T3 and the low potential side switching element T4, but other power switching elements such as metal oxide semiconductor field effect transistors (MOSFETs) may also be used.

[0016] A high potential HV potential is connected to the collector of the high potential side switching element T3. A low potential ground potential (GND potential) is connected to the emitter of the low potential side switching element T4. A VS potential on the negative side of a high potential side power supply (high potential side power supply) 104 is connected to a connection point 105 between the emitter of the high potential side switching element T3 and the collector of the low potential side switching element T4. Furthermore, a load (not shown) such as a motor is connected to the connection point 105.

[0017] The HVIC 100 applies a drive signal to the gate of the high potential side switching element T3, which drives the gate of the high potential side switching element T3 by turning it on and off in response to an input signal IN from an external microcomputer or the like. The HVIC 100 includes a low potential side circuit (low side circuit) 101 and a high potential side circuit (high side circuit) 102. The low side circuit 101 is connected to a VCC potential on the positive side of a low potential side power supply (low potential side power supply) 103 and a GND potential on the negative side of the low potential side power supply 103. Furthermore, the low side circuit 101 is connected to the gates of level shift elements (level shifters) T1 and T2.

[0018] The low-side circuit 101 operates with a GND potential as a reference potential and a VCC potential higher than the GND potential as a power supply potential. The low-side circuit 101 generates an on / off signal with the GND potential as a reference in response to an input signal IN from an external microcomputer or the like, and outputs the signal to the gates of the level shift elements T1 and T2.

[0019] The level shift elements T1 and T2 transmit signals between the low-side circuit 101 and the high-side circuit 102. The level shift elements T1 and T2 convert an on / off signal based on the GND potential from the low-side circuit 101 into an on / off signal based on the VS potential, and output the converted on / off signal to the high-side circuit 102. The level shift elements T1 and T2 are composed of, for example, a high-voltage n-channel MOSFET.

[0020] The source of the level shift element T1 is connected to the GND potential. The drain of the level shift element T1 is connected to the high side circuit 102 and one end of the level shift resistor R1. The other end of the level shift resistor R1 is connected to the VB potential on the positive side of the high potential power supply 104. The drain of the level shift element T1 and one end of the level shift resistor R1 are connected to the cathode of the diode D1. The anode of the diode D1 is connected to the VS potential on the negative side of the high potential power supply 104 and the high side circuit 102. The diode D1 has a function of preventing an excessive drop in the drain potential (Dr potential) of the level shift element T1.

[0021] The source of the level shift element T2 is connected to the GND potential. The drain of the level shift element T2 is connected to the high side circuit 102 and one end of the level shift resistor R2. The other end of the level shift resistor R2 is connected to the VB potential on the positive side of the high potential power supply 104. The drain of the level shift element T2 and one end of the level shift resistor R2 are connected to the cathode of the diode D2. The anode of the diode D2 is connected to the VS potential on the negative side of the high potential power supply 104 and the high side circuit 102. The diode D2 has a function of preventing an excessive drop in the drain potential (Dr potential) of the level shift element T2.

[0022] The cathode of a high-voltage diode D0 called a high-voltage junction termination (HVJT) is connected to the VB potential on the positive electrode side of the high-voltage power supply 104. The anode of the diode D0 is connected to the GND potential.

[0023] The high-side circuit 102 operates with the VS potential as a reference potential and a VB potential higher than the VS potential as a power supply potential. In response to on / off signals from the level shift elements T1 and T2, the high-side circuit 102 outputs a drive signal based on the VS potential to the gate of the high-potential side switching element T3, thereby driving the gate of the high-potential side switching element T3. The high-side circuit 102 includes, for example, a CMOS circuit of an n-channel MOSFET and a p-channel MOSFET in the output stage.

[0024] The VB potential is the highest potential applied to the HVIC 100, and in normal conditions not affected by noise, it is kept about 15V higher than the VS potential. The VS potential repeatedly rises and falls between the HV potential on the high potential side (e.g., about 400V to 600V) and the GND potential on the low potential side as the high potential side switching element T3 and the low potential side switching element T4 are complementarily turned on and off, fluctuating between 0V and several hundred volts. Note that the VS potential may also become a negative potential.

[0025] <Structure of Semiconductor Device> FIG. 2 shows a planar layout of a semiconductor device according to the first embodiment, which corresponds to the HVIC 100 shown in FIG. - The semiconductor device includes a substrate (semiconductor chip) 1 of a semiconductor substrate (type). The substrate 1 is, for example, a silicon (Si) substrate. The substrate 1 may be a semiconductor substrate of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), diamond, or the like. The substrate 1 may also be a p - A p-type semiconductor substrate and a p-type - The epitaxial layer may be a silicon nitride layer.

[0026] The base 1 may be fixed at a GND potential. A well region 2 of a second conductivity type (n-type) is provided on the upper part of the base 1. The well region 2 has a substantially rectangular planar pattern. A VB potential is applied to the well region 2. A high side circuit (high side circuit region) 102 is formed in the well region 2. Various elements included in the high side circuit 102 are not shown in FIG. 2.

[0027] A n-type semiconductor layer having a lower impurity concentration than the well region 2 is disposed in contact with the well region 2 so as to surround the well region 2. - The mold is provided with a pressure-resistant region 8. The pressure-resistant region 8 is annular and has a planar pattern with a substantially rectangular outer shape.

[0028] A p-type voltage-withstanding region 3 is provided in contact with the voltage-withstanding region 8 so as to surround the outer periphery of the voltage-withstanding region 8. The voltage-withstanding region 3 is annular and has a planar pattern with a substantially rectangular outer shape. A GND potential is applied to the voltage-withstanding region 3. The outer periphery of the voltage-withstanding region 3 is surrounded by a base 1.

[0029] p-type breakdown voltage region 3 and n -A high voltage junction termination (HVJT) (3,8) is formed by a pn junction in the high voltage region 8 of the diode. The HVJT (3,8) corresponds to the high voltage diode D0 shown in FIG. 1. The HVJT (3,8) is annular and has a planar pattern with a substantially rectangular outer shape. The HVJT (3,8) electrically separates a high side circuit 102 on the inner side of the HVJT (3,8) from a low side circuit (low side circuit region) 101 formed on the substrate 1 on the outer side of the HVJT (3,8). The HVJT (3,8) allows normal operation even when the potential of the high side circuit 102 is several hundred volts higher than the potential of the low side circuit 101.

[0030] 2, the low-side circuit 101 is provided below the high-side circuit 102 via an HVJT (3, 8). In FIG. 2, various elements constituting the low-side circuit 101 are omitted from illustration.

[0031] As shown in Fig. 2, a level shift element 20a is integrally formed with a portion of the HVJT (3, 8). The level shift element 20a is provided including a portion of the voltage-resistant region 8. The level shift element 20a corresponds to the level shift element T1 shown in Fig. 1. Note that in Fig. 2, a level shift element corresponding to the level shift element T2 shown in Fig. 1 is omitted from illustration.

[0032] The level shift element 20a is composed of a high-voltage n-channel MOSFET (HVNMOS). + A carrier supply region (source region) 21a, a gate electrode 22a and an n + The level shift element 20a has a carrier receiving region (drain region) 23a. The source region 21a, the gate electrode 22a, and the drain region 23a have linear planar patterns extending parallel to each other. A part of the voltage withstanding region 8 sandwiched between the source region 21a and the drain region 23a constitutes the drift region of the level shift element 20a.

[0033] The level shift element 20a is surrounded by p -A slit region 6a is provided in the semiconductor device according to the first embodiment. The isolation region 6a has a substantially U-shaped planar pattern with a bottom on the high-side circuit 102 side and an opening on the low-side circuit 101 side. Each end of a pair of straight line portions connected to the bottom of the substantially U-shape of the isolation region 6a contacts the voltage-withstand region 3. That is, the semiconductor device according to the first embodiment has a structure (split RESURF structure) in which the level shift element 20a is electrically isolated from the HVJT (3, 8) by surrounding it with the isolation region 6a.

[0034] Field plates (10, 11, 12) are provided above the HVJT (3, 8) and the level shift element 20a. The field plates (10, 11, 12) have the function of making the high voltage applied inside the HVIC uniformly distributed with a small current. In the semiconductor device according to the first embodiment, the field plates (10, 11, 12) have a resistive field plate (RFP) structure (resistive element).

[0035] The field plates (10, 11, 12) have a spiral planar pattern. The width of the field plates (10, 11, 12) in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend is, for example, about 1 μm. The spacing between adjacent spiral lines of the field plates (10, 11, 12) in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend is, for example, about 1 μm.

[0036] 1 shows an example in which the field plates (10, 11, 12) are wound about five times, but there is no particular limitation on the number of spiral wires (turns) of the field plates (10, 11, 12). The number of turns of the field plates (10, 11, 12) can be set appropriately depending on the width of the voltage-resistant region 8 in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend, etc.

[0037] An inner end 10a of the field plate (10, 11, 12) is connected to a first potential on the high potential side, for example, a VB potential. The first potential may be a VS potential or may be a drain potential of the level shift element 20a. The drain potential of the level shift element 20a is a potential between the VB potential and the VS potential.

[0038] The outer peripheral end 10b of the field plate (10, 11, 12) is connected to a second potential lower than the first potential, for example, a ground potential (GND potential). The second potential may be a potential different from the GND potential.

[0039] FIG. 3 shows a cross section taken along line AA′ passing through the level shift element 20a in FIG. - An n-type well region 2 is provided on an upper portion of a mold base 1. The well region 2 is composed of a diffusion layer into which n-type impurities are ion-implanted. A high-side circuit 102 is formed in the well region 2.

[0040] The upper part of the substrate 1 is in contact with the well region 2. - A p-type breakdown voltage region 8 is provided on the substrate 1. The breakdown voltage region 8 is made of a diffusion layer into which n-type impurities are ion-implanted. The depth of the breakdown voltage region 8 is shallower than the depth of the well region 2. A p-type breakdown voltage region 8 is provided on the substrate 1. The breakdown voltage region 8 is made of a diffusion layer into which n-type impurities are ion-implanted. The depth of the breakdown voltage region 8 is shallower than the depth of the well region 2. - The isolation region 6a is formed of a diffusion layer into which p-type impurities are ion-implanted. The depth of the isolation region 6a is deeper than the depth of the voltage-resistant region 8.

[0041] As shown in FIG. 3, the level shift element 20a is - The n-type well region 2 is separated from the n-type well region 2 by a p-type isolation region 6a. - A part of the voltage-resistant region 8 separated from the n-type well region 2 by the n-type isolation region 6a constitutes the drift region of the level shift element 20a. +An n-type drain region 23a is provided. The drain region 23a is composed of a diffusion layer into which n-type impurities are ion-implanted. An insulating film 71 and an insulating film 72 are provided on the upper surface side of the drain region 23a. A drain electrode 32 is connected to the drain region 23a through a via 32a made of a metal or the like provided in an opening (contact hole) of the insulating films 71 and 72. The drain electrode 32 may be made of a metal mainly composed of, for example, aluminum (Al) or copper (Cu).

[0042] A silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film of these can be used as the insulating film 71. The insulating film 71 may be an insulating film formed by a chemical vapor deposition (CVD) method using a gas of an organosilicon compound such as tetraethoxysilane (TEOS), or the like.

[0043] The insulating film 72 may be a silicon oxide film (SiO2 film) that does not contain impurities and is called an "NSG film", a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), etc. Furthermore, a single layer film of a silicon oxide film doped with phosphorus and boron (BPSG film) or a silicon nitride film (Si3N4 film), or a composite film in which a plurality of types of these are selected and combined, may also be used as the insulating film 72.

[0044] A p-type breakdown voltage region 3 is provided on the upper part of the substrate 1, in contact with the breakdown voltage region 8 on the opposite side of the well region 2. The breakdown voltage region 3 is composed of a diffusion layer into which p-type impurities are ion-implanted. A part of the breakdown voltage region 3 in contact with the breakdown voltage region 8 constituting the drift region of the level shift element 20a functions as a base region of the level shift element 20a.

[0045] The upper portion of the voltage-resistant region 3, which functions as the base region of the level shift element 20a, is provided with n +A p-type source region 21a is provided. The source region 21a is made of a diffusion layer into which n-type impurities are ion-implanted. A p-type impurity having a higher impurity concentration than the voltage-resistant region 3 is provided in contact with the source region 21a above the voltage-resistant region 3 which functions as a base region of the level shift element 20a. + A p-type contact region 4 is provided on the semiconductor substrate 1. The contact region 4 is made of a diffusion layer into which p-type impurities are ion-implanted.

[0046] A source electrode 31 is connected to the source region 21a and the contact region 4 through a via 31a made of a metal or the like provided in an opening (contact hole) of the insulating film 71 and the insulating film 72. The source electrode 31 may be made of a metal containing, for example, aluminum (Al), copper (Cu), or the like as a main component.

[0047] A gate electrode 22a is provided on the upper surface side of the voltage-resistant region 3 sandwiched between the source region 21a and the voltage-resistant region 8 via a gate insulating film 25. As the gate insulating film 25, any one of a single layer film of a silicon oxide film (SiO2 film), a silicon oxynitride film (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, or a composite film in which a plurality of these films are laminated, can be used. As the material of the gate electrode 22a, for example, a polysilicon layer (doped polysilicon layer) to which p-type impurities or n-type impurities are added at a high impurity concentration, or a high-melting point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0048] 4 shows a cross section taken along line BB', which is perpendicular to line AA' in Fig. 2 and passes through part of one of the spiral lines of level shift element 20a and field plate (10, 11, 12). As shown in Fig. 4, field plate (10, 11, 12) has a first layer (lower layer) 10 and second layers (upper layers) 11, 12 provided above (on the upper side of) first layer 10.

[0049] As shown in FIG. 2, the first layer 10 constitutes most of the field plate (10, 11, 12) and is provided in a portion excluding the portion passing above the isolation region 6a. As shown in FIGS. 3 and 4, the first layer 10 is provided on the upper surface side of the insulating film 71. As shown in FIG. 4, the first layer 10 is provided above the voltage-resistant region 8. The first layer 10 crosses above the level shift element 20a. The first layer 10 is divided above the isolation region 6a that sandwiches the level shift element 20a. The divided distance (spacing) d3 of the first layer 10 is larger than the width w1 of the isolation region 6a. The first layer 10 is not provided at least above the isolation region 6a.

[0050] The first layer 10 is made of a resistive thin film such as high-resistance polysilicon. The polysilicon constituting the first layer 10 contains p-type impurities or n-type impurities at a concentration of, for example, 1×10 17 cm -3 That's it, 1×10 20 cm -3 The polysilicon constituting the first layer 10 has a sheet resistance of, for example, about 2 kΩ / sq. Note that the first layer 10 may be made of a metal film containing aluminum (Al), copper (Cu), or the like as a main component, instead of a resistive thin film.

[0051] As shown in Fig. 2, the second layers 11 and 12 are selectively (locally) provided above the separation region 6a in each spiral line of the field plate (10, 11, 12). Fig. 2 illustrates a case in which the width of the second layers 11 and 12 in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend is substantially the same as the width of the first layer 10. The width of the second layers 11 and 12 may be wider than the width of the first layer 10, or narrower than the width of the first layer 10.

[0052] As shown in FIG. 4, the second layers 11, 12 are provided on the upper surface side of the insulating film 72. The second layers 11, 12 may be provided on the upper surface side of an insulating film (not shown) that is higher than the insulating film 72. The second layers 11, 12 are provided at least above the separation region 6a. FIG. 4 illustrates a case in which the thickness of the second layers 11, 12 is approximately the same as the thickness of the first layer 10. The thickness of the second layers 11, 12 may be thicker than the thickness of the first layer 10, or may be thinner than the thickness of the first layer 10.

[0053] Although not shown, an insulating film may be provided on the upper surface side of the second layers 11 and 12 so as to cover the second layers 11 and 12. This insulating film may be made of the same material as the material forming the insulating film 72 described above. Furthermore, this insulating film may be formed so as to cover the upper surface side of the insulating film 72.

[0054] The second layers 11 and 12 are made of a metal mainly composed of, for example, aluminum (Al) or copper (Cu). The second layers 11 and 12 may be made of the same material as the source electrode 31 and the drain electrode 32, and in that case, they can be formed in the same process as the process of forming the source electrode 31 and the drain electrode 32. The second layers 11 and 12 may be made of a material different from the source electrode 31 and the drain electrode 32. The second layers 11 and 12 may be made of polysilicon like the first layer 10. The second layers 11 and 12 may be made of the same material as the first layer 10, or may be made of a material different from the first layer 10.

[0055] As shown in Fig. 4, one end and the other end of the second layer 11 are provided so as to overlap the divided end of the first layer 10. One end and the other end of the second layer 11 are electrically connected to the divided first layer 10 through vias 11a and 11b made of metal or the like provided in openings (contact holes) of the insulating film 72. One end and the other end of the second layer 12 are electrically connected to the divided first layer 10 through vias 12a and 12b made of metal or the like provided in openings (contact holes) of the insulating film 72. That is, the first layer 10 and the second layers 11 and 12 are connected in series.

[0056] 4, the distance d1 between the second layers 11, 12 and the isolation region 6a corresponds to the sum of the thicknesses of the insulating films 71 and 72. The distance d2 between the first layer 10 and the voltage withstanding region 8 corresponds to the thickness of the insulating film 71. Thus, the distance d1 between the second layers 11, 12 and the isolation region 6a is greater than the distance d2 between the first layer 10 and the voltage withstanding region 8.

[0057] Here, as shown in Figure 4, p - A parasitic n-type MOSFET is configured in which the isolation region 6a serves as a channel (channel formation region), the voltage-withstanding region 8 constituting the drift region of the level shift element 20a sandwiched between the isolation regions 6a serves as a source, the voltage-withstanding region 8 located on the opposite side to the voltage-withstanding region 8 that serves as the source of the isolation region 6a serves as a drain, and the portion of the field plate (10, 11, 12) located directly above the isolation region 6a serves as a gate.

[0058] According to the semiconductor device of the first embodiment, the distance d1 between the second layers 11, 12 and the isolation region 6a is made larger than the distance d2 between the first layer 10 and the withstand voltage region 8. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET compared to the case where, for example, a field plate with a constant distance between the isolation region 6a and the withstand voltage region 8 is used, so that the operation of the parasitic n-type MOSFET can be suppressed. For example, this is effective even in cases where the voltage between the field plate (10, 11, 12) and the isolation region 6a (the gate voltage of the parasitic n-type MOSFET) is momentarily biased by noise. In addition, the larger the distance d1 between the second layers 11, 12 and the isolation region 6a, the higher the gate threshold voltage of the parasitic MOS can be, and the greater the effect of suppressing the operation of the parasitic MOS can be.

[0059] Furthermore, as shown in FIG. 1, in a plan view, the field plates (10, 11, 12) can cover the same area as when a field plate is used in which the distance between the isolation region 6a and the voltage-withstand region 8 is constant, and therefore resistance to surface charging can be maintained.

[0060] Furthermore, even when the first layer 10 is made of polysilicon and the second layers 11, 12 are made of metal, the second layers 11, 12 are provided locally only above the region including the isolation region 6a, so that the current consumption of the field plates (10, 11, 12) can be kept small. Therefore, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plates (10, 11, 12), and the operation of the parasitic n-type MOSFET can be suppressed.

[0061] Second embodiment Fig. 5 is a plan view of the semiconductor device according to the second embodiment, and Fig. 6 is a cross-sectional view taken along line BB' in Fig. 5. As shown in Fig. 5 and Fig. 6, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a second layer 11 of the field plate (10, 11) provided above the HVJT (3, 8) and the level shift element 20a is provided so as to cross above the isolation region 6a and the level shift element 20a.

[0062] 5 and 6, the field plate (10, 11) has a first layer 10 and a second layer 11 provided above the first layer 10. As shown in Fig. 6, the first layer 10 is divided at a position above the isolation region 6a and above the voltage-withstanding region 8 that is sandwiched between the isolation regions 6a and constitutes the drift region of the level shift element 20a. The first layer 10 is not provided above the isolation region 6a or above the voltage-withstanding region 8 that constitutes the drift region of the level shift element 20a.

[0063] The second layer 11 is selectively (locally) provided from above the isolation region 6a to above the voltage-resistant region 8 constituting the drift region of the level shift element 20a. One end and the other end of the second layer 11 are electrically connected to the first layer 10, which is separated from each other, through vias 11a and 11b made of a metal or the like provided in openings (contact holes) of the insulating film 72.

[0064] A distance d1 between the isolation region 6a and the level shift element 20a and the second layer 11 is larger than a distance d2 between the voltage-withstanding region 8 other than the level shift element 20a and the first layer 10. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0065] In the semiconductor device according to the second embodiment, the distance d1 between the second layer 11 and the isolation region 6a is made larger than the distance d2 between the first layer 10 and the voltage-withstanding region 8 other than the level shift element 20a. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11, 12), as compared to the case where a field plate having a constant distance between the isolation region 6a and the voltage-withstanding region 8 is used.

[0066] Furthermore, when the first layer 10 of the field plate (10, 11, 12) is made of polysilicon, the voltage of the first layer 10 gradually drops from the high potential side to the low potential side. In contrast, by making the second layer 11 of metal and providing the second layer 11 so as to cross above the isolation region 6a and the level shift element 20a, the potential of the field plate (10, 11, 12) in the portion where the second layer 11 is provided is kept at the same potential, so that the potential can be kept more uniform over the entire level shift element 20a in the direction in which the second layer 11 crosses the level shift element 20a.

[0067] Third embodiment The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that a plurality (two) level shift elements 20a, 20b are integrally formed in a part of the HVJT (3,8) as shown in Fig. 7. The level shift elements 20a, 20b are provided adjacent to each other on one side of a rectangle formed by the planar pattern of the HVJT (3,8). The arrangement positions of the level shift elements 20a, 20b are not limited thereto. For example, the level shift elements 20a, 20b may be provided on opposing sides of the rectangle formed by the planar pattern of the HVJT (3,8).

[0068] The level shift element 20b has a similar configuration to the level shift element 20a. + The source region 21b, the gate electrode 22b and the n + The level shift element 20b has a drain region 23b. The source region 21b, the gate electrode 22b, and the drain region 23b have linear planar patterns extending parallel to each other. A part of the voltage-withstanding region 8 sandwiched between the source region 21b and the drain region 23b constitutes the drift region of the level shift element 20b.

[0069] The level shift element 20b is surrounded by p - A type isolation region 6b is provided. The isolation region 6b electrically isolates the level shift element 20b from the well region 2.

[0070] Field plates (10, 11, 12) are provided above the HVJT (3, 8) and the level shift elements 20a, 20b. The field plates (10, 11, 12) have a first layer 10 and second layers 11, 12 above the first layer 10. The second layer 11 is provided so as to cross above the isolation region 6a and the level shift element 20a. The second layer 12 is provided so as to cross above the isolation region 6b and the level shift element 20b. Other configurations of the semiconductor device according to the third embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0071] According to the semiconductor device of the third embodiment, the distance between the second layer 11 and the isolation region 6a and the distance between the second layer 12 and the isolation region 6b are made larger than the distance between the first layer 10 and the voltage-withstanding region 8 other than the level shift elements 20a, 20b. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11, 12), compared to the case where a field plate having a constant distance between the isolation regions 6a, 6b and the voltage-withstanding region 8 is used.

[0072] Furthermore, when the first layer 10 of the field plate (10, 11, 12) is made of polysilicon, the voltage of the first layer 10 gradually drops from the high potential side to the low potential side. In contrast, by making the second layers 11, 12 of metal and providing the second layers 11, 12 so as to cross the isolation regions 6a, 6b and the level shift elements 20a, 20b, respectively, the potential of the field plate (10, 11, 12) in the portion where the second layers 11, 12 are provided is kept at the same potential, so that the potential can be kept more uniform throughout each of the level shift elements 20a, 20b in the direction in which the second layers 11, 12 cross the level shift elements 20a, 20b.

[0073] (Fourth embodiment) The semiconductor device according to the fourth embodiment is common to the semiconductor device according to the third embodiment shown in Fig. 7 in that a plurality of (two) level shift elements 20a, 20b are integrally formed in a portion of the HVJT (3, 8) as shown in Fig. 8. However, the semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment shown in Fig. 7 in that a second layer 11 of a field plate (10, 11) is provided so as to continuously traverse above the plurality of level shift elements 20a, 20b and the plurality of isolation regions 6a, 6b surrounding the plurality of level shift elements 20a, 20b, respectively, as shown in Fig. 8.

[0074] Field plates (10, 11) are provided above the HVJT (3, 8) and the level shift elements 20a, 20b. The field plates (10, 11) have a first layer 10 and a second layer 11 above the first layer 10. The second layer 11 is provided to cross above the isolation regions 6a, 6b and the level shift elements 20a, 20b. Other configurations of the semiconductor device according to the fourth embodiment are similar to those of the semiconductor device according to the third embodiment, and therefore repeated explanations will be omitted.

[0075] In the semiconductor device according to the fourth embodiment, the distance between the second layer 11 and the isolation regions 6a, 6b is made larger than the distance between the first layer 10 and the voltage-withstanding region 8 other than the level shift elements 20a, 20b. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11), as compared to the case where a field plate having a constant distance between the isolation regions 6a, 6b and the voltage-withstanding region 8 is used.

[0076] Furthermore, when the first layer 10 of the field plate (10, 11) is made of polysilicon, the voltage of the first layer 10 gradually drops from the high potential side to the low potential side. In contrast, by making the second layer 11 of metal and providing the second layer 11 so as to continuously cross above the isolation regions 6a, 6b and the level shift elements 20a, 20b, the level shift elements 20a, 20b can be kept at approximately the same potential in the direction in which the second layer 11 crosses the level shift elements 20a, 20b.

[0077] Fifth embodiment As shown in Fig. 9, the semiconductor device according to the fifth embodiment has a plurality of level shift elements 20a, 20b and a plurality of isolation regions 6a, 6b surrounding the plurality of level shift elements 20a, 20b, which is common to the semiconductor device according to the fourth embodiment shown in Fig. 8. However, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the fourth embodiment shown in Fig. 8 in that the second layers 11, 12, 13 of the field plates (10, 11, 12, 13) are provided locally above the plurality of isolation regions 6a, 6b without crossing the plurality of level shift elements 20a, 20b, as shown in Fig. 9.

[0078] Field plates (10, 11, 12, 13) are provided above the HVJT (3, 8) and the level shift elements 20a, 20b. The field plates (10, 11, 12, 13) have a first layer 10 and second layers 11, 12, 13 above the first layer 10. The second layer 11 is provided to cross one of a pair of straight line portions formed by the planar pattern of the isolation region 6a. The second layer 12 is provided to cross the other of the pair of straight line portions formed by the planar pattern of the isolation region 6a, the voltage-resistant region 8 between the isolation region 6a and the isolation region 6b, and one of the pair of straight line portions formed by the planar pattern of the isolation region 6b. The second layer 13 is provided to cross the other of the pair of straight line portions formed by the planar pattern of the isolation region 6b. Other configurations of the semiconductor device according to the fifth embodiment are similar to those of the semiconductor device according to the fourth embodiment, so that repeated explanations will be omitted.

[0079] In the semiconductor device according to the fifth embodiment, the distance between the second layers 11, 12, 13 and the isolation regions 6a, 6b is made larger than the distance between the first layer 10 and the voltage-withstanding region 8 other than the level shift elements 20a, 20b. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11, 12, 13), as compared to the case where a field plate having a constant distance between the isolation regions 6a, 6b and the voltage-withstanding region 8 is used.

[0080] Sixth embodiment Fig. 10 is a plan view of a semiconductor device according to a sixth embodiment. The cross section taken along line AA' in Fig. 10 is similar to Fig. 3, and the cross section taken along line BB' in Fig. 10 is shown in Fig. 11. As shown in Figs. 3, 10 and 11, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment in that the field plates (10, 11) have a capacitive field plate structure (also called a "multiple floating field plate (MFFP) structure").

[0081] As shown in Fig. 11, the field plate (10, 11) has a first layer 10 and a second layer 11 above the first layer 10. The second layer 11 has multiple annular and concentric planar patterns as shown in Fig. 10. The first layer 10 is hidden below the second layer 11 in Fig. 10, but has multiple approximately annular and approximately concentric planar patterns along the second layer 11.

[0082] As shown in FIG. 11, the first layer 10 is provided above the voltage-resistant region 8, but is selectively (locally) separated only above the isolation region 6a. The second layer 11 is provided above the voltage-resistant region 8 and the isolation region 6a. The potentials of the first layer 10 and the second layer 11 are both floating potentials. No via is provided to connect the first layer 10 and the second layer 11 to each other, and the first layer 10 and the second layer 11 are electrically isolated from each other. The first layer 10 and the second layer 11 are capacitively coupled via the insulating film 72.

[0083] The first layer 10 and the second layer 11 are made of, for example, polysilicon or metal. The first layer 10 and the second layer 11 may be made of the same material as each other, or may be made of different materials. Other configurations of the semiconductor device according to the sixth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0084] According to the semiconductor device of the sixth embodiment, when the field plate (10, 11) has a capacitive field plate structure, the distance d1 between the isolation region 6a and the second layer 11 is made larger than the distance d2 between the voltage withstand region 8 and the first layer 10. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plate (10, 11), as compared to the case where a field plate having a constant distance between the isolation region 6a and the voltage withstand region 8 is used.

[0085] Seventh embodiment As shown in FIG. 12, the semiconductor device of the seventh embodiment differs from the semiconductor device of the first embodiment shown in FIG. 4 in that the thickness d4 of the insulating film 71 located on the upper surface of the isolation region 6a is thicker than the thickness d5 of the insulating film 71 located on the upper surface of the voltage-resistant region 8.

[0086] A field plate 10 is provided on the upper surface side of the insulating film 71, with a serpentine cross-sectional pattern according to the thicknesses d4, d5 of the insulating film 71. The field plate 10 is composed of a single layer. The field plate 10 is composed of, for example, polysilicon or metal. The field plate 10 may be, for example, a resistive field plate structure having a spiral planar pattern, or a capacitive field plate structure having a concentric planar pattern. Other configurations of the semiconductor device according to the seventh embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0087] In the semiconductor device according to the seventh embodiment, the distance d4 between the isolation region 6a and the field plate 10 is made larger than the distance d5 between the voltage withstand region 8 and the field plate 10. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plate 10, as compared to the case where a field plate with a constant distance between the isolation region 6a and the voltage withstand region 8 is used.

[0088] Eighth embodiment As shown in FIG. 13, the semiconductor device according to the eighth embodiment has a base 1 of p - A semiconductor substrate 1a having a p-type - 3 in that it is composed of an n-type epitaxial layer 1b and an n-type epitaxial layer 2a that is in contact with the lower surface of the well region 2 and has a higher impurity concentration than the well region 2. + The semiconductor device according to the first embodiment shown in FIG. 3 differs from the semiconductor device according to the first embodiment in that a mold-embedded layer 9 is provided.

[0089] The field plates of the semiconductor device according to the eighth embodiment are substantially similar to the field plates (10, 11, 12) of the semiconductor device according to the first embodiment. Other configurations of the semiconductor device according to the eighth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0090] 4, in the semiconductor device according to the eighth embodiment, like the semiconductor device according to the first embodiment, the distance d1 between the isolation region 6a and the field plate 10 is made larger than the distance d2 between the voltage withstand region 8 and the field plate 10. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11, 12) compared to the case where a field plate with a constant distance between the isolation region 6a and the voltage withstand region 8 is used.

[0091] Ninth embodiment As shown in Fig. 14, the semiconductor device according to the ninth embodiment is different from the semiconductor device according to the first embodiment shown in Fig. 3 in that it is configured on an SOI (Silicon on Insulator) substrate. - Type or p - The semiconductor device includes a support substrate 400 of a semiconductor type. An insulating film 401 such as an oxide film is provided on the upper surface side of the support substrate 400. - A mould base 1 is provided.

[0092] The field plates of the semiconductor device according to the ninth embodiment are substantially similar to the field plates (10, 11, 12) of the semiconductor device according to the first embodiment. Other configurations of the semiconductor device according to the ninth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0093] 4, in the semiconductor device according to the ninth embodiment, similarly to the semiconductor device according to the first embodiment, the distance d1 between the isolation region 6a and the field plate 10 is made larger than the distance d2 between the voltage withstand region 8 and the field plate 10. This makes it possible to increase the gate threshold voltage of the parasitic n-type MOSFET and suppress the operation of the parasitic n-type MOSFET without significantly changing the basic characteristics of the field plates (10, 11, 12) compared to the case where a field plate with a constant distance between the isolation region 6a and the voltage withstand region 8 is used.

[0094] (Other embodiments) As described above, the present invention has been described by the first to ninth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0095] For example, although the semiconductor device according to the first embodiment has a configuration in which one chip has high side circuit 102 for one phase, the present invention is not limited to this, and one chip may have high side circuits for multiple phases (for example, three phases). The same applies to the semiconductor devices according to the second to eighth embodiments.

[0096] In the semiconductor device according to the first embodiment, the first layer 10 is divided above the isolation region 6a and the second layers 11 and 12 are provided in all the spiral lines in the direction perpendicular to the direction in which the spirals of the field plate (10, 11, 12) extend, but this does not necessarily have to be applied to all the spiral lines. For example, among the spiral lines in the direction perpendicular to the direction in which the spirals of the field plate (10, 11, 12) extend, a part of the inner circumference side, which is the high potential side, may have a structure in which the first layer 10 is divided above the isolation region 6a and the second layers 11 and 12 are provided, and a part of the outer circumference side, which is the low potential side, may have a structure in which the first layer 10 is not divided above the isolation region 6a and the second layers 11 and 12 are not provided. The same applies to the semiconductor devices according to the second to eighth embodiments.

[0097] Furthermore, although the semiconductor device according to the first to ninth embodiments is an HVIC, the present invention is also applicable to semiconductor devices other than an HVIC.

[0098] In addition, the configurations disclosed in the first to ninth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0099] 1...Substrate (semiconductor chip) 1a...Semiconductor substrate 1b…Epitaxial layer 2. Well area 3...Pressure resistance range 4…Contact area 6a, 6b...separation region (slit region) 8...Pressure-resistant area 9…Buried layer 10...Field plate (first layer) 10a,10b...end 11~13…2nd layer 11a, 11b, 12a, 12b...Via 20a, 20b...Level shift element 21a, 21b... carrier supply region (source region) 22a, 22b...gate electrode 23a, 24b... Carrier receiving region (drain region) 25...Gate insulating film 31...Source electrode 31a…Via 32...Drain electrode 32a…Via 71, 72...Insulating film 101…Low potential side circuit (low side circuit) 102...High side circuit 103...Power supply (low potential side power supply) 104...Power supply (high potential side power supply) 105…Connection point 200…Power conversion section 400…Support substrate 401...insulating film D0~D2: Diode R1, R2: Level shift resistors T1, T2: Level shift element (level shifter) T3: High potential side switching element T4: Low potential side switching element

Claims

1. A substrate of a first conductivity type; a first well region of a second conductivity type provided on the substrate, in which a high side circuit is formed; a first withstanding voltage region of a second conductivity type that is annularly provided around the first well region and has a lower impurity concentration than the first well region; a second withstanding voltage region of a first conductivity type provided in an annular shape on an outer periphery of the first withstanding voltage region in contact with the first withstanding voltage region; a first level shift element including a part of the first voltage withstanding region; a first isolation region of a first conductivity type provided so as to surround the first level shift element; a field plate provided above the first breakdown voltage region and the first isolation region with an insulating film interposed therebetween, the field plate having a first distance from the first isolation region that is greater than a second distance from the first breakdown voltage region; A semiconductor device comprising:

2. The field plate traverses above the first level shifting element at the second distance. The semiconductor device according to claim 1 .

3. The field plate crosses above the first voltage withstanding region and the first level shift element at the first distance. The semiconductor device according to claim 1 .

4. a second level shift element including another part of the first withstand voltage region; a second isolation region of the first conductivity type provided so as to surround the second level shift element; Further comprising: The field plate crosses above the first voltage withstanding region, the first level shift element, the second isolation region, and the second level shift element at the first distance. The semiconductor device according to claim 1 .

5. The field plate is a first layer provided above the first voltage withstanding region and separated above the first isolation region; a second layer disposed above the first isolation region; Equipped The semiconductor device according to claim 1 .

6. The first layer is electrically connected to the second layer. The semiconductor device according to claim 5 .

7. The first layer is made of polysilicon. The second layer is made of a metal. The semiconductor device according to claim 5 .

8. The second layer is provided locally above the first isolation region. The semiconductor device according to claim 5 .

9. The second layer is further provided above the first voltage-resistant region. The semiconductor device according to claim 5 .

10. a thickness of the insulating film on the first isolation region is greater than a thickness of the insulating film on the first voltage withstanding region; The field plate is composed of a single layer having a meandering cross-sectional pattern. The semiconductor device according to claim 1 .

11. The field plate has a spiral planar pattern. The semiconductor device according to claim 1 .

12. One end of the spiral planar pattern on the inner periphery side is connected to a first potential, The other end of the spiral planar pattern on the outer periphery side is connected to a second potential lower than the first potential. The semiconductor device according to claim 11.

13. The field plate has a concentric planar pattern. The semiconductor device according to claim 1 .

14. The potential of the field plate is a floating potential. The semiconductor device according to claim 13.

15. The first isolation region has a U-shaped planar pattern including two straight line portions each having an end in contact with the second withstand voltage region. The semiconductor device according to claim 1 .

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