Method for manufacturing silicon carbide semiconductor device

Abstract

To provide a method for manufacturing a silicon carbide semiconductor device that enables the number of defective products to be reduced.SOLUTION: There is provided a method for manufacturing a silicon carbide semiconductor device including: a semiconductor substrate including a first semiconductor layer 2 of a first conductivity type; a second semiconductor layer 6 of a second conductivity type formed on the first semiconductor layer 2; and a trench 16 penetrating the second semiconductor layer 6 and reaching the first semiconductor layer 2. The method includes the steps of: selectively forming base regions 3 and 4 of the second conductivity type in the first semiconductor layer 2 by first ion implantation; and selectively forming a source region 7 of the first conductivity type in the surface layer of the second semiconductor layer 6 by second ion implantation, and in the first ion implantation, the semiconductor substrate is tilted at 3 degrees or more with respect to a perpendicular line.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are several types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density and can handle larger currents than MOSFETs, but they cannot be switched at high speeds. Specifically, bipolar transistors can only be used at switching frequencies of a few kHz, while IGBTs can only be used at switching frequencies of a few tens of kHz. On the other hand, power MOSFETs have a lower current density and are more difficult to use at high currents than bipolar transistors and IGBTs, but they are capable of high-speed switching operations up to a few MHz.

[0004] However, there is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, with development currently approaching the material limit. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed, and high-temperature characteristics.

[0005] The reason behind this is that SiC is a very chemically stable material, with a wide band gap of 3 eV, making it extremely stable for use as a semiconductor even at high temperatures. In addition, the maximum electric field strength is more than one order of magnitude greater than that of silicon. Since SiC is likely to exceed the material limits of silicon, it is expected to see great growth in future applications for power semiconductors, especially MOSFETs. In particular, it is expected to have a low on-resistance. Vertical SiC-MOSFETs with even lower on-resistance while maintaining high voltage characteristics are anticipated.

[0006] The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET as an example. Fig. 23 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Fig. 23 shows an example of a trench MOSFET 150. As shown in Fig. 23, n + An n-type buffer layer 118 is deposited on the front surface of the silicon carbide substrate 101, and an n-type - A silicon carbide epitaxial layer 102 is deposited.

[0007] n - The n-type silicon carbide epitaxial layer 102 has + Type region 117, 1st p + Mold base region 103, second p + A type base region 104, an n-type high concentration region 105, and a p-type base layer 106 are selectively provided. ++ Type source region 107, p ++ A mold contact region 108 is optionally provided.

[0008] Also, n ++ A trench 116 is provided that penetrates the p-type source region 107 and the p-type base layer 106 to reach the n-type high concentration region 105. A gate insulating film 109 is provided along the inner wall of the trench 116, on the bottom and side walls of the trench 116, and a gate electrode 110 is provided inside the gate insulating film 109 in the trench 116. ++ type contact region 108 and n ++A source electrode 112 is provided on the surface of the n-type source region 107, and a source electrode pad 115 is provided on the source electrode 112. An interlayer insulating film 111 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 110 embedded in the trench 116. A barrier metal 114 is provided between the source electrode 112 and the interlayer insulating film 111. + A back surface electrode 113 is provided on the back surface of the silicon carbide substrate 101 .

[0009] 1st p. + The base region 103 and the second p + By providing the type base region 104, a first p + The base region 103 and the second p + A base region 104 and an n - The n-type silicon carbide epitaxial layer 102 and + A pn junction can be formed between the gate insulating film 109 and the type region 117. By forming such a pn junction, it is possible to prevent a high electric field from being applied to the gate insulating film 109 at the bottom of the trench 116. Therefore, even when a wide band gap semiconductor is used as the semiconductor material, it is possible to achieve a high withstand voltage.

[0010] 1st p. + The base region 103 and the second p + The base region 104 is an n - The n-type epitaxial layer is grown on the front surface of the silicon carbide epitaxial layer 102, and then a p-type dopant such as aluminum (Al) is ion-implanted into the n-type epitaxial layer. Summary of the Invention [Problem to be solved by the invention]

[0011] FIG. 24 is a top view showing a silicon carbide semiconductor wafer. The above-mentioned trench MOSFET 150 is formed on a silicon carbide semiconductor wafer. Here, the direction parallel to the orientation flat 121 is the X-axis direction, and the direction perpendicular to the orientation flat 121 is the Y-axis direction. The silicon carbide semiconductor wafer 160 has an off-angle of 4 degrees in order to epitaxially grow a semiconductor layer on the silicon carbide semiconductor wafer 160. The off-angle has an error of ±0.5 degrees according to the off-angle standard. FIG. 25 is a cross-sectional view of the silicon carbide semiconductor wafer in the X-axis direction. As shown in FIG. 25, an off-angle is provided in the X-axis direction.

[0012] Since the silicon carbide semiconductor wafer 160 has an off-angle, it is assumed that channeling does not occur. + The base region 103 and the second p + Type base region 104 (hereinafter, p + When forming a silicon carbide semiconductor wafer (referred to as a mold base region) by ion implantation, ion implantation has conventionally been performed at an angle of 0 degrees from the center of silicon carbide semiconductor wafer 160, without tilting the ion beam. Here, silicon carbide semiconductor wafer 160 having a crystalline structure has a portion where atoms are densely arranged and a portion where atoms are sparsely arranged, depending on the direction of the crystal. Channeling is a phenomenon in which, when ion implantation is performed from a direction where atoms are sparse, the probability that the implanted ions will collide with crystal atoms is reduced, and the probability that they will be implanted deep into the crystal is increased.

[0013] However, when ion implantation is performed at an angle of 0 degrees from the center of the silicon carbide semiconductor wafer 160, a maximum tilt of 1.6 degrees occurs when ion implantation is performed on a 6-inch diameter silicon carbide semiconductor wafer 160 using a single-scan ion implantation device with only one scanning direction (for example, an ion implantation device manufactured by ULVAC, Inc.: Model No. IH-860DSIC). FIG. 26 is a cross-sectional view showing ion implantation in the conventional method for manufacturing a silicon carbide semiconductor device from the Y-axis direction. In this way, when the scanning direction is the Y-axis direction, a maximum tilt of 1.6 degrees occurs in the Y-axis direction. FIG. 27 is a cross-sectional view showing ion implantation in the conventional method for manufacturing a silicon carbide semiconductor device from the X-axis direction. In this way, when the scanning direction is the X-axis direction, a maximum tilt of 1.6 degrees occurs in the X-axis direction. In addition, when the off-angle standard (±0.5 degrees) is taken into consideration, a tilt of 2.4 degrees (4-1.6) and a minimum tilt of 1.9 degrees (4-0.5-1.6) occurs between the ion beam and the front surface of the silicon carbide semiconductor wafer 160.

[0014] Fig. 28 is a top view showing the Von of silicon carbide semiconductor devices formed on a silicon carbide semiconductor wafer. In Fig. 28, the on-voltage (Von) of the silicon carbide semiconductor devices is classified into 11 stages from 1.0 V to 2.0 V, and the distribution of Von on the silicon carbide semiconductor wafer is shown. According to Fig. 28, silicon carbide semiconductor devices with high Von are concentrated in region S at the lower right of the silicon carbide semiconductor wafer.

[0015] Fig. 29 is a graph showing a normal probability distribution plot of Von of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer. In Fig. 29, the horizontal axis shows Von in units of V, and the vertical axis shows standard deviation σ. When the distribution of Von of a silicon carbide semiconductor device is a normal distribution, it is plotted as a straight line, but in Fig. 29, the part with high Von deviates from the straight line. This is because there are many silicon carbide semiconductor devices with high Von, and therefore the standard deviation σ of the part with high Von is low. Since silicon carbide semiconductor devices with high Von are defective products, the process capability index Cpk (Process Capability Index Katayori), which indicates the ability to not produce defective products, is low at 0.54.

[0016] FIG. 30 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device formed on the left side of a silicon carbide semiconductor wafer. For example, the structure of a silicon carbide semiconductor device formed in region Sl of FIG. 28 is shown. FIG. 31 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device formed in the center of a silicon carbide semiconductor wafer. For example, the structure of a silicon carbide semiconductor device formed in region Sc of FIG. 28 is shown. FIG. 32 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device formed on the right side of a silicon carbide semiconductor wafer. For example, the structure of a silicon carbide semiconductor device formed in region Sr of FIG. 28 is shown.

[0017] Comparing the structures in FIG. 30 to FIG. 32, the width of the JFET (Junction Field Effect Transistor), for example, the first p + The mold base region 103 and the second p + The width of the n-type high concentration region 105 sandwiched between the first p-type base region 104 is approximately the same. + The base region 103 and the second p + The base region 104 is an n - It can be seen that the n-type impurity ions penetrate deeply into the n-type silicon carbide epitaxial layer 102. As a result, the narrow portion of the n-type high concentration region 105 increases, the JFET resistance increases, and Von increases.

[0018] This is because the right side of the silicon carbide semiconductor wafer is tilted by 2.4 degrees, with a minimum of 1.9 degrees, causing channeling and causing the ions implanted by ion implantation to move to n - This is because the ions are implanted deep into the silicon carbide epitaxial layer 102 .

[0019] Here, the case of a 6-inch silicon carbide semiconductor wafer has been described, but with an 8-inch silicon carbide semiconductor wafer, a maximum tilt of 2.1 degrees occurs. This results in a tilt of 1.9 degrees (4-2.1) and a minimum of 1.4 degrees (4-0.5-2.1) between the ion beam and the front surface of the silicon carbide semiconductor wafer 160. For this reason, channeling occurs, as in the case of a 6-inch diameter wafer.

[0020] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of reducing the number of defective products. [Means for solving the problem]

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device comprising a semiconductor substrate having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, and a trench penetrating the second semiconductor layer to reach the first semiconductor layer, the method including: selectively forming a base region of a second conductivity type in the first semiconductor layer by a first ion implantation; and selectively forming a source region of a first conductivity type in a surface layer of the second semiconductor layer by a second ion implantation, wherein the first base region has a bottom surface located deeper than the trench, and the first ion implantation into the first base region is tilted by 3 degrees or more with respect to a perpendicular to the semiconductor substrate. Effect of the Invention

[0022] Advantageous Effects of Invention According to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to reduce defective products. [Brief description of the drawings]

[0023] [Figure 1] 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a silicon carbide semiconductor device according to an embodiment during manufacture. [Diagram 2] 5A to 5C are cross-sectional views (part 2) illustrating schematic diagrams of a silicon carbide semiconductor device according to the embodiment during manufacture. [Diagram 3] 5A to 5C are cross-sectional views (part 3) illustrating schematic configurations of the silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 4] 4 is a cross-sectional view (part 4) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. [Diagram 5]5 is a cross-sectional view (part 5) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. [Figure 6] 6 is a cross-sectional view illustrating a silicon carbide semiconductor device according to the embodiment during its manufacture (part 6). FIG. [Figure 7] 1 is a top view showing ion implantation tilted in a direction different from the off angle in the method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. [Figure 8] 13 is a top view in another direction showing ion implantation with an inclination in the off-angle direction in the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. [Figure 9] 9 is a cross-sectional view of the ion implantation of FIGS. 7 and 8 in the manufacturing method of the silicon carbide semiconductor device according to the embodiment, viewed from the Y-axis direction. [Figure 10] 9 is a cross-sectional view of the ion implantation of FIGS. 7 and 8 in the manufacturing method of the silicon carbide semiconductor device according to the embodiment, viewed from the X-axis direction. [Figure 11] 1 is a top view showing ion implantation with an inclination in the off-angle direction in the method for manufacturing a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 12] 12 is a cross-sectional view of the ion implantation of FIG. 11 in the manufacturing method of the silicon carbide semiconductor device according to the embodiment, viewed from the Y-axis direction. [Figure 13] 1 is a graph showing Von of a silicon carbide semiconductor device according to an embodiment. [Figure 14] 2 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment formed on a right side of a silicon carbide semiconductor wafer. FIG. [Figure 15] 1 is a table showing conditions of ion implantation according to an embodiment and a conventional example. [Figure 16] 16 is a graph showing Von under the ion implantation conditions of FIG. 15. [Figure 17] 16 is a graph showing a breakdown voltage under the ion implantation conditions of FIG. 15. [Figure 18] 16 is a graph showing an oxide film electric field under the ion implantation conditions of FIG. 15. [Figure 19]4A to 4C are cross-sectional views showing shadowing during ion implantation in the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20] 1 is a graph showing the impurity concentration of the first p+ type base region when ion implantation is performed at a plurality of tilt angles (linear axis). [Figure 21] 1 is a graph (logarithmic axis) showing the impurity concentration of the first p + type base region when ion implantation is performed at a plurality of tilt angles. [Figure 22] 13 is a graph showing leakage current between DS when ion implantation is performed at a plurality of tilt angles. [Figure 23] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. [Figure 24] FIG. 2 is a top view showing a silicon carbide semiconductor wafer. [Diagram 25] 2 is a cross-sectional view of the silicon carbide semiconductor wafer in the X-axis direction. [Figure 26] 1 is a cross-sectional view taken from the Y-axis direction illustrating ion implantation in a conventional method for manufacturing a silicon carbide semiconductor device. [Figure 27] 1 is a cross-sectional view taken from the X-axis direction illustrating ion implantation in a conventional method for manufacturing a silicon carbide semiconductor device. [Figure 28] FIG. 2 is a top view showing Von of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer. [Figure 29] 1 is a graph showing a normal probability distribution plot of Von of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer. [Diagram 30] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device formed on the left side of a silicon carbide semiconductor wafer. [Diagram 31] 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device formed in the center of a silicon carbide semiconductor wafer. [Diagram 32] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device formed on the right side of a silicon carbide semiconductor wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] A preferred embodiment of the method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before the index represents a negative index. In addition, the description of "same" or "equivalent" should include up to 5% in consideration of variations in manufacturing.

[0025] (Embodiment) The structure of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device according to the embodiment is similar to that of a conventional silicon carbide semiconductor device, and therefore is not illustrated. The manufacturing method of the silicon carbide semiconductor device according to the embodiment will be described below. Figures 1 to 6 are cross-sectional views each showing a schematic state during the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0026] First, n-type silicon carbide + A silicon carbide substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1 is prepared. + The n-type silicon carbide substrate 1 is manufactured so that the surface has a predetermined angle with respect to a specific crystal plane. This predetermined angle is called the off angle. + On the first main surface of the silicon carbide substrate 1, an n-type impurity such as nitrogen atoms (N) is doped to form an n-type silicon carbide layer. + An n-type low-concentration buffer layer 18a having a low impurity concentration is epitaxially grown on the silicon carbide substrate 1. Next, an n-type low-concentration buffer layer 18a made of silicon carbide is formed on the surface of the n-type low-concentration buffer layer 18a while being doped with n-type impurities, for example, nitrogen atoms (N). +An n-type high-concentration buffer layer 18b having a high impurity concentration is epitaxially grown on the silicon carbide substrate 1. The n-type low-concentration buffer layer 18a and the n-type high-concentration buffer layer 18b together form the n-type buffer layer 18.

[0027] Next, a first n-type impurity layer made of silicon carbide is formed on the surface of the n-type high-concentration buffer layer 18b while being doped with n-type impurities, for example, nitrogen atoms (N). - The silicon carbide epitaxial layer 2a is epitaxially grown to a thickness of, for example, about 30 μm. The state up to this point is shown in FIG.

[0028] Next, the 1nth - A mask (not shown) having a desired opening is formed on the surface of the first silicon carbide epitaxial layer 2a by photolithography, for example, an oxide film. Then, using this oxide film as a mask, n-type impurities, for example, nitrogen atoms, may be ion-implanted by ion implantation. This results in a first n-type impurity layer. - The n-type silicon carbide epitaxial layer 2a includes + A mold area 17 is formed.

[0029] Next, n + The mask used in the ion implantation for forming the mold region 17 is removed. - On the surface of the silicon carbide epitaxial layer 2a, a mask for ion implantation having a predetermined opening is formed, for example, of an oxide film by photolithography. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form a lower first p-type impurity layer having a depth of about 0.5 μm. + The base region 3a is formed. + When the type region 17 is formed, n + Type region 17 n + A lower first p + The base region 3a is + The lower portion 1p is formed so as to overlap the mold region 17. + At the same time, a second p +A second conductive type base region (second base region) 4 may be formed in the lower first p + The base region 3a and the second p + The lower first p is formed so that the distance between the lower first p and the mold base region 4 is about 1.5 μm. + The base region 3a and the second p + The impurity concentration of the base region 4 is set to, for example, 5×10 18 / cm 3 Set it to a certain extent.

[0030] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening to form a first n - A lower n-type high concentration region 5a having a depth of, for example, about 0.5 μm may be formed in a part of the surface region of the silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high concentration region 5a is, for example, 1×10 17 / cm 3 The state up to this point is shown in Figure 2.

[0031] Next, the 1nth - A second n-type silicon carbide epitaxial layer 2a is formed on the surface of the n-type silicon carbide epitaxial layer 2a by doping with n-type impurities such as nitrogen. - The second n-type silicon carbide epitaxial layer 2b is formed to a thickness of about 0.5 μm. - The impurity concentration of the silicon carbide epitaxial layer 2b is 3×10 15 / cm 3 The following is set to about 1n - The n-type silicon carbide epitaxial layer 2a and the n-type - The silicon carbide epitaxial layer 2b is formed of n - This results in a silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2.

[0032] Next, the 2nd - An ion implantation mask having a predetermined opening is formed on the surface of the silicon carbide epitaxial layer 2b by photolithography, for example, using an oxide film. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form an upper first p-type impurity layer having a depth of about 0.5 μm. + The mold base region 3b is a lower first p+ The lower portion 1p is formed so as to overlap the mold base region 3a. + The mold base region 3a and the upper portion 1p + The base region 3b forms a continuous region, and the first p + The upper first base region (second conductivity type base region, first base region) 3. + The impurity concentration of the base region 3b is set to, for example, 5×10 18 / cm 3 Set it so that it is about the same.

[0033] Next, a part of the ion implantation mask may be removed, and an n-type impurity such as nitrogen may be ion-implanted into the opening to form an upper n-type high concentration region 5b having a depth of, for example, about 0.5 μm in a part of the surface region of the second silicon carbide epitaxial layer 2b. The impurity concentration of the upper n-type high concentration region 5b may be set to, for example, 1×10 17 / cm 3 The upper n-type heavily doped region 5b and the lower n-type heavily doped region 5a are formed so that at least a portion of them are in contact with each other to form the n-type heavily doped region 5. However, there are cases where the n-type heavily doped region 5 is formed over the entire surface of the substrate, and cases where it is not formed. The state up to this point is shown in FIG.

[0034] Next, n - A p-type base layer (second semiconductor layer of a second conductivity type) 6 is formed by epitaxial growth on the surface of the silicon carbide epitaxial layer 2 to a thickness of about 1.3 μm. The impurity concentration of the p-type base layer 6 is 4×10 17 / cm 3 After the p-type base layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the p-type base layer 6. In addition, the p-type base layer 6 is n - Alternatively, the n-type epitaxial layer 2 may be formed by ion-implanting a p-type impurity such as aluminum into the surface of the n-type silicon carbide epitaxial layer 2 .

[0035] Next, an ion implantation mask having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6. An n-type impurity such as phosphorus (P) is ion-implanted into this opening, so that n is implanted into a part of the surface of the p-type base layer 6. ++ A source region (first semiconductor region of the first conductivity type) 7 is formed. ++ The impurity concentration of the n-type source region 7 is set to be higher than the impurity concentration of the p-type base layer 3. ++ The ion implantation mask used for forming the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner, and p-type impurities such as aluminum are ion-implanted into a portion of the surface of the p-type base layer 6 to form a p ++ A contact region 8 may be formed. ++ The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 3. The state up to this point is shown in FIG.

[0036] Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700°C to form the first p + Mold base region 3, second p + Type base region 4, n ++ Type source region 7, p ++ Type contact region 8 and n + An activation process is carried out on the mold region 17. As described above, the ion implantation regions may be activated all at once by one heat treatment, or the heat treatment may be carried out each time an ion implantation is performed.

[0037] Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6, for example, from an oxide film. Next, the p-type base layer 6 is penetrated by dry etching to form the n-type high concentration region 5 (or the n-type high concentration region 5 if the n-type high concentration region 5 is not formed). - A trench 16 is formed in the n-type silicon carbide epitaxial layer 2 (hereinafter abbreviated as (2)). The bottom of the trench 16 is connected to the second p-type high concentration region 6(2). + This may even reach the mold base region 4. The trench mask is then removed, as shown in FIG.

[0038] Next, n ++ A gate insulating film 9 is formed along the surface of the source region 7 and the bottom and sidewalls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0039] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0040] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. ++ Type source region 7 and p ++ A contact hole is formed exposing the mold contact region 8. Then, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG.

[0041] The interlayer insulating film 11 is selectively removed, and a nickel (Ni) or Ti film is formed on the surface of the silicon carbide semiconductor substrate. + A Ni or Ti film is formed on the back side of the silicon carbide substrate 1. Next, a heat treatment at about 1000° C. is performed to bond the front side of the silicon carbide semiconductor base to the n-type silicon carbide semiconductor base. + An ohmic electrode is formed on the rear surface side of the silicon carbide substrate 1 .

[0042] Next, a conductive film that will become a source electrode (not shown) is provided so as to contact the ohmic electrode portion formed in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed to leave the source electrode only in the contact hole, and n + Type source region 7 and p ++ The mold contact region 8 is brought into contact with the source electrode. Next, the source electrode other than the contact hole is selectively removed.

[0043] Next, n + A back electrode (not shown) made of, for example, a nickel (Ni) film is formed on the second main surface of the silicon carbide substrate 1. Then, a heat treatment is performed at a temperature of, for example, about 970° C. to form an n-type silicon carbide substrate. + The silicon carbide substrate 1 and the back electrode are connected to each other by ohmic junction.

[0044] Next, an electrode pad to become a source electrode pad (not shown) is deposited on the source electrode on the front surface of the silicon carbide semiconductor substrate and in the opening of the interlayer insulating film 11 by, for example, a sputtering method. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be made of, for example, aluminum containing silicon at a rate of 1% (Al-Si). Next, the source electrode pad is selectively removed.

[0045] Next, on the surface of the drain electrode (not shown), films of, for example, titanium (Ti), nickel (Ni) and gold (Au) are formed in this order as a drain electrode pad (not shown).

[0046] In the method for manufacturing a silicon carbide semiconductor device according to the embodiment, + Mold base region 3a, upper part 1p + The base region 3b and the second p +When forming the type base region 4 by ion implantation, the ion beam for ion implantation is tilted at 3 degrees or more with respect to a perpendicular line from the center of the silicon carbide semiconductor wafer. Therefore, in the embodiment, the ions are implanted with a certain degree or more of tilt with respect to the front surface of the silicon carbide semiconductor wafer, so that channeling can be prevented. The direction of this tilt may be either the direction of the off angle or a direction different from the off angle.

[0047] In a silicon carbide semiconductor wafer, an orientation flat is provided in, for example, the <11-20> direction to indicate the crystal orientation of the silicon carbide semiconductor substrate. For example, the orientation flat is formed by polishing the edge of the silicon carbide semiconductor substrate to make a part of the circumference straight (see FIG. 24). If the direction parallel to the orientation flat is the X-axis and the direction perpendicular to the orientation flat is the Y-axis, the off-angle is provided in the X-axis direction (see FIG. 27). In this case, the direction of the off-angle is the positive direction of the X-axis, and the direction different from the off-angle is the Y-axis direction. The perpendicular line is a straight line in the Z-axis direction perpendicular to the X-axis and Y-axis directions.

[0048] First, a form in which a tilt is provided in a direction different from the off angle will be described. FIG. 7 is a top view showing ion implantation in which a tilt is provided in a direction different from the off angle in the manufacturing method for a silicon carbide semiconductor device according to an embodiment. FIG. 8 is a top view in another direction showing ion implantation in which a tilt is provided in the direction of the off angle in the manufacturing method for a silicon carbide semiconductor device according to an embodiment. FIG. 9 is a cross-sectional view of the ion implantation in FIGS. 7 and 8 in the manufacturing method for a silicon carbide semiconductor device according to an embodiment, as viewed from the Y-axis direction. FIG. 10 is a cross-sectional view of the ion implantation in FIGS. 7 and 8 in the manufacturing method for a silicon carbide semiconductor device according to an embodiment, as viewed from the X-axis direction.

[0049] 8 and 10, a tilt angle θ is provided in the Y-axis direction between the ion beam L reaching the center O of the silicon carbide semiconductor wafer 60 and a perpendicular line N from the center O of the silicon carbide semiconductor wafer 60. As will be described later, this tilt angle θ is preferably 7 degrees or more.

[0050] Next, a form in which an inclination is provided in the off-angle direction will be described. Fig. 11 is a top view showing ion implantation in which an inclination is provided in the off-angle direction in the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Fig. 12 is a cross-sectional view of the ion implantation in Fig. 11 in the method for manufacturing a silicon carbide semiconductor device according to an embodiment, as viewed from the Y-axis direction.

[0051] 11 and 12, the ion beam L is tilted by moving the ion beam inlet in the positive direction of the X-axis by the amount of arrow A. Therefore, a tilt angle θ is provided between the ion beam L that reaches the center O of the silicon carbide semiconductor wafer 60 and a perpendicular line N from the center O of the silicon carbide semiconductor wafer 60 in the X-axis direction. As will be described later, this tilt angle θ is preferably 3 degrees or more. When tilting in the same direction as the off angle, the off angle is 4 degrees, and therefore the tilt angle θ is smaller by the amount of the off angle.

[0052] Also, the bottom page 1 + The base region 3b and the second p + When the mold base region 4 is formed in a stripe shape, a tilt angle θ may be provided in the longitudinal direction of the stripe between the ion beam L that reaches the center O of the silicon carbide semiconductor wafer 60 and a perpendicular line N from the center O of the silicon carbide semiconductor wafer 60. When the longitudinal direction of the stripe is in a direction different from the off angle, the tilt angle θ is preferably 7 degrees or more, and when the longitudinal direction of the stripe is in the same direction as the off angle, the tilt angle θ is preferably 3 degrees or more.

[0053] Furthermore, when the trenches 16 are formed in a stripe shape, a tilt angle θ may be provided between the ion beam L reaching the center O of the silicon carbide semiconductor wafer 60 and a perpendicular line N from the center O of the silicon carbide semiconductor wafer 60 in the longitudinal direction of the stripe shape of the trenches 16. When the longitudinal direction of the stripe shape of the trenches 16 is in a direction different from the off angle, the tilt angle θ is preferably 7 degrees or more, and when the longitudinal direction of the stripe shape of the trenches 16 is in the same direction as the off angle, the tilt angle θ is preferably 3 degrees or more.

[0054] Furthermore, when trenches 16 are formed in a polygonal cell shape, a tilt angle θ may be provided between ion beam L that reaches center O of silicon carbide semiconductor wafer 60 in a direction different from the off angle and a perpendicular line N from center O of silicon carbide semiconductor wafer 60. By implanting ions in a direction different from the off angle, channeling can be prevented.

[0055] Fig. 13 is a graph showing Von of a silicon carbide semiconductor device according to an embodiment. In Fig. 13, the horizontal axis shows the angle between the crystal plane of the silicon carbide semiconductor wafer and an ion beam with a tilt angle of 0 degrees (hereinafter referred to as tilt angle), in degrees. The vertical axis shows Von of the silicon carbide semiconductor device, in V. Fig. 13 shows the Von of a first p + The base region 3 and the second p + 4 is a graph showing Von of a silicon carbide semiconductor device in which a type base region 4 is formed.

[0056] 13, the silicon carbide semiconductor wafer has an off-angle of 4 degrees, so the 4 degree part is the center part. In addition, a 6-inch silicon carbide semiconductor wafer has a tilt of ±1.6 degrees, and because of the off-angle standard (±0.5 degrees), the tilt angle is between a minimum of 1.9 degrees and a maximum of 6.1 degrees.

[0057] According to FIG. 13, when the tilt angle is 0 degrees or more and 1.5 degrees or less, Von increases significantly as the tilt angle approaches 6 degrees. Also, when the tilt angle is 2 degrees or more and 2.5 degrees or less, Von increases as the tilt angle approaches 6 degrees. On the other hand, when the tilt angle is 3 degrees or more and 7 degrees or less, Von does not increase even when the tilt angle is close to 6 degrees. Therefore, by setting the tilt angle to 3 degrees or more, it is possible to suppress the increase in Von. Also, when the tilt is set in a direction different from the off angle, since there is no off angle of 4 degrees, it is possible to suppress the increase in Von by setting the tilt angle to 7 degrees or more.

[0058] Here, the larger the tilt angle, the larger the angle between the front surface of the silicon carbide semiconductor wafer and the ion beam (hereinafter referred to as the incident angle), and the ions do not penetrate deep into the semiconductor layer. Therefore, it is better to have a small tilt angle. In other words, it is preferable that the tilt angle is as small as possible, but not smaller than the angle at which channeling does not occur.

[0059] FIG. 13 shows the results for a silicon carbide semiconductor wafer with a diameter of 6 inches. In the case of a silicon carbide semiconductor wafer with a diameter of 8 inches, a tilt of ±2.1 degrees occurs, and due to the off-angle standard (±0.5 degrees), the tilt angle is from a minimum of 1.4 degrees to a maximum of 6.6 degrees. For this reason, in the case of a silicon carbide semiconductor wafer with a diameter of 8 inches, it is preferable to make the tilt angle larger by about 0.5 degrees than in the case of a silicon carbide semiconductor wafer with a diameter of 6 inches. For example, when providing a tilt in the off-angle direction, the increase in Von can be suppressed by setting the tilt angle to 3.5 degrees or more. In addition, when providing a tilt in a direction different from the off-angle, since there is no off-angle of 4 degrees, the increase in Von can be suppressed by setting the tilt angle to 7.5 degrees or more.

[0060] Furthermore, when the off-angle of the silicon carbide semiconductor wafer is 2 degrees, it is preferable to increase the tilt angle by 2 degrees when providing an inclination in the off-angle direction. For example, in the case of a silicon carbide semiconductor wafer with a diameter of 6 inches, the increase in Von can be suppressed by setting the tilt angle to 5 degrees or more. In the case of a silicon carbide semiconductor wafer with a diameter of 8 inches, the increase in Von can be suppressed by setting the tilt angle to 5.5 degrees or more.

[0061] 14 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment formed on the right side of a silicon carbide semiconductor wafer. The structure in FIG. 14 has a tilt angle of 7 degrees and a first p + The base region 3 and the second p + 13B. On the other hand, when the tilt angle is 0 degree, the first p + The base region 103 and the second p +The structure of the silicon carbide semiconductor device in the region where the type base region 104 is formed and the inclination angle is about 6 degrees (A in FIG. 13) is as shown in FIG.

[0062] Comparing FIG. 14 and FIG. 32, in FIG. 14, the first p + The base region 3 and the second p + The base region 4 is - The dopant does not penetrate deeply into the silicon carbide epitaxial layer 2. Therefore, the JFET resistance does not increase, and an increase in Von can be suppressed.

[0063] So far, page 1 + The base region 3 and the second p + When forming the base region 4, the ion beam for ion implantation is tilted. Next, the effect of tilting the ion beam when forming other regions will be described. FIG. 15 is a table showing the conditions of ion implantation according to the embodiment and the conventional method. In FIG. 15, p + The mold base region is a first p + The base region 3 and the second p + It shows a mold base region 4. The same applies to the following description.

[0064] Condition 1 in Figure 15 is p + Type base region, n ++ Type source region 107, n + This is an example of a conventional method for manufacturing a silicon carbide semiconductor device in which none of the mold regions 117 is tilted. + This is an example of an embodiment in which ion implantation is performed only in the base region with a tilt angle of 7 degrees in the Y-axis direction (a direction different from the off angle). + This is an example of an embodiment in which ion implantation is performed only in the base region with a tilt angle of 3 degrees in the positive direction (off-angle direction) along the X-axis. + Type base region, n ++ Type source region 7, n + This is an example of a method for manufacturing a silicon carbide semiconductor device in which ion implantation is performed on all of the type regions 17 with a tilt angle of 7 degrees in the Y-axis direction. + Type base region, n++ Type source region 7, n + This is an example of a manufacturing method for a silicon carbide semiconductor device in which ion implantation is performed on all of mold regions 17 with a tilt angle of 3 degrees in the positive direction along the X-axis.

[0065] The results of conditions 1 to 5 in FIG. 15 are shown in FIGS. 16 to 18. FIG. 16 is a graph showing Von under the ion implantation conditions in FIG. 15. In FIG. 16, the vertical axis shows Von in units of V. The horizontal axis shows the incidence angle (angle from the wafer) in units of degrees. As shown in FIG. 16, in the case of condition 1, when the incidence angle becomes 2.5 degrees or less, Von becomes high due to channeling, but in the cases of conditions 2 to 5, Von remains low. Note that in FIG. 16, since the data for conditions 2 to 5 overlap, only condition 5 is shown in addition to condition 1.

[0066] Fig. 17 is a graph showing the breakdown voltage under the ion implantation conditions of Fig. 15. In Fig. 17, the vertical axis shows the breakdown voltage (BV) in V. The horizontal axis shows the incidence angle (angle from the wafer) in degrees. As shown in Fig. 17, in the case of condition 1, the breakdown voltage increases when the incidence angle is 3 degrees or less, but in the cases of conditions 2 to 5, there is no significant change in the breakdown voltage.

[0067] Fig. 18 is a graph showing the oxide film electric field under the ion implantation conditions of Fig. 15. In Fig. 18, the vertical axis shows the oxide film electric field in V. The horizontal axis shows the incidence angle (angle from the wafer) in degrees. As shown in Fig. 18, there was no significant change in the oxide film electric field under any of Conditions 1 to 5.

[0068] From the above, n ++ Type source region 7, n + Even if ion implantation is not performed by providing a tilt angle to the p + By performing ion implantation with a tilt angle in the mold base region, it is possible to prevent an increase in Von. The effect of preventing an increase in Von was the same whether the tilt was in the X-axis direction or the Y-axis direction.

[0069] Next, the difference in effect between a tilt in the direction of the off-angle and a tilt in a direction different from the off-angle will be described. FIG. 19 is a cross-sectional view showing shadowing during ion implantation in a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Ion implantation is performed on a semiconductor substrate using an oxide film mask 19 with a height t of about 1.45 μm and an opening in the area to be formed. If the ion beam A is tilted during ion implantation, it will be cast in the shadow of the oxide film mask 19, and no area will be formed in the opening of the oxide film mask 19, which may result in the formed area being misaligned (shadowing). In the example of FIG. 19, the 1nth - A first p-type silicon carbide epitaxial layer is formed on the first p-type silicon carbide epitaxial layer. + The mold base region 3 is offset by a distance L.

[0070] 20 and 21 show the first p when ion implantation is performed at a plurality of tilt angles. + 20 is a graph showing the impurity concentration in the base region. In FIG. 20, the vertical axis is a linear axis, and in FIG. 21, the vertical axis is a logarithmic axis. In FIG. 20 and FIG. 21, the vertical axis shows the impurity concentration, and the unit is cm -3 The horizontal axis is the first p + The unit of the measurement is μm. + It can be seen that in a region 0.5 nm or deeper from the surface of the base region 3, the impurity concentration decreases as the tilt angle in ion implantation increases.

[0071] Moreover, Fig. 22 is a graph showing the leakage current between the DS when ion implantation is performed at a plurality of tilt angles. In Fig. 22, the horizontal axis shows the leakage current (IDSS) between the drain electrode and the source electrode (between the DS) in units of A, and the vertical axis shows the standard deviation σ. Fig. 22 shows the distribution of the leakage current when a voltage of 1200 V is applied between the drain electrode and the source electrode, with graph A showing the results when tilted 3 degrees in the X-axis direction, and graph B showing the results when tilted 7 degrees in the Y-axis direction. As shown in Fig. 22, when tilted 7 degrees in the Y-axis direction, the leakage current between the DS increases due to the effect of shadowing.

[0072] Thus, when the tilt angle is large, the effect of shadowing occurs, so when the sidewall of trench 16 is formed on the m-plane, it is preferable to perform ion implantation at a tilt of 3 degrees or more in the off-angle direction rather than at a tilt of 7 degrees or more in a direction different from the off-angle (in the case of the m-plane, the off-angle is 4 degrees, so a tilt of 3 degrees or more gives a total of 7 degrees or more). On the other hand, when the sidewall of trench 16 is formed on the a-plane, it is preferable to perform ion implantation at a tilt of 7 degrees or more in a direction different from the off-angle rather than at a tilt of 3 degrees or more in the off-angle direction (in the case of the a-plane, it is tilted in a direction different from the off-angle, so it is tilted 7 degrees or more).

[0073] As described above, according to the method for manufacturing a silicon carbide semiconductor device according to the embodiment, the first p + Type base region and second p + When forming the mold base region by ion implantation, the ion beam for ion implantation is tilted at an angle of 3 degrees or more with respect to a perpendicular line from the center of the silicon carbide semiconductor wafer. As a result, in the embodiment, the ions are implanted with an inclination of at least a certain degree with respect to the front surface of the silicon carbide semiconductor wafer, thereby reducing the influence of channeling.

[0074] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications. In addition, each of the above-mentioned embodiments has been described using silicon carbide as a wide band gap semiconductor, but the present invention can also be applied to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0075] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for manufacturing a silicon carbide semiconductor device used in an inverter circuit in which a diode is connected in anti-parallel to a silicon carbide semiconductor device. [Explanation of symbols]

[0076] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 2a 1stn - Silicon carbide epitaxial layer 2b 2nd n - Silicon carbide epitaxial layer 3, 103 1st p. + Type-based regions 3a Lower 1st p. + Type-based regions 3b Upper 1st p. + Type-based regions 4, 104 2nd p. + Type-based regions 5, 105 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6, 106 p-type base layer 7, 107 n ++ Type Source Area 8, 108 p. ++ Mold Contact Area 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 112 Source electrode 113 Back electrode 114 Barrier Metal 115 Source electrode pad 16, 116 Trench 17, 117 n + type area 18, 118 n-type buffer layer 18a n-type low concentration buffer layer 18b n-type high concentration buffer layer 19 Oxide film mask 121 Orientation Flat 150 Trench MOSFET 60, 160 Silicon carbide semiconductor wafer

Claims

1. A method for manufacturing a silicon carbide semiconductor device comprising: a semiconductor substrate having a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; and a trench penetrating the second semiconductor layer to reach the first semiconductor layer, the method comprising: selectively forming a base region of a second conductivity type in the first semiconductor layer by a first ion implantation; selectively forming a first conductivity type source region in a surface layer of the second semiconductor layer by second ion implantation; Including, a first base region having a bottom surface located deeper than the trench, and the first ion implantation into the first base region is tilted by 3 degrees or more with respect to a perpendicular line to the semiconductor substrate.

2. A method for manufacturing a silicon carbide semiconductor device comprising: a semiconductor substrate having a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; and a trench penetrating the second semiconductor layer to reach the first semiconductor layer, the method comprising: selectively forming a base region of a second conductivity type in the first semiconductor layer by a first ion implantation; selectively forming a first conductivity type source region in a surface layer of the second semiconductor layer by second ion implantation; Including, a first base region having a bottom surface located deeper than the trench, and in a process for forming the first base region, the first ion implantation is performed at a tilt of 3 degrees or more compared to the second ion implantation.

3. 3 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising the step of burying a gate electrode in the trench via an insulating film to form a gate trench. 4 .

4. The method for manufacturing a silicon carbide semiconductor device according to claim 3 , wherein the gate trench is formed in a stripe shape.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein the base region is sandwiched between two of the gate trenches when viewed from above.

6. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the step of forming the first base region includes the step of masking a portion where the gate trench is to be formed when performing the first ion implantation, and providing an opening in a portion sandwiched between the gate trenches in a top view.

7. The step of forming the first base region includes the steps of forming a lower first base region; forming an upper first base region overlapping the lower first base region; 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, further comprising the steps of:

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of forming the base region includes the step of forming a second base region at least a portion of which is in contact with a bottom of the trench.

9. forming a semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor layer in the first semiconductor layer by a third ion implantation; 9. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein, in the step of forming the base region, the first ion implantation is performed at a tilt of 3 degrees or more compared to the second ion implantation and the third ion implantation.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein the semiconductor substrate has an off angle of 4 degrees±0.5 degrees.

11. 11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein a sidewall of the trench is an m-plane, and the first ion implantation is performed with an inclination of 3 degrees or more in an off-angle direction.

12. 11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein a sidewall of the trench is an a-plane, and the first ion implantation is performed at an angle of 7 degrees or more in a direction different from an off angle.

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