A low-power fractional analog PLL without feedback divider

Abstract

An integrated circuit device (200) is provided. In some examples, the integrated circuit device includes a first timing resetter (216) configured to receive a reference clock signal (201) and a voltage controlled oscillator (VCO) output signal (212), the first retimer configured to provide a first retimed clock signal (216A) in response to the reference clock signal and the VCO output signal. A first multiplexer (215) receives the first retimed clock signal and provides a feedback clock signal (215A). A phase frequency detector (202) receives a feedback clock signal and a reference clock signal and provides error signals (202A and 203A) in response to the feedback clock signal and the reference clock signal. A VCO (211) receives a voltage signal (220A) based on the error signal, the VCO configured to provide a VCO output signal (212) in response to the voltage signal.

Description

[Background technology]

[0001] In a battery-powered device, battery life depends on the power consumption by various systems within the device. A wireless device that may transmit and / or receive may have, for example, a signal chain and a local oscillator (LO) system. The signal chain may include filters, amplifiers, analog-to-digital converters, and other components. Reducing the power consumed by these devices in the wireless device's signal chain is one area to conserve power, but various components of the wireless device's LO system also consume power, which, if conserved, may also extend battery life.

[0002] One component of the LO can be a phase-locked loop (PLL). PLLs have a wide range of applications, from simple clock clean-up circuits to LOs for high-frequency wireless communication links, such as those used in radio connections. The PLL compares the phase of a reference signal with the phase of an adjustable feedback signal. The comparison can be achieved using a feedback loop, and the PLL is locked when the comparison in the feedback loop is in a steady state, i.e., when the output frequency and phase match the reference frequency and phase in the error detector.

[0003] In order to maintain lock, a significant amount of power is generally consumed by the PLL. One means of reducing the amount of power consumed by the PLL is to turn off the PLL when not needed. In wireless devices such as mobile phones, the device spends a lot of time in sleep mode, and many circuits of the wireless device are turned off. When in sleep mode, the wireless device may operate in listen mode or sniff mode with very low active power consumption. In listen mode or sniff mode, the wireless device listens for a signal and comes out of sleep mode to resume normal operation. However, since an accurate LO may be required during the listen or sniff function, power may still be consumed by the PLL during listen or sniff mode.

[0004] In high frequency wireless communications, fractional PLLs may be used to adjust the output to the required high frequency channel, and may include a feedback divider circuit that consumes a relatively large amount of power even when the wireless device is in listen or sniff mode. Some PLLs include a voltage controlled oscillator (VCO). Therefore, in some applications, the VCO of the PLL may be run in open loop to avoid the power consumed in the feedback divider circuit. However, residual frequency error and increased phase noise limit the usefulness of open loop VCOs, and for some wireless communications, open loop VCOs do not provide acceptable results even during listen or sniff operation. Summary of the Invention

[0005] In some examples, an integrated circuit is provided that includes a fractional PLL configured to operate in a divider disabled mode. The fractional PLL may include a phase frequency detector (PFD), a charge pump, a loop filter, a VCO, a feedback divider, a sigma-delta modulator, a retimed clock signal based on a VCO output, and / or other suitable components. The feedback divider may be disabled so that the feedback divider circuit of the fractional PLL does not consume power. The retimed clock signal may be multiplexed with sigma-delta modulation from the sigma-delta modulator. The retimed clock signal may include multiple retimed clock signals. The PFD may determine an error between the retimed clock signal and a reference clock, and use the error between the retimed clock signal and the reference clock to adjust the output of the VCO to achieve lock of the PLL while the feedback divider is disabled.

[0006] In some examples, an integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, the first re-timer configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. The integrated circuit device also includes a first multiplexer configured to receive the first re-timed clock signal and provide a feedback clock signal. The integrated circuit device also includes a phase frequency detector (PFD) configured to receive the feedback clock signal and the reference clock signal and provide an error signal in response to the feedback clock signal and the reference clock signal. The integrated circuit device also includes a VCO configured to receive a voltage signal based on the error signal, the VCO configured to provide a VCO output signal in response to the voltage signal.

[0007] In some examples, an integrated circuit includes a first retimer, the first retimer including a first input coupled to a reference clock, a second input, and an output. The integrated circuit also includes a first multiplexer, the first multiplexer including a first input coupled to an output of the first retimer, a second input, and an output. The integrated circuit also includes a PFD, the PFD including a first input coupled to the reference clock, a second input coupled to the output of the first multiplexer, and an output. The integrated circuit also includes a charge pump, the charge pump including an input coupled to the output of the PFD, and an output. The integrated circuit also includes a filter, the filter including an input coupled to the output of the charge pump, and an output. The integrated circuit also includes a VCO, the VCO including an input coupled to the output of the filter and an output coupled to the second input of the first retimer. The integrated circuit also includes a feedback divider, the feedback divider including a first input coupled to the output of the VCO and an output coupled to the second output of the first multiplexer.

[0008] In some examples, a method includes receiving, by a retimer, a reference clock signal and a voltage controlled oscillator (VCO) output signal. The method further includes retiming, by the retimer, the reference clock signal according to the VCO output signal to generate a retimed clock signal. The method further includes determining, by a phase frequency detector (PFD), an error signal based on the retimed clock signal and the reference clock signal. The method further includes modifying the VCO output signal based on the error signal. [Brief description of the drawings]

[0009] The features of the present invention will be understood from the following detailed description and the accompanying drawings.

[0010] [Figure 1] FIG. 2 is a circuit diagram of an LO PLL circuit.

[0011] [Figure 2A] 1 is a circuit diagram of a LO PLL circuit in accordance with some aspects of the present disclosure.

[0012] [Figure 2B] FIG. 1 is a timing diagram according to some aspects of the present disclosure.

[0013] [Figure 3A] 1 is a circuit diagram of a LO PLL circuit in accordance with some aspects of the present disclosure.

[0014] [Figure 3B] FIG. 1 is a timing diagram according to some aspects of the present disclosure.

[0015] [Figure 4] FIG. 1 is a timing diagram according to some aspects of the present disclosure.

[0016] [Diagram 5] 1 is a flowchart of a method for providing local oscillation in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Specific examples are described in detail below with reference to the accompanying drawings, in which it is understood that these examples are not intended to be limiting, and that no features are required for any particular example unless specifically stated.

[0018] An example of an LO using a fractional PLL includes a PFD, a charge pump, a filter, a VCO, and a divider circuit. The LO compares the reference clock signal with a feedback signal from a feedback divider and uses the result of this comparison to control the VCO until the PLL locks. The LO may include one or more filters and amplifiers to process the error signal. The feedback circuit may also include a modulator and one or more divider buffers.

[0019] A divider circuit may provide a feedback clock signal that is compared to a reference clock signal. In some cases, the divider circuit is disabled. When the divider circuit is disabled, such as by disconnecting the VCO output from the divider circuit, the feedback clock signal may be derived from the phase information of the VCO, resulting in a retime clock signal. The edges of the retime clock signal bring the VCO phase information to the PFD at the correct phase detection time.

[0020] In some cases, the retime clock signal may be extended for multiple subsequent clock edges to provide a group of retime clock signals that may be used for fractional synthesis. In some cases, the divider circuit may include a sigma-delta modulator, the output of which may be used to randomly select from the group of retime clock signals to generate an error signal that drives the VCO output frequency to an integer plus a fractional multiple of the reference frequency.

[0021] In these and other examples, disabling the divider circuit reduces LO power consumption and improves residual frequency error and phase noise.

[0022] Of course, these advantages are merely examples, and the advantages are not required for any particular embodiment.

[0023] Examples of integrated circuit devices with disabled divider circuits are described hereinafter with reference to the drawings.

[0024] The divider circuit may be associated with fractional synthesis. Fractional-N frequency synthesis provides small step sizes (narrow channels) over a wide bandwidth without requiring large division ratios. This solves the problems associated with very large division ratios in the digital dividers of the LO phase-locked loop, which may occur when very high frequencies are used, such as those in wireless communications. Radio frequencies may be in the gigahertz range. For example, frequency ranges used in wireless communications include the 900 MHz, 2.4 GHz, 3.6 GHz, 4.9 GHz, 5 GHz, 5.9 GHz, and 60 GHz bands. Channel spacing in these frequency bands may be only a few kilohertz (e.g., 200 KHz). Dividing such high frequencies into a reference clock signal, such as 40 MHz or 80 MHz, may require very large division ratios, resulting in performance issues and requiring a large amount of power.

[0025] To achieve small steps between channels at high frequencies while still providing a reasonable operating frequency, very large division ratios are required. For example, a PLL operating at 10 MHz and requiring a step size of 100 Hz would require a division ratio of 100,000. Such large division ratios impact the performance of the PLL as the PLL bandwidth can be approximately one tenth of the reference comparison frequency. In the above example, this means that the PLL bandwidth is only 10 Hz, which can degrade performance due to slower PLL frequency switching, larger passive component size, and potentially larger phase noise at frequencies close to the carrier.

[0026] In fractional-N synthesis, large division ratios are avoided because the dividers take fractional division ratios instead of integer division ratios. To achieve this, the dividers switch between division ratios. For example, the percentage of the various division ratios determined to give the required frequency may be changed between N, N+1, N-1, and N-2. Division ratios between N, N+1, N-1, and N-2 provide frequencies between four division ratios, which is considered as second order modulation. In another example, the primary modulation provides a division ratio range of N, and N+1 provides frequencies between two division ratios. Third order modulation may provide division ratios between N, N+1, N+2, N+3, N-1, N-2, N-3, and N-4. Additional orders of modulation may also be used. The advantage of using fractional-n synthesis is that the step frequency may be reduced while maintaining a high comparison frequency and loop bandwidth to improve the overall performance of the synthesizer.

[0027] In this regard, Figure 1 is a circuit diagram of a LO PLL circuit 100 using a fractional PLL with sigma-delta modulation. A reference clock signal 101A is received by a PFD 102. The reference clock signal 101A from a reference clock 101 is a stable and accurate frequency reference to which the output is phase locked. The reference clock signal 101A may be derived, for example, from a crystal oscillator or a temperature controlled crystal oscillator.

[0028] The PFD 102 compares the feedback clock signal 116 with the reference clock signal 101A and derives a phase error signal 102A and 102B between the reference clock signal 101A and the feedback clock signal 116. The PFD 102 may include, for example, two flip-flops coupled to an AND gate.

[0029] Charge pumps 103 and 104 convert the phase error signals 102A and 102B into charge pump output signals that include a train of positive or negative current pulses proportional to the phase error. Charge pump 103 may provide an up pulse and charge pump 104 may provide a down pulse. The duration of the up pulse is proportional to the difference, if any, between reference clock signal 101A and feedback clock signal 116. The duration of the down pulse may be pre-determined by PFD 102. For example, the delay of the down pulse may be defined by an internal circuit element of PFD 102, such as an inverter delay. When LO PLL circuit 100 using fractional synthesis is locked, the average duration of the up pulse is equal to the duration of the down pulse. By using integer-N synthesis, locking is achieved when the duration of the up pulse is equal to the duration of the down pulse.

[0030] Charge pumps 103 and 104 respond to phase error signals 102A and 102B by pumping current to loop filter 120 or pumping current from loop filter 120 to ground. Charge pumps 103 and 104 may be equally weighted current sources.

[0031] The loop filter 120 includes an amplifier 108, a capacitor C1106, a resistor R1107, a capacitor C2105, a resistor R2109, and a capacitor C3110. The loop filter 120 integrates the current pulses from the charge pumps 103 and 104 to provide a clean voltage signal 120A to the VCO 111. The active loop filter topology using the op-amp 108 also allows the loop filter 120 to reach a higher tuning voltage while ensuring a good bias margin for the charge pump current source. The active filter includes an amplifier 108, a capacitor C1106, a resistor R1107, and a capacitor C2105, and the active filter controls the voltage signal 120A. The capacitor C2105 filters high frequency noise spurs caused by sampling. The resistor R1107 provides stability by isolating the phase correction component of the error signal from the frequency correction component. The passive low pass filter includes resistor R2 109 and capacitor C3 110 to remove high frequency jitter.

[0032] The voltage signal 120A from the loop filter 120 drives the VCO 111. The VCO 111 outputs a frequency based on the voltage signal 120A. For example, when the voltage signal 120A rises, the frequency of the VCO 111 may increase, and when the voltage signal 120A falls, the frequency of the VCO 111 may decrease. The VCO output 112 is fed back to the LO PLL circuit 100.

[0033] In the feedback loop of the LO PLL circuit 100, the VCO output 112 is received by a divider buffer 113. The output of the divider buffer 113 is received by a feedback divider 114. The feedback divider 114 also receives a modulation signal 115A from a sigma-delta modulator 115. The feedback divider 114 functions as an adjustable frequency divider, and the control for the feedback divider 114 is provided by the modulation signal 115A from the sigma-delta modulator 115. The sigma-delta modulator 115 provides a certain density of pulses, which represents the average value of the signal over a certain period of time. The modulation signal 115A from the sigma-delta modulator 115 is the divider coefficient of the feedback divider 114, which allows for fractional-N synthesis. A feedback clock signal 116 is provided to the sigma-delta modulator 115 and the PFD 102, where the process begins again.

[0034] The fractional synthesis of FIG. 1 may be explained by the following example. In a PLL that has a reference clock of 19.68 MHz and can be tuned from 2.402 GHz to 2.480 GHz in 1 MHz steps, if the divider factor N is set to 122, the PLL outputs 2.40096 GHz, and if the divider factor N is set to 123, the PLL outputs 2.42064 GHz. If the desired output is 2.403 GHz, the divider factor N may be required to be a non-integer value between 122 and 123. This cannot be directly implemented, since the divider factor must be an integer value. However, the divider factor may be updated every reference period, so that the divider factor is switched between N=122 and N=123, such that the average factor over many reference periods converges to the desired N value between 122 and 123. The modulation from the sigma-delta modulator 115 provides the average factor to converge to the desired N value.

[0035] FIG. 1 shows an example timing diagram for reference clock signal 101A and feedback clock signal 116. In this example, the modulation orders from sigma-delta modulator 115 are N, N+1, N-1, and N-2, giving frequencies between four division ratios. FIG. 1 only shows N-2, N-1, and N+1. The timing diagram in FIG. 1 discloses the difference between reference clock signal 101A and feedback clock signal 116 over three division ratios.

[0036] 1, the divider circuitry, including feedback divider 114, divider buffer 113, and sigma-delta modulator 115, consumes most of the power in the PLL. For example, LO PLL circuitry 100 may consume approximately 7 mA of power, while the divider circuitry may consume approximately 4 mA of the 7 mA.

[0037] 2A is a circuit diagram of a LO PLL circuit 200 according to some aspects of the disclosure. A reference clock signal 201A is received by a PFD 202. The reference clock signal 201A from a reference clock 201 is a stable and accurate frequency reference to which the output is phase locked. The reference clock signal 201A may be derived, for example, from a crystal oscillator or a temperature controlled crystal oscillator. The clock reference 201 is received by a retimer 216. The retimer 216 also receives a VCO output signal 212. The retimer 216 generates a retime clock signal 216A that provides the phase information of the VCO 211 to the PFD 202 at the precise phase detection time. For example, the retimer 216 latches when the reference clock 201 is high and the VCO output signal 212 goes high. Similarly, retime clock signal 216A goes low, for example, when reference clock signal 201A is low and VCO output signal 212 goes low. As a result, phase information from VCO 211 is captured and comprises retime clock signal 216A, which can be used in a feedback loop to adjust the output of VCO 211. The function of retimer 216 is further described below with reference to FIG. 2B.

[0038] Retime clock signal 216A is provided to multiplexer 215. Multiplexer 215 also receives feedback divider signal 214A from feedback divider 214. Multiplexer 215 selects between retime clock signal 216A and feedback divider signal 214A. In one example, when feedback divider 214 is disabled, multiplexer output 215A includes retime clock signal 216A. In one example, when feedback divider 214 is enabled, multiplexer output 215A includes feedback divider signal 214A.

[0039] The PFD 202 receives the reference clock signal 201A and the multiplexer output 215A. The PFD 202 compares the multiplexer output 215A with the reference clock signal 201A and derives a phase error signal between the multiplexer output 215A and the reference clock signal 201A. As described above with reference to FIG. 1, the charge pumps 203 and 204 convert the phase error signals 202A and 202B from the PFD 202 into a train of positive or negative current pulses proportional to the phase error. The current pulses from the charge pumps 203 and 204 are filtered by the loop filter 220, which includes an amplifier 208, a capacitor C1 206, a resistor R1 207, a capacitor C2 205, a resistor R2 209, and a capacitor C3 210. The voltage signal 220A from the loop filter 220 is input to the VCO 211 to control the VCO output signal 212, as described above with reference to FIG. 1. In one example, the loop filter 220 may include fewer components than those listed here. For example, the loop filter 220 may exclude the passive filter including resistor R2 209 and capacitor C3 210.

[0040] In one example, the LO PLL circuit 200 may include means for disabling the feedback divider 214 and operating the LO PLL circuit in a divider disabled mode. The feedback divider 214 may be disabled to conserve power. For example, when the wireless device is in a sleep mode, the wireless device may enter a low power operating mode or a sniffer / listen mode to conserve power. In the low power operating mode or sleep mode, the LO PLL circuit 200 may disable the feedback divider 214. Then, in one example, a signal may be received indicating that the wireless device is "wake-up" to receive a message, so that the divider disabled mode is turned off or removed to allow the feedback divider 214 to resume normal operation. The feedback divider 214 may be disabled, for example, by a switch at node 217, and the VCO output signal 212 is switched between the feedback divider 214 and the retimer 216. A signal received by LO PLL circuit 200 or at a switch may indicate that LO PLL circuit 200 is to operate in a divider disabled mode, for example, by switching VCO output signal 212 to retimer 216. In another example, feedback divider 214 may be disabled using a buffer or inverter (not shown) between divider buffer 213 and node 217. In one example, the buffer or inverter may include an output enable function that receives a signal to operate in a divider disabled mode that may be used to disable divider buffer 213 and feedback divider 214 from receiving VCO output signal 212. This effectively disables feedback divider 214 and divider buffer 213. In one example, a buffer or inverter may be placed between retimer 216 and node 217 to disable or enable VCO output signal 212 to retimer 216. These are exemplary means by which feedback divider 214 may be disabled to conserve power and are not intended to limit the disclosure. Any means of controlling the VCO output signal 212 to disable the feedback divider 214 is contemplated.The means for disabling the feedback divider 214 may be controlled by software, hardware, or a combination of hardware and software.

[0041] In one embodiment, when LO PLL circuit 200 is in listen mode or sniffer mode, feedback divider 214 may operate in a divider disabled mode, disabled using any one or more of the above means, thereby conserving energy. LO PLL circuit 200 is configured, for example, by the above means, such that VCO output signal 212 may be received by retimer 216 when feedback divider 214 is disabled.

[0042] 2B is a timing diagram 250 in accordance with some aspects of the disclosure. Timing diagram 250 illustrates a reference clock signal 201A, a VCO output signal 212, a retime clock signal 216A, an up pulse signal 254, and a down pulse signal 255. In one example, reference clock signal 201A is slower than VCO output signal 212.

[0043] Retimer 216 receives reference clock signal 201A from clock reference 201 and VCO output signal 212 from VCO 211. Retimer 216 outputs retime clock signal 216A. Retimer 216 may include one or more latches. When reference clock signal 201A goes high and VCO output signal 212 goes high, retimer 216 latches VCO output signal 212 and retime clock signal 216A from retimer 216 goes high. When reference clock signal 201A goes low and VCO output signal 212 goes low, retime clock signal 216A from retimer 216 goes low.

[0044] Referring now to up pulse signal 254, an up pulse is triggered when reference clock signal 201A goes high, and the up pulse goes low when retime clock signal 216A goes high, so the width of up pulse signal 254 is proportional to the phase difference between reference clock signal 201A and retime clock signal 216A.

[0045] Referring now to the down pulse signal 255, in one example, the PFD 202 predefines the width of the down pulse signal. For example, but not limited to, a component of the PFD 202, such as an inverter, may define the down pulse signal 255. In one example, the down pulse signal 255 may be defined by other hardware, software, or a combination of hardware and software.

[0046] In integer N synthesis, when the width of the up pulse signal 254 is equal to the width of the down pulse signal 255, the LO PLL circuit 200 is locked.

[0047] 3A is a circuit diagram of a LO PLL circuit 300 using fractional synthesis in accordance with some aspects of the disclosure. The LO PLL circuit 300 includes a retimer 316 that may provide one or more retime clock signals. In one example, the retimer 316 provides a first retime clock signal 321, a second retime clock signal 322, a third retime clock signal 323, and a fourth retime clock signal 324, each having a subsequent edge based on the VCO output signal 312. In one example, the second retime clock signal 322 may be delayed by one cycle of the VCO output signal 312, the third retime clock signal 323 may be delayed by two cycles of the VCO output signal 312, and the fourth retime clock signal 324 may be delayed by three cycles of the VCO output signal 312. The one or more retime clock signals may be delayed by any amount, and the above examples are not limiting.

[0048] To generate retimer clock signals 321, 322, 323, and 324, retimer 316 receives reference clock signal 301A from reference clock 301 and VCO output signal 312 from VCO 311. In this example, retimer 316 may represent four retimers. In other examples, retimer 316 may represent more or fewer retimers. Returning to FIG. 3A, reference clock signal 301A may be applied in series to the four retimers of retimer 316, so that each retimer receives VCO output signal 312 in turn. The delay caused by the series connection of reference clock signal 301A passing through each retimer provides subsequent delayed retimer clock signals 321, 322, 323, and 324 (collectively, retimer clock signals 316A) from retimer 316. For example, in the series connection of FIG. 3A, reference clock signal 301A is shown being received by retimer 325. Retimer clock signal 321 from retimer 325 is then provided to retimer 326. Retimer 326 outputs retime clock signal 322, which is received by retimer 327, which outputs retime clock signal 323. Retimer clock signal 323 is received by retimer 328, which outputs retime clock signal 324. Retimer clock signal 324 is received by retimer 329. Each retimer 325-329 may have a different effect on the respective incoming retime clock signal received. Each retimer 325-329 may delay or advance the timing.

[0049] Each of the retime clock signals 316A is determined as described above with reference to Figures 2A and 2B. When reference clock signal 301A goes high and VCO output signal 312 goes high, the retime clock signal goes high, and when reference clock signal 301A goes low and VCO output signal 312 goes low, the retime clock signal goes low. As described above, because reference clock signal 301A is received serially between one or more retimers of retimer 316, retime clock signal 316A of retimer 316 may be delayed, resulting in multiple subsequent clock edges being received by multiplexer 315.

[0050] The multiplexer 315 receives the retime clock signal 316A and the feedback divider signal 314A. The multiplexer 315 also receives a modulated signal 318A from a sigma-delta modulator 318. In one example, the modulated signal 318A is a sigma-delta modulated signal. Although the example of FIG. 3A discloses a sigma-delta modulator 318, the disclosure is not limited to sigma-delta modulation and other modulators, etc. may be used to realize fractional synthesis.

[0051] In an example where fractional synthesis uses second order modulation, there are four retime clock signals and modulated signal 318A includes four sigma-delta modulated signals received by multiplexer 315. In one example, modulated signal 318A may include modulation based on division ratios between N-1, N+1, N, and N-2. The present disclosure may be used with modulation of different orders.

[0052] The multiplexer 319 receives the feedback divider signal 314A and the reference clock signal 301A. In one example, the multiplexer 319 outputs the modulator input signal 319A to the sigma-delta modulator 318. The modulator input signal 319A acts as a clock signal for the sigma-delta modulator 318. When the feedback divider 314 is disabled, the multiplexer 319 allows the sigma-delta modulator 318 to continue to provide the modulated signal 318A to the multiplexer 315. For example, when the feedback divider 314 is enabled, the modulator input signal 319A includes the feedback divider signal 314A. When the feedback divider 314 is disabled, the modulator input signal 319A includes the reference clock signal 301A. Thus, the LO PLL circuit 300 continues to function even when the feedback divider 314 is disabled.

[0053] Retime clock signal 316A is provided to multiplexer 315, which also receives feedback divider signal 314A from feedback divider 314. Multiplexer 315 selects between retime clock signal 316A and feedback divider signal 314A. When feedback divider 314 is disabled, multiplexer 315 outputs one of retime clock signals 321, 322, 323, and 324. As will be explained in more detail with reference to FIG. 3B below, multiplexer 315 outputs the retime clock signal (321, 322, 323, and 324) that aligns with the correct edges of modulated signal 318A.

[0054] The PFD 302 receives the reference clock signal 301A and the multiplexer output 315A from the multiplexer 315. The PFD 302 compares the reference clock signal 301A and the multiplexer output 315A and derives a phase error signal between the reference clock signal 301A and the multiplexer output 315A. As described above with reference to FIG. 1, the charge pumps 303 and 304 convert the phase error signal 302A and 302B from the PFD 302 into a train of positive or negative current pulses proportional to the phase error. The current pulses from the charge pumps 303 and 304 are filtered by the loop filter 320, which includes the amplifier 308, the capacitor C1 306, the resistor R1 307, the capacitor C2 305, the resistor R2 309, and the capacitor C3 310. A voltage signal 320A from loop filter 320 is input to VCO 311 to control the frequency and phase of VCO output signal 312 as described with reference to Figure 1. In one example, loop filter 320 may include fewer components than those listed here. For example, loop filter 320 may exclude the passive filter including resistor R2 309 and capacitor C3 310.

[0055] In one example, the LO PLL circuit 300 may include a means for disabling the feedback divider 314. For example, a switch at node 317 may be used to switch the VCO output signal 312 between the feedback divider 314 and the retimer 316. In another example, the feedback divider 314 may be disabled using a buffer or inverter (not shown) between the divider buffer 313 and node 317. In one example, the buffer or inverter may include an output enable function that may be used to disable the divider buffer 313 and the feedback divider 314 from receiving the VCO output signal 312, thereby effectively disabling the feedback divider 314 and the divider buffer 313. In one example, a buffer or inverter may be placed between the retimer 316 and node 317 to disable or enable the VCO output signal 312 to the retimer 316. These are exemplary means by which the feedback divider 314 may be disabled to conserve power and are not intended to limit the disclosure. Any means of controlling the VCO output signal 312 is contemplated to disable the feedback divider 314. The means of disabling the feedback divider 314 may be controlled by software, hardware, or a combination of hardware and software.

[0056] In one embodiment, when LO PLL circuit 300 is in listen or sniffer mode, feedback divider 314 may be disabled using any one or more of the means described above, thereby conserving energy. LO PLL circuit 300 is configured, for example, by the means described above, such that when feedback divider 314 is disabled, VCO output signal 312 is received by retimer 316.

[0057] 3B is a timing diagram 350 illustrating a reference clock signal 301A and a VCO output signal 312 in accordance with some aspects of the disclosure. In an example using secondary modulation in which a sigma-delta modulator 318 switches an N counter between four different values, the VCO output signal 312 is delayed in a retimer 316 to generate retime clock signals 321, 322, 323, and 324. As discussed above, each retime clock signal may then be delayed by an equal or other amount.

[0058] For each sigma-delta modulation value (N-1, N-2, N, N+1) in Figure 3B, when the feedback divider 314 is disabled, a retime clock signal may be output to the PFD 302, where the edges of the retime clock signal are aligned with the corresponding sigma-delta modulation. Referring to Figure 3B, in one example, at N-1, the exact edge 358 is an edge of the retime clock signal 323, so that the multiplexer output 315A includes the retime clock signal 323. At N+1, the exact edge 359 is an edge of the retime clock signal 322, so that the multiplexer output 315A includes the retime clock signal 322. At N, the exact edge 360 ​​is again an edge of the retime clock signal 323, so that the multiplexer output 315A includes the retime clock signal 322. Through this process, retime clock signals 321, 322, 323, and 324 maintain the phase information of VCO output signal 312 so that fractional synthesis can be performed when feedback divider 314 is disabled. Additionally, VCO output signal 312 to retimer 316 may be disabled after generation of retime clock signal 324 and re-enabled when reference clock signal 301A goes high to conserve power consumption in retimer 316.

[0059] FIG. 4 is a timing diagram 400 according to some aspects of the disclosure illustrating the difference between fractional synthesis and integer synthesis as described above with reference to FIGS. 3A and 3B. FIG. 4 shows a reference clock signal 401, a VCO output signal 402, and a retime clock signal 403 as described above with reference to FIGS. 2B and 3B. In integer synthesis, lock is achieved by the PLL in the LO when the width of the up pulse train 404 is equal to the width of the down pulse train 405. In fractional synthesis as disclosed with reference to FIGS. 3A and 3B, lock is achieved by the PLL in the LO when the average width of the up pulse train 406 is equal to the width of the down pulse train 407.

[0060] The operation of the receiver is further described with reference to Figures 2A, 3A, and 5. Figure 5 is a flow chart of a method 500 for implementing local oscillation in accordance with certain aspects of the present disclosure. The method 500 is suitable for implementation by the LO PLL circuit 200 of Figure 2 and the LO PLL circuit 300 of Figure 3, or other suitable integrated circuits. The processes of the method 500 may be implemented in an order other than that described, and the processes may be implemented simultaneously in parallel. Also, in some examples of the present disclosure, the processes of the method 500 may be omitted or substituted.

[0061] 2A and 3A, feedback divider 314 of LO PLL circuit 300 and feedback divider 214 of LO PLL circuit 200 may be disabled. Feedback dividers 314 and 214 may be disabled by any one or more of the means described above with reference to FIGURES 2A and 3A, including using switches or other logic circuit elements that disconnect feedback dividers 314 and 214 and divider buffers 313 and 213, respectively, from VCO output signals 312 and 212. Additional hardware, software, and / or a combination of hardware and software may be used to disable feedback dividers 314 and 214 and divider buffers 313 and 213 so that they do not use power.

[0062] 2A and 3A, reference clock signal 201A is received by retimer 216 of FIG. 2A, and reference clock signal 301A is received by retimer 316 of FIG. 3A.

[0063] Referring to block 506, the retimers 316 and 216 receive the VCO output signal 312 and the VCO output signal 212, respectively.

[0064] Referring to block 508 and FIG. 3A, retimer 316 generates retime clock signal 316A. As described above with reference to FIG. 3A, retime clock signal 316A may include retime clock signals 321, 322, 323, and 324, each having a subsequent edge based on VCO output signal 312. When reference clock signal 301A goes high and VCO output signal 312 goes high, the retime signal goes high, and when reference clock signal 301A goes low and VCO output signal 312 goes low, the retime signal goes low. As described above, because reference clock signal 301A is received serially between one or more retimers of retimer 316, the output of retimer 316 may be delayed to generate multiple subsequent VCO clock edges that are used in the fractional synthesis process disclosed herein to determine an error between a selected clock edge of VCO output signal 312 and reference clock signal 301A.

[0065] 2A, the retimer 216 generates a retime clock signal 216A that provides the phase information of the VCO 211 to the PFD 202 at the correct phase detection time. For example, the retimer timer 216 latches when the reference clock signal 201A is high and the VCO output signal 212 goes high. Similarly, the retime clock signal 216A goes low, for example, when the reference clock signal 201A is low and the VCO output signal 212 goes low. The result is the retime clock signal 216A generated by the retimer 216 based on the reference clock signal 201A and the VCO output signal 212.

[0066] 3A and 3B, multiplexer 315 receives retime clock signal 316A from retimer 316 and modulated signal 318A from sigma-delta modulator 318. Modulated signal 318A is multiplexed with retime clock signal 316A from retimer 316, and a retime clock signal 321, 322, 323, or 324 that aligns with the correct edges of modulated signal 318A is generated by multiplexer 315 as multiplexer output 315A that is received by PFD 302.

[0067] Referring to block 512, FIG. 2A, and FIG. 3A, an error signal is determined based on the retime clock signal. In FIG. 2A, the PFD 202 receives the reference clock signal 201A and the multiplexer output 215A. The PFD 202 compares the reference clock signal 201A with the multiplexer output 215A and derives phase error signals 202A and 202B between the reference clock signal 201A and the multiplexer output 215A. In FIG. 3A, the PFD 302 receives the reference clock signal 301A and the multiplexer output 315A. The PFD 302 compares the reference clock signal 301A with the multiplexer output 315A and derives phase error signals 302A and 302B between the reference clock signal 301A and the multiplexer output 315A.

[0068] Referring to block 514, FIG. 2A, and FIG. 3A, a phase error signal between a reference clock signal and a retime clock signal based on the VCO output signal is used to adjust the VCO, thereby adjusting the frequency and phase of the VCO output signal. In one example, the phase error signal from the PFD can be amplified and filtered as described above. Referring to FIG. 2A, voltage signal 220A represents the phase error, and voltage signal 220A controls VCO output signal 212 as described with reference to FIG. 1. Referring to FIG. 3A, voltage signal 320A represents the phase error, and voltage signal 320A controls VCO output signal 312 as described with reference to FIG.

[0069] The LO PLL circuits 200 and 300 or other integrated circuit devices may implement the processes of the method 500 using any combination of dedicated hardware and instructions stored on a non-transitory medium. Thus, the elements of the LO PLL circuits 200 and 300 may include processing resources coupled to a non-transitory computer-readable medium. The processing resources may include one or more microcontrollers, ASICs, CPUs, GPUs, and / or other processing resources configured to execute instructions stored on the non-transitory computer-readable medium. Examples of suitable non-transitory computer-readable media include one or more flash memory devices, battery-backed RAM, SSDs, HDDs, optical media, and / or other memory devices suitable for storing instructions for the processing resources.

[0070] It will be understood that the present disclosure provides many illustrative embodiments and that modifications to these embodiments are possible. Such modifications are expressly included within the scope of the present disclosure. Also, the application of these teachings to other environments, applications, and / or purposes is consistent with and contemplated by the present disclosure.

[0071] The term "coupled" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain operation, or in a second example, device A is coupled to device B via an intervening component C if the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

Claims

1. 1. An integrated circuit device, comprising: a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal and to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal; a first multiplexer configured to receive the first retime clock signal and to provide a feedback clock signal; and a phase frequency detector (PFD) configured to receive the feedback clock signal and the reference clock signal and to provide an error signal in response to the feedback clock signal and the reference clock signal; a voltage controlled oscillator (VCO) configured to receive a voltage signal based on the error signal and to provide the VCO output signal in response to the voltage signal; 1. An integrated circuit device comprising:

2. 2. The integrated circuit device of claim 1, a charge pump configured to receive the error signal and to provide a charge pump output signal; a filter configured to receive the charge pump output signal and to provide the voltage signal; and the feedback divider configured to receive the VCO output signal and provide a feedback divider signal to the first multiplexer and to be disabled; The integrated circuit device further comprises:

3. 3. An integrated circuit device according to claim 2, comprising: the feedback divider is further configured to receive a modulated signal; The integrated circuit device, wherein the first multiplexer is further configured to receive the modulated signal.

4. 4. An integrated circuit device according to claim 3, The integrated circuit device further comprising a modulator configured to provide the modulated signal, the modulator being a sigma-delta modulator.

5. 5. An integrated circuit device according to claim 4, The integrated circuit device further comprising a second multiplexer configured to receive the reference clock signal and the feedback divider signal and to provide a clock input signal to the modulator.

6. 2. The integrated circuit device of claim 1, a second retimer configured to receive the first retime clock signal, the reference clock signal, and the VCO output signal, and to provide a second retime clock signal in response to the reference clock signal and the VCO output signal; a third retimer configured to receive the second retime clock signal, the reference clock signal, and the VCO output signal, and to provide a third retime clock signal in response to the reference clock signal and the VCO output signal; a fourth retimer configured to receive the third retime clock signal, the reference clock signal, and the VCO output signal, and to provide a fourth retime clock signal in response to the reference clock signal and the VCO output signal; The integrated circuit device further comprises:

7. 7. An integrated circuit device according to claim 6, The integrated circuit device, wherein the first multiplexer is further configured to receive the second, third and fourth retime clock signals.

8. 8. An integrated circuit device according to claim 7, The integrated circuit device, wherein the first multiplexer is further configured to provide a feedback clock signal based on the first, second, third and fourth retime clock signals.

9. 4. An integrated circuit device according to claim 3, The integrated circuit device, wherein the feedback divider is further configured to be disabled in response to a low power mode of operation.

10. 3. An integrated circuit device according to claim 2, comprising: The integrated circuit device further includes a divider buffer coupled to the feedback divider.

11. 3. An integrated circuit device according to claim 2, comprising: The integrated circuit device, wherein the filter comprises an active filter.

12. 2. The integrated circuit device of claim 1, The error signal includes an up pulse or a down pulse.

13. 1. An integrated circuit comprising: a first retimer including a first input coupled to a reference clock, a second input, and an output; a first multiplexer including a first input coupled to an output of the first retimer, a second input, and an output; a phase frequency detector (PFD) including a first input coupled to the reference clock, a second input coupled to an output of the first multiplexer, and an output; a charge pump including an input coupled to an output of the PFD and an output; a filter including an input coupled to an output of the charge pump and an output; a voltage controlled oscillator (VCO) including an input coupled to an output of the filter and an output coupled to a second input of the first retimer; 4. An integrated circuit comprising:

14. 14. An integrated circuit according to claim 13, comprising: a feedback divider including a first input coupled to the output of the VCO and an output coupled to a second input of the first multiplexer; a modulator including an input and an output coupled to a second input of the feedback divider; The integrated circuit further comprises:

15. 15. An integrated circuit according to claim 14, comprising:

2. The integrated circuit further comprising: a second multiplexer, the second multiplexer including a first input coupled to the reference clock, a second input coupled to the output of the feedback divider, and an output coupled to the input of the modulator.

16. 16. An integrated circuit according to claim 15, comprising: a second retimer including an input coupled to the reference clock and an output coupled to the first multiplexer; a third retimer including an input coupled to the reference clock and an output coupled to the first multiplexer; a fourth retimer including an input coupled to the reference clock and an output coupled to the first multiplexer; The integrated circuit further comprises:

17. 1. A method comprising: receiving a reference clock signal and a voltage controlled oscillator (VCO) output signal by a retimer; retiming the reference clock signal according to the VCO output signal by the retimer to generate a retimed clock signal; determining an error signal based on the retime clock signal and the reference clock signal by a phase frequency detector (PFD); modifying the VCO output signal based on the error signal; A method comprising:

18. 20. The method of claim 17, The method, wherein the retime clock signals include a first retime clock signal based on the reference clock signal and the VCO output signal, a second retime clock signal based on the reference clock signal and the VCO output signal, a third retime clock signal based on the reference clock signal and the VCO output signal, and a fourth retime clock signal based on the reference clock signal and the VCO output signal.

19. 20. The method of claim 17, receiving the retime clock signal by a multiplexer; receiving a feedback divider signal by the multiplexer; receiving a modulated signal from a modulator by said multiplexer; Further comprising: The multiplexer is configured to output the error signal.

20. 20. The method of claim 19, Receiving a signal to operate in a divider disabled mode; disabling the feedback divider signal in response to receiving the signal to operate in the divider disabled mode; The method further comprises:

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