An instruction packing scheme for VLIW CPU architectures.

Abstract

A processor is provided, the processor including a core configured to perform a decode operation on a multi-instruction packet (500) including a plurality of instructions. The decode operation includes receiving a multi-instruction packet (500) including first and second instructions (502, 504). The first instruction (502) includes a primary portion (508) and a secondary portion (510) in a fixed first location. The second instruction (504) includes a primary portion (512) in a fixed second location between the primary portion of the first instruction (502) and the secondary portion of the first instruction. An opcode portion of each of the primary portions (510, 512) of the first and second instructions is accessed and decoded. An instruction packet is created including the primary and secondary portions (508, 510) of the first instruction, and a second instruction packet is created including the primary portion (512) of the second instruction. The first and second instruction packets are dispatched to respective first and second functional units.

Description

[Technical field]

[0001] In a Very Long Instruction Word (VLIW) central processing unit (CPU), instructions are grouped into execute packets that contain multiple instructions. The instructions within a packet may be of variable size. An iterative scheme may be used to identify and decode each separate instruction. Each instruction may include a size portion and an operation code (opcode) portion. To determine the size of the opcode portion to be decoded, the decode scheme may iterate through each instruction to determine its size. The entire opcode portion is then decoded to determine what type of instruction it is and where it should be routed for further processing. After decoding an instruction, the next instruction is located and examined in a similar manner to decode its opcode portion. Summary of the Invention

[0002] According to one aspect, a processor includes a core configured to perform a decode operation on a multi-instruction packet including a plurality of instructions. The decode operation includes receiving a multi-instruction packet including a first instruction including a primary portion at a fixed first location and a secondary portion, and a second instruction including a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. The decode operation also includes accessing the primary portion of the first instruction, decoding an operation code (opcode) portion of the primary portion of the first instruction, and accessing the primary portion of the second instruction. The decode operation also includes decoding an opcode portion of the primary portion of the second instruction, creating a first instruction packet including the primary portion of the first instruction and the secondary portion of the first instruction, and creating a second instruction packet including the primary portion of the second instruction. The decode operation further includes dispatching the first instruction packet to a first functional unit and dispatching the second instruction packet to a second functional unit different from the first functional unit.

[0003] According to another aspect, a method implemented on a processor core includes receiving a first multi-instruction packet, the first multi-instruction packet including a primary portion of a first instruction at a fixed first location, a primary portion of a second instruction at a fixed second location following the fixed first location, and a secondary portion of the first instruction following the primary portion of the second instruction. The method also includes decoding an operation code (opcode) portion of the primary portion of the first instruction in the first multi-instruction packet, the primary portion of the first instruction located at a fixed first location in the first multi-instruction packet. The method also includes decoding an operation code ("opcode") portion of the primary portion of the first instruction, decoding an opcode portion of the primary portion of the second instruction, and accessing the secondary portion of the first instruction. The method further includes creating a first instruction packet including the primary and secondary portions of the first instruction, and dispatching the first instruction packet and the second instruction to separate functional units, respectively. [Brief description of the drawings]

[0004] In the drawings:

[0005] [Figure 1] 1 is a block diagram of a processor for receiving, decoding, and dispatching instructions according to an example.

[0006] [Diagram 2] FIG. 2 is a block diagram illustrating 16-bit CPU instructions, according to an example.

[0007] [Diagram 3] FIG. 2 is a block diagram illustrating 32-bit CPU instructions, according to an example.

[0008] [Figure 4] FIG. 2 is a block diagram illustrating 48-bit CPU instructions, according to an example.

[0009] [Diagram 5]FIG. 2 is a block diagram illustrating an instruction packet of multiple instructions according to an example.

[0010] [Figure 6] 1 is a flow chart of a decoding scheme according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 illustrates a block diagram of a central processing unit or processor 100 according to an example. As illustrated, the processor 100 includes a core 102, which includes a pre-fetch instruction buffer 104, a decoder 106, and one or more functional units 108, such as a comparator, a control unit, an arithmetic logic unit (ALU), etc. The core 102 may also include other hardware components, such as a subtractor, fetch logic, etc. The core 102 may execute various machine instructions 110 of an instruction set 112, which may be stored in a memory within the core 102 or may be otherwise accessible to the core 102. The machine instructions 112 include an instruction set that includes various operations to be performed. During the course of executing a program, the instruction buffer 104 may receive instruction packets from a memory 114 external to the processor 100.

[0012] The decoder 106 includes decode logic 116 that decodes each instruction packet as described herein. Following decoding, a dispatch unit 118 sends each instruction to its designated functional unit for execution. In one example, the processor 100 operates as a very long instruction word (VLIW) processor that can operate multiple instructions simultaneously in corresponding functional units. Preferably, a compiler organizes the instructions in multi-instruction packets that are executed together. The instruction dispatch unit 118 directs each instruction to a target functional unit 108. In one example, the instruction dispatch unit 118 can operate on multiple instructions in parallel, such as having at least a portion of each instruction processed simultaneously. The number of such parallel instructions can be set by the number of instructions in the multi-instruction packet. The packet size calculation unit 120 keeps track of each instruction packet forwarded from the instruction buffer 104.

[0013] 2 illustrates a CPU instruction 200 having a 16-bit format. The instruction 200 includes a link portion 202 having 1 bit, a size portion 204 having 2 bits, and an opcode portion 206 having 13 bits. The link portion 202 indicates whether the instruction 200 is the last instruction in an instruction packet of multiple instructions, or whether there are additional instructions in the instruction packet following the instruction 200. For example, a value of 0b1 (e.g., a single bit with a binary value of 1) may indicate that there is at least one additional instruction in the packet following the current instruction, while a value of 0b0 may indicate that the current instruction is the last instruction in the packet, or vice versa. The size portion 204 indicates the size of the instruction 200. In an instruction set in which the instruction 110 can be one of multiple sizes (e.g., one of three sizes: 16 bits, 32 bits, or 48 bits), the size portion 204 may be, for example, 2 bits to indicate the size of the current instruction. In one example, a bit code of 0b00 may indicate that the instruction size is 16 bits, 0b01 may indicate that the instruction size is 32 bits, and 0b10 may indicate that the instruction size is 48 bits. Other implementations are possible. Opcode portion 206 includes an operation code that provides the instruction to be executed by instruction 200 and includes any additional information associated with the opcode, such as operands. Portions 202, 204, 206 together occupy 16 bits of instruction 200 and form a primary portion 208 of instruction 200.

[0014] 3 shows a CPU instruction 300 having a 32-bit format, including a link portion 302, a size portion 304, and an opcode portion 306. The link portion 302 and the size portion 304, similar to the link portion 202 and the size portion 204 of the instruction 200, respectively indicate whether additional instructions follow and indicate the size of the instruction 300. The opcode portion 306 occupies 29 bits in the 32-bit instruction 300. As shown in FIG. 3, the first 13 bits of the opcode portion 306, together with the link portion 302 and the size portion 304, form the primary portion 308 of the instruction 300. The remaining 16 bits of the opcode portion 306 that are not included in the primary portion 308 form the secondary portion 310 of the instruction 300.

[0015] 4 shows a CPU instruction 400 having a 48-bit format, including a link portion 402, a size portion 404, and an opcode portion 406. The link portion 402 and the size portion 404 indicate whether additional instructions follow and indicate the size of the instruction 400, respectively, similar to the link portion 202 and the size portion 204 of the instruction 200. The opcode portion 406 occupies 45 bits in the 48-bit instruction 400. As shown in FIG. 4, the first 13 bits of the opcode portion 406, together with the link portion 402 and the size portion 404, form a primary portion 408 of the instruction 400. The remaining 32 bits of the opcode portion 406 that are not included in the primary portion 408 form a secondary portion 410 of the instruction 400.

[0016] 1-4, machine instruction set 112 includes at least one instruction having a format based on one of instructions 200, 300, and 400. However, in a machine instruction set 112 having many instructions, two or all formats of the three instructions 200, 300, and 400 may be represented. Machine instruction set 112 may include multiple separate instructions of one or more of the formats of instructions 200, 300, and 400, such that there may be one or more 16-bit instructions (based on instruction 200), one or more 32-bit instructions (based on instruction 300), and / or one or more 48-bit instructions (based on instruction 400) in set 112. Also, the bit lengths in machine instruction set 112 are not limited to the 16-bit, 32-bit, or 48-bit examples provided herein, but may include bit lengths of any size.

[0017] As described above, the first 13 bits of the opcode portion 206, 306, 406 of the instruction 200, 300, 400, together with the respective link portion 202, 302, 402 and size portion 204, 304, 404, form the primary portion 208, 308, 408. These first 13 bits contain instructions where a reduction in the amount of time required to identify, decode, and transmit the bits for further processing leads to an increase in CPU speed and performance. Thus, the CPU can operate more quickly because the 13 bits can be identified, decoded, and processed more quickly. Any remaining bits of the instruction in the secondary portion do not need to be decoded as part of the decoding process to determine where the instruction needs to be routed (e.g., to a particular functional unit 108). Instead, the secondary portion information can be provided to the respective functional unit to execute the instruction without spending time decoding the secondary portion. In this way, the processor 100 avoids decoding the secondary portion when decoding the instructions 200, 300, 400 to determine where the instructions 200, 300, 400 should be dispatched.

[0018] 5 is a diagram illustrating an example multi-instruction packet 500 of a plurality of instructions, according to one example. The multi-instruction packet 500 includes three instructions selected from the machine instruction set 112, including a first 48-bit instruction 502, a second 32-bit instruction 504, and a third 16-bit instruction 506. As shown, the instruction 502 is divided into two segments, a primary segment 508 at the beginning of the multi-instruction packet 500, and a secondary segment 510 following the instruction 506. The instruction 504 is also divided into two segments, a primary segment 512 following the primary segment 508 of the instruction 502, and a secondary segment 514 following the secondary segment 510 of the instruction 502. Finally, the instruction 506 includes a primary segment 516 following the primary segment 512 of the instruction 504. Because the instruction 506 is a 16-bit instruction, an additional segment for a secondary opcode is not included in the multi-instruction packet 500. The example multi-instruction packet 500 illustrated in FIG. 5 includes three instructions, although instruction packets including one or more instructions within the packet are also contemplated.

[0019] FIG. 6 is a flow chart illustrating a decoding technique 600 that may be performed by a decoder (e.g., decoder 106 of FIG. 1) according to an example. With reference to FIGS. 5 and 6, a multi-instruction packet 500 is received, for example, from instruction buffer 104 at step 602. As shown in FIG. 5, primary segments 508, 512, 516 are contiguously placed at the beginning of multi-instruction packet 500. According to some examples, the primary segments of all instructions in the multi-instruction packet are contiguously placed at the beginning of the instruction packet, followed by any secondary segments. At step 604, the start of the first or next instruction is determined. When executed for the first time, an instruction start flag may be evaluated to indicate that the next instruction to be decoded begins at bit 0. At step 606, a link portion of the first instruction 502, labeled "L0" in FIG. 5 (e.g., a link portion corresponding to link portion 402 illustrated in FIG. 4) is accessed and decoded based on the instruction start flag to determine whether additional instructions follow the instruction. Because the first instruction 502 is not the only instruction in the example shown in FIG. 5, the link portion indicates that at least one additional instruction follows. Such an indication may be indicated, for example, by a value of 0b1. Next, the size portion of the first instruction 502, labeled "S0" in FIG. 5 (e.g., the size portion corresponding to size portion 404 shown in FIG. 4), is accessed and decoded in step 608. Knowing where the link portion L0 is located, the size portion is known to be, for example, the next two bits. Because the primary portion or segment 508 of the instruction 502 includes the 13 bits following the size portion S0, the opcode primary portion of the first instruction 502, labeled "OP0 primary" in FIG. 5 (e.g., the opcode portion corresponding to opcode portion 406 shown in FIG. 4), is accessed and decoded in step 610.

[0020] For the first 48-bit instruction 502, because there is an additional 32-bit opcode in the secondary portion 510, the decoder 106 knows that additional opcode bits for instruction 502 can be found in the multi-instruction packet 500. However, obtaining this additional opcode is deferred until all primary segments have been decoded, which may result in reduced processing time and therefore improved CPU speed and performance.

[0021] At step 612, the method 600 determines whether an additional instruction follows the recently decoded instruction in the current instruction packet based at least in part on the link portion of the recently decoded instruction. In the example shown in FIG. 5, at least instructions 504 and 506 follow instruction 502. Thus, additional instructions follow at 614, so the method 600 returns to step 604 to begin decoding the next instruction. Because each primary interval 508, 512, 516 is 16 bits long, the decoder (e.g., decoder 106 of FIG. 1) knows that the next instruction starts 16 bits after the link portion of the previous instruction. Thus, determining the start of the next instruction involves adding 16 to the start of the previous instruction. In this manner, the CPU processing operations used to determine the start bit of the subsequent instruction based on the size of the previous instruction (e.g., the subsequent instruction does not start at a fixed position) can be avoided.

[0022] In the example shown in FIG. 5, the second instruction 504 begins at bit 16. Thus, without basing the determination of the start of instruction 504 on the size of the first instruction 502, the link portion L1 can be read at the start bit position (step 606), the size portion S1 can be read at the two bits following the start bit position L1 (step 608), and the opcode portion OP2 can be read at the 13 bits following the size portion S1 (step 610). Thus, instruction 504 can be quickly identified and subsequently decoded without using an operationally expensive method to determine the start of instruction 504 based on the size of the previous instruction. Similar to instruction 502, instruction 504 includes an additional opcode in secondary segment 514, the retrieval of which is deferred until all primary segments have been decoded.

[0023] Because the third instruction 506 follows the second instruction 504, the link portion L1 of the second instruction 504 indicates that at least one additional instruction follows the second instruction 504. Thus, the method 600 returns (614) to step 604 again to decode the third instruction 506 according to the steps outlined above in steps 604-610.

[0024] Following the decoding of the third instruction 506, a determination of whether additional instructions follow (at step 612) indicates that the third instruction 506 was the last instruction. Thus, the method 600 moves 616 to step 618 to create a complete instruction packet for each instruction 502, 504, 506. For instructions 502, 504, their primary and secondary portions are combined. Thus, based on the decoded size portions 204, 304, 404, the method 600 can determine the length of any secondary portions 310, 410 to be combined with their respective primary portions 308, 408. At step 620, the generated instruction packets are sent to the appropriate functional units 108, for example, by dispatch unit 118 (FIG. 1).

[0025] Multi-instruction packets, such as those described herein, include instructions that are executed in parallel or substantially simultaneously. However, the size of the instruction buffer 104 (FIG. 1) may be larger than a particular multi-instruction packet. For example, the instruction buffer 104 may be a 128-bit register that can hold, for example, a single 128-bit multi-instruction packet. In another example, the instruction buffer 104 can hold eight single-instruction 16-bit packets. It is contemplated that in some examples the size of the instruction buffer 104 may be larger or smaller than 128 bits. If less than all bits of the instruction buffer 104 are used for one single or multi-instruction packet, the packet size calculation unit 120 (FIG. 1) may track and identify where the most recent single or multi-instruction packet ends and / or where the next single or multi-instruction packet begins. Decode logic 116 (FIG. 1) may examine the remainder of instruction buffer 104 following each successfully decoded single or multiple instruction packet to determine, for example, whether the second and third bits following the last decoded single or multiple instruction packet include a size indicator to indicate whether additional instruction packets are to follow. If such additional instructions are to follow, decoder 106 (FIG. 1) may decode the next instruction packet (sent with the previous instruction packet) without the instruction buffer 104 having to be reloaded with the next instruction packet from memory storage.

[0026] Additional timing savings can be achieved by ensuring that the placement or ordering of instructions within each multi-instruction packet is by size. For example, decoding time can be reduced by encoding each packet such that the instruction sizes follow from largest to smallest. An example packet encoding table is shown below: TIFF2024502606000002.tif9150

[0027] For each instruction in Table 1, an example of the ordering of instructions (I0-I7) in various instruction packets (P1-P10) occupying all bits of the 128-bit instruction buffer is shown as an example. If one ensures that the possible instructions (IQ-I7) in each packet are ordered from largest to smallest, it is possible to reduce CPU decode time based on encountering a 16-bit instruction in a particular packet. For example, in instruction packet P2 in Table 1, the first 16-bit instruction is encountered in instruction I2. Because the instructions are ordered from largest to smallest in length, the decode technique 600 can know that any subsequent instructions in the same instruction packet are also 16-bit, and therefore does not need to decode the size portion of any subsequent instructions. Thus, for instruction packet P2, the decode of instruction I3 can skip its size decode. Similarly, instruction packets P4-P5 and P7-P10 can avoid instruction size decode after the first 16-bit instruction is identified.

[0028] Although the instruction packets (P1-P10) in Table 1 are shown using all 128 bits (or all bits of the instruction buffer 104), other instruction packets may be transferred from the instruction buffer that do not use all 128 bits. For example, an instruction packet may contain a 48-bit instruction followed by three 16-bit instructions. However, the packet encoding scheme described above will work for these packets that do not use all 128 bits. Thus, after a 16-bit instruction is found, the decoding of each subsequent instruction may skip decoding the size of the instruction.

[0029] The foregoing description of various preferred embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, as many modifications and variations are possible in light of the above teachings. The illustrative embodiments as set forth above have been chosen and described in order to best explain the principles of the invention and its practical application, so that those skilled in the art may best utilize the invention with various modifications in the various embodiments as suited to the particular use contemplated. The scope of the present invention is therefore defined by the claims appended hereto.

Claims

1. 1. A processor comprising:

1. A core configured to perform a decode operation on a multi-instruction packet including a plurality of instructions, the decode operation comprising: receiving the multi-instruction packet, the multi-instruction packet comprising: a first command including a primary portion at a fixed first position and a secondary portion; a second instruction including a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction; receiving the multi-command packet, accessing a primary portion of the first instruction; Decoding an operation code (opcode) portion of a primary portion of the first instruction; accessing a primary portion of the second instruction; decoding an opcode portion of a primary portion of the second instruction; creating a first instruction packet including a primary portion of the first instruction and a secondary portion of the first instruction; creating a second instruction packet including a primary portion of the second instruction; dispatching the first instruction packet to a first functional unit; dispatching the second instruction packet to a second functional unit different from the first functional unit; A processor including the core.

2. 2. The processor of claim 1, 22. The processor of claim 21, wherein dispatching the first instruction packet to a first functional unit comprises dispatching the first instruction packet to the first functional unit based on the decoded opcode portion of a primary portion of the first instruction.

3. 2. The processor of claim 1, A processor, wherein dispatching the first instruction packet avoids decoding a secondary portion of the first instruction.

4. 2. The processor of claim 1, 22. The processor of claim 21, wherein creating the second instruction packet further comprises creating the second instruction packet including a secondary portion of the second instruction located after the secondary portion of the first instruction in the multi-instruction packet.

5. 2. The processor of claim 1, the act of decoding comprises: accessing a primary portion of a third instruction in the multi-instruction packet, the primary portion of the third instruction being located at a fixed third position in the multi-instruction packet; decoding an opcode portion of the primary portion of the third instruction; Further comprising: the fixed third position is after a fixed second position in the multi-instruction packet and before a secondary portion of the first instruction.

6. 6. The processor of claim 5, the act of decoding further includes creating a third instruction packet including a primary portion of the third instruction; a number of bits in the first instruction packet is equal to or greater than a number of bits in the second instruction packet; A processor, wherein the number of bits of the third instruction packet is equal to the number of bits of the second instruction packet.

7. 6. The processor of claim 5, the act of decoding further includes creating a third instruction packet including a primary portion of the third instruction; a number of bits in the first instruction packet is equal to or greater than a number of bits in the second instruction packet; The third instruction packet has a number of bits less than the second instruction packet.

8. 2. The processor of claim 1, A processor, wherein a number of bits in a primary portion of the first instruction is equal to a number of bits in a primary portion of the second instruction.

9. 9. The processor of claim 8, A processor, wherein the first instruction packet number of bits comprises at least 32 bits and the second instruction packet number of bits comprises at least 16 bits.

10. 2. The processor of claim 1, the act of decoding comprises: Decoding a link portion of the primary portion of the second instruction; determining whether there are additional instructions in the multi-instruction packet after the second instruction based on the decoded link portion; The processor further comprises:

11. 1. A method implemented on a processor core, comprising: receiving a first multi-instruction packet, the first multi-instruction packet comprising: a primary portion of a first instruction at a fixed first location; a primary portion of a second instruction at a fixed second location subsequent to the fixed first location; a secondary portion of the first instruction following the primary portion of the second instruction; receiving the first multi-instruction packet, Decoding an operation code ("opcode") portion of a primary portion of the first instruction; decoding an opcode portion of a primary portion of the second instruction; accessing a secondary portion of the first instruction; creating a first instruction packet including a primary and secondary portion of the first instruction; dispatching the first instruction packet and the second instruction to respective separate functional units; A method comprising:

12. 12. The method of claim 11, The method, wherein dispatching the first instruction packet and the second instruction to separate functional units comprises dispatching the first instruction packet and the second instruction in parallel to separate functional units.

13. 12. The method of claim 11, the size of the first instruction packet is one of 48 bits, 32 bits, and 16 bits; if the size of the first instruction packet is 48 bits, a size of a second instruction packet containing the second instruction is one of 48 bits, 32 bits, and 16 bits; if the size of the first instruction packet is 32 bits, the size of the second instruction packet is one of 32 bits and 16 bits; A method, wherein if the first instruction packet is 16 bits in size, then the second instruction packet is 16 bits in size.

14. 14. The method of claim 13, The method further comprising decoding a size portion of the primary portion of the first instruction to determine a size of the first instruction packet.

15. 15. The method of claim 14, The method further comprising: decoding a size portion of the secondary portion of the second instruction to determine a size of the second instruction only if a size of the first instruction packet exceeds 16 bits.

16. 12. The method of claim 11, accessing a secondary portion of the second instruction located after the secondary portion of the first instruction in the first multi-instruction packet; creating a secondary command packet including a primary and secondary portion of the secondary command; The method further comprises:

17. 17. The method of claim 16, the method further comprising: decoding an opcode portion of a primary portion of a third instruction in the first multi-instruction packet, the primary portion of the third instruction being located at a fixed third location in the first multi-instruction packet after the fixed second location and before a secondary portion of the first instruction.

18. 12. The method of claim 11, The method further comprising receiving the first multi-instruction packet from a computer memory into an instruction buffer.

19. 20. The method of claim 18, A method according to claim 1, wherein the instruction buffer is 128 bits in size.

20. 20. The method of claim 18, If the size of the first multi-instruction packet is less than the size of the instruction buffer, determining whether there is a second multi-instruction packet in the instruction buffer following the first multi-instruction packet.

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