True Single Phase Clock (TSPC) Based Latch Array

Abstract

A latch array including rows of master latches coupled to columns of slave latches, each master latch including an OR-AND inverter (OAI) gate cross-coupled with a NAND gate to receive and latch input data, each slave latch including an AND-OR inverter (AOI) gate cross-coupled with a NOR gate to receive and latch data from the master latch, and an inverter including an input coupled to the AOI gate and an output for producing output data based on the input data. Alternatively, each master latch including an AOI gate cross-coupled with a NOR gate to receive and latch input data, each slave latch including an OAI gate cross-coupled with a NAND gate to receive and latch data from the master latch, and an inverter including an input coupled to the OAI gate and an output for producing output data.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending non-provisional application Ser. No. 17 / 162,647, filed with the United States Patent and Trademark Office on January 29, 2021, and assigned to the assignee of the present application, which is expressly incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

[0003] Aspects of the present disclosure relate generally to memory devices, and more particularly to true single phase clock (TSPC) based latch arrays. [Background technology]

[0004] An integrated circuit (IC), such as a system on a chip (SOC), may include a memory device for storing data that is being processed and / or will be processed by one or more digital processing cores. In some cases, the memory device is configured as a static random access memory (SRAM) device. However, to reduce power consumption, a latch array may be more suitable than an SRAM device. Summary of the Invention [Means for solving the problem]

[0005] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and it is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0006] An aspect of the present disclosure relates to an apparatus including: an OR-AND inverter (OAI) gate including an OR gate having a first input configured to receive a first clock and a second input configured to receive input data, a first NAND gate having a first input coupled to the output of the OR gate, and a second NAND gate having a first input configured to receive the first clock, a second input coupled to the output of the first NAND gate, and an output coupled to the second output of the first NAND gate.

[0007] Another aspect of the present disclosure relates to an apparatus including: an AND-OR inverter (AOI) gate including an AND gate including a first input configured to receive input data and a second input configured to receive a clock, a first NOR gate including a first input coupled to the output of the AND gate, and a latch including a second NOR gate including a first input configured to receive the clock, a second input coupled to the output of the first NOR gate, and an output coupled to the second input of the first NOR gate.

[0008] Another aspect of the present disclosure relates to a method including, in response to a first edge of a first clock, operating a first latch in a transparent mode by enabling an OR-AND inverter (OAI) gate to receive data and apply the inverted data to an input of a NAND gate cross-coupled to the OAI gate, and, in response to a second edge of the first clock, operating the first latch in an opaque mode by disabling an OR portion of the OAI gate and allowing the cross-coupled OAI gate and the NAND gate to latch data.

[0009] Another aspect of the present disclosure relates to a wireless communication device including at least one antenna configured to wirelessly receive a radio frequency (RF) receive signal and wirelessly transmit an RF transmit signal, a transceiver configured to convert the RF receive signal to a baseband receive signal and convert the baseband transmit signal to an RF transmit signal, one or more digital signal processing cores configured to process the baseband receive signal to generate first data and generate the baseband transmit signal based on the second data, and a latch array configured to store the first data and second data. The latch array includes at least a first latch including an OR-AND inverter (OAI) gate including an OR gate having a first input configured to receive a first clock and a second input configured to receive the first data and the second data, a first NAND gate having a first input coupled to the output of the OR gate, and a second NAND gate having a first input configured to receive the first clock, a second input coupled to the output of the first NAND gate, and an output coupled to the second input of the first NAND gate.

[0010] Another aspect of the present disclosure relates to a method that includes, in response to a first edge of a first clock, operating a first latch in a transparent mode by enabling an AND-OR inverter (AOI) gate to receive data and apply inverted data to an input of a NOR gate cross-coupled to the AOI gate, and, in response to a second edge of the first clock, operating the first latch in an opaque mode by disabling the AND portion of the AOI gate and allowing the cross-coupled AOI gate and the NOR gate to latch the data.

[0011] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a block diagram of an exemplary latch array according to certain aspects of the present disclosure. [Figure 2] FIG. 10 is a schematic diagram of an exemplary transmission gate-based flip-flop according to another aspect of the present disclosure. [Figure 3] FIG. 1 is a schematic diagram of an exemplary true single-phase clock (TSPC) flip-flop according to another aspect of the present disclosure. [Figure 4] FIG. 10 is a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop according to another aspect of the present disclosure. [Figure 5] FIG. 10 is a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop according to another aspect of the present disclosure. [Figure 6] FIG. 10 is a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop according to another aspect of the disclosure. [Figure 7] FIG. 10 is a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop according to another aspect of the disclosure. [Figure 8] 10 is a flow diagram of an exemplary method for storing data according to another aspect of the present disclosure. [Figure 9] 10 is a flow diagram of an exemplary method for storing data according to another aspect of the present disclosure. [Figure 10] FIG. 10 is a block diagram of an example wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The detailed description set forth below with reference to the accompanying drawings is intended as a description of various configurations and does not represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0014] FIG. 1 illustrates a block diagram of an exemplary latch array 100 according to certain aspects of the present disclosure. The latch array 100 is a memory device for storing data or bits using an array of latches or flip-flops. In some cases, memory arrays are used in place of static random access memory (SRAM) devices because memory arrays may have, on average, five to ten times more power than SRAM devices. That is, for a given storage capacity, the latch array 100 consumes five to ten times less power than an SRAM memory device. The latch array 100 may use a lower supply voltage compared to that used in SRAM devices (e.g., 0.57 volts (V) or less for the latch array compared to 0.75 V for the SRAM device). The latch array 100 may be configured to access / write pulses faster than SRAM devices. The latch array 100 may be easily configurable for design for test (DFT) and may be configured more densely than SRAM devices.

[0015] Latch array 100 includes a set of master latches (M-LCH) 110-0 to 110-3 (e.g., four, but may be any other number depending on the desired size of the array), a set of clock gating circuits (CGC) 120-0 to 120-3 (e.g., four, but may be any other number depending on the desired size of the array), an array of slave latches 130-00 to 130-33 (e.g., a 4x4 array, but may be any other desired array size), and a set of multiplexers 140-0 to 140-3 (e.g., four, but may be any other number depending on the desired size of the array).

[0016] The set of master latches 110-0 through 110-3 includes a set of clock inputs (clk) configured to receive a master clock signal mclk (referred to herein as master clock mclk), a set of data inputs (d) configured to receive data D0 through D3 to be stored in latch array 100, and a set of data outputs (q). A clock is a substantially periodic timing signal, typically a square wave, whose rising and falling edges control the operation of the flip-flops described herein. The set of clock gating circuits (CGCs) 120-0 through 120-3 each include a set of clock inputs (clk_in) configured to receive the master clock mclk, a set of enable inputs (en) configured to receive a write address signal (WADDR), and a set of clock outputs (clk_ou) configured to generate a set of slave clock signals sclk0 through sclk3 (referred to herein as slave clocks sclk0 through sclk3).

[0017] A first column of the array of slave latches 130-00 through 130-03 includes a set of clock inputs (clk) coupled to the clock outputs (clk_ou) of clock gating circuit (CGC) 120-0, a set of data inputs (d) coupled to the data outputs (q) of the sets of master latches 110-0 through 110-3, respectively, and a set of data outputs (q). A second column of the array of slave latches 130-10 through 130-13 includes a set of clock inputs (clk) coupled to the clock outputs (clk_ou) of clock gating circuit (CGC) 120-1, a set of data inputs (d) coupled to the data outputs (q) of the sets of master latches 110-0 through 110-3, respectively, and a set of data outputs (q).

[0018] A third column of the array of slave latches 130-20 through 130-23 includes a set of clock inputs (clk) coupled to the clock outputs (clk_ou) of clock gating circuit (CGC) 120-2, a set of data inputs (d) coupled to the data outputs (q) of the sets of master latches 110-0 through 110-3, respectively, and a set of data outputs (q). A fourth column of the array of slave latches 130-30 through 130-33 includes a set of clock inputs (clk) coupled to the clock outputs (clk_ou) of clock gating circuit (CGC) 120-3, a set of data inputs (d) coupled to the data outputs (q) of the sets of master latches 110-0 through 110-3, respectively, and a set of data outputs (q).

[0019] The set of multiplexers 140-0 to 140-1 includes a first set of inputs coupled to the set of data outputs (q) of the first column of slave latches 130-00 to 130-03, respectively, a second set of inputs coupled to the set of data outputs (q) of the second column of slave latches 130-10 to 130-13, respectively, a third set of inputs coupled to the set of data outputs (q) of the third column of slave latches 130-20 to 130-23, respectively, a fourth set of inputs coupled to the set of data outputs (q) of the fourth column of slave latches 130-30 to 130-33, respectively, and a set of select inputs configured to receive a read address signal (RADDR).

[0020] A data write operation of the latch array 100 operates as follows: The write address signal (WADDR) selects one of the columns of slave latches to which data is to be written during a particular data write interval. For example, the write address signal (WADDR) may select the first column of slave latches 130-0 to 130-3 to which a set of data D0 to D3 is to be written, respectively. In response to an edge (e.g., a falling edge) of the master clock mclk and the write address signal (WADDR) addressing the first column of slave latches 130-00 to 130-03, the clock gating circuit (CGC) 120-0 also causes the slave clock sclk0 to exhibit consecutive edges (consecutive falling and rising edges) substantially time-aligned with or within tolerance margins of the falling and rising edges of the master clock mclk, as discussed in detail herein. In this example, because the write address signal (WADDR) addresses the first column of slave latches 130-00 through 130-03, the clock gating circuits (CGCs) 120-1, 120-2, and 120-3 associated with the unaddressed columns maintain the corresponding slave clocks sclk1 through sclk3 at a low logic level. The unasserted slave clocks sclk1 through sclk3 (at a low logic level in some implementations and at a high logic level in other implementations) render the unaddressed slave latches 130-10 through 130-13, 130-20 through 130-23, and 130-30 through 130-33 opaque, preventing corruption of the data stored in those slave latches.

[0021] A falling edge of the master clock mclk causes the set of master latches 110-0 through 110-3 to become transparent, allowing them to receive data D0 through D3, respectively. A falling edge of the slave clock sclk0 causes the first column of slave latches 130-00 through 130-03 to remain opaque. The next successive rising edges of the master clock mclk cause the set of master latches 110-0 through 110-3 to become opaque, allowing them to hold the data D0 through D3 received by that successive rising edge, respectively. The next successive rising edges of the slave clock sclk0 cause the first column of slave latches 130-00 through 130-03 to become transparent, allowing them to receive data D0 through D3 from the set of master latches 110-0 through 110-3, respectively. The next successive falling edges of the master clock mclk make the set of master latches 110-0 through 110-3 transparent to receive new data D0 through D3, respectively. The next successive falling edges of the slave clock sclk0 make the first column of slave latches 130-00 through 130-03 opaque to hold / store the data D0 through D3 that the successive rising edges receive from master latches 110-0 through 110-3, respectively. The write operation operates in the same way as other columns of slave latches operate when they are addressed.

[0022] A data read operation of latch array 100 operates as follows: A read address signal (RADDR) selects one of the columns of slave latches from which data is to be read during a particular data read interval. For example, the read address signal (RADDR) may select the first column of slave latches 130-00 through 130-03, respectively, from which data D0 through D3 are to be read. In response, the set of multiplexers 140-0 through 140-3 select a first set of inputs for routing data D0 through D3 from the set of outputs (q) of the first column of slave latches 130-00 through 130-03 to generate a set of outputs Q0 through Q3, respectively. The read operation operates in the same manner as other columns of slave latches operate when those columns are addressed.

[0023] FIG. 2 illustrates a schematic diagram of an exemplary flip-flop 200 according to another aspect of the present disclosure. As discussed in more detail herein, flip-flop 200 may be a transmission gate-based flip-flop. Flip-flop 200 includes a master latch (M-LCH) 210 and, specifically, a set of slave latches shown as slave latches (S-LCH) 250. Master latch 210 may correspond to one of the sets of master latches 110-0 through 110-3 discussed previously. Slave latch (S-LCH) 250 may correspond to one of the slave latches coupled to master latch 210. As a specific example, master latch 210 may correspond to master latch 110-0, and slave latch 250 may correspond to slave latch 130-00.

[0024] The master latch 210 includes a transmission gate 212, a NOR gate 214, a first inverter 216, and a second inverter 218. The transmission gate 212 receives input data d m The transmission gate 212 includes an input configured to receive the master clock mclk, and a complementary control input configured to receive the complementary master clock mclk.

[0025]

number

[0026] The transmission gate 212 includes non-complementary control inputs configured to receive a first input of a NOR gate 214. The NOR gate 214 includes a second input configured to receive a reset signal (rst). The NOR gate 214 includes an output coupled to an input of a first inverter 216. The first inverter 216 includes an output coupled to the first input of the NOR gate 214. The second inverter 218 has an input configured to receive the master clock mclk, and a complementary master clock mclk to the transmission gate 212.

[0027]

number

[0028] The output is configured to generate:

[0029] Slave latch 250 includes a first inverter 252, a transmission gate 254, a second inverter 256, a third inverter 258, and a fourth inverter 260. First inverter 252 includes an input coupled to the output of NOR gate 214 of master latch 210 and an output coupled to an input of transmission gate 254. Transmission gate 254 includes a non-complementary control input configured to receive a corresponding slave clock sclk, and a corresponding complementary slave clock

[0030]

number

[0031] The transmission gate 254 includes an output coupled to an input of a second inverter 256. The second inverter 256 includes an output coupled to an input of a third inverter 258. The third inverter 258 includes an output coupled to an input of the second inverter 256. The fourth inverter 260 has an input configured to receive the slave clock sclk, and a complementary slave clock sclk for the transmission gate 254.

[0032]

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[0033] As indicated by the ellipsis, the output of master latch 210 (e.g., the output of NOR gate 214) is coupled to the data inputs of other slave latches in the same column as slave latch 250.

[0034] In operation, when substantially simultaneous falling edges occur in the master clock mclk and the slave clock sclk, the transmission gate 212 of the master latch 210 is transparent and the transmission gate 254 of the slave latch 250 is opaque. Thus, the data d at the input of the master latch 210 m propagates through transmission gate 212 to the first input of NOR gate 214. However, because transmission gate 254 is opaque, data d m does not propagate to the input of the second inverter 256 of the slave latch 250. The second inverter 256 and the third inverter 258 are cross-coupled, and therefore the previous data d m-1 The output data q s Latch as

[0035] When the next substantially simultaneous rising edges occur in the master clock mclk and the slave clock sclk, the transmission gate 212 of the master latch 210 is opaque and the transmission gate 254 of the slave latch 250 is transparent. If the reset signal (rst) is not asserted (e.g., logic low), the NOR gate 214 and the first inverter 216 of the master latch 210 transmit the data d m The opacity of the transmission gate 212 allows the next data d m+1 (or noise at the input of master latch 210) is latched by cross-coupled NOR gate 214 and inverter 216. m The transparency of the transmission gate 254 prevents the data d m passes through the first inverter 252 and transmission gate 254 to the input of the second inverter 256 .

[0036] When the next consecutive simultaneous falling edges occur in the master clock mclk and the slave clock sclk, the transmission gate 212 of the master latch 210 becomes transparent again and the transmission gate 254 of the slave latch 250 becomes opaque again. Thus, the new data d at the input of the master latch 210m+1 propagates through transmission gate 212 to the first input of NOR gate 214, but does not propagate to second inverter 256 because transmission gate 254 is opaque. Second inverter 256 and third inverter 258 are cross-coupled, and therefore data d m The output data q s The process repeats, receiving and recording new data by flip-flop 200.

[0037] There are several drawbacks associated with the transmission gate-based flip-flop 200. First, the flip-flop 200 requires the use of non-complementary and complementary clocks to generate these clocks.

[0038]

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[0039] and

[0040]

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[0041] and inverters 218 and 260. Furthermore, transmission gates 212 and 254 are also driven by a master clock and a slave clock, respectively. Thus, flip-flop 200 consumes a significant amount of clock power. Second, flip-flop 200 requires a significant amount of clock transistors, such as 12 clock transistors (e.g., 8 for transmission gates 212 and 254 and 4 for inverters 218 and 260). Therefore, at least for power efficiency, another type of master-gate flip-flop may be more suitable.

[0042] 3 illustrates a schematic diagram of an exemplary true single-phase clock (TSPC) flip-flop 300 according to another aspect of the present disclosure. As the name suggests, the TSPC flip-flop 300 uses a complementary master clock within a master latch.

[0043]

number

[0044] The generation of the complementary slave clock in each of the slave latches

[0045]

number

[0046] Because TSPC flip-flop 300 does not require the generation of a complementary clock, TSPC flip-flop 300 generally consumes less clock power than transmission gate-based flip-flop 200. Furthermore, TSPC flip-flop 300 requires fewer clock transistors (e.g., 6) compared to the block transistors (e.g., 12) of transmission gate-based flip-flop 200.

[0047] Specifically, the TSPC flip-flop 300 includes a master latch 310 and a set of slave latches 350-0 through 350-3. The master latch 310 may correspond to any one of the master latches 110-0 through 110-3 of the latch array 100. The set of slave latches 350-0 through 350-3 may correspond to a column of slave latches of the latch array 100 coupled to the master latch 310. For example, the master latch 310 may correspond to the master latch 110-0 of the latch array 100, and the set of slave latches 350-0 through 350-3 may correspond to the slave latches 130-00 through 130-30, respectively.

[0048] The master latch 310 includes an inverter 312, a NOR gate 314, and an AND-OR inverter (AOI) gate 316 including an AND gate 318 and a NOR gate 320. The inverter 312 includes an input configured to receive the master clock mclk, and an output coupled to a first input of the NOR gate 314 and a first input of an AND gate 318 of the AOI gate 316. The AND gate 318 of the AOI gate 316 receives the input data d m AND gate 318 includes an output coupled to a first input of NOR gate 320 of AOI gate 316. NOR gate 314 includes an output coupled to a second input of NOR gate 320 of AOI gate 316. NOR gate 320 of AOI gate 316 also includes an output coupled to a second input of NOR gate 314.

[0049] The sets of slave latches 350-0 through 350-3 are similarly configured. Taking slave latch 350-0 as an example, slave latch 350-0 includes AOI gate 352-0, which includes AND gate 354-0 and NOR gate 356-0, a first inverter 358-0, and a second inverter 360-0. AND gate 354-0 of AOI gate 352-0 includes a first input configured to receive the corresponding slave clock sclk0 and an output coupled to the first input of NOR gate 356-0 of AOI gate 352-0. NOR gate 356-0 of AOI gate 352-0 includes a second input coupled to the output of NOR gate 314 of master latch 310. NOR gate 356-0 of AOI gate 352-0 includes outputs coupled to the inputs of first inverter 358-0 and second inverter 360-0, respectively. The first inverter 358-0 has an output coupled to the second input of the AND gate 354-0 of the AOI gate 352-0. The second inverter 360-0 outputs the output data q s0 The output is configured to generate:

[0050] As noted, the other slave latches 350-1 through 350-3 in the set or column are configured similarly to slave latch 350-0, but instead are configured to receive corresponding slave clocks sclk1 through sclk-3, respectively. For clarity, slave latch 350-3 includes AOI gate 352-3, which includes AND gate 354-3 and NOR gate 356-3, a first inverter 358-3, and a second inverter 360-3. AND gate 354-3 of AOI gate 352-3 includes a first input configured to receive corresponding slave clock sclk3, and an output coupled to a first input of NOR gate 356-3 of AOI gate 352-3. NOR gate 356-3 of AOI gate 352-3 includes a second input coupled to the output of NOR gate 314 of master latch 310. NOR gate 356-3 of AOI gate 352-3 includes an output coupled to the inputs of first inverter 358-3 and second inverter 360-3, respectively. First inverter 358-3 includes an output coupled to the second input of AND gate 354-3 of AOI gate 352-3. Second inverter 360-3 outputs output data q s3 The output is configured to generate:

[0051] In operation, when the master clock mclk and the slave clock sclk0 exhibit substantially time-aligned falling and rising edges, respectively, the master latch 310 is transparent and the slave latch 350-0 is opaque. The inverter 312 inverts the low logic level of the master clock mclk to produce a high logic level at the first input of the AND gate 318 of the AOI gate 316. Thus, the data d at the second input of the AND gate 318 m is allowed to propagate to the first input of NOR gate 320. The high logic level produced by inverter 312 causes NOR gate 314 to output a low logic level. Thus, the output of NOR gate 320 at AOI gate 316 is the inverted input data

[0052]

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[0053] Therefore, since the master latch 310 is in a transparent mode, the master latch 310 generates the input data d m received.

[0054] The high logic level of the slave clock sclk0 is used to invert the previous data d through the NOR gate 356-0 and the first inverter 358-0. m-1 The feedback of AOI gate 352-0 enables AND gate 354-0 to be active. Thus, the previous data d from master latch 310 m-1 is latched by the feedback network, and the second inverter 360-0 outputs the previous data d m-1 The output data q so As discussed, one of the slave clocks is asserted at a given time (e.g., a logic zero (0) in this example) and the other slave clocks sclk1 through sclk3 are at a logic one (1), thereby setting the other slave latches 350-1 through 350-3 in a latched or opaque configuration.

[0055] When the master clock mclk and the slave clock sclk0 exhibit the next consecutive substantially time-aligned rising and falling edges, respectively, the master latch 310 becomes opaque and the slave latch 350-0 becomes transparent. The inverter 312 inverts the high logic level of the master clock mclk, resulting in a low logic level at the first input of the AND gate 318 of the AOI gate 316. Thus, the AND gate 318 is disabled, allowing the new data d m+1 (or noise at the input) is input to the master latch 310. m The low logic level produced by inverter 312 prevents data d from being corrupted by NOR gate 314 through cross-coupled NOR gates 314 and 320. m This allows the device to latch the

[0056] The low logic level of the slave clock sclk0 disables AND gate 354-0 of AOI gate 352-0, disabling the latching operation of the feedback network of slave latch 350. The low logic level of the slave clock sclk0 via AND gate 354-0 disables the latching operation of the feedback network of slave latch 350. The low logic level of the slave clock sclk0 via AND gate 354-0 disables NOR gate 356-0 from latching the currently latched data d from master latch 310. m In other words, the slave latch 350-0 responds to the current data d m from the master latch 310. Thus, the NOR gate 356-0 receives the inverted current data

[0057]

number

[0058] The first inverter 358-0 and the second inverter 360-0 output the current data d m The foregoing process is repeated to receive and latch new data in response to rising and falling edges of the master clock mclk and the slave clock associated with the addressed column of slave latches.

[0059] A drawback of TSPC flip-flop 300 is that the output of NOR gate 314 can logically toggle, corrupting the data latched by the unaddressed slave latch. For example, assume that unaddressed slave latch 350-3 latches a logic one (0) and the current data dm to be written to addressed slave latch 350-0 is a logic one (1). If unaddressed slave latch 350-0 latches a logic zero (0), the output of NOR gate 356-3 will be at a logic one (1). If the master clock mclk goes high and the data dm is written to the output of NOR gate 314, the output of NOR gate 356-3 will be at a logic one (1). mWhen the unaddressed slave latch 350-3 latches a logic one (1), the NOR gate 356-3 of the unaddressed slave latch 350-3 responds with a logic one (1) because its second input is coupled to the output of the NOR gate 314 of the master latch 310. Thus, the NOR gate 314 changes its output to a logic zero (0), thereby corrupting the latched data in the unaddressed slave latch 350-3.

[0060] 4 illustrates a schematic diagram of an exemplary true single-phase clock (TSPC) flip-flop 400 according to another aspect of the present disclosure. Again, as the name suggests, the TSPC flip-flop 400 uses a complementary master clock within a master latch.

[0061]

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[0062] The generation of the complementary slave clock in each of the slave latches

[0063]

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[0064] Because TSPC flip-flop 400 does not require the generation of a complementary clock, TSPC flip-flop 400 generally consumes less clock power than transmission gate-based flip-flop 200. Furthermore, TSPC flip-flop 400 requires fewer clock transistors (e.g., 8) compared to the clock transistors (e.g., 12) of transmission gate-based flip-flop 200.

[0065] In particular, the TSPC flip-flop 400 includes a master latch 410 and a set of slave latches 450-0 through 450-3. The master latch 410 may correspond to any one of the master latches 110-0 through 110-3 of the latch array 100. The set of slave latches 450-0 through 450-3 may correspond to a column of slave latches of the latch array 100 coupled to the master latch 410. For example, the master latch 410 may correspond to the master latch 110-0 of the latch array 100, and the set of slave latches 450-0 through 450-3 may correspond to the slave latches 130-00 through 130-30, respectively.

[0066] The master latch 410 includes a NAND gate 412 and an OR-AND inverter (OAI) gate 414 including an OR gate 416 and a NAND gate 418. The NAND gate 412 includes a first input configured to receive the master clock mclk and an output (node ​​pn2) coupled to a first input of the NAND gate 418 of the OAI gate 414. The OR gate 416 of the OAI gate 414 includes a first input configured to receive the master clock mclk and an output (node ​​pn2) coupled to a first input of the NAND gate 418 of the OAI gate 414. m OR gate 416 includes an output coupled to a second input of NAND gate 418 of OAI gate 414. NAND gate 418 includes an output (node ​​pn1) coupled to a second input of NAND gate 412.

[0067] The sets of slave latches 450-0 through 450-3 are similarly configured. Taking slave latch 450-0 as an example, slave latch 450-0 includes an AND-OR inverter (AOI) gate 452-0, which includes AND gate 454-0 and NOR gate 456-0, a NOR gate 458-0, and an inverter 460-0. AND gate 454-0 of AOI gate 452-0 includes a first input coupled to the output of NAND gate 412 of master latch 410 (node ​​pn2), a second input configured to receive the corresponding slave clock sclk0, and an output coupled to the first input of NOR gate 456-0 of AOI gate 452-0. NOR gate 456-0 of AOI gate 452-0 includes a second input coupled to the output of NOR gate 458-0 (node ​​pn4). NOR gate 456-0 of AOI gate 452-0 includes an output (node ​​pn3) coupled to a first input of NOR gate 458-0 and to an input of inverter 460-0. NOR gate 458-0 includes a second input configured to receive corresponding slave clock sclk0. The output (node ​​pn3) of NOR gate 456-0 is complementary output data

[0068]

number

[0069] , the output of inverter 460-0 is configured to produce non-complementary output data qs0, and the output (node ​​pn4) of NOR gate 458-0 is configured to produce internal signal x0.

[0070] As noted, the other slave latches 450-1 through 450-3 in the set or column are configured similarly to slave latch 450-0, but instead are configured to receive corresponding slave clocks sclk1 through sclk-3, respectively. For clarity, slave latch 450-3 includes AOI gate 452-3, which includes AND gate 454-3 and NOR gate 456-3, NOR gate 458-3, and inverter 460-3. AND gate 454-3 of AOI gate 452-3 includes a first input coupled to the output of NAND gate 412 of master latch 410 (node ​​pn2), a second input configured to receive corresponding slave clock sclk3, and an output coupled to the first input of NOR gate 456-3 of AOI gate 452-3. NOR gate 456-3 of AOI gate 452-3 includes a second input coupled to the output of NOR gate 458-3 (node ​​pn4). NOR gate 456-3 of AOI gate 452-3 includes an output (node ​​pn3) coupled to a first input of NOR gate 458-3 and to an input of inverter 460-3. NOR gate 458-3 includes a second input configured to receive corresponding slave clock sclk3. The output (node ​​pn3) of NOR gate 456-3 is complementary output data

[0071]

number

[0072] and the output of inverter 460-3 is configured to produce non-complementary output data q s3 and the output of NOR gate 458-3 (node ​​pn4) is configured to produce internal signal x3.

[0073] Data d mto slave latch 450-0 may be as follows: when master clock mclk and slave clock sclk0 exhibit substantially time-aligned falling edges, master latch 410 becomes transparent and slave latch 450-0 becomes opaque. In response to the low logic level of master clock mclk, NAND gate 412 outputs a logic one (1) at node pn2. Also, in response to the low logic level of master clock mclk, OR gate 416 of OAI gate 414 outputs a logic one (1) at node pn3. m (even though inverted) propagates through NAND gate 418 to the second input of NAND gate 412. Thus, master latch 410 allows input data d m The master latch 410 is in a transparent mode because it can receive the

[0074] For slave latch 450-0, the low logic level of slave clock sclk0 disables AND gate 454-0 of AOI gate 452-0, making slave latch 450-0 opaque. Thus, cross-coupled AOI gate 452-0 and NOR gate 458-0 receive the previous inverted data.

[0075]

number

[0076] or

[0077]

number

[0078] The inverter 460-0 keeps the previous inverted data in a latched state.

[0079]

number

[0080] or

[0081]

number

[0082] is inverted to output data q s0 Similarly, the unaddressed slave latches 450-1 through 450-3 also have their AND gates 454-1 through 454-3 disabled in this example via a low logic level on the slave clocks sclk1 through sclk3, respectively. Thus, in contrast to the TSPC flip-flop 300, the toggling of the output (node ​​pn2) of the NAND gate 412 of the master latch 410 does not corrupt the latching of data in the unaddressed slave latches 450-1 through 450-3.

[0083] When the master clock mclk and the slave clock sclk0 exhibit the next successive substantially time-aligned rising edges, the master latch 410 becomes opaque and the slave latch 450-0 becomes transparent. In response to the high logic level of the master clock mclk, the NAND gate 412 is enabled, thereby applying the current data d to the cross-coupled NAND gate 412 and the OAI gate 414. m Also, in response to the high logic level of the master clock mclk, the OR gate 416 of the OAI gate 414 is disabled, thereby latching the new data d m+1 (or noise at the input) is applied to the current data d by the cross-coupled NAND gate 412 and the OAI gate 414. m Therefore, the master latch 410 is in an opaque mode.

[0084] For the slave latch 450-0, the high logic level of the slave clock sclk0 enables the AND gate 454-0 of the AOI gate 452-0. Thus, the current data d mpropagates (even though inverted) through NOR gate 456-0 to the first input of NOR gate 458-0. The high logic level of slave clock sclk0 disables NOR gate 458-0, causing NOR gate 458-0 to generate internal signal x0 as logic 0 (0) at node pn4. Thus, slave latch 450-0 is in transparent mode. As for the unaddressed slave latches 450-1 through 450-3, in this example, their AND gates 454-1 through 454-3 are disabled via the low logic levels of slave clocks sclk1 through sclk3, respectively. Thus, the current data d at the output (node ​​pn2) of NAND gate 412 of master latch 410 is m The logic value of does not affect the data latched by the unaddressed slave latches 450-1 to 450-3.

[0085] 5 illustrates a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop 500 according to another aspect of the present disclosure. TSPC 500 may be a more detailed (e.g., transistor-level) exemplary implementation of TSPC 400 discussed previously. TSPC 500 includes a master latch (M-LCH) 510 and a slave latch (S-LCH) 550, each of which may correspond to master latch 410 and any one of the sets of slave latches 450-0 through 450-3. Master latch 510 includes an OR-AND inverter (OAI) gate 512 cross-coupled with a NAND gate 520. Slave latch 550 includes an AND-OR inverter (AOI) gate 552 cross-coupled with a NOR gate 556, and an inverter 560.

[0086] The master latch 510 includes a first p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) M1 and a second PMOS FET M2 coupled in series between an upper voltage rail Vdd and the output (node ​​pn1) of the OAI gate 512. The master latch 510 further includes a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET) M3 and a second NMOS FET M4 coupled in series between the output (node ​​pn1) of the OAI gate 512 and a lower voltage rail (e.g., ground). The PMOS FET M1 includes a gate configured to receive the master clock mclk, and the PMOS FET M2 includes a gate configured to receive the input data d m NMOS FET M3 includes a gate coupled to the output of NAND gate 520 (node ​​pn2), and NMOS FET M4 includes a gate coupled to the output of NAND gate 520 (node ​​pn3), and NMOS FET M5 includes a gate coupled to the output of NAND gate 520 (node ​​pn4), and NMOS FET M6 includes a gate coupled to the output of NAND gate 520 (node ​​pn5). m The gate is configured to receive the signal.

[0087] Master latch 510 further includes PMOS FET M5, NMOS FET M6, NMOS FET M7, and inverter 514. PMOS FET M5 is coupled between the upper voltage rail Vdd and the output of OAI gate 512 (node ​​pn1) and includes a gate coupled to the output of NAND gate 520 (node ​​pn2). NMOS FETs M6 and M7 are coupled in series between the output of OAI gate 512 (node ​​pn1) and the lower voltage rail. Inverter 514 includes inputs coupled to the output of OAI gate 512 (node ​​pn1) and an output coupled to the gate of NMOS FET M6. NMOS FET M7 includes a gate configured to receive master clock mclk. As discussed further herein, the circuit including inverter 514 and NMOS FET M6 addresses racing conditions and falling clock transparency (FCT) margins, as discussed in more detail further herein.

[0088] The NAND gate 520 further includes a PMOS FET M8 coupled in parallel with PMOS FET M9 between the upper voltage rail Vdd and the output (node ​​pn2) of the NAND gate 520, and an NMOS FET M10 and an NMOS FET M11 coupled in series between the output (node ​​pn2) of the NAND gate 520 and the lower voltage rail. The PMOS FET M8 and the NMOS FET M10 include gates coupled to the output (node ​​pn1) of the OAI gate 512, the PMOS FET M9 includes a gate configured to receive the master clock mclk, and the NMOS FET M11 includes a gate configured to receive the master clock mclk.

[0089] With respect to the slave latch 550, the AOI gate 552 includes a PMOS FET M12 and a PMOS FET M13 coupled in series between the upper voltage rail Vdd and the output of the AOI gate 552 (node ​​pn3). The AOI gate 552 further includes an NMOS FET M14 and an NMOS FET M15 coupled in series between the output of the AOI gate 552 (node ​​pn3) and the lower voltage rail. The PMOS FET M12 includes a gate coupled to the output of the NOR gate 556 of the slave latch 550 (node ​​pn4). The PMOS FET M13 includes a gate coupled to the output of the NAND gate 520 of the master latch 510 (node ​​pn2). The NMOS FET M14 includes a gate coupled to the output of the inverter 514 of the master latch 510. The NMOS FET M15 also includes a gate configured to receive the corresponding slave clock sclk.

[0090] AOI gate 552 further includes a PMOS FET M16 coupled in series with PMOS FET M17 between the upper voltage rail Vdd and the output of AOI gate 552 (node ​​pn3). In addition, AOI gate 552 includes an NMOS FET M18 coupled between the output of AOI gate 552 (node ​​pn3) and the lower voltage rail. AOI gate 552 further includes an inverter 554 having an input coupled to the output of AOI gate 552 (node ​​pn3) and an output coupled to the gate of PMOS FET M17. PMOS FET M16 includes a gate configured to receive a corresponding slave clock sclk. NMOS FET M18 includes a gate coupled to the output of NOR gate 556 (node ​​pn4). Thus, the circuit including inverter 554 and PMOS FET M17 addresses racing conditions as discussed further herein.

[0091] NOR gate 556 of slave latch 550 includes a first input coupled to the output (node ​​pn3) of AOI gate 552, a second input configured to receive a corresponding slave clock sclk, and an output (node ​​pn4) for generating an internal signal x. Inverter 560 includes an input coupled to the output (node ​​pn3) of AOI gate 552 and an output configured to generate output data q.

[0092] Writing of data dm to the slave latch 550 may be as follows: When the master clock mclk and the slave clock sclk exhibit substantially time-aligned falling edges, the master latch 510 becomes transparent and the slave latch 550 becomes opaque. For example, in response to a low logic level of the master clock mclk, the PMOS FET M9 turns on, applying Vdd (logic one (1)) to the output (node ​​pn2) of the NAND gate 520. Also, in response to a low logic level of the master clock mclk, the PMOS FET M1 turns on, thereby applying Vdd to the source of the PMOS FET M2. Because the output (node ​​pn2) of the NAND gate 520 is at logic one (1), the NMOS FET M3 is turned on. Therefore, the output (node ​​pn1) of the OAI gate 512 is at logic one (1) and the input data d m of(

[0093]

number

[0094] In this case, data d is received (even if it is inverted). m When the data d is at logic one (1), the node pn1 is at logic zero (0). m is at logic zero (0), node pn1 is at logic one (1). Therefore, the master latch 510 receives the input data d m The master latch 510 is in a transparent mode because it can receive the

[0095] For the slave latch 550, a low logic level of the slave clock sclk turns off NMOS FET M15, disabling the AND operation of NMOS FETs M14 and M15. This configures the slave latch 550 in an opaque mode. A low logic level of the slave clock sclk enables NOR gate 556. Therefore, the output of NOR gate 556, which is fed back to the gate of NMOS FET M18, is the same as the previous data d m-1 Therefore, the inverted previous data d m-1(i.e.,

[0096]

number

[0097] ) is logic zero (0) and the slave clock sclk is at logic zero (0), NOR gate 556 outputs internal signal x as logic one (1). The internal signal x being logic one (1) turns on NMOS FET M18, coupling the low voltage rail to node pn3, thereby latching logic zero (0) at node pn3. Inverter 560 then generates output signal q as logic one (1). Thus, output data q is the sum of input data d m-1 Based on.

[0098] Inverted previous data d m-1 (i.e.,

[0099]

number

[0100] ) is at logic one (1) and the slave clock sclk is at logic zero (0), NOR gate 556 outputs internal signal x as logic zero (0). The internal signal x being logic zero (0) turns off NMOS FET M18. Inverter 554 inverts the logic one (1) at node pn3 to generate a logic zero (0) at the gate of PMOS FET M17. Because the slave clock sclk is also at logic zero (0), PMOS FETs M16 and M17 turn on, applying the upper voltage rail Vdd to node pn3, thereby latching a logic one (1) at node pn3. Inverter 560 then generates output signal q as logic zero (0). Thus, output data q is equal to or greater than the input data d m-1 Based on.

[0101] When the master clock mclk and the slave clock sclk0 exhibit the next consecutive substantially time-aligned rising edges, the master latch 510 becomes opaque and the slave latch 550 becomes transparent. In response to the high logic level of the master clock mclk, the PMOS FET M1 turns off, thereby disabling the logical OR operation of the FETs M1-M4. The high logic level of the master clock mclk also turns off the PMOS FET M9. Thus, the cross-coupled NAND gate operation of M5-M7 with the inverter 514 and the FETs M8, M10, and M11 of the NAND gate 520, converts the data d previously received in the master transparent interval into a logical OR operation. m Latch the

[0102] That is, data d m is a logic one (1), node pn1 is at a logic zero (0). Inverter 514 inverts the logic zero (0) to generate a logic one (1) at the gate of NMOS FET M6. When the gate of NMOS FET M7 receives the high logic level of the master clock mclk, NMOS FETs M6 and M7 turn on, coupling the lower voltage rail to node pn1, thereby latching a logic zero (0) at node pn1. The logic zero (0) at node pn1 turns on PMOS FET M8 and turns off NMOS FET M10. Turning on PMOS FET M8 applies the upper voltage rail Vdd to node pn2, thereby latching a logic one (1) at node pn2. Node pn2 at a logic one (1) turns off PMOS FET M4, effectively disconnecting Vdd from the logic zero (0) at node pn1.

[0103] Conversely, data d mis a logic zero (0), node pn1 is at a logic one (1). Inverter 514 inverts the logic one (1) to generate a logic zero (0) at the gate of NMOS FET M6. Thus, NMOS FET M6 is turned off, effectively decoupling node pn1 from the lower voltage rail. The logic one (1) at node pn1 turns PMOS FET M8 off and NMOS FET M10 on. Turning PMOS FET M8 off effectively decouples node pn2 from the upper voltage rail Vdd. Turning NMOS FET M10 on and having the master clock mclk at a logic one (1) to turn on NMOS FET M11 couples the lower voltage rail to node pn2, ensuring that node pn2 is at a logic zero (0).

[0104] For the slave latch 550, a high logic level of the slave clock sclk turns on the NMOS FET M15 and turns off the PMOS FET M16, causing the NOR gate 556 to generate the internal signal x as a logic 0 (0), turns on the PMOS FET M12, and turns off the NMOS FET M18. m is at logic one (1) at node pn2, then node pn1 is at logic zero (0), in which case the output of inverter 514

[0105]

number

[0106] is at a logic one (1). Because the gate of NMOS FET M14 is coupled to the output of inverter 514, a logic one (1) turns on NMOS FET M14, and thus turning on both NMOS FETs M14 and M15 applies the lower voltage rail to node pn3, thereby

[0107]

number

[0108] Set the data latched in the master latch to logic zero (0). m is at logic 0 (0) at node pn2, both PMOS FETs M12 and M13 are turned on, applying the upper voltage rail to node pn3, thereby

[0109]

number

[0110] to logic one (1). Therefore, the slave latch 550 stores the data d m from the master latch 510, the slave latch 550 is in a transparent mode. Racing Conditions

[0111] Referring simply to FIG. 4, the master latch 410 becomes opaque and the input data d m is a logic zero (0), the master clock mclk has a high logic level and the inverted data of a high logic level at the output of the NAND gate 418

[0112]

number

[0113] is input to the NAND gate 412 at node pn2. m is a logical zero (0), which causes the output to be a logical zero (0).

[0114] However, because node pn2 of master latch 410 is coupled to the set of slave latches 450-0 through 450-3, node pn2 may experience a relatively large capacitance. Thus, in response to a high logic level of master clock mclk, node pn2 may slowly decrease toward logic zero (0). If the high logic level of master clock mclk reaches the second input of NAND gate 418 before node pn2 is at logic zero (0), NAND gate 418 receives both its inputs at logic one (1) and outputs logic zero (0). If the logic zero (0) output by NAND gate 418 reaches the second input of NAND gate 412 before node pn2 decreases to logic zero (0), NAND gate 412 will couple node pn2 to the input data d m is a logical zero (0), and remains a logical one (1).

[0115] This is called a racing condition because the path from master clock mclk to pn2 through NAND gate 412 must be faster than the path from master clock mclk to pn2 through OAI gate 414 and NAND gate 412.

[0116] A similar racing condition occurs in slave latches. For example, consider slave latch 450-0. Slave latch 450-0 becomes opaque and data d at node pn2 m When the data d at node pn2 is a logic one (1), the low logic level of slave clock sclk0 causes NOR gate 458-0 to output a logic one (1). In that case, the low logic level of slave clock sclk0 causes AND gate 454-0 to output a logic zero (0). Since the inputs to NOR gate 456-0 are a logic zero (0) and a logic one (1), NOR gate 456-0 outputs a logic zero (0). Inverter 460-0 inverts the logic zero (0) at the output of NOR gate 456-0, causing the data d at node pn2 to m , which generates a logic one (1) that correlates to the logic one (1) of .

[0117] However, if the low logic level of slave clock sclk0 causes AND gate 454-0 to output a logic 0 (0) before NOR gate 458-0 outputs a logic 1 (1), NOR gate 456-0 receives a logic 0 (0) at its input and outputs a logic 1 (1). In response to the logic 1 (1) output by NOR gate 456-0 (at the first input of NOR gate 458-0), NOR gate 458-0 maintains internal signal x0 at a logic 0 (0). Inverter 460-0 inverts the logic (1) output by NOR gate 456-0 to generate data d at node pn2. m It outputs a logic zero (0) which does not correlate to the logic one (1) of the

[0118] Again, this is called a racing condition because the path from slave clock sclk0 to the input of NOR gate 456-0 via NOR gate 458-0 must be faster than the path from slave clock sclk0 to the input of NOR gate 456-0 via AND gate 454-0.

[0119] Referring again to FIG. 5, to ensure that the correct path and sequence is taken when master latch 510 and slave latch 550 transition to opaque mode, master latch 510 includes inverter 514 and NMOS FET M6 in the configuration previously discussed, and slave latch 550 includes inverter 554 and PMOS FET M17 in the configuration previously discussed.

[0120] For example, in master latch 510, the proper sequence is for node pn2 to fall first before node pn1 changes. Thus, the inversion by inverter 514 prevents NMOS FET M6 from turning on and causing node pn1 to fall while NMOS FET M7 is turned on, while node pn1 remains at a high logic level, but this is not possible if the input data d mis 0 (zero), and the master clock mclk goes high, configuring the master latch 510 in an opaque mode.

[0121] Similarly, in the slave latch 550, in the proper sequence, node pn3(

[0122]

number

[0123] The internal signal x must go high before the input data d can change. Therefore, turning off PMOS FET M17 while node pn3 is at logic 0 (0) due to inversion by inverter 554 prevents PMOS FET M16 from turning on and causing node pn3 to go high. Therefore, the internal signal x can go high while node pn3 remains at a low logic level, which is the same as when the input data d m is one (1), which is the correct response when the slave clock sclk goes low to configure the slave latch 550 in opaque mode. Falling Clock Transparency (FCT) Margin

[0124] According to ideal operation of the TSPC flip-flop 500, the master clock mclk and the slave clock sclk are in phase. That is, the master clock mclk and the slave clock sclk each have a falling edge that is substantially time-aligned. However, if the slave clock sclk is out of phase with respect to the master clock mclk and the slave latch 550 is configured in the typical manner (the gate of NMOS FET M14 is coupled to node pn2), node pn3 will be inadvertently discharged. If the master clock mclk exhibits a falling edge that configures the master latch 510 in a transparent mode before the slave clock sclk exhibits a falling edge that configures the slave latch 550 in an opaque mode, node pn2 will go to a logic high while the slave clock sclk is still a logic high. Thus, node pn2 and the slave clock sclk will turn on NMOS FETs M14-M15 at a logic high, which inadvertently discharges node pn3. In contrast, in ideal operation, node pn2 and slave clock sclk rise and fall simultaneously, so that slave clock sclk being low prevents node pn3 from being discharged.

[0125] The falling clock transparency (FCT) margin is the tolerable skew, or time difference, between the falling edge of the master clock mclk and the falling edge of the slave clock sclk. In a typical implementation of the slave latch 550, where the gate of NMOS FET M14 is coupled to pn2, the FCT margin is one transistor stage delay, or more specifically, the delay associated with turning on PMOS FET M9 in response to the falling edge of the master clock mclk.

[0126] However, in the slave latch 550, the gate of NMOS FET M14 is connected to node

[0127]

number

[0128] Node

[0129]

number

[0130] The signal at node pn1 is a delayed version of the data at node pn2. For example, in response to a falling edge of the master clock mclk,

[0131]

number

[0132] goes high after three transistor stages: (1) turning on PMOS FET M9 in response to the falling edge of the master clock mclk (i.e., node pn2 going high); (2) turning on NMOS FET M3 in response to node pn2 going high (node ​​pn1 going low due to NMOS FETs M3-M4 being turned on); and (3) turning on the PMOS FET inside inverter 514 in response to a low at node pn1. Thus, the slave clock sclk may be able to stay high for three transistor stage delays before node pn3 is inadvertently pulled down. Thus, pulling the gate of NMOS FET M14 to node

[0133]

number

[0134] By combining the FETs, the FCT margin can be extended to three transistor stages.

[0135] 6 illustrates a schematic diagram of an exemplary true single-phase clock (TSPC) flip-flop 600 according to another aspect of the present disclosure. TSPC flip-flop 600 is an exemplary complementary version of TSPC flip-flop 400 discussed previously.

[0136] Specifically, TSPC flip-flop 600 includes a master latch 610 and a set of slave latches 650-0 through 650-3. Master latch 610 may correspond to any one of master latches 110-0 through 110-3 of latch array 100. The set of slave latches 650-0 through 650-3 may correspond to a column of slave latches of latch array 100 coupled to master latch 610. For example, master latch 610 may correspond to master latch 110-0 of latch array 100, and the set of slave latches 650-0 through 650-3 may correspond to slave latches 130-00 through 130-30, respectively.

[0137] The master latch 610 includes a NOR gate 612 and an AND-OR inverter (AOI) gate 614 including an AND gate 616 and a NOR gate 618. The NOR gate 612 includes a first input configured to receive the master clock mclk and an output (node ​​pn2) coupled to a first input of the NOR gate 618 of the AOI gate 614. The AND gate 616 of the AOI gate 614 includes a first input configured to receive the master clock mclk and an output (node ​​pn3) coupled to a first input of the NOR gate 618 of the AOI gate 614. m AND gate 616 includes an output coupled to a second input of NOR gate 618 of AOI gate 614. NOR gate 618 includes an output (node ​​pn1) coupled to a second input of NOR gate 612.

[0138] The sets of slave latches 650-0 through 650-3 are similarly configured. Taking slave latch 650-0 as an example, slave latch 650-0 includes OR-AND inverter (OAI) gate 652-0, which includes OR gate 654-0 and NAND gate 656-0, NAND gate 658-0, and inverter 660-0. OR gate 654-0 of OAI gate 652-0 includes a first input coupled to the output of NOR gate 612 of master latch 610 (node ​​pn2), a second input configured to receive the corresponding slave clock sclk0, and an output coupled to the first input of NAND gate 656-0 of OAI gate 652-0. NAND gate 656-0 of OAI gate 652-0 includes a second input coupled to the output of NAND gate 658-0 (node ​​pn4). NAND gate 656-0 of OAI gate 652-0 includes an output (node ​​pn3) coupled to a first input of NAND gate 658-0 and to an input of inverter 660-0. NAND gate 658-0 includes a second input configured to receive corresponding slave clock sclk0. The output (node ​​pn3) of NAND gate 656-0 is complementary output data

[0139]

number

[0140] and the output of inverter 660-0 is configured to produce non-complementary output data q s0 and the output of NAND gate 658-0 (node ​​pn4) is configured to produce internal signal x0.

[0141] As noted, the other slave latches 650-1 through 650-3 in the set or column are configured similarly to slave latch 650-0, but instead are configured to receive corresponding slave clocks sclk1 through sclk-3, respectively. For clarity, slave latch 650-3 includes an OR-AND inverter (OAI) gate 652-3, which includes OR gate 654-3 and NAND gate 656-3, a NAND gate 658-3, and an inverter 660-3. OR gate 654-3 of OAI gate 652-3 includes a first input coupled to the output of NOR gate 612 of master latch 610 (node ​​pn2), a second input configured to receive corresponding slave clock sclk3, and an output coupled to the first input of NAND gate 656-3 of OAI gate 652-3. NAND gate 656-3 of OAI gate 652-3 includes a second input coupled to the output of NAND gate 658-3 (node ​​pn4). NAND gate 656-3 of OAI gate 652-3 includes an output (node ​​pn3) coupled to a first input of NAND gate 658-3 and to an input of inverter 660-3. NAND gate 658-3 includes a second input configured to receive corresponding slave clock sclk3. The output (node ​​pn3) of NAND gate 656-3 is complementary output data

[0142]

number

[0143] and the output of inverter 660-3 is configured to produce non-complementary output data q s3 and the output of NAND gate 658-3 (node ​​pn4) is configured to produce internal signal x3.

[0144] Data d mto slave latch 650-0 may be as follows: When master clock mclk and slave clock sclk0 exhibit substantially time-aligned rising edges, master latch 610 becomes transparent and slave latch 650-0 becomes opaque. In response to a high logic level of master clock mclk, NOR gate 612 outputs a logic 0 (0) at node pn2. Also, in response to a high logic level of master clock mclk, AND gate 616 of AOI gate 614 outputs a logic 0 (0) at node pn3. m (even though inverted) propagates through NOR gate 618 to the second input of NOR gate 612. Thus, master latch 610 allows input data d m , the master latch 610 is in a transparent mode.

[0145] For slave latch 650-0, the high logic level of slave clock sclk0 disables OR gate 654-0 of OAI gate 652-0, making slave latch 650-0 opaque. Thus, cross-coupled OAI gate 652-0 and NAND gate 658-0 receive the previous inverted data

[0146]

number

[0147] or

[0148]

number

[0149] The inverter 660-0 keeps the previous inverted data

[0150]

number

[0151] or

[0152]

number

[0153] is inverted to output data q s0 Similarly, the unaddressed slave latches 650-1 through 650-3 also have their OR gates 654-1 through 654-3 disabled, in this example, via the high logic level slave clocks sclk1 through sclk3, respectively. Thus, in contrast to the TSPC flip-flop 300, the toggling of the output (node ​​pn2) of the NOR gate 612 of the master latch 610 does not corrupt the latching of data in the unaddressed slave latches 650-1 through 650-3.

[0154] When the master clock mclk and slave clock sclk0 exhibit the next consecutive time-aligned falling edges, master latch 610 becomes opaque and slave latch 650-0 becomes transparent. In response to the low logic level of master clock mclk, NOR gate 612 is enabled, thereby applying the current data d to cross-coupled NOR gate 612 and AOI gate 614. m Also, in response to the master clock mclk being at a low logic level, the AND gate 616 of the AOI gate 614 is disabled, thereby latching the new data d m+1 (or noise at the input) is filtered by the cross-coupled NOR gate 612 and the AOI gate 614 to filter out the current data d m Therefore, the master latch 610 is in an opaque mode.

[0155] For the slave latch 650-0, the low logic level of the slave clock sclk0 enables the OR gate 654-0 of the OAI gate 652-0. Thus, the current data d mpropagates (even though inverted) through NAND gate 656-0 to the first input of NAND gate 658-0. The low logic level of slave clock sclk0 disables NAND gate 658-0, causing NAND gate 658-0 to generate internal signal x0 as a logic one (1) at node pn4. Thus, slave latch 650-0 is in transparent mode. As for the unaddressed slave latches 650-1 to 650-3, in this example, their OR gates 654-1 to 654-3 are disabled via the high logic level of slave clocks sclk1 to sclk3, respectively. Thus, the current data d at the output (node ​​pn2) of NOR gate 612 of master latch 610 m The logic value of does not affect the data latched by the unaddressed slave latches 650-1 to 650-3.

[0156] FIG. 7 shows a schematic diagram of another exemplary true single-phase clock (TSPC) flip-flop 700 according to another aspect of the present disclosure. TSPC 700 is an exemplary complementary version of TSPC 500 discussed previously. TSPC 700 includes a master latch (M-LCH) 710 and a slave latch (S-LCH) 750, which may correspond to master latch 610 and any one of the set of slave latches 650-0 through 650-3, respectively. Master latch 710 includes an AND-OR inverter (AOI) gate 712 cross-coupled with a NOR gate 720. Slave latch 750 includes an OR-AND inverter (OAI) gate 752 cross-coupled with a NAND gate 756 and an inverter 760.

[0157] Specifically, the master latch 710 includes a first PMOS FET T1 and a second PMOS FET T2 coupled in series between an upper voltage rail Vdd and the output (node ​​pn1) of the AOI gate 712. The master latch 710 further includes a first NMOS FET T3 and a second NMOS FET T4 coupled in series between the output (node ​​pn1) of the AOI gate 712 and a lower voltage rail (e.g., ground). The PMOS FET T1 is coupled to the input data dm , PMOS FET T2 has a gate coupled to the output of NOR gate 720 (node ​​pn2), and NMOS FET T3 has a gate coupled to the output of NOR gate 720 (node ​​pn3). m , and NMOS FET T4 includes a gate configured to receive the master clock mclk.

[0158] The master latch 710 further includes a PMOS FET T5, a PMOS FET T6, an NMOS FET T7, and an inverter 714. The PMOS FETs T5 and T6 are coupled in series between the upper voltage rail Vdd and the output of the AOI gate 712 (node ​​pn1). The PMOS FET T5 includes a gate configured to receive the master clock mclk, and the PMOS FET T6 includes a gate coupled to the output of the inverter 714. The inverter 714 includes an input coupled to the output of the AOI gate 712 (node ​​pn1). The NMOS FET T7 is coupled between the output of the AOI gate 712 (node ​​pn1) and the lower voltage rail and includes a gate coupled to the output of the NOR gate 720 (node ​​pn2). Similarly, the circuit including the inverter 714 and the PMOS FET T6 addresses racing conditions and falling clock transparency (FCT) margins, as previously discussed.

[0159] NOR gate 720 further includes PMOS FETs T8 and T9 coupled in series between the upper voltage rail Vdd and the output (node ​​pn2) of NOR gate 720, and NMOS FET T10 coupled in parallel with NMOS FET T11 between the output (node ​​pn2) of NOR gate 720 and the lower voltage rail. PMOS FET T9 and NMOS FET T10 include gates coupled to the output (node ​​pn1) of AOI gate 712, PMOS FET T8 includes a gate configured to receive the master clock mclk, and NMOS FET T11 includes a gate configured to receive the master clock mclk.

[0160] With respect to slave latch 750, OAI gate 752 includes PMOS FET T12 and PMOS FET T13 coupled in series between the upper voltage rail Vdd and the output (node ​​pn3) of OAI gate 752. OAI gate 752 further includes NMOS FET T14 and NMOS FET T15 coupled in series between the output (node ​​pn3) of OAI gate 752 and the lower voltage rail. PMOS FET T12 includes a gate configured to receive a corresponding slave clock sclk, and PMOS FET T13 includes a gate configured to receive a corresponding slave clock sclk at the output of inverter 714.

[0161]

number

[0162] , NMOS FET T14 has its gate coupled to the output of NOR gate 720 (node ​​pn2), and NMOS FET T15 has its gate coupled to the output of NAND gate 756 (node ​​pn4).

[0163] OAI gate 752 further includes a PMOS FET T16 coupled between the upper voltage rail Vdd and the output of OAI gate 752 (node ​​pn3), and includes a gate coupled to the output of NAND gate 756 (node ​​pn4). Additionally, OAI gate 752 includes NMOS FETs T17 and T18 coupled in series between the output of OAI gate 752 (node ​​pn3) and the lower voltage rail. OAI gate 752 further includes an inverter 754 having an input coupled to the output of OAI gate 752 (node ​​pn3) and an output coupled to the gate of NMOS FET T17. NMOS FET T18 includes a gate configured to receive the corresponding slave clock sclk. Similarly, the circuit including inverter 754 and NMOS FET T17 addresses racing conditions, as previously discussed.

[0164] NAND gate 756 of slave latch 750 includes a first input coupled to the output (node ​​pn3) of OAI gate 752, a second input configured to receive a corresponding slave clock sclk, and an output (node ​​pn4) for generating an internal signal x. Inverter 760 includes an input coupled to the output (node ​​pn3) of OAI gate 752 and an output configured to generate output data q.

[0165] Data d m to the slave latch 750 may be as follows: When the master clock mclk and the slave clock sclk exhibit substantially time-aligned rising edges, the master latch 710 becomes transparent and the slave latch 750 becomes opaque. For example, in response to a high logic level of the master clock mclk, the NMOS FET T11 turns on, applying a low voltage rail (e.g., logic 0 (0)) to the output (node ​​pn2) of the NOR gate 720. Also, in response to a high logic level of the master clock mclk, the NMOS FET T4 turns on, thereby grounding the source of the NMOS FET T3. Because the output (node ​​pn2) of the NOR gate 720 is at logic 0 (0), the PMOS FET T2 is turned on. Thus, the output (node ​​pn1) of the AOI gate 712 writes the input data dm (e.g.,

[0166]

number

[0167] In this case, data d is received (even if it is inverted). m When the data d is at logic one (1), the node pn1 is at logic zero (0). m is at logic zero (0), node pn1 is at logic one (1). Therefore, the master latch 710 receives the input data d m , the master latch 710 is in a transparent mode.

[0168] For the slave latch 750, a high logic level of the slave clock sclk turns off the PMOS FET T12 and disables the AND operation of the NMOS FETs T13-T15. This configures the slave latch 750 in an opaque mode. A high logic level of the slave clock sclk enables the NAND gate 756. Therefore, the output of the NAND gate 756, which is fed back to the gate of the PMOS FET T16, is the same as the previous data d m-1 Therefore, the inverted previous data d m-1 (i.e.,

[0169]

number

[0170] ) is a logic one (1) and the slave clock sclk is at a logic one (1), the NAND gate 756 outputs the internal signal x as a logic zero (0). The internal signal x being a logic zero (0) turns on the PMOS FET T16, coupling the upper voltage rail Vdd to the node pn3, thereby latching a logic one (1) at the node pn3. The inverter 760 then generates the output signal q as a logic zero (0). Thus, the output data q is the sum of the input data d m-1 Based on.

[0171] Inverted previous data d m-1 (i.e.,

[0172]

number

[0173] ) is at logic 0 (0) and the slave clock sclk is at logic 1 (1), the NAND gate 756 outputs the internal signal x as logic 1 (1). The internal signal x being logic 1 (1) turns off the PMOS FET T16. The inverter 754 may invert the logic 0 (0) at the node pn3 to generate a logic 1 (1) at the gate of the NMOS FET T17. Because the slave clock sclk is also at logic 1 (1), the NMOS FETs T17 and T18 turn on, applying the lower voltage rail to the node pn3, thereby latching a logic 0 (0) at the node pn3. The inverter 760 then generates the output signal q as logic 1 (1). Therefore, the output data q is equal to the input data d m-1 Based on.

[0174] When the master clock mclk and the slave clock sclk0 exhibit the next consecutive substantially time-aligned falling edges, the master latch 710 becomes opaque and the slave latch 750 becomes transparent. In response to the low logic level of the master clock mclk, the NMOS FET T4 turns off, thereby disabling the logical AND operation of the FETs T1-T4. The low logic level of the master clock mclk also turns off the NMOS FET M11. Thus, the cross-coupled NOR gate operation of T5-T7 with the inverter 714 and the FETs T8, T9, and T10 of the NOR gate 720, converts the previously received data d m is latched at the master transmission interval.

[0175] That is, when data dm is logic zero (0), node pn1 is at logic one (1). Inverter 714 inverts the logic one (1) to generate a logic one (0) at the gate of PMOS FET T6. When the gate of PMOS FET T5 receives the low logic level of the master clock mclk, PMOS FETs T5 and T6 turn on, coupling the upper voltage rail Vdd to node pn1, thereby latching a logic one (1) at node pn1. The logic one (1) at node pn1 turns off PMOS FET T9 and turns on NMOS FET T10. Turning on NMOS FET T10 applies the lower voltage rail to node pn2, thereby latching a logic one (0) at node pn2. Node pn2 at logic zero (0) turns off NMOS FET T7, effectively decoupling the lower voltage rail from the logic one (1) at node pn1.

[0176] Conversely, data d m is a logic one (1), node pn1 is at a logic zero (0). Inverter 714 inverts the logic zero (0) to generate a logic one (1) at the gate of PMOS FET T6. PMOS FET T6 is therefore turned off, effectively decoupling node pn1 from the upper voltage rail Vdd. The logic zero (0) at node pn1 turns on PMOS FET T9 and turns off NMOS FET T10. Turning off NMOS FET T10 effectively decouples node pn2 from the lower voltage rail. Turning on PMOS FET T9, and the master clock mclk being at a logic zero (0), and turning on PMOS FET T8 couples the upper voltage rail Vdd to node pn2, ensuring that node pn2 is at a logic one (1).

[0177] For the slave latch 750, the slave clock sclk at a low logic level turns on PMOS FET T12, turns off NMOS FET T18, and causes the NAND gate 756 to generate an internal signal x as a logic one (1), turning on NMOS FET T15 and turning off PMOS FET T16. m is logic 0 (0) at node pn2, then node pn1 is at logic 1 (1), in which case the output of inverter 714

[0178]

number

[0179] is at logic zero (0). With the gate of PMOS FET T13 coupled to the output of inverter 714, logic zero (0) turns on PMOS FET T13, which turns on both PMOS FETs T12 and T13, applying the upper voltage rail Vdd to node pn3, which

[0180]

number

[0181] Sets the d latched in the master latch to logic one (1). m is at logic one (1) at node pn2, NMOS FETs T14 and T15 are both turned on, applying the lower voltage rail to node pn3, thereby

[0182]

number

[0183] to logic zero (0). Therefore, the slave latch 750 stores the data d m from the master latch 710, so that the slave latch 750 is in a transparent mode.

[0184] 8 shows a flow diagram of an exemplary method 800 for storing data according to another aspect of the present disclosure. Method 800 includes, in response to a first edge of a first clock, operating a first latch in a transparent mode by enabling an OR-AND inverter (OAI) gate to receive data and apply the inverted data to an input of a NAND gate cross-coupled to the OAI gate (block 810). Method 800 further includes, in response to a second edge of the first clock, operating the first latch in an opaque mode by disabling the OR portion of the OAI gate and allowing the cross-coupled OAI gate and NAND gate to latch the data (block 820). The first latch including the OAI gate and the NAND gate may correspond to any one of master latches 410 and 510 discussed previously. Method 800 may further include preventing the output of the OAI gate from changing logic state prior to the output of the NAND gate changing logic state in response to a second edge of the first clock.

[0185] Method 800 may further include operating a second latch in a transparent mode by enabling an AND-OR inverter (AOI) gate to receive data from the first latch and apply inverted data to an input of a NOR gate cross-coupled to the AOI gate in response to a first edge of the second clock. The second latch including the AOI gate and the NOR gate may correspond to any one of slave latches 450-0 through 450-3 and 550 discussed previously. Additionally, method 800 may include preventing the output of the AOI gate from changing logic states prior to the output of the NOR gate changing logic states in response to a second edge of the second clock. Method 800 may also include delaying application of data from the first latch to the second latch to increase a tolerance margin between the second edge of the second clock and the first edge of the first clock.

[0186] FIG. 9 shows a flow chart of an exemplary method 900 for storing data according to another aspect of the present disclosure. Method 900 includes operating a first latch in a transparent mode by enabling an AND-OR inverter (AOI) gate to receive data and apply the inverted data to an input of a NOR gate cross-coupled to the AOI gate in response to a first edge of a first clock (block 910). Method 900 further includes operating the first latch in an opaque mode by disabling the AND portion of the AOI gate and allowing the cross-coupled AOI gate and NOR gate to latch data in response to a second edge of the first clock (block 920). The first latch including the AOI gate and the NOR gate may correspond to any one of the master latches 610 and 710 discussed above. Method 900 may further include preventing the output of the AOI gate from changing logic state before the output of the NOR gate changes logic state in response to a second edge of the first clock.

[0187] Method 900 further includes operating a second latch in a transparent mode by enabling an OR-AND inverter (OAI) gate to receive data from the first latch and apply inverted data to an input of a NAND gate cross-coupled to the OAI gate in response to a first edge of the second clock. The second latch including the OAI gate and the NAND gate may correspond to any one of slave latches 650-0 through 650-3 and 750 discussed previously. Additionally, method 900 may include preventing the output of the OAI gate from changing logic states prior to the output of the NAND gate changing logic states in response to a second edge of the second clock. Method 900 may also include delaying application of data from the first latch to the second latch to increase a tolerance margin between the second edge of the second clock and the first edge of the first clock.

[0188] 10 shows a block diagram of an exemplary wireless communication device 1000 according to another aspect of the present disclosure. The wireless communication device 1000 includes an integrated circuit (IC) 1010, which may be configured as a system on a chip (SOC), a transceiver 1050, and at least one antenna 1060. The IC or SOC 1010 includes a latch array 1020 and one or more digital signal processing cores 1030. The latch array 1020 may be configured similarly to the latch array 100, with a master latch configured as any of the previously discussed master latches 410 and 510, and a slave latch configured as any of the previously discussed slave latches 450-0 through 450-3 and 550.

[0189] The at least one antenna 1060 is configured to wirelessly receive radio frequency (RF) receive signals and wirelessly transmit RF transmit signals. The transceiver 1050 is configured to convert the RF receive signals to baseband receive signals and convert the baseband transmit signals to RF transmit signals. The one or more digital processing cores may be configured to process the baseband receive signals to generate first data and generate the baseband transmit signals based on the second data. The latch array may be configured to store the first data and the second data.

[0190] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0191] 100 Latch Array 110-0 to 110-3 Master Latch (M-LCH) 120-0 to 120-3 Clock Gating Circuit (CGC) 130-0 to 130-33 Slave latch 140-00~140-3 Multiplexer 200 flip-flops 210 Master Latch (M-LCH) 212 Transmission Gate 214 NOR Gate 216 First Inverter 218 Second inverter, inverter 250 Slave Latch (S-LCH) 252 First Inverter 254 Transmission Gate 256 Second Inverter 258 Third Inverter 260 Third Inverter, Inverter 300 True Single-Phase Clock (TSPC) Flip-Flops 310 Master Latch 312 Inverter 314 NOR Gate 316 AND-OR Inverter (AOI) Gate 318 AND Gate 320 NOR Gate 350-0~350-3 Slave Latch 352-0 AOI Gate 352-3 AOI Gate 354-0 AND Gate 354-3 AND Gate 356-0 NOR gate 356-3 NOR gate 358-0 First Inverter 358-3 First inverter 360-0 Second inverter 360-3 Second inverter 400 True Single-Phase Clock (TSPC) Flip-Flops 410 Master Latch 412 NAND gates 414 OR-AND Inverter (OAI) Gate 416 OR Gate 418 NAND gates 450-0~450-3 Slave Latch 452-0 AND-OR Inverter (AOI) Gate 452-3 AOI Gate 454-0~454-3 AND gate 456-0 NOR gate 456-3 NOR gate 456-0 NOR gate 458-3 NOR gate 458-0 NOR gate 460-0 inverter 460-3 Inverter 500 True Single Phase Clock (TSPC) Flip-Flops 510 Master Latch (M-LCH) 512 OR-AND Inverter (OAI) Gate 514 Inverter 520 NAND gates 550 Slave Latch (S-LCH) 552 AND-OR inverter, AOI gate 554 Inverter 556 NOR Gate 560 Inverter 600 True Single-Phase Clock (TSPC) Flip-Flops 610 Master Latch 612 NOR Gate 614 AND-OR Inverter (AOI) Gate 616 AND Gate 618 NOR Gate 650-0~650-3 Slave Latch 652-0 OR-AND inverter (OAI) gate 652-3 OR-AND inverter (OAI) gate 654-0 to 654-3 OR gate 656-0 NAND gate 656-3 NAND gate 658-0 NAND gate 658-3 NAND gate 660-0 Inverter 660-3 Inverter 700 True Single-Phase Clock (TSPC) Flip-Flops 710 Master Latch (M-LCH) 712 AND-OR Inverter (AOI) Gate 714 Inverter 720 NOR Gate 750 Slave Latch (S-LCH) 752 OR-AND Inverter (OAI) Gate 754 Inverter 756 NAND gates 760 Inverter 800 ways 900 methods 1000 Wireless Communication Devices 1010 Integrated Circuits (ICs) 1020 Latch Array 1030 Digital Signal Processing Core 1050 Transceiver 1060 Antenna

Claims

1. An apparatus comprising: An OR-AND inverter (OAI) gate, an OR gate including a first input configured to receive a first clock and a second input configured to receive input data; a first NAND gate having a first input coupled to an output of the OR gate; an OR-AND inverter (OAI) gate, a second NAND gate including a first input configured to receive the first clock, a second input coupled to the output of the first NAND gate, and an output coupled to the second input of the first NAND gate; a first latch including: an AND gate including a first input coupled to the output of the second NAND gate of the first latch and a second input configured to receive a second clock; a first NOR gate having a first input coupled to an output of the AND gate; an AND-OR inverter (AOI) gate including: a second NOR gate including a first input configured to receive the second clock, a second input coupled to an output of the first NOR gate, and an output coupled to the second input of the first NOR gate; and a second latch including Device.

2. The OAI gate: a first field effect transistor (FET) including a gate configured to receive the first clock; a second FET including a gate configured to receive the input data, the first FET and the second FET being coupled in series between a first voltage rail and the output of the first NAND gate; a third FET including a gate coupled to the output of the second NAND gate; a fourth FET including a gate configured to receive the input data, the third FET and the fourth FET being coupled in series between the output of the first NAND gate and a second voltage rail; and a fifth FET including a gate coupled to the output of the second NAND gate, the fifth FET being coupled between the first voltage rail and the output of the first NAND gate; a sixth FET including a gate configured to receive the first clock, the sixth FET being coupled between the output of the first NAND gate and the second voltage rail; an inverter including an input coupled to the output of the first NAND gate; a seventh FET including a gate coupled to an output of the inverter, the seventh FET being coupled between the output of the first NAND gate and the sixth FET; Including, The first FET, the second FET, and the fifth FET are each configured as a p-channel metal oxide semiconductor field effect transistor (PMOS FET), and the third FET, the fourth FET, the sixth FET, and the seventh FET are each configured as an n-channel metal oxide semiconductor field effect transistor (NMOS FET).

2. The apparatus of claim 1.

3. The second NAND gate: a first field effect transistor (FET) including a gate coupled to the output of the first NAND gate, the first FET being coupled between a first voltage rail and the output of the second NAND gate; a second FET including a gate configured to receive the first clock, the second FET being coupled between the first voltage rail and the output of the second NAND gate; a third FET including a gate coupled to the output of the first NAND gate; a fourth FET including a gate configured to receive the first clock, the third FET and the fourth FET being coupled in series between the output of the second NAND gate and a second voltage rail; Including, The first FET and the second FET are each configured as a p-channel metal oxide semiconductor field effect transistor (PMOS FET), and the third FET and the fourth FET are each configured as an n-channel metal oxide semiconductor field effect transistor (NMOS FET).

2. The apparatus of claim 1.

4. 2. The apparatus of claim 1 , wherein the second latch further comprises an inverter having an input coupled to the output of the NOR gate and an output configured to produce output data based on the input data.

5. The AOI gate is a first field effect transistor (FET) including a gate coupled to the output of the second NOR gate; a second FET including a gate coupled to the output of the second NAND gate of the first latch, the first FET and the second FET being coupled in series between a first voltage rail and the output of the first NOR gate; a third FET including a gate coupled to an output of an inverter of the first latch, the input of the inverter being coupled to the output of the first NAND gate; a fourth FET including a gate configured to receive the second clock, the third FET and the fourth FET being coupled in series between the output of the first NOR gate and a second voltage rail; and a fifth FET including a gate configured to receive the second clock, the fifth FET being coupled between the first voltage rail and the output of the first NOR gate; a sixth FET including a gate coupled to the output of the second NOR gate, the sixth FET being coupled between the output of the first NOR gate and the second voltage rail; an inverter including an input coupled to the output of the first NOR gate; a seventh FET including a gate coupled to an output of the inverter, the seventh FET being coupled between the fifth FET and the output of the first NOR gate; 2. The apparatus of claim 1, wherein the first FET, the second FET, the fifth FET, and the seventh FET are each configured as a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET), and the third FET, the fourth FET, and the sixth FET are configured as n-channel metal-oxide-semiconductor field effect transistors (NMOS FET).

6. An apparatus comprising: an AND gate including a first input configured to receive input data and a second input configured to receive a clock; a first NOR gate having a first input coupled to an output of the AND gate; an AND-OR inverter (AOI) gate including: a second NOR gate having a first input configured to receive the clock, a second input coupled to the output of the first NOR gate, and an output coupled to the second input of the first NOR gate; a first latch including: An OR-AND inverter (OAI) gate, an OR gate including a first input configured to receive a first clock and a second input configured to receive input data; a first NAND gate having a first input coupled to an output of the OR gate; an OR-AND inverter (OAI) gate, a second NAND gate including a first input configured to receive a second clock, a second input coupled to the output of the first NAND gate, and an output coupled to the second input of the first NAND gate; and a second latch including Device.

7. 7. The apparatus of claim 6, wherein the second latch further comprises an inverter having an input coupled to the output of the first NAND gate and an output configured to produce output data based on the input data.

8. The AOI gate is a first field effect transistor (FET) including a gate coupled to the output of the second NOR gate; a second FET including a gate configured to receive the input data, the first FET and the second FET being coupled in series between a first voltage rail and the output of the first NOR gate; a third FET including a gate configured to receive a signal based on a delayed version of the input data; a fourth FET including a gate configured to receive the clock, the third FET and the fourth FET being coupled in series between the output of the first NOR gate and a second voltage rail; a fifth FET including a gate configured to receive the clock, the fifth FET being coupled between the first voltage rail and the output of the first NOR gate; a sixth FET including a gate coupled to the output of the second NOR gate, the sixth FET being coupled between the output of the first NOR gate and the second voltage rail; an inverter including an input coupled to the output of the first NOR gate; a seventh FET including a gate coupled to an output of the inverter, the seventh FET being coupled between the fifth FET and the output of the first NOR gate.

7. The apparatus of claim 6.

9. 9. The apparatus of claim 8, wherein the first FET, the second FET, the fifth FET, and the seventh FET are each configured as a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET), and the third FET, the fourth FET, and the sixth FET are configured as n-channel metal-oxide-semiconductor field effect transistors (NMOS FET).

10. 1. A method comprising: operating a first latch in a transparent mode by enabling an OR-AND inverter (OAI) gate to receive data and apply an inverted data to an input of a NAND gate cross-coupled to said OAI gate in response to a first edge of a first clock; in response to a second edge of the first clock, disabling an OR portion of the OAI gate and allowing the cross-coupled OAI gate and NAND gate to latch the data, thereby operating the first latch in an opaque mode; operating a second latch in a transparent mode by enabling an AND-OR inverter (AOI) gate to receive the data from the first latch and to apply the inverted data to an input of a NOR gate cross-coupled to the AOI gate in response to a first edge of a second clock; and in response to a second edge of the second clock, disabling an AND portion of the AOI gate and allowing the cross-coupled AOI gate and NOR gate to latch the data, thereby operating the second latch in an opaque mode. method.

11. 11. The method of claim 10, further comprising preventing an output of the OAI gate from changing logic state prior to an output of the NAND gate changing logic state in response to the second edge of the first clock.

12. 11. The method of claim 10, further comprising the step of preventing the output of the AOI gate from changing logic state prior to the output of the NOR gate changing logic state in response to the second edge of the second clock.

13. 11. The method of claim 10, further comprising delaying application of the data from the first latch to the second latch to increase a tolerance margin between the second edge of the second clock and the first edge of the first clock.

14. 1. A wireless communication device, comprising: at least one antenna configured to wirelessly receive radio frequency (RF) receive signals and wirelessly transmit RF transmit signals; A transceiver comprising: converting the RF received signal into a baseband received signal; Converting a baseband transmission signal into the RF transmission signal A transceiver configured as described above. One or more digital signal processing cores, Processing the baseband received signal to generate first data; generating the baseband transmission signal based on second data one or more digital signal processing cores configured to a latch array configured to store the first data and the second data, the latch array including at least the device according to any one of claims 1 to 9; 2. A wireless communication device comprising:

15. 1. A method comprising: operating a first latch in a transparent mode by enabling an AND-OR inverter (AOI) gate to receive data and apply an inverted data to an input of a NOR gate cross-coupled to said AOI gate in response to a first edge of a first clock; operating the first latch in an opaque mode by disabling an AND portion of the AOI gate and allowing the cross-coupled AOI gate and NOR gate to latch the data in response to a second edge of the first clock; operating a second latch in a transparent mode by enabling an OR-AND inverter (OAI) gate to receive the data from the first latch and apply the inverted data to an input of a NAND gate cross-coupled to the OAI gate in response to a first edge of a second clock; and in response to a second edge of the second clock, disabling an OR portion of the OAI gate and allowing the cross-coupled OAI gate and NAND gate to latch the data, thereby operating the second latch in an opaque mode. method.

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