Look-up table based analog-to-digital converter

Abstract

The analog-to-digital converter system (10) includes a digital-to-analog converter (32) for generating a calibration voltage based on a digital input code, and an analog-to-digital converter (18) connected to the digital-to-analog converter (32) for receiving the calibration voltage from the digital-to-analog converter (32), receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating a digital output code based on the sampled voltage. The analog-to-digital converter system (10) may have a look-up table (20) connected to the analog-to-digital converter (18) for storing a first digital output code in association with the digital input code. A method for calibrating the analog-to-digital converter system (10) is also described.

Description

[Technical field]

[0001] Analog-to-digital (A / D) converters (ADCs) can be used to generate digital codes that represent analog signals. Analog-to-digital converters for digitizing signals in radio frequency sampling receivers can be required to operate at high speeds. Analog-to-digital converters are described in U.S. Patent Application Publication Nos. 2012 / 0212358 (Shi et al.), 2015 / 0244386 (El-Chammas), 2019 / 0007071 (Nagarajan et al.), and 2019 / 0280703 (Naru et al.). [Patent Document 1] U.S. Patent Application Publication No. 2012 / 0212358 [Patent Document 2] U.S. Patent Application Publication No. 2015 / 0244386 [Patent Document 3] U.S. Patent Application Publication No. 2019 / 0007071 [Patent Document 4] U.S. Patent Application Publication No. 2019 / 0280703

[0002] Some analog-to-digital converters have one or more voltage-to-delay (V2D) components and operate, at least in part, in the delay domain. Delay-based analog-to-digital converters are described in U.S. Patent Application Nos. 16 / 217,643 (Soundararajan et al., filed December 12, 2018) (U.S. Publication No. 2020 / 0195268 (June 18, 2020)), 16 / 410,698 (Dusad et al., filed May 13, 2019) (U.S. Patent No. 10,673,456 (June 2, 2020)), and 16 / 517,796 (Pentakota et al., filed July 22, 2019) (U.S. Patent No. 10,673,453 (June 20, 2020)). The entire disclosures of U.S. patent application Ser. Nos. 16 / 217,643, 16 / 410,698 and 16 / 517,796 are incorporated herein by reference. Additionally, the entire disclosures of five U.S. patent applications identified in Table 1 below are incorporated herein by reference. The delay-based analog-to-digital converter can be operated at high speeds with reduced area and power requirements, if desired. [Patent Document 5] U.S. Patent Application No. 16 / 217,643 [Patent Document 6] U.S. Patent Application No. 16 / 410,698 [Patent Document 7] U.S. Patent Application No. 16 / 517,796 [Table 1] Summary of the Invention

[0003] The present description relates to an analog-to-digital converter system, and in particular to an analog-to-digital converter system having a digital-to-analog converter for generating a calibration voltage based on a digital input code, and an analog-to-digital converter coupled to the digital-to-analog converter for receiving the calibration voltage from the digital-to-analog converter, receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating the digital output code based on the sampled voltage.

[0004] The present description also relates to a lookup table based analog-to-digital converter system, and in particular to a lookup table based analog-to-digital converter system having a digital-to-analog converter for generating a calibration voltage based on a digital input code, an analog-to-digital converter connected to the digital-to-analog converter for receiving the calibration voltage, receiving a sampled voltage, generating a first digital output code based on the calibration voltage, and generating a second digital output code based on the sampled voltage, and a lookup table connected to the analog-to-digital converter for storing the first digital output code in association with the digital input code.

[0005] The present description also relates to a method of calibrating an analog-to-digital converter system, the method including causing a digital-to-analog converter to generate a calibration voltage based on a digital input code, causing the analog-to-digital converter to receive the calibration voltage from the digital-to-analog converter, generate a first digital output code based on the calibration voltage, generate a second digital output code based on the sampled voltage, and storing the first digital output code in a lookup table in association with the digital input code. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a delay-based analog-to-digital converter system.

[0007] [Diagram 2] FIG. 2 is a diagram of how the lookup table of the analog-to-digital converter system of FIG. 1 is populated and used.

[0008] [Diagram 3]2 is a block diagram of the analog-to-digital converter system of FIG. 1, showing two analog-to-digital converters and two look-up tables arranged in parallel.

[0009] [Figure 4] FIG. 2 is a block diagram of the analog-to-digital converter system of FIG. 1, showing three analog-to-digital converters arranged in parallel.

[0010] [Diagram 5] FIG. 2 is a block diagram of the back end of the analog-to-digital converter of FIG. 1.

[0011] [Figure 6] FIG. 6 is a block diagram of a combiner for connecting the multi-bit stage shown in FIG. 5 to the first one of the single-bit stages.

[0012] [Figure 7] 6 is a graph showing the AND gate delay and the comparator delay produced by the AND gate and the delay comparator, respectively, of the back end of FIG. 5, where the AND gate delay and the comparator delay are functions of the input signal delay.

[0013] [Figure 8] 8 is a graph showing the output signal delay as a function of the input signal delay of FIG. 7;

[0014] [Figure 9] FIG. 6 is a circuit diagram of an example of a comparator circuit merged into the sign-out circuit and delay-out circuit for the back-end of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] FIG. 1 illustrates an analog-to-digital converter system 10 constructed in accordance with the present disclosure. The system 10 receives a sampled voltage V on an input line 16. INThe system includes at least first and second multiplexers 12 and 14, which may be analog multiplexers for receiving an output voltage V1 from the first multiplexer 12 on line 17, an analog-to-digital converter 18 for receiving an output voltage V1 from the first multiplexer 12 on line 17, and a look-up table (LUT) 20. As will be explained in more detail hereinafter, the look-up table 20 may be constructed of digital memory circuits and may form one or more portions of a memory / digital processor system 300 (FIG. 4). The look-up table 20 is populated in a calibration mode. The populated table 20 is then used as an information resource in an analog-to-digital conversion (or mission) mode.

[0016] The analog-to-digital converter system 10 also includes a third multiplexer 22 (FIG. 1), which may be a digital multiplexer for receiving a digital code from the analog-to-digital converter 18 on line 24 and applying the digital code to the look-up table 20. As will be described in more detail hereinafter, the third multiplexer 22 operates in a calibration mode and an analog-to-digital conversion (or mission) mode on read and write paths 26 and 28, respectively. The first and second multiplexers 12 and 14 and the third multiplexer 22 are operated by a calibration controller 30. A digital-to-analog (D / A) converter (DAC) 32 is also operated by the calibration controller 30. The digital-to-analog converter 32 is coupled to a calibration voltage V DAC is applied on line 34 to the first and second multiplexers 12 and 14. The calibration voltage V DAC is generated by digital-to-analog converter 32 based on a digital input code 100 (FIG. 2) applied to digital-to-analog converter 32 (FIG. 1) by calibration controller 30 on line 36.

[0017] The first multiplexer 12, the analog-to-digital converter 18, and the third multiplexer 22 can be operated together in a calibration mode and an analog-to-digital conversion mode. In the calibration mode, the calibration controller 30 outputs a series of two ∧ N(2 N 2) to generate a digital code 100 (FIG. 2) for digital-to-analog converter 32 to convert the corresponding sequence of 2 ∧ N different voltages V DAC =Vr / (2 ∧ N) is applied on line 34, where Vr is the sampled voltage V expected to be sampled and input on line 16. IN where N bits is the resolution of the first analog-to-digital converter 18. Thus, for example, V IN is expected to be in the range of 0V to 5V, then Vr is a value near 5V.

[0018] In the calibration mode, as shown as an example (N=9) in FIG. 2, the calibration controller 30 (FIG. 1) outputs a series of two ∧ 9=512 to the digital-to-analog converter 32 (FIG. 1). DAC Generate the calibration voltage V DAC is transmitted by the first multiplexer 12 on line 17 to the first analog-to-digital converter 18 as an output voltage V1. The first analog-to-digital converter 18 receives the calibration voltage V DAC (V1) into a corresponding N+n-bit output code 102 (FIG. 2). To populate the lookup table, the output code 102 is recorded in the lookup table 20 via the third multiplexer 22 (FIG. 1) and the write path 26.

[0019] 2, N+n>N (i.e., n>0) to accommodate the non-linearity of the first analog-to-digital converter 18. In the illustrated example, the total number (N+n) of possible output codes 102 that can be output by the analog-to-digital converter 18 must be greater than the actual number (N) of input codes 100 stored in the lookup table 20. This is because, in operation, the relationship between the output codes generated by the analog-to-digital converter 18 and the corresponding input codes transmitted on line 36 is not expected to be linear. In the illustrated example, N=9, 2 9 =512, the input codes 100 stored in the lookup table 20 range from 0 to 511, with the least significant bit (LSB) of each input code 100 representing 1 millivolt (mv) on line 17, while N+n=11, 2 11 = 2048, so the total number of different codes 102 that can be output by the analog-to-digital converter 18 ranges from 0 to 2047.

[0020] In the look-up table 20, the 2 ∧ The N output code 102 is sent by the calibration controller 30 to the digital-to-analog converter 32. ∧The lookup table 20 is correlated with N input codes 100. An empirically developed transfer function 104 (FIG. 2) from the input code 100 to the recorded output code 102 is nonlinear, but monotonic, and unique for each input code 100. In the illustrated example, the transfer function 104 is established empirically by observing the output of the analog-to-digital converter 18 in a calibration mode in response to different input codes 100 being input to the digital-to-analog converter 32. Also, the illustrated method of populating the lookup table 20 is memoryless in the sense that the mapping of a particular input code value (e.g., 5) to an output code value (e.g., 14) is independent of the value of the previous input code (e.g., 4). If desired, each capture of an output code may include capturing multiple codes from the analog-to-digital converter 18 and averaging the codes to remove noise before mapping.

[0021] In an analog-to-digital conversion (or mission) mode, which is also illustrated by way of example in FIG. 2, the first multiplexer 12 (FIG. 1) receives the sampled voltage V IN on line 16. The first multiplexer 12, under the control of the calibration controller 30, receives the sampled voltage V IN (V1) to the analog-to-digital controller 18, which outputs a corresponding code to the third multiplexer 22. The calibration controller 30 causes the third multiplexer 22 to apply the code to the lookup table 20 via a read path 28.

[0022] The unknown sampled voltage V IN For each unknown voltage V (V1), the N+n bit output of the analog-to-digital converter 18 is looked up in the look-up table 20 and the calibrated value (in terms of the N bit input code) is output on line 50. Based on FIG. INIf (V1) causes analog-to-digital converter 18 to output a code for 37 units (for example), then lookup table 20 is used to output a code for 10 units on output line 50. In the illustrated example, in mission mode, lookup table 20 is used to select the stored input code whose corresponding output code is closest to the code output by analog-to-digital converter 18, but if the code output by analog-to-digital converter 18 is equidistant between two stored output codes, then lookup table 20 is used to select the stored input code whose stored output code is the smaller of the two stored output codes. Thus, in the example illustrated in FIG. 2, since 37 is equidistant between 34 and 40 and 34 is less than 40, the selected stored input code is 34.

[0023] A specific illustrated example is when the calibration controller 30 issues an input code 100 for 10 units in the calibration mode, the digital-to-analog converter 32 outputs a voltage V DAC (V1) is applied, the voltage is converted by the analog-to-digital converter 18 to an output code 102 for 34 units, and the output code 100 (34 units) is correlated to the input code 102 for 10 units and recorded in the look-up table 20. In other words, when the system 10 is calibrated, a correlation between an input code of 10 units and an output code of 34 units is observed, and the observed output code (34 units) is associated with the input code (10 units) and stored in the look-up table 20. The transfer function 104 is based on calibration, and the correlation stored in the look-up table 20 is created by experiment (i.e., observation). However, the present description is not limited to the illustrated example.

[0024] In the illustrated configuration, the digital-to-analog converter 32 generates a calibration voltage V that covers the input range Vr of the analog-to-digital converter 18. DACIn the calibration mode, the linear output V of the digital-to-analog converter 32 is DAC is input to the analog-to-digital converter 18. For each such input code 100, Vr / (2 ∧ At step intervals of n (N), an N+n-bit output code 102 is output by the analog-to-digital converter 18. The look-up table 20 may include memory elements of a digital-like circuit. In the illustrated example, the output codes 102 on lines 24, 28 in the calibration mode are stored in memory elements of the look-up table 20.

[0025] Thus, during the calibration mode, the nonlinear input-output characteristic of the analog-to-digital converter 18 (circuit block) is obtained using a known input code 100. The calibration process in which the look-up table 20 is populated can be a relatively time-consuming process that is performed at regular but long intervals. Then, during the analog-to-digital conversion mode, the unknown sampled voltage V IN , the system 10 converts the output code 102 into a sampled voltage V IN The nonlinear processing performed by analog-to-digital converter 18 can be performed at high speed, during which the output code of the nonlinear block is passed through the inverse of the block's transfer function 104 (FIG. 2) obtained in the calibration mode to obtain a linear output (e.g., the code output on line 50). In the illustrated configuration, the calibration and analog-to-digital conversion processes can be advantageously performed without complex arithmetic functions or hardware requiring significant space and power.

[0026] If desired, the analog-to-digital converter 18 may be constructed as shown, as an example, and as described in connection with FIGS. 5-9. The analog-to-digital converter 18 may have a delay circuit and a delay comparator operated in parallel to generate two bits of digital information. The delay residues from the multi-bit stages may be combined by a combiner and applied to a series of single-bit stages. If desired, the first, second, and third through i-th single-bit stages may be constructed and operated in successive stages to provide each bit of digital information to the look-up table 20. It is possible to design time-based units of the type used in the systems described hereinafter to operate the time-based units at high speeds, but they are inherently nonlinear. In the delay-based signal processing examples described hereinafter in connection with FIGS. 5-9, the residues passed at each stage are monotonic but nonlinear.

[0027] 3 and 4, the analog-to-digital converter system 10 may have two, three, four, or more channels. Two channels are shown in FIG. 3. Three channels are shown in FIG. 4. As shown in FIG. 3, the second channel includes a second analog-to-digital converter 110, a second look-up table 112, and a combiner circuit 114. The second analog-to-digital converter 110 is essentially the same as the first analog-to-digital converter 18 in the sense that both are made of essentially the same components arranged in substantially the same configuration. Nevertheless, due to differences in manufacturing, the two analog-to-digital converters 18 and 110 may have different transfer functions 104, and as a result, it may be desirable to calibrate the two devices 18 and 110 separately. A fourth multiplexer, similar to the third multiplexer 22 shown in FIG. 1, is disposed between the second analog-to-digital converter 110 and the second look-up table 112. The third and fourth multiplexers 22 may be constructed and operated in essentially the same manner, and are not shown in FIG. 3 for clarity of illustration.

[0028] 3 shows that the first channel is operated in a calibration mode and the second channel is operated in an analog-to-digital conversion mode. Thus, the first multiplexer 12 provides (via MUX12 output, V1) a calibration voltage V DAC to a first analog-to-digital converter 18 to populate a first look-up table 20, while a second multiplexer 14 receives (via MUX14 output, V2) the sampled voltage V INv to a second analog-to-digital converter 110 to generate an output code, which is subjected to the inversion of a transfer function stored in a second lookup table 112 for the second analog-to-digital converter 110 to generate a calibrated code, which is output via a combiner circuit 114 on line 50.

[0029] If desired, the analog-to-digital converter system 10 can be operated in a calibration mode while the first channel is operated in an analog-to-digital conversion mode. In that case, the second multiplexer 14 can be connected to a calibration voltage V DAC (V2) to the second analog-to-digital converter 110 to populate the second look-up table 112, while the first multiplexer 12 transmits the sampled voltage V IN (V1) is sent to a first analog-to-digital converter 18 to generate an output code which is then subjected to the inversion of a transfer function stored in a first look-up table 20 to generate a calibrated code which is output on line 50 via a combiner circuit 114. In the illustrated configuration, the combiner circuit 114 is selectively operated under the control of the calibration controller 30.

[0030] Referring to Fig. 4, the third channel may be provided with a third analog-to-digital converter 200 and a fifth multiplexer 202, which is a digital multiplexer. In each of the three channels, buffers 204, 206, and 208 are disposed between the respective multiplexers 12, 14, and 202 and the respective analog-to-digital converters 18, 110, and 200. For clarity of illustration, the buffers 204, 206, and 208 are not shown in Figs. 1 and 3. Similarly, suitable digital multiplexers may be disposed between the three analog-to-digital converters 18, 110, and 200 and the memory / digital processor system 300. The look-up tables 20 and 112 for the first and second channels are part of the memory / digital processor system 300, as are similar look-up tables for the third channel. Each of the three look-up tables operates as described above in connection with the look-up table 20 for the first channel.

[0031] As shown in FIG. 4, the second sampled voltage V IN2 (2) is applied to the multiplexers 14 and 202 of the second and third channels, and the first sampled voltage V IN (1) is applied to the multiplexers 12 and 14 of the first and second channels, and the calibration voltage V DAC (D) is applied to all three channel multiplexers 12, 14, and 202. If desired, the analog to digital converter system 10 can be configured to receive and process the third and fourth sampled voltages (0) and (3) which are applied to the first and fourth multiplexers 12 and 202, respectively. All three channels and the digital to analog converter 32 are operated under the control of a calibration controller 30, which is not shown in FIG. 4 for clarity.

[0032] Thus, if desired, one of the channels of the analog-to-digital converter system 10 can be calibrated while one or more of the other channels are used for analog-to-digital conversion. The multi-channel configuration has the advantage of being relatively easy to expand. In the illustrated configuration, all of the channels can be calibrated using only a single digital-to-analog converter 32, and the number of channels per system can be increased without a proportional increase in high linearity blocks, thus saving power and area. Also, there is no need to match requirements between different channels. In the illustrated configuration, each analog-to-digital converter 18, 100, and 200 can be calibrated independently, thereby reducing or eliminating the requirement for background estimation and calibration algorithms.

[0033] According to another aspect of the present description, if the non-linear analog-to-digital converter is unable to exit the mission mode, the same type of auxiliary analog-to-digital converter may be used in a round robin manner, i.e., while the first analog-to-digital converter is in the calibration phase, the other analog-to-digital converter operates in the mission mode, and vice versa. In this aspect of the present description, the input and digital-to-analog converter output are multiplexed to the first analog-to-digital converter and the auxiliary analog-to-digital converter.

[0034] If desired, some or all of the elements of the devices and systems described herein may be integrated into an integrated circuit (IC) or formed on or above a single semiconductor die (not shown) according to various semiconductor and / or other processes. The conductive lines may be metal structures formed in an insulating layer above the semiconductor die, doped regions (which may be silicided) formed in the semiconductor die, or doped semiconductor structures (which may be silicided) formed on the semiconductor die. Transistors used to implement some example circuit structures may be bipolar junction transistors (BJTs) or metal oxide semiconductor field effect transistors (MOSFETs), and may be n-type or p-type. Integrated devices and elements may also include resistors, capacitors, logic gates, and other suitable electronic devices not shown for clarity.

[0035] The analog-to-digital system 10 may have a good signal-to-noise ratio (SNR), operate at high speeds, and function with lower technology nodes. In accordance with one aspect of the present description, advantages are achieved by providing a linear analog-to-digital converter system having highly nonlinear delay-based components (e.g., of the type shown in FIG. 5), but with reduced area and power requirements, operates at high speeds, and is well scalable with technology nodes. In summary, the present description may be used to provide a highly linear high-speed analog-to-digital converter system 10 that uses inherently nonlinear analog blocks operatively connected to digital circuits.

[0036] In terms of scalability, the performance of digital integrated circuits has improved greatly with CMOS scaling, but this has not been applicable to analog integrated circuits. In accordance with the present description, CMOS scaling can be used to improve performance in analog integrated circuits by using time domain (or delay domain) signal processing. Thus, an analog-to-digital converter system using a time-to-digital converter (TDC) is advantageous. Time-to-digital converters can be inherently nonlinear, but can be designed to be memoryless and monotonic, and can have very good bit error rate (BER) performance because they do not require significant feedback loops. These advantageous properties can be achieved, if desired, by using memoryless devices to build the back-end of the analog-to-digital converter 18, as illustrated in Figures 5-9. As indicated above, in accordance with one aspect of the present description, the mapping of a particular input code value (e.g., 5) to an output code value (e.g., 14) does not depend on the previous input code value (e.g., 4). Also, the back end of the analog-to-digital converter 18 can be constructed so that every time the input code (on line 36) increases during calibration, the corresponding output code (on line 24) also increases, although not necessarily linearly.

[0037] This description provides many advantages. One such advantage is the ability to decouple coupling constraints. In particular, an effectively high speed linear analog-to-digital converter system can be constructed by combining at least three components: (1) a linear, slow digital-to-analog converter 32; (2) one or more non-linear digital-to-analog converters 18, 110, and 200 formed from high speed analog blocks; and (3) a memory / digital processing system 300 having one or more high speed digital-like lookup tables 20 and 112.

[0038] With the architecture described herein, high linearity requirements can be passed to the digital-to-analog converter 32 instead of the analog-to-digital converters 18, 110, and 200. This is an advantage because it is relatively easy to design and implement analog circuits that operate at low speeds with linearity and precision. In accordance with this description, one or more analog-to-digital converters 18, 110, and 200 can be designed to operate at high speeds by compromising linearity. However, the analog-to-digital converters 18, 110, and 200, in combination with the look-up tables 20 and 112, can operate like a linear analog-to-digital converter. Similarly, the memories 20 and 122 can be implemented in digital circuits and configured for high speeds.

[0039] Interfacing external analog signals to high-speed digital processing cores generally requires analog-to-digital converters. As data transmission speeds increase, analog-to-digital converters may be required to operate at very high speeds with good signal-to-noise ratios. Without the benefits of the present description, such constraints may result in high power dissipation and large area requirements for the supporting integrated circuit. These issues may be particularly pronounced at Ghz rates due to analog non-idealities that may limit performance. The present description provides a lookup table based analog-to-digital converter approach that may open up a wide range of architectures using one or more analog-to-digital converters that are inherently non-linear, but can be calibrated to provide superior performance to highly linear analog-to-digital converters.

[0040] The analog-to-digital converter 18 shown in FIG. 1 may have a front end and a back end. The front end may perform a voltage-to-delay function. The back end may perform a delay-to-digital function. In accordance with one aspect of the present description, the front end of the analog-to-digital converter 18 may include one or more voltage-to-delay devices for converting an analog signal on line 17 to delayed signals A0 and B0 on ​​lines 488 and 490 (FIG. 5), such that the delayed signals A0 and B0 represent the voltage V1 on line 17. The front end voltage-to-delay devices that may be used to generate the delayed signals A0 and B0 based on the input voltage V1 may be constructed and operated as described, for example, in U.S. Pat. No. 10,673,456 (based on U.S. patent application Ser. No. 16 / 410,698). The voltage-to-delay device may include, for example, a conversion and folding circuit as described in U.S. Pat. No. 10,673,456, which includes a voltage-to-delay converter block including a preamplifier for converting a voltage signal into a delayed signal, and a folding block including a logic gate coupled to the preamplifier for selecting early and late arriving ones of the delayed signals.

[0041] An example of a voltage-delay device that may be used within the front end of the analog-to-digital converter 18 and may be used to generate the delayed signals A0 and B0 based on the input voltage V1 is shown in U.S. patent application Ser. No. 17 / 131,981, filed Dec. 23, 2020. A voltage-delay device constructed in accordance with U.S. patent application Ser. No. 17 / 131,981 may, for example, have first and second comparators connected to first and second lines carrying complementary voltages representative of the input voltage V1, and generate first and second output signals during an active phase when the complementary voltages reach appropriate threshold voltages such that the delay between the output signals represents the input voltage V1. However, this description is not limited to the devices and processes detailed herein. Other suitable devices may perform suitable voltage-delay functions within the front end of the analog-to-digital converter 18. As noted above, U.S. Patent No. 10,673,456 and U.S. patent application Ser. No. 17 / 131,981 are incorporated herein by reference in their entirety. [Patent Document 8] U.S. Patent Application No. 17 / 131,981

[0042] An example of a back end of an analog-to-digital converter is shown by way of example in Figs. 5-9. The back end may, for example, include a multi-bit stage 798 and first through i-th single-bit stages 7102 and 7104 connected in series with the multi-bit stage 798. If desired, the back end may include three, four, or more such single-bit stages (i=3, 4, or more). The single-bit stages 7102 and 7104 shown in Fig. 5 are examples of consecutive non-linear stages. The back end receives delayed signals A0 and B0 from the voltage-to-delay circuit of the front end. The timing of the delayed signals A0 and B0 has a delay that represents the voltage V1 on line 17. The back end works in conjunction with the calibration engine / controller 740 to generate a corresponding multi-bit digital code that is output on line 24 (Fig. 1). Thus, the digital code on line 24 predictably corresponds very closely to the voltage V1 on line 17.

[0043] Multi-bit stage 798 (FIG. 5) may include delay circuits and delay comparators operating in parallel to generate M bits of digital information on lines 330, 332, 334, and 336. In the illustrated example, M=2. However, M may be greater than two. This description is not limited to the illustrated example. The delay remainder from multi-bit stage 798 may be combined by combiner 304 and applied to a first single-bit stage 7102. If desired, the first through i-th single-bit stages 7102 and 7104 may be constructed and operated as successive stages to provide respective bits of digital information to calibration engine / controller 740.

[0044] The first stage 798 may have, for example, four delay comparators 306, 308, 310, and 312 and is connected to the combiner 304. However, the description is not limited to the details of the shown example. The description may be implemented with a first stage having fewer or more than four delay comparators, if desired. In the configuration shown in the figure, the first stage 798 generates two bits of digital information for the calibration engine / controller 740. In the illustrated embodiment, successive stages 7102 and 7104 each generate a single bit of digital information for the calibration engine / controller 740.

[0045] In the illustrated example, the rising edge of signal B0 on ​​line 490 precedes the rising edge of signal A0 on line 488. The first signal A0 is applied to threshold inputs 494 of delay comparators 306, 308, 310, and 312. In the illustrated configuration, by way of example, delay comparators 306, 308, 310, and 312 are essentially identical to one another. The second signal B0 is applied to four different delay circuits 314, 316, 318, and 320, which in turn generate four corresponding signals B0 on ​​respective lines 322, 324, 326, and 328. 04 , B 03 , B 02 , and B 01 Generate.

[0046] Corresponding signal B 04 , B 03 , B 02 , and B 01 The timing of the delayed signal B is delayed with respect to the timing of the signal B on line 490 by a different known amount that is equal to or less than the maximum gain of the front end. 04 , B 03 , B 02 , and B 01 is applied to a first input 492 of each of the delay comparators 306, 308, 310, and 312. The first delay comparator 306 determines which signal (B 04A0 or A1) arrives first at the first delay comparator 306. Similarly, the second delay comparator 308 issues a code signal on line 330 indicating which signal (B 03 A0) arrives first at the second delay comparator 308. Similarly, the third and fourth delay comparators 310 and 312 issue sign signals on lines 334 and 336 that represent which signal arrives first at the third and fourth delay comparators 310 and 312.

[0047] Since the delay circuits 314, 316, 318, and 320 are different from each other, the delayed signal B 04 , B 03 , B 02 , and B 01 The timing of the rising edges of input signals A0 and B0 differ from one another. Each of delay comparators 306, 308, 310, and 312 issues a sign signal on a respective digital line 330, 332, 334, and 336 to calibration engine / controller 740. The sign signals on lines 330, 332, 334, and 336 are functionally related to the difference between the rising edges of input signals A0 and B0, and thus are functionally related to the voltage V1 on line 17.

[0048] The amount of delay provided by the four delay comparators 306, 308, 310, and 312 are different from one another so that the sign signals 330, 332, 334, and 336 provide four binary data points for determining the two bits of the output. For example, B0 leads A0, B 01 If A0 leads B0, then the calibration engine / controller 740 determines that the delay between the timing of signals A0 and B0 is greater than the delay introduced by the four delay circuits 320. Similarly, if B0 leads A0 and A0 is greater than B 02 , B 03 , and B 04 , then the calibration engine / controller 740 determines that the delay between the timing of signals A0 and B0 is less than each of the delays introduced by the third, second, and first delay circuits 318, 316, and 314.

[0049] If desired, the structure and operation of delay comparators 306, 308, 310, and 312 may be the same as that of delay comparator 482 described hereinafter. In operation, delay comparators 306, 308, 310, and 312 generate respective delayed signals IN4, IN3, IN2, and IN1 on respective output lines 338, 340, 342, and 344. Delayed signals IN4, IN3, IN2, and IN1 are applied to combiner 304 by output lines 338, 340, 342, and 344. In the illustrated configuration, delay circuits 314, 316, 318, and 320 are different from one another, resulting in different amounts of delay, while delay comparators 306, 308, 310, and 312 are essentially the same. Thus, the timing of the rising edges of delayed signals IN4, IN3, IN2, and IN1 are different from one another.

[0050] In the example shown in FIG. 6, the combiner 304 has two fifth delay circuits 350 and 352, two AND gates 354 and 356, and a sixth delay circuit 358. In the illustrated configuration, the fifth delay circuits 350 and 352 are essentially identical to each other. However, this description is not limited to the details of the structure shown and described herein. The third and fourth delay signals IN2 and IN1 are applied to the fifth delay circuits 350 and 352 on conductive lines 342 and 344, and the first and second delay signals IN4 and IN3 are applied to the AND gates 354 and 356 on conductive lines 338 and 340. The output signals from the fifth delay circuits 350 and 352 are also applied to the AND gates 354 and 356 on conductive lines 362 and 364, respectively. The output signal from one AND gate 356 is applied on conductive line 360 ​​to a sixth delay circuit 358, and the other AND gate 354 produces a signal A1 on conductive line 488A1. The sixth delay circuit 358 produces a signal B1 on conductive line 490B1.

[0051] In operation, the timing of the rising edges of the signals output from the fifth and sixth delay circuits 350, 352, and 358 on conductive lines 362, 364, and 490 are delayed relative to the respective timing of the rising edges of the signals input to the delay circuits 350, 352, and 358. The timing of the rising edges of the signals output from the AND gates 354 and 356 on lines 488A1 and 360 correspond to the respective timing of the later arriving signals input to the AND gates 354 and 356. The relative timing of the rising edges of the signals A1 and B1 on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the voltage V1 on line 17 (FIG. 1). In other words, the delay circuits 350, 352, and 358 and the logic gates 354 and 356 establish a transfer function between the delay of the incoming signals IN4, IN3, IN2, and IN1 and the delay of the first and second signals A1 and B1.

[0052] For the illustrated configuration, the transfer functions are as follows: [A] If the timing of the signal on line 338 precedes the timing of the signal on line 362 (the timing of the signal on line 362 corresponds to the timing of the signal on line 342 delayed by the fifth delay circuit 350), then the timing of the signal on line 488A1 corresponds to the timing of the signal on line 362, but if the timing of the signal on line 362 precedes the timing of the signal on line 338, then the timing of the signal on line 488A1 corresponds to the timing of the signal on line 338. [B] If the timing of the signal on line 340 precedes the timing of the signal on line 364 (the timing of the signal on line 364 corresponds to the timing of the signal on line 344 delayed by the fifth delay circuit 352), then the timing of the signal on line 360 ​​corresponds to the timing of the signal on line 364, but if the timing of the signal on line 364 precedes the timing of the signal on line 340, then the timing of the signal on line 360 ​​corresponds to the timing of the signal on line 340. [C] The timing of the signal on line 490B1 corresponds to the timing of the signal on line 360 ​​delayed by the sixth delay circuit 358.

[0053] The amount by which the delay elements 350, 352, and 358 delay the signals transmitted therethrough may be selected to maximize or improve as much as possible the gain of the first and second signals A1 and B1. The combiner 304 operates in a delay mode in which the gain is related to the delay (rather than the voltage). If the gain of the first and second signals A1 and B1 is too low, i.e., if the first and second signals A1 and B1 are too close to each other, the information represented by the relative timing of these signals may be difficult to resolve.

[0054] One aspect of this description is that the timing of signals on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the timing of signals on lines 338, 340, 342, and 344. If a set of signal timings on lines 338, 340, 342, and 344 is a first set of signal timings on lines 488A1 and 490B1, then whenever the same set of signal timings occurs on lines 338, 340, 342, and 344, the same first set of signal timings can be expected to occur on lines 488A1 and 490B1. Similarly, if another set of signal timings on lines 338, 340, 342, and 344 results in a second set of signal timings on lines 488A1 and 490B1, then the same second set of signal timings can be expected to occur on lines 488A1 and 490B1 whenever another set of signal timings occurs on lines 338, 340, 342, and 344. Also, because the timings of the signals on lines 338, 340, 342, and 344 are functionally (e.g., predictably) related to voltage V1, the timings of the signals on lines 488A1 and 490B1 are also functionally related to voltage V1.

[0055] 5, signals A1 and B1 generated by combiner 304 are applied on output lines 488A1 and 490B1 to a second stage 7102. The second stage (which is the first remaining stage) 7102 is coupled (via combiner 304) to the first stage 798, and the i-th stage 7104 (which is the second remaining stage in the illustrated example) is coupled to the second stage 7102.

[0056] In the illustrated example, the second through i-th stages 7102 and 7104 each include an AND gate (such as AND gate 476 for stage 7102 and AND gate 478 for stage 7104) and a delay comparator (such as delay comparator 482 for stage 7102 and delay comparator 484 for stage 7104). However, the illustrated AND gates are merely examples of logic gates that may be employed in accordance with the present description. If desired, the present description may be implemented with or without AND gates and / or with or without gates other than AND gates.

[0057] Also, in the illustrated configuration, AND gates 476 and 478 may be essentially identical to one another, and delay comparators 482 and 484 may be essentially identical to one another. Conductive output lines 488A1 and 490B1 from combiner 304 are coupled to inputs of a first AND gate 476 and delay comparator 482. Specifically, conductive line 488A1 is coupled to a first input 492 of delay comparator 482, and conductive line 490B1 is coupled to a threshold input 494 of delay comparator 482.

[0058] An output line 488A2 from the AND gate 476 is electrically coupled to one of the inputs of the AND gate 478 and to an input 492 of the delay comparator 484. A conductive line 490B2 from the first delay comparator 482 is electrically coupled to another one of the inputs of the AND gate 478 and to a threshold input 494 of the delay comparator 484. The pattern produced by the second and third stages 7102 and 7104 may continue for any desired number of additional stages. Each successive stage has AND gates and delay comparators essentially identical to the AND gates and delay comparators of the second and third stages 7102 and 7104 and is electrically coupled to the AND gates and delay comparators of the preceding stage in the same manner.

[0059] In operation, signal A N and B. N (N=1, 2, 3... for stages 7102 and 7104... respectively) are applied to AND gates 476 and 478, respectively, to provide corresponding signals A N+1 For each of the AND gates 476 and 478, the signal A N+1 The timing of the rising edge of signal A N and B. N In particular, for each of AND gates 476 and 478, the timing of the rising edge of signal A N+1 The timing of the rising edge of signal A N and B. N The rising edge of signal A arrives first. N and B. N The rising edge of the later arriving signal is N and B. N 7, the AND-gate delay 7100 introduced by each AND gate is linearly related to the absolute value of the input signal delay T_IN, which is the sum of the amount of time related to how far the first arriving AND gate lags the rising edge of the first arriving AND gate 7100. As shown in FIG. 7, the AND-gate delay 7100 introduced by each AND gate is linearly related to the absolute value of the input signal delay T_IN, which is the sum of the amount of time related to how far the first arriving AND gate lags the rising edge of the first arriving AND gate 7100. N and B NIn the illustrated configuration, the relationship between the AND gate delay 7100 and the input signal delay T_IN is N Or B N It is linear regardless of whether it comes first or later.

[0060] Signal A N and B. N is also applied to an input 492 and a threshold input 494 of the delay comparators 482 and 484, respectively, to provide the delay comparators 482 and 484 with a corresponding signal B N+1 For each of the delay comparators 482 and 484, the signal B N+1 The timing of the rising edge of signal A N and B. N In particular, for each one of the delay comparators 482 and 484, the timing of the rising edge of the signal B N+1 The timing of the rising edge of signal A is: N and B. N , whichever arrives first, plus (2) a comparator delay 7102 (FIG. 7) that is logarithmically inversely proportional to the absolute value of the input signal delay T_IN. (In other words, the more similar the input values ​​are, the larger the comparator delay will be, and the larger the difference between the two inputs to the comparator, the smaller the comparator delay.)

[0061] Subtracting the AND gate delay 7100 from the comparator delay 7102 gives the output signal delay T_OUT (FIG. 8) for any given single bit stage 7102 and 7104. If the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, then the output signal delay T_OUT is positive (this is because the absolute value of the signal B generated by each delay comparator 482 and 484 is greater than the threshold delay T_THRES). N+1 The rising edge of the signal A is generated by respective AND gates 476 and 478. N+1 On the other hand, if the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is negative (this means that the delay precedes the rising edge of the signal B). N+1The rising edge of the corresponding signal A N+1 (This means that the delay is delayed relative to the rising edge of the output signal T_OUT.) The positive or negative nature of the output signal delay T_OUT is reported to the calibration engine / controller 740 on the signal line of the subsequent delay comparator.

[0062] In operation, the first delay comparator 482 issues a first code signal ("1" or "0") on the digital line 408 (an example of a digital output) to the calibration engine / controller 740. The first code signal (an example of a digital signal according to the present description) is based on which rising edge of signals A1 and B1 is received first by the first delay comparator 482, so that the first code signal reflects the order of the rising edges of signals A1 and B1 applied to the first input 492 and threshold input 494 of the delay comparator 482. The AND gate 476 and the delay comparator 482 generate signals A2 and B2 that are applied to the AND gate 478 and the delay comparator 484 of the third stage 104. The delay comparator 484 outputs a second code signal ("1" or "0") on the second digital line 412 to the calibration engine / controller 40. The second code signal is based on which rising edge of signals A2 and B2 is received first by the second delay comparator 484, and as a result, the second code signal reflects the order of the rising edges of signals A2 and B2 applied to inputs 492 and 494 of the second delay comparator 484.

[0063] The delay between signals A1 and B1 can be predicted as a function of the input voltage V1, and vice versa, and the signal A output by the subsequent stage can be predicted as a function of the input voltage V2. N+1 and B N+1 The delay between the signal A received from the previous stage N and B. N, and vice versa, so that the sign signal output by the delay comparator of the cascade of stages can be predicted as a function of the voltage V1, and vice versa. Thus, a code consisting of the sign signal can be reliably compared to a predefined correlation to determine an approximation of the input voltage V1. In operation, the timing of the signals on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the timing of the signals on lines 488 and 490, as described above. The timing of the signals on lines 488A2 and 490B2 is functionally (e.g., predictably) related to the timing of the signals on lines 488A1 and 490B1. The timing of the signals on lines 488A3 and 490B3 is functionally (e.g., predictably) related to the timing of the signals on lines 488A2 and 490B2, and so on.

[0064] Also, if a set of signal timings on lines 488 and 490 becomes the first set of signal timings on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc., then whenever the same set of signal timings occurs on lines 488 and 490, the same first set of signal timings can be expected to occur on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc. Similarly, if another distinct set of signal timings on lines 488 and 490 results in a second set of signal timings on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc., then it can be expected that the same second set of signal timings will occur on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc. whenever another set of signal timings occurs on lines 488 and 490. Also, because the timings of the signals on lines 488 and 490 are functionally (e.g., predictably) related to the input voltage V1, the timings of the signals on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc. that determine the sign signal of the output code are also functionally related to the input voltage V1.

[0065] 9, the delay comparator 482 includes a comparator circuit 2083 that includes first, second, third, fourth, fifth, sixth, seventh, and eighth transistors 2400, 2402, 2404, 2406, 2408, 2410, 2412, and 2414. In the illustrated example, the timing of the delay comparator 482 is controlled by a signal from a clock (CLK) applied to the gates of the first and fourth transistors 2400, 2406 on conductive line 2122. First and second signals A1, B1 on lines 488A1 and 490B1 are applied to the gates of the sixth and fifth transistors 2410 and 2408, respectively. The drains of the first, second, and fifth transistors 2400, 2402, and 2408 are electrically connected to each other and to the third and eighth transistors 2404 and 2414 via a first conductive line 2416. The drains of the third, fourth, and sixth transistors 2404, 2406, and 2410 are similarly electrically connected to each other and to the second and seventh transistors 2402 and 2412 via a second conductive line 2418.

[0066] The first and second conductive lines 2416 and 2418 of the comparator circuit 2083 are electrically connected to the sign-out circuit 2420 via the third and fourth conductive lines 2422 and 2424, respectively. As shown in FIG. 9, the sign-out circuit 2420 is merged with the comparator circuit 2083. The sign-out circuit 2420 includes first, second, third and fourth transistors 2426, 2428, 2430 and 2432. The third conductive line 2422 is electrically connected to the gates and sources of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively, while the fourth conductive line 2424 is electrically connected to the sources and gates of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively.

[0067] In operation, when the delay comparator 482 is enabled by the clock signal on line 2122, a sign signal is generated in the sign out circuit 2420 on line 408. The sign signal is forwarded to the calibration engine / processor 40 on line 408 and represents the order in which the output signals A1 and B1 arrive at the first and threshold inputs 492 and 494 of the delay comparator 482. The operation of the sign out circuit 2420 is controlled by an inverted clock signal CLKZ applied to the gates of the third and fourth transistors 2430 and 2432 of the sign out circuit 2420. The inverted clock signal CLKZ is an inverted version of the clock signal applied to the gates of the first and fourth transistors 2400 and 2406 of the comparator circuit 2083 on line 2122.

[0068] The third and fourth conductive lines 2422 and 2444 are also electrically connected to a delay out circuit 2450. As shown in FIG. 9, the delay out circuit 2450 is merged with the comparator circuit 2083. The delay out circuit 2450 includes first, second and third transistors 2442, 2444 and 2446. The third conductive line 2422 is electrically connected to the gates and sources of the first and second transistors 2442 and 2444 of the delay out circuit 2450, respectively, while the fourth conductive line 2424 is electrically connected to the sources and gates of the first and second transistors 2442 and 2444 of the delay out circuit 2450, respectively.

[0069] In operation, a delayed signal B2 is generated on line 490B2 that is electrically connected to the drains of both the first and second transistors 2442 and 2444 of the delay out circuit 2450. The timing of the rising edge of the delayed signal B2 on line 490B2 relative to the timing of the earlier arriving rising edge of the signals A1 and B2 on the inputs 492 and 494 is the comparator delay 7102 (FIG. 7). The operation of the delay out circuit 2450 (FIG. 9) is controlled by the same inverted clock signal CLKZ that is applied to the third and fourth transistors 2430, 2432 of the sign out circuit 2420. The inverted clock signal CLKZ is applied to the gate of the third transistor 2446 of the delay out circuit 2450. The drain of the third transistor 2446 of the delay out circuit 2450 is electrically connected to the drains of the first and second transistors 2442, 2444 of the delay out circuit 2450.

[0070] What has been described above is an example. This description encompasses changes, modifications, and variations of the subject matter described herein that fall within the scope of this application, including the appended claims. For example, one or more clockless delay comparators can be used in the back-end of the analog-to-digital converter 18, if desired.

[0071] As used herein, the term "comprising" means including, but not limited to. The term "based on" means based at least in part on. Also, when a specification or claim refers to "a," "first," or "another" element, or the like, it includes one or more such elements and does not require or exclude two or more such elements.

[0072] What is claimed as new and desired to be protected is:

Claims

1. 1. An analog-to-digital converter system, comprising: a calibration circuitry having a digital code input and a calibration voltage output based on said digital code input; a first analog-to-digital converter (ADC) having an input operable to be connected to the calibration voltage output or a sampled voltage, the first analog-to-digital converter operable to output a first digital output code based on the calibration voltage output and to output a second digital output code based on the sampled voltage and the first digital output code; An analog-to-digital converter system comprising:

2. 2. An analog-to-digital converter system according to claim 1, the calibration circuitry includes a digital-to-analog converter; The analog-to-digital converter system comprises: an analog-to-digital converter system further comprising: a first multiplexer coupled to the digital-to-analog converter and the first analog-to-digital converter, the first multiplexer selectively transmitting the calibration voltage output and a sampled voltage to the analog-to-digital converter.

3. 3. An analog-to-digital converter system according to claim 2, comprising: an analog-to-digital converter system further comprising: a calibration controller coupled to the digital-to-analog converter and to the first multiplexer, the calibration controller transmitting the digital code input to the digital-to-analog converter and causing the first multiplexer to transmit the calibration voltage output to the analog-to-digital converter while the digital code input is transmitted to the digital-to-analog converter.

4. 4. An analog-to-digital converter system according to claim 3, an analog-to-digital converter system further comprising a second analog-to-digital converter coupled to the digital-to-analog converter, the second analog-to-digital converter receiving the calibration voltage output from the digital-to-analog converter and the sampled voltage, and generating a digital output code based on the calibration voltage output and the sampled voltage.

5. 5. An analog-to-digital converter system according to claim 4, comprising: an analog-to-digital converter system further comprising a second multiplexer coupled to the digital-to-analog converter and the second analog-to-digital converter, the second multiplexer selectively transmitting the calibration voltage output to the second analog-to-digital converter.

6. 2. An analog-to-digital converter system according to claim 1, The analog to digital converter system further comprising a look-up table that stores the first digital output code in association with the digital code input.

7. 2. An analog-to-digital converter system according to claim 1, An analog-to-digital converter system, wherein the first analog-to-digital converter includes circuitry for converting a voltage into a delayed signal and generating the first and second digital output codes based on the delayed signal.

8. 1. A lookup table based analog to digital converter system, comprising: a digital to analog converter having a digital code input and a calibration voltage output based on said digital code input; a first analog-to-digital converter coupled to the calibration voltage output and to a sampled voltage input, the first analog-to-digital converter operable to output a first digital output code based on the calibration voltage output and to output a second digital output code based on the sampled voltage input; a lookup table coupled to the first analog to digital converter, the lookup table storing the first digital output code in association with the digital code input; A lookup table based analog to digital converter system comprising:

9. 9. The look-up table based analog to digital converter system of claim 8, comprising: a first multiplexer coupled to the digital-to-analog converter and the first analog-to-digital converter, the first multiplexer selectively transmitting one of the calibration voltage output and the sampled voltage input to the first analog-to-digital converter.

10. 10. The lookup table based analog to digital converter system of claim 9, comprising: a calibration controller coupled to the digital-to-analog converter and the first multiplexer, the calibration controller transmitting the digital code input to the digital-to-analog converter and causing the first multiplexer to transmit the calibration voltage output to the first analog-to-digital converter while the digital code input is transmitted to the digital-to-analog converter.

11. 11. The lookup table based analog to digital converter system of claim 10, comprising: a second analog-to-digital converter coupled to the digital-to-analog converter, the second analog-to-digital converter receiving the calibration voltage output from the digital-to-analog converter and the sampled voltage input, and generating a digital output code based on the calibration voltage output and the sampled voltage input.

12. 12. The lookup table based analog to digital converter system of claim 11, comprising: a second multiplexer coupled to the digital-to-analog converter and the second analog-to-digital converter, the second multiplexer selectively transmitting the calibration voltage output to the second analog-to-digital converter.

13. 9. The look-up table based analog to digital converter system of claim 8, comprising: A lookup table based analog to digital converter system, wherein the first analog to digital converter includes circuitry for converting a voltage to a delayed signal and generating the first and second digital output codes based on the delayed signal.

14. 1. A method for calibrating an analog to digital converter system, comprising: generating a calibration voltage based on the digital input code by a digital-to-analog converter; generating a first digital output code based on the calibration voltage with a first analog-to-digital converter; generating a second digital output code based on a voltage sampled by the first analog-to-digital converter; storing the first digital output code in a lookup table in association with the digital input code; A method comprising:

15. 15. A calibration method according to claim 14, comprising the steps of: The method of calibration further comprising using a first multiplexer to selectively transmit one of the calibration voltage and the sampled voltage to the analog-to-digital converter.

16. 16. A calibration method according to claim 15, comprising the steps of: transmitting said digital input code to said digital-to-analog converter; transmitting the calibration voltage to the first analog-to-digital converter while the digital input code is transmitted to the digital-to-analog converter; The calibration method further comprises:

17. 17. A calibration method according to claim 16, comprising the steps of: The method of calibration further comprising causing a second analog-to-digital converter to receive the calibration voltage from the digital-to-analog converter and generate a digital output code based on the calibration voltage and the sampled voltage.

18. 15. A calibration method according to claim 14, comprising the steps of: The method of calibration, wherein the first analog-to-digital converter includes circuitry for converting a voltage into a delayed signal, and the first and second digital output codes are generated based on the delayed signal.

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