Measurement of voltage levels at voltage nodes using measurement integrated circuits

Abstract

One or more examples relate to methods and apparatus for measuring a voltage node. An exemplary method may include providing a circuit including at least a first capacitor and a second capacitor between an input of the measurement circuit and a voltage node associated with a higher voltage domain than the measurement circuit, generating, by the measurement circuit, a first digital value representing a voltage level related to the voltage level at the voltage node at least in part in response to performing a measurement process using the circuit, and generating, by a processor, a second digital value representing the voltage level at the voltage node at least in part in response to the first digital value and a scaling factor representing a pre-specified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node.

Description

[Technical field]

[0001] (Priority Claim) This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Application No. 63 / 200,837, filed March 31, 2021, entitled "ON CHIP MEASUREMENT OF HIGH VOLTAGE NODE WITH LOW VOLTAGE MEASUREMENT CIRCUIT AND RELATED SYSTEMS, METHODS AND DEVICES," the disclosure and contents of which are incorporated herein by reference in their entirety.

[0002] FIELD OF THEINVENTION One or more examples relate to measurements of analog nodes, and more particularly, to on-chip measurements of voltage nodes. [Background technology]

[0003] Integrated circuits (chips) are used in a variety of applications, including automotive and industrial.

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[0015] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which that element is first introduced. [Brief description of the drawings]

[0016] [Figure 1] 1 is a schematic diagram illustrating an apparatus according to one or more embodiments. [Diagram 2] 1 is a schematic diagram illustrating a voltage monitoring system according to one or more embodiments. [Diagram 3] FIG. 1 is a flow diagram illustrating a process for measuring the voltage of a higher node using a measurement circuit having a lower voltage domain than the voltage domain of the voltage node, in accordance with one or more embodiments. [Figure 4] FIG. 1 is a flow diagram illustrating a measurement process in accordance with one or more embodiments. [Diagram 5] FIG. 2 is a schematic diagram illustrating a cross-sectional view of an NMOS switch in accordance with one or more embodiments. [Figure 6] 1 is a schematic diagram illustrating a voltage monitoring system according to one or more embodiments. [Figure 7A] FIG. 1 is a flow diagram illustrating a process for measuring the voltage of a higher node using a measurement circuit having a lower voltage domain than the voltage domain of the voltage node, in accordance with one or more embodiments. [Figure 7B] FIG. 1 is a flow diagram illustrating a process for measuring the voltage of a higher node using a measurement circuit having a lower voltage domain than the voltage domain of the voltage node, in accordance with one or more embodiments. [Figure 8] FIG. 8 is a flow diagram illustrating a first measurement process of the process depicted by FIGS. 7A and 7B, according to one or more embodiments. [Figure 9] FIG. 8 is a flow diagram illustrating a second measurement process of the process depicted by FIGS. 7A and 7B, according to one or more embodiments. [Figure 10] FIG. 1 is a schematic diagram illustrating an electronic system according to one or more embodiments. [Figure 11] 3 is a timing diagram illustrating signals from a contemplated operation of the voltage monitoring system of FIG. 2 in accordance with one or more embodiments. [Figure 12] 7 is a timing diagram illustrating signals from a contemplated operation of the voltage monitoring system of FIG. 6 in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which show, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized and changes in structure, materials, and processes may be made as permitted herein without departing from the scope of the present disclosure.

[0018] The figures presented herein are not meant to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0019] The following description may include examples to assist those skilled in the art in enabling the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the relevant description is illustrative, and the scope of the disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of the disclosure to specific components, steps, features, functions, etc.

[0020] It will be readily understood that the components of the examples, as generally described and illustrated in the Figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. Although various aspects of the examples may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0021] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic between various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like are omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of one skilled in the art.

[0022] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will appreciate that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0023] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, all of which are encompassed by the use of the term "processor." A general purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. While a general purpose computer including a processor is considered a special purpose computer, a general purpose computer is intended to execute computing instructions (such as, but not limited to, software code) associated with the embodiments of the present disclosure.

[0024] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in another order, in parallel, or substantially simultaneously. Additionally, the order of the acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structures, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0025] Any reference to elements herein using a designation such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0026] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, such as within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0027] As used herein, any relative terms such as "over," "under," "on," "underlying," "upper," "lower," and the like are used for clarity and convenience in understanding the disclosure and the accompanying drawings, and are not intended to be implied in or dependent upon any particular priority, orientation, or order unless the context clearly dictates otherwise.

[0028] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with one another. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers present. In contrast, when an element is described as "directly coupled" to another element, there are no intervening elements or layers present. The term "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly indicated otherwise or the context indicates otherwise to one of ordinary skill in the art.

[0029] Measurement circuitry, such as an analog-to-digital-converter (ADC), may be used to measure the voltage level at a node and generate a digital value corresponding to the measured voltage level. An ADC typically has a range of voltage levels (referred to herein as the "input range") over which it can generate a digital value that accurately corresponds to the voltage levels present at its input, without the aid of other circuitry placed between the node of interest and the ADC's input.

[0030] For digital measurement circuits implemented in an integrated circuit (IC), such as, but not limited to, successive approximation register (SAR) ADCs, the input range is typically constrained by the type of IC technology. As a non-limiting example, a digital ADC implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) type integrated circuit typically has an input range of less than 3.3V (e.g., but not limited to, 0V to 1.2V, 0V to 1.8V, 0V to 3.3V). As used herein, the term "measurement circuit" refers to a digital measurement circuit implemented in an integrated circuit. In an IC, a measurement circuit in an electronic system with other IC blocks is referred to herein as "on-chip", i.e., the measurement circuit is on the IC.

[0031] An IC may interface with electronic circuits that operate in a higher voltage domain than the chip or generate voltages in a higher voltage domain than the chip. As a non-limiting example, the voltage levels used to represent signals in the voltage domain of a given electronic circuit may be higher than the voltage levels used to represent signals in the voltage domain of the IC that interfaces with the electronic circuit (e.g., but not limited to, 5-10V versus 1.2V-3.3V).

[0032] When the voltage level at the node of interest (the node to be measured) is outside the input range of the measurement circuit, one technique known to the inventors of the present disclosure is to measure an input voltage having a voltage level that is some pre-specified ratio of the voltage level at the node of interest. For example, a resistive voltage divider circuit may couple the node of interest to the input of the measurement circuit to provide an input voltage having a voltage level that is a pre-specified ratio of the voltage level at the node of interest. The digital value generated by the measurement circuit corresponds to the voltage level of the input voltage and is then adjusted (e.g., including but not limited to, scaled up) by a processor that knows the relationship (e.g., including but not limited to, a transfer function) between the voltage at the node of interest and the voltage at the output of the voltage divider circuit.

[0033] If the output impedance of the voltage source providing the voltage to the node of interest is low, the effect of the low output impedance on the relationship between the node of interest and the output of the voltage divider circuit is negligible. Thus, for a low output impedance voltage source, if the relationship is pre-specified in the processor that receives the digital value generated by the measurement circuit, the processor should theoretically be able to calculate a digital value representing the voltage level at the node of interest in response to the pre-specified relationship and the digital value representing the voltage level at the input of the measurement circuit.

[0034] During chip operation, high impedance nodes are frequently created for specific applications. In a non-limiting example of an automotive chip, high voltage, high impedance (HVHZ) nodes are created and used intensively. Such HVHZ nodes are monitored on-chip, including by measurement circuitry, as a non-limiting example, to comply with functional safety requirements. Although various embodiments are described herein with reference to high voltage, high impedance nodes, the disclosure is not so limited and various embodiments may include and / or relate to measuring any voltage node having a high impedance or low impedance higher than, the same as, or lower than the measurement circuitry. The disclosed examples may be utilized, but are not limited to, to measure high impedance, high voltage nodes, low impedance, high voltage nodes, high impedance, low voltage nodes, or low impedance low voltage nodes.

[0035] When a node of interest that is in a higher voltage domain than the measurement circuit is coupled to the measurement circuit by a high impedance node (i.e., a high impedance output of a voltage source), the inventors of the present disclosure understand that the effect of the high impedance on the relationship between the node of interest and the output of a voltage divider circuit (or other scaling circuit) cannot be ignored and may be significant in practice. Thus, a pre-specified relationship may not accurately represent the relationship between the output of the voltage divider and the node of interest if it does not take into account such high impedance effects.

[0036] As a non-limiting example, an HVHZ node may load a resistive divider circuit (as such resistors implemented on-chip are typically much smaller than the impedance of the HVHZ node) and cause a voltage drop between the node of interest and the input to the resistive divider circuit.

[0037] One technique known to the inventors of the present disclosure for addressing the above-mentioned voltage drops is to increase the resistance or physical size of the resistors in the resistive divider circuit, typically to megaohms (M Ohms). However, chip designers may not be able to afford to pay attention to the real area requirements for M Ohm resistors.

[0038] As used herein, the term "high voltage node" means a voltage node that has a higher voltage domain than the voltage domain of a measurement circuit. The voltage domain may be higher because the voltage level used to represent the signal at the voltage node may be higher than the voltage used to represent the signal in the measurement circuit. The voltage domain may be higher because the voltage level at the voltage node may be higher than the input range over which the measurement circuit can reliably measure the voltage level at the node.

[0039] FIG. 1 is a schematic diagram illustrating an apparatus 100 according to one or more embodiments.

[0040] The apparatus 100 includes a processor 114, a measurement circuit 102, a voltage scaling circuit 104, and a voltage node 106. The processor 114 is coupled to receive the output of the measurement circuit 102. The measurement circuit 102 is coupled to the voltage node 106 via the voltage scaling circuit 104.

[0041] The measurement circuit 102 generally detects an input voltage V at an input 108 of the measurement circuit 102. IN In one or more examples, the digital measurement circuit generates a first digital value 116 that represents the voltage level of the input voltage V IN may be for a single-ended input, such as, but not limited to, the single-ended input of a SAR ADC.

[0042] The voltage scaling circuit 104 couples the input 108 of the measurement circuit 102 to a voltage node 106. The voltage node 106 is connected to a voltage domain V Domain1 , and the measurement circuit 102 is associated with the voltage domain V Domain2 Associated with VDomain1 is V Domain2 The voltage scaling circuit 104 generates a voltage V scaled according to a pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit 104. SCALE where the input voltage of the voltage scaling circuit 104 is the voltage V appearing at the input 110 of the voltage scaling circuit 104. DC and the output voltage of the voltage scaling circuit 104 is a scaled voltage V appearing at the output 112 of the voltage scaling circuit 104. SCALE In one or more examples, the voltage V SCALE is the voltage V DC is a scaled-down version of the voltage V SCALE The voltage level of is the scaled voltage V DC voltage level, and the scaled voltage V SCALE Voltage level and voltage V DC The relationship between the voltage levels of V and V is a pre-specified relationship that may also be characterized herein as "proportional." In one or more examples, the voltage scaling circuit 104 generates the scaled voltage V at least in part in response to a control signal 124 for the measurement process generated by the logic 122 of the measurement circuit 102. SCALE Generate.

[0043] The processor 114 generally calculates the voltage V at least in part in response to the first digital value 116 and the scaling factor 120. DC The voltage scaling circuit 104 generates a second digital value 118 representing a voltage level of the first digital value 116. The scaling factor 120 represents a pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit 104 described above. In one or more examples, the processor 114 adjusts (e.g., but is not limited to, increase) the first digital value 116 utilizing the scaling factor 120 to obtain the second digital value 118.

[0044] 2 is a schematic diagram illustrating a voltage monitoring system 200 according to one or more embodiments. The voltage monitoring system 200 is a non-limiting example of the device 100.

[0045] The voltage monitoring system 200 includes a measurement circuit 204 coupled to a voltage node 202 via a voltage scaling circuit 214 and an optional analog connection 206 .

[0046] The voltage scaling circuit 214 generally scales down the voltage from a first voltage level at the input 216 to a second, lower voltage level at the output 210. The voltage scaling circuit 214 is coupled in the voltage monitoring system 200 to scale the voltage V at the voltage node 202 (the input voltage of the voltage scaling circuit 214) according to a pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit 214. DC The scaled voltage V is a scaled-down version of SCALE (the output voltage of the voltage scaling circuit 214).

[0047] The measurement circuit 204 is generally a digital measurement circuit and optionally includes a successive approximation register 232 (SAR ADC 232). The measurement circuit 204 receives an input voltage V IN to generate a first digital value 212 representing a voltage level of V IN is optionally for a single-ended voltage input of the SAR ADC 232.

[0048] The processor 226 knows the pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit 214 via a scaling factor 234 (a function or value stored or configured in or accessible to the processor 226) and increases the first digital value 212 using the scaling factor 234 to increase the voltage V at the voltage node 202. DC The second digital value 236 represents the voltage level of

[0049] Optional analog connection 206 (optionality is indicated by the dashed border of block 206) is generally for providing electrical connections between analog nodes of the chip. In FIG. 2, analog connection 206 is an access point to one or more analog nodes for measurement or monitoring of such analog nodes and their analog circuits, for example, by measurement circuit 204. Analog connection 206 provides at least a portion of a voltage path between voltage node 202 and measurement circuit 204. In the example shown in FIG. 2, analog connection 206 provides a scaled voltage V SCALE V IN to an input 230 of the measurement circuitry 204. In one or more examples, the analog connection 206 may couple the voltage scaling circuitry 214, which is physically located at the voltage node 202, to the measurement circuitry 204, which is physically located elsewhere on-chip. The analog connection 206 may include, by way of non-limiting example, on-chip metal wires and CMOS switches configured as an analog test bus.

[0050] Returning to the voltage scaling circuit 214, the voltage scaling circuit 214 includes several on-chip capacitors, here two capacitors CAP1 and CAP2, each of which has a first end coupled to ground respectively, and switches, here switches 218, 220, 222, and 224, which are controlled to be on (i.e., turned on) or off (i.e., turned off) for switchable coupling and isolation via respective control signals S1, S2, and S3 as shown, i.e., control signals S1, S2, and S3 generated by logic 238 of the measurement circuit 204. In certain CMOS processes, the on-chip capacitors and transistor switches can be implemented to support high voltages, for example, high voltage gate oxide capacitors can support up to 20V, and high voltage NMOS or PMOS transistors that make up the switches can support up to 20V.

[0051] Generally speaking, the operation of the voltage scaling circuit 214 may be controlled at least in part in response to control signals S1, S2, and S3 generated by logic 238 according to a "charging phase" and a "charge sharing phase." During the charging phase, capacitor CAP1 is coupled (i.e., switchably coupled) to voltage node 202 (via switch 218 that is on in response to signal S1) and isolated (i.e., switchably isolated) from the remainder of the voltage scaling circuit 214, including capacitor CAP2 (switch 220 is off in response to signal S2). Capacitor CAP2 is isolated (i.e., switchably isolated) from capacitor CAP1 (switch 220 is off in response to signal S2) and from output 210 of voltage scaling circuit 214 (switch 224 is off in response to signal S3), and is coupled (i.e., switchably coupled) in series between the ground connections (switch 222 is on in response to signal S4), and thus is reset (charged to) a ground voltage (e.g., but not limited to, 0 volts).

[0052] During the charge-sharing phase, capacitor CAP1 is isolated (i.e., switchably isolated) from voltage node 202 (switch 218 is off), capacitors CAP1 and CAP2 are coupled (i.e., switchably coupled) to each other (switch 220 is on in response to signal S2), and the second end of capacitor CAP2 is isolated (i.e., switchably isolated) from ground (switch 222 is off in response to signal S4).

[0053] The charging phase and the charge sharing phase are represented by Equation 1:

number

number

[0054] In one or more examples, the capacitance values ​​of the capacitors CAP1 and CAP2 are scaled into the voltage domain of the measurement circuit 204. SCALE A value may be selected that is expected to yield

[0055] Switching current I sw1 is the average current between impedance Rout and CAP1 when switch 218 is turned on periodically. If there is an initial charge of 0 volts across CAP1 at the beginning of each on cycle of switch 218, then the current I sw1 The size of is given by the formula: sw1 =C1 * (V DC ) * f S1 where f S1 is the frequency of the signal S1 used to turn the switch 218 on and off. With a slow clock frequency (approximately 1 kHz to 10 kHz) and a small capacitance C1 (approximately 300 fF), the switching current I sw1 is small (less than 0.1μA). The switching current I sw1 If is small and the impedance of Rout is up to about 1M ohms, the voltage drop I across the impedance Rout sw1 * Rout<0.1V is negligible. In other words, V DC Because of switch 218, there is no voltage drop across impedance Rout and it appears as if CAP1 is charging.

[0056] When switch 222 and its various CMOS transistors are turned on, a path to ground is provided. When switch 222 and its various CMOS transistors are turned off (i.e., transitioning from on to off), a leakage current I LEAK (More specifically, a mixture of reverse-biased PN junction leakage current and subthreshold leakage current of the high voltage / low voltage transistor switch) flows through the turned off CMOS transistor of switch 222 to ground.

[0057] When the switch 222 is turned off during the charge sharing phase, some of the charge stored in the capacitor CAP1 during the charging phase is transferred to the leakage current I LEAK The current is discharged from the capacitors CAP1 and CAP2 through V DC From V SCALE This contributes to scaling down the leakage current I LEAK can increase dramatically with temperature, and the operating temperature of such circuits can operate up to, for example, 145° C. in automotive applications.

[0058] Therefore, a slow clock frequency means a long clock period T, and the charge loss due to leakage current is a function of the clock off period (on time = off time = T / 2) of the switch 222, i.e., I leak * T / 2, the low-frequency control signal S1 has at least one drawback. leak However, the slower the clock, the larger the error, which can reduce the accuracy of the measurement.

[0059] FIG. 3 is a flow diagram illustrating a process 300 for measuring the voltage of a voltage node using a measurement circuit having a lower voltage domain than the voltage domain of the voltage node, in accordance with one or more embodiments.

[0060] In operation 302, the process 300 starts with a second voltage domain (e.g., V DOMAIN22 ) and a first voltage domain (e.g., V DOMAIN1 2 ) between a high voltage node (e.g., but not limited to, voltage node 202) having a second voltage domain lower than the first voltage domain. The isolated capacitor includes at least a first capacitor (e.g., but not limited to, CAP1 in FIG. 2 ) and a second capacitor (e.g., but not limited to, CAP2 in FIG. 2 ).

[0061] As a non-limiting example, the voltage node 202 is associated with a higher voltage domain than the measurement circuit 204, which is the voltage domain V DOMAIN1 (associated with voltage node 202) is a voltage domain V DOMAIN2 This is because a higher voltage level is used to represent the signal (associated with the measurement circuit 204). Alternatively, this can be expressed as DOMAIN1 A domain V represents signals using a voltage level lower than DOMAIN2 (associated with the measurement circuit 204).

[0062] As a non-limiting example with reference to FIG. 2, capacitors CAP1 and CAP2 are initially isolated (i.e., switchably isolated) from one another (i.e., are “isolated capacitors”) because switch 220 coupling capacitors CAP1 and CAP2 is off in response to signal S2; capacitor CAP1 is initially isolated (i.e., switchably isolated) from voltage node 202 because switch 218 coupling capacitor CAP1 to voltage node 202 is off in response to signal S2; and the second end of capacitor CAP2 is initially isolated (i.e., switchably isolated) from ground because switch 222 coupling the second end of capacitor CAP2 to ground is off in response to signal S4.

[0063] In operation 304, the process 300 measures the voltage level of the voltage at the voltage node (e.g., V at voltage node 202) by a measurement circuit (e.g., but not limited to, measurement circuit 204 of FIG. 2). DC ) associated with the voltage level (e.g., but not limited to, the input voltage V IN 2 ) in response at least in part to performing a measurement process utilizing a circuit including the first and second capacitors (e.g., but not limited to, via a voltage scaling circuit 214 responsive to signals S1-S4 in measurement circuit 204 of FIG. 2 and timing control by logic 238 to perform the measurement process utilizing voltage scaling circuit 214).

[0064] In operation 306, the process 300 may include, by a processor (such as, but not limited to, the processor 226), determining the voltage level of the voltage at the voltage node (e.g., V at the voltage node 202). DC The process 300 generates a second digital value (e.g., but not limited to, second digital value 236) representing the first digital value (e.g., but not limited to, first digital value 212) and a scaling factor (e.g., but not limited to, scaling factor 234). The scaling factor determines the ratio of the voltage level represented by the first digital value and the voltage level at the high voltage node (e.g., V at voltage node 202). DC In one or more examples, a digital value representing a voltage level of a voltage at a high voltage node (e.g., V at voltage node 202) may be used to represent a pre-specified relationship between the voltage at the high voltage node and, but not limited to, a digital value representing a voltage level of a voltage at a high voltage node (e.g., V at voltage node 202). DC To obtain a second digital value (such as, but not limited to, a first digital value), the process 300 adjusts the first digital value at least in part according to the relationship represented by the scaling factor to obtain a second digital value.

[0065] 4 is a flow diagram illustrating a measurement process 400 according to one or more embodiments. The measurement process 400 is a non-limiting example of a measurement process performed in operation 304 of process 300.

[0066] In operation 402, the measurement process 400 optionally provides a circuit including an isolated capacitor between an input of the measurement circuit and a voltage node, as described with reference to operation 302 of process 300 shown by FIG. 3, where the high voltage node has a higher voltage domain than the voltage domain of the measurement circuit, and the isolated capacitor includes at least a first capacitor and a second capacitor.

[0067] In operation 404, the measurement process 400 couples the first capacitor to the voltage node (e.g., but not limited to, turning on switch 218 in response to signal S1) to initiate full charging of the first capacitor at least in part in response to the voltage at the voltage node. The first capacitor and the second capacitor remain isolated (i.e., switchably isolated) during operation 404 because switch 220 coupling capacitors CAP1 and CAP2 is off in response to signal S2.

[0068] In operation 406, the measurement process 400 couples the second capacitor between the two ground connections to begin discharging the second capacitor CAP2 (e.g., but not limited to, turning on the switch 222 in response to the signal S4 to couple the second end of the capacitor CAP2 to ground such that CAP2 is coupled in series between the two ground connections). Optionally, this may reset the second capacitor CAP2 by draining any charge stored in the second capacitor.

[0069] In operation 408, the measurement process 400 isolates the first capacitor and the voltage node (e.g., but not limited to, turning off switch 218 in response to signal S1) and isolates the second end of the second capacitor CAP2 and one of the ground connections (e.g., but not limited to, turning off switch 222 in response to signal S4) to terminate the charging of the first capacitor and the discharging of the second capacitor, respectively.

[0070] In operation 410, the measurement process 400 couples (e.g., but is not limited to, coupling in parallel) the second capacitor with the first capacitor (e.g., but is not limited to, turning on switch 220 in response to signal S2) to share the charge of the first capacitor with the second capacitor. The charge stored in the first capacitor (e.g., but is not limited to, the charge stored during operation 406) is shared between the parallel-coupled first capacitor and second capacitor during operation 410.

[0071] In operation 412, the measurement process 400 couples (e.g., but is not limited to, turning on switch 224 in response to signal S3) the input of the measurement circuit with a circuit including a coupled (e.g., but is not limited to, parallel coupled) first and second capacitors to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

[0072] When the measurement process 400 is performed, the voltage generated at the input of the measurement circuit in operation 412 is related to (i.e., has a known relationship to) the voltage at the voltage node. Such relationship may be pre-specified by a scaling factor and utilized to calculate the voltage level of the voltage at the voltage node.

[0073] 5 is a schematic diagram illustrating a cross-sectional view of an NMOS switch 500. FIG. 5 illustrates various leakage currents, including a reverse bias pn junction leakage current to ground (indicated by reference numeral 502) and a sub-threshold leakage current to ground (indicated by reference numeral 504). For example, one or more of the switch 222 of FIG. 2 or the switch 622 of FIG. 6 may be implemented by the NMOS switch 500. As can be seen, the NMOS switch 500 has three terminals (i.e., a gate, a drain, and a source). The gate of the NMOS switch 500 is coupled to ground to turn the switch off, and the drain is coupled to a scaled voltage V SCALE and the source may be coupled to ground. The P-substrate (or P-well) is coupled to ground. It should be noted that some CMOS processes use a P-substrate and others use a P-well, neither of which is beyond the scope of this disclosure.

[0074] As mentioned above, when the switch 222 is turned off during the charge sharing phase, some of the charge stored during the previous charging phase is leaked into the leakage current I LEAK The voltage V DC contributes to the scaling down of the scaled voltage V SCALE In one or more examples, the circuitry of an analog connection, such as analog connection 206, may include several CMOS transistor type switches coupled to ground. Such switches and their respective CMOS transistors are typically configured to provide a voltage, e.g., between the analog connection 206 and a scaled voltage V SCALE to the measurement circuit 204, the analog connection 206 may exhibit leakage current to ground through the turned off switch.

[0075] Without limitation, in order for a voltage monitoring system, such as voltage monitoring system 200, to operate over a wide temperature range, the inventors of the present disclosure understand that it is desirable to take leakage currents in voltage scaling circuit 214 and analog connection 206 into account in the measurement process.

[0076] 6 is a schematic diagram illustrating a voltage monitoring system 600 according to one or more embodiments. The voltage monitoring system 600 includes a measurement circuit 604 coupled to a voltage node 602 via a voltage scaling circuit 614 and an analog connection 606.

[0077] The voltage monitoring system 600 includes a voltage node 602, a voltage scaling circuit 614, an optional analog connection 606, a measurement circuit 604, and a processor 628. The measurement circuit 604 is coupled to the voltage node 602 via the voltage scaling circuit 614 and the optional analog connection 606. The processor 628 receives a first digital value 612 generated by the measurement circuit 604.

[0078] Voltage scaling circuit 614 includes several on-chip capacitors, here capacitors CAP1, CAP2, and CAP3, each coupled to ground, and switches, here switches 618, 620, 626, and 622, that are controlled to be on (or turned on) or off (or turned off) via respective control signals S1, S2, S3, S5, and S4 shown, i.e., control signals S1, S2, S3, S5, and S4 generated by logic 634 of measurement circuit 604. Switch 624 is turned on or off by signal S3 generated by logic 634 of measurement circuit 604 and provides a scaled voltage V SCALE Voltage scaling circuit 614 includes a capacitor CAP3 and a switch 626 that are not included in voltage scaling circuit 214 of FIG.

[0079] Because the voltage monitoring system 600 is similar to the voltage monitoring system 200, similar elements of the voltage monitoring system 600 will not be described again here to avoid unnecessary duplication. The voltage monitoring system 600 obtains a measurement result 630 (also referred to herein as a “final digital value 630”), in which the current leakage I in the voltage scaling circuit 614 and the optional analog connection 606 is LEAKThe effect of may be reduced compared to the voltage monitoring system 200, as described below.

[0080] In one or more examples, the reduced leakage current affected result (i.e., the effect of leakage current on the final digital value 630) is calculated using the voltage scaling circuit 614, the optional analog connection 606, and the measurement circuit 604 to produce a scaled voltage V DC The difference between the two values ​​obtained from the two measurements is calculated by taking two measurements of the first scaled voltage V SCALE1 is performed with capacitor CAP3 isolated (i.e., switchably isolated) from capacitors CAP1 and CAP2 during the charge-sharing phase (e.g., but not limited to, switch 626 being turned off when switch 620 is on), and the other of the two measurements, i.e., the second scaled voltage V SCALE2 is performed with capacitor CAP3 coupled (i.e., switchably coupled) to capacitors CAP1 and CAP3 during the charge-sharing phase (e.g., without limitation, switches 626 and 620 are turned on). The difference between the two measurements and V DC The relationship between is expressed by Equation 3.

[0081]

number

number

number

[0082] Notably, the voltage monitoring system 600 may measure voltages when no or negligible leakage current occurs or is expected without going beyond the scope of this disclosure. As a non-limiting example, the voltage monitoring system 600 may measure voltages in a temperature range or sub-range that is unlikely to cause leakage current, i.e., a temperature range that includes a portion of the sub-range that may cause leakage current and a portion of the sub-range that may not.

[0083] 7A and 7B are flow diagrams illustrating a process 700 for measuring the voltage of a voltage node using a measurement circuit having a lower voltage domain than the voltage domain of the voltage node, in accordance with one or more embodiments.

[0084] In operation 702, process 700 provides a circuit including an isolated capacitor (i.e., a switchably isolated capacitor) between an input of a measurement circuit (e.g., but not limited to, a voltage input of measurement circuit 604) and a voltage node associated with a higher voltage domain than the measurement circuit (e.g., but not limited to, a voltage node 602). The isolated capacitor includes at least a first capacitor (e.g., but not limited to, CAP1 in FIG. 6), a second capacitor (e.g., but not limited to, CAP2 in FIG. 6), and a third capacitor (e.g., but not limited to, CAP3 in FIG. 6).

[0085] As a non-limiting example, the voltage node 602 is associated with a higher voltage domain than the measurement circuit 604, which is the voltage domain V DOMAIN1 (associated with voltage node 602) is a voltage domain V DOMAIN2 This is because the signal is represented using a higher voltage level (associated with the measurement circuit 604) or using a voltage level outside the input range of the measurement circuit 604. Alternatively, this can be achieved by using a voltage domain V DOMAIN1 A domain V represents a signal using a voltage level lower than DOMAIN2(associated with the measurement circuit 604).

[0086] As a non-limiting example with reference to FIG. 6 , a first end of each of capacitors CAP1, CAP2, and CAP3 is coupled (i.e., switchably coupled) to ground, and capacitors CAP1 and CAP2 are initially isolated (i.e., switchably isolated) from one another because switch 620 coupling capacitors CAP1 and CAP2 is off in response to signal S2; CAP1 is initially isolated (i.e., switchably isolated) from voltage node 602 because switch 618 coupling capacitor CAP1 to voltage node 602 is off in response to signal S1; the second end of capacitor CAP2 is initially isolated (i.e., switchably isolated) from ground because switch 622 coupling the second end of capacitor CAP2 to ground is off in response to signal S4; Capacitors CAP2 and CAP3 are initially isolated from each other (i.e., switchably isolated) because switch 626, which couples the second end of each of capacitors CAP3 to capacitor CAP2, is off in response to signal S5; the second end of capacitor CAP3 is initially isolated from ground (i.e., switchably isolated) because switch 626 and switch 622, which couple the second end of capacitor CAP3 to ground, are off in response to signals S5 and S4, respectively.

[0087] At operation 704, the process 700 measures the voltage at a voltage node (e.g., V at voltage node 602) by a measurement circuit (e.g., but not limited to, measurement circuit 604). DC ) at the input voltage V IN6. The measurement circuit 604 generates a first digital value (e.g., but not limited to, a first one of the digital values ​​612) representing a first measurement process utilizing a circuit including the first, second, and third capacitors (e.g., but not limited to, via a voltage scaling circuit 614 responsive to signals S1-S5 in the measurement circuit 604 and timing control by logic 634 to perform one or more measurement processes utilizing the voltage scaling circuit 614, including the first measurement process).

[0088] At operation 706, the process 700 generates, by a processor (e.g., but not limited to, processor 628), a second digital value transiently representing a voltage level at the voltage node. The process 700 generates the second digital value at least in part in response to the first digital value (e.g., but not limited to, a first one of the first digital values ​​612) and a first scaling factor (e.g., but not limited to, scaling factor 636a). The first scaling factor represents a pre-specified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node.

[0089] At operation 708, process 700 generates, by the measurement circuit, at least in part in response to performing a second measurement process using the circuit, a third digital value (e.g., but not limited to, a second one of digital values ​​612) representing a further voltage level related to the voltage level at the voltage node.

[0090] At operation 710, the process 700 generates, by the processor, a fourth digital value that transiently represents a further voltage level at the voltage node. The process 700 generates the fourth digital value at least in part in response to the third digital value and a second scaling factor (e.g., but not limited to, scaling factor 636b). The second scaling factor represents a pre-specified relationship between the voltage level represented by the third digital value and the voltage level at the voltage node.

[0091] In one or more examples, to obtain a digital value that transiently represents the voltage level of the voltage at the voltage node (e.g., but not limited to, the second digital value in operation 706 or the fourth digital value in operation 710), process 700 adjusts the first digital value or the third digital value at least in part in response to the relationship represented by the first scaling factor or the second scaling factor, respectively.

[0092] In operation 712, process 700 generates a final value representing the voltage level at the voltage node, at least in part in response to the second digital value and the fourth digital value generated by the processor in operations 706 and 710, respectively.

[0093] 8 and 9 are flow diagrams illustrating a first measurement process 800 and a second measurement process 900, respectively, in accordance with one or more embodiments. The first measurement process 800 and the second measurement process 900 are non-limiting examples of the first measurement process and the second measurement process performed in the process 700.

[0094] 8, in operation 802, a first measurement process 800 optionally provides an isolated capacitor (e.g., but not limited to, a switchably isolated capacitor of a voltage scaling circuit 614) between an input of a measurement circuit (e.g., but not limited to, a voltage input of the measurement circuit 604) and a voltage node associated with a higher voltage domain than the measurement circuit (e.g., but not limited to, a voltage node 602). The isolated capacitor includes at least a first capacitor (e.g., but not limited to, CAP1 of FIG. 6), a second capacitor (e.g., but not limited to, CAP2 of FIG. 6), and a third capacitor (e.g., but not limited to, CAP3 of FIG. 6).

[0095] As a non-limiting example with reference to FIG. 6 , capacitors CAP1 and CAP2 are initially isolated from one another (i.e., switchably isolated) because a switch 620 coupling CAP1 and CAP2 is off in response to signal S2; CAP1 is initially isolated from voltage node 602 (i.e., switchably isolated) because a switch 618 coupling capacitor CAP1 to voltage node 602 is off in response to signal S1; capacitors CAP2 and CAP3 are initially isolated from one another (i.e., switchably isolated) because a switch 626 coupling the second ends of CAP2 and CAP3 is off in response to signal S5; and the second end of CAP2 is initially isolated from ground (i.e., switchably isolated) because a switch 622 coupling the second end of CAP2 to ground is off in response to signal S4.

[0096] In operation 804, the first measurement process 800 couples the first capacitor to a voltage node (e.g., but not limited to, switch 618 being turned on in response to signal S1) to initiate full charging of the first capacitor in response to the voltage at the voltage node.

[0097] In operation 806, the first measurement process 800 couples the second capacitor between the two ground connections to begin discharging the second capacitor (e.g., but not limited to, the switch 622 is turned on in response to a signal S4 coupling a second end of the second capacitor CAP2 to ground such that CAP2 is coupled in series between the two ground connections).

[0098] In operation 808, the first measurement process 800 isolates the first capacitor and the voltage node (e.g., but not limited to, switch 618 is turned off in response to signal S1) and isolates the second end of the capacitor from ground (e.g., but not limited to, switch 622 is turned off in response to signal S5) to terminate the charging of the first capacitor and the discharging of the second capacitor, respectively.

[0099] In operation 810, the first measurement process 800 couples the second capacitor and the first capacitor to share the charge of the first capacitor with the second capacitor (e.g., but not limited to, switch 620 is turned on in response to signal S2 such that CAP1 and CAP2 are coupled in parallel).

[0100] In operation 812, the first measurement process 800 couples the input of the measurement circuit with a circuit including a first capacitor and a second capacitor coupled in parallel (e.g., but not limited to, switch 624 is turned on in response to signal S4 such that the measurement inputs, CAP1 and CAP2, are coupled in parallel) to generate a voltage at the input of the measurement circuit that is proportional to the voltage at the voltage node (e.g., a first scaled voltage having a voltage level proportional to the voltage level at the voltage node).

[0101] 9, in optional operation 902, the second measurement process 900 isolates (i.e., switchably isolates) the first capacitor, the second capacitor, and the input of the measurement circuit. The second measurement process 900 differs from the first measurement process 800 at least in part by utilizing the capacitor CAP3. When the second measurement process 900 follows the first measurement process 800, the voltage node and the first capacitor are already isolated (i.e., switchably isolated). Thus, the switch 618 is turned off in response to the signal S1, the switch 620 is turned off in response to the signal S2, the switch 626 is turned off in response to the signal S5, the switch 622 is turned off in response to the signal S4, and the switch 624 is turned off in response to the signal S3.

[0102] In operation 904, the second measurement process 900 couples (i.e., switchably couples) the second capacitor and the third capacitor (e.g., but not limited to, the switch 626 is turned on in response to the signal S5 such that the second capacitor and the third capacitor are coupled in parallel).

[0103] In operation 906, the second measurement process 900 couples (i.e., switchably couples) the first capacitor to the voltage node (e.g., but not limited to, switch 618 being turned on in response to signal S1) to initiate full charging of the first capacitor in response to the voltage at the voltage node.

[0104] In operation 908, the second measurement process 900 couples (i.e., switchably couples) the series-coupled second / third capacitors between the two ground connections to discharge the parallel-coupled second / third capacitors (e.g., but not limited to, the switch 622 is turned on in response to the signal S4 to couple the second ends of the parallel-coupled second / third capacitors CAP2 / CAP3 to ground).

[0105] In operation 910, the second measurement process 900 isolates (i.e., switchably isolates) the first capacitor and the voltage node and isolates (i.e., switchably isolates) the second ends of the coupled second / third capacitors from ground to terminate the charging of the first capacitor and the discharging of the coupled second / third capacitors, respectively (e.g., but not limited to, switches 618 and 622 are turned off in response to signals S1 and S4, respectively).

[0106] In operation 912, the second measurement process 900 couples the first, second, and third capacitors to share the charge of the first capacitor with the coupled second / third capacitors (e.g., but not limited to, switch 620 is turned on in response to signal S2 and switch 626 is already on in response to signal S3 such that CAP1, CAP2, and CAP3 are coupled in parallel).

[0107] At operation 914, the second measurement process 900 couples the input of the measurement circuit with a circuit including the coupled first, second, and third capacitors (e.g., but not limited to, switch 624 is turned on in response to signal S4) to generate a further voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node (e.g., a second scaled voltage having a voltage level proportional to the voltage level at the voltage node).

[0108] 10 is a schematic diagram illustrating an IC 1000 including multiple scaling connections for coupling an analog test bus 1014 to high voltage nodes, here a first high voltage node 1006 and a second high voltage node 1008, due to the relatively small layout area cost of each scaling circuit, here a first scaling connection 1010 and a second scaling connection 1012. Additionally, a first SAR ADC 1002 and a second SAR ADC 1016 are provided, each coupled to the analog test bus 1014 and each providing a respective output to a processor 1004. The processor 1004 includes one or more scaling coefficients 1018.

[0109] For an assumed measurement of a first high voltage node 1006 coupled to an analog test bus 1014 via a first scaling connection 1010, a scaled voltage V SCALE The value of is determined by the SAR ADC 1002 and provided to the processor 1004. For an assumed measurement of a second high voltage node 1008 coupled to an analog test bus 1014 via a second scaling connection 1012, the scaled voltage V of the second high voltage node 1008 is SCALE The value of is read by the SAR ADC 1016 and provided to the processor 1004. Supporting multiple HV nodes simultaneously, each with its own SAR ADC, may enable high speed parallel measurements, which may reduce measurement time and benefit production testing.

[0110] FIG. 11 is a timing diagram 1100 showing signals S1, S2, S3, and S4 of FIG. 2 during an assumed operation of voltage monitoring system 200 according to measurement process 400, where a high value indicates that the signal is asserted so that the respective switch is turned on and a low value indicates that the signal is deasserted so that the respective switch is turned off.

[0111] At time T1, signals S1 and S4 are asserted to turn on switches 218 and 222, thereby coupling the first capacitor CAP1 to the voltage node 202 and coupling the second end of the second capacitor CAP2 in series between the two ground connections. At time T2, signals S1 and S4 are deasserted to turn off switches 218 and 222, thereby isolating the first capacitor CAP1 and the voltage node 202 and isolating the second end of the second capacitor CAP2 from the second of the two ground connections. At time T3, signal S2 is asserted to turn on switch 220, starting charge sharing between the first capacitor CAP1 and the second capacitor CAP2. At time T4, signal S3 is asserted to turn on switch 224, and a voltage proportional to the voltage at the voltage node 202 is generated at the input of measurement circuit 204. At time T5, signal S3 is deasserted to turn off switch 224, ending the generation of a voltage at the input of measurement circuit 204. Signal S2 remains asserted and switch 220 is on from time T3 until a time corresponding to or after time T5. In a specific, non-limiting example, the time skew from time T2 to T3 is 100 nanoseconds (ns), from time T3 to T4 is 100 ns, and the period of T is 100 μs.

[0112] Figure 12 is a timing diagram 1200 illustrating signals S1, S2, S3, S4, and S5 of Figure 6 during an assumed operation of voltage monitoring system 600 according to second measurement process 900. Notably, the timing diagram for an assumed operation of voltage monitoring system 600 according to first measurement process 800 substantially coincides with timing diagram 1100 in which signal S5 is deasserted for the entire period shown.

[0113] Generally, the descriptions of times T1, T2, T3, T4, and T5 in timing diagram 1200 are the same as those in timing diagram 1100. At time T1, signal S5 is asserted to turn on switch 626, coupling capacitors CAP3 and CAP2 in parallel. Signal S5 is asserted for the entire period T shown in FIG. 12 (times T1 through T6).

[0114] As used in this disclosure, the term "combination" referring to a plurality of elements may include a combination of all elements or any of various different subcombinations of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to any one of A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0115] The terms used in this disclosure, and particularly in the appended claims (such as, but not limited to, the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," and the term "includes" should be interpreted as, but not limited to, "including, but not limited to"). As used herein, the term "each" means part or whole. As used herein, the term "each and all" means whole.

[0116] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce the recitation of claims. However, the use of such phrases should not be construed as limiting any particular claim that includes such introduced claim recitation to embodiments that include only one such recitation, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean, but not limited to, "at least one" or "one or more"). The same applies to the use of express articles used to introduce claim recitations.

[0117] In addition, even when a particular number recited in an introduced claim is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., an express recitation of "two recitations" without other modifiers means, without limitation, at least two recitations or more than two recitations). Furthermore, when a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, it is generally intended that such a structure includes only A, only B, only C, A and B together, A and C together, B and C together, or A, B, and C together.

[0118] Additionally, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either one of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0119] Further non-limiting examples include the following:

[0120] Example 1: The method includes providing a circuit including isolated capacitors including at least a first capacitor and a second capacitor between an input of a measurement circuit and a voltage node associated with a higher voltage domain than the measurement circuit; generating, by the measurement circuit, a first digital value representing a voltage level related to the voltage level at the voltage node at least in part in response to performing a measurement process using the circuit; and generating, by a processor, a second digital value representing the voltage level at the voltage node at least in part in response to the first digital value and a scaling factor representing a pre-specified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node.

[0121] Example 2: The method of Example 1, wherein the measurement process includes the steps of coupling the first capacitor to a voltage node to initiate full charging of the first capacitor, coupling the second capacitor in series between two ground connections to initiate full discharging of the second capacitor, isolating the first capacitor from the voltage node and isolating the second capacitor from one of the two ground connections to terminate charging and discharging of each of the first capacitor and the second capacitor, coupling the first capacitor and the second capacitor in parallel to share the charge of the first capacitor with the second capacitor, and coupling an input of the measurement circuit to a circuit including the parallel-coupled first capacitor and second capacitor to generate a voltage level at an input of the measurement circuit that is proportional to the voltage level at the voltage node.

[0122] Example 3: An apparatus comprising: a measurement circuit for generating a first digital value, the first digital value representing a voltage level at an input of the measurement circuit, the measurement circuit including logic for generating a control signal for the measurement process; a voltage scaling circuit for coupling the input of the measurement circuit to a voltage node associated with a high voltage domain higher than the measurement circuit, the voltage scaling circuit responsive to the control signal generated by the logic of the measurement circuit to generate a scaled voltage according to a pre-specified relationship between an input voltage and an output voltage of the voltage scaling circuit; and a processor for generating a second digital value representing the voltage level at the voltage node at least in part in response to the first digital value and a scaling coefficient representing the pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit.

[0123] Example 4: The apparatus of Example 3, wherein the voltage scaling circuit includes a first capacitor, a second capacitor, and a switch for alternately coupling or isolating the first capacitor and the second capacitor at least partially in response to a control signal for the measurement process.

[0124] Example 5: An apparatus as described in Example 3 or 4, wherein the control signal for the measurement process controls the voltage scaling circuit to couple the first capacitor to the voltage node to initiate full charging of the first capacitor, couple the second capacitor in series across the ground connection to initiate discharging of the second capacitor, isolate the first capacitor from the voltage node and isolate the second capacitor from the ground connection to terminate charging of the first capacitor and discharging of the second capacitor, couple the second capacitor and the first capacitor to share the charge of the first capacitor with the second capacitor, and couple the coupled first and second capacitors to the input of the measurement circuit to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

[0125] Example 6: An apparatus described in any one of Examples 3 to 5, wherein the voltage scaling circuit includes an input for switchably coupling to the first capacitor and an output for switchably coupling to the first capacitor and the second capacitor.

[0126] Example 7: The apparatus of any one of Examples 3 to 6, wherein the measurement circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC).

[0127] Example 8: The apparatus of any one of Examples 3-7, including an analog connection for coupling the measurement circuit to the voltage scaling circuit.

[0128] Example 9: The method includes providing a circuit including isolated capacitors, including at least a first capacitor, a second capacitor, and a third capacitor, between an input of a measurement circuit and a voltage node associated with a higher voltage domain than the measurement circuit; generating, by the measurement circuit, a first digital value representing a voltage level related to a voltage level at the voltage node, at least in part in response to performing a first measurement process utilizing the circuit; and scaling, by a processor, at least in part, the first digital value and a first scaling factor representing a prespecified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node. generating, by the measurement circuitry at least in part in response to performing a second measurement process using the circuit, a third digital value representing a further voltage level related to the voltage level at the voltage node; generating, by the processor, at least in part in response to the third digital value and the second scaling factor, a fourth digital value transiently representing the voltage level at the voltage node; and generating, at least in part in response to the second digital value and the fourth digital value, a final digital value representing the voltage level at the voltage node.

[0129] Example 10: The method of Example 9, wherein the first measurement process includes the steps of coupling the first capacitor to a voltage node to initiate full charging of the first capacitor, coupling the second capacitor in series between two ground connections to initiate discharging of the second capacitor, isolating the first capacitor from the voltage node and isolating the second capacitor from the ground connection to terminate charging of the first capacitor and discharging of the second capacitor, respectively, coupling the first capacitor and the second capacitor to share the charge of the first capacitor with the second capacitor, and coupling an input of the measurement circuit and a circuit including the coupled first capacitor and second capacitor to generate a voltage level at the input of the measurement circuit proportional to the voltage level at the voltage node.

[0130] Example 11: The method of Example 9 or 10, wherein the second measurement process includes the steps of coupling the second capacitor and the third capacitor, coupling the first capacitor to a voltage node to start full charging of the first capacitor, coupling the coupled second capacitor and the third capacitor between two ground connections to start discharging the coupled second capacitor and the third capacitor, isolating the first capacitor from the voltage node and isolating one end of the coupled first capacitor and second capacitor from one of the two ground connections to finish charging the first capacitor and discharging the coupled second capacitor and the third capacitor, respectively, coupling the first capacitor and the coupled second capacitor and the third capacitor to share the charge of the first capacitor with the coupled second capacitor and the third capacitor, and coupling the input of the measurement circuit to a circuit including the coupled first, second, and third capacitors to generate a further voltage level at the input of the measurement circuit proportional to the voltage level at the voltage node.

[0131] Example 12: An apparatus comprising: a measurement circuit for generating a digital value representative of a voltage level at an input of the measurement circuit, the measurement circuit including logic for generating control signals including a control signal for a first measurement process and a control signal for a second measurement process; a voltage scaling circuit for coupling the input of the measurement circuit to a voltage node associated with a higher voltage domain than the measurement circuit, the voltage scaling circuit generating a first scaled voltage at the input of the measurement circuit according to a first pre-specified relationship between an input voltage and an output voltage of the voltage scaling circuit in response to the control signal for the first measurement process generated by the logic of the measurement circuit, and generating a second scaled voltage at the input of the measurement circuit according to a second pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit in response to the control signal for the second measurement process generated by the logic of the measurement circuit; and a processor for generating a digital value transiently representative of a voltage level at the voltage node in at least partial response to a first scaling coefficient representative of the first pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit, a second scaling coefficient representative of the second pre-specified relationship between the input voltage and the output voltage of the voltage scaling circuit, and the digital value generated by the measurement circuit.

[0132] Example 13: The apparatus of Example 12, wherein the digital values ​​generated by the measurement circuit include a first digital value representing a first scaled voltage generated by the voltage scaling circuit in response to a control signal for the first measurement process, and a second digital value representing a second scaled voltage generated by the voltage scaling circuit in response to a control signal for the second measurement process.

[0133] Example 14: An apparatus as described in Example 12 or 13, wherein the voltage scaling circuit includes a first capacitor, a second capacitor, a third capacitor, and a switch for alternately coupling or isolating the first capacitor, the second capacitor, and the third capacitor at least partially in response to control signals for each of the first measurement process and the second measurement process.

[0134] Example 15: An apparatus described in any one of Examples 12 to 14, wherein the control signal for the first measurement process controls the voltage scaling circuit to couple the first capacitor to the voltage node to begin charging the first capacitor, couple the second capacitor between the two ground connections to begin discharging the second capacitor, isolate the first capacitor from the voltage node and isolate one end of the second capacitor and one of the two ground connections to end the charging of the first capacitor and the discharging of the second capacitor, couple the first capacitor to the second capacitor to share the charge of the first capacitor with the second capacitor, and couple the input of the measurement circuit to the output of the voltage scaling circuit to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

[0135] Example 16: The apparatus of any one of Examples 12 to 15, wherein the control signal for the second measurement process controls the voltage scaling circuit to couple the second capacitor and the third capacitor, couple the first capacitor to the voltage node to initiate charging of the first capacitor, couple the coupled second capacitor and the third capacitor between two ground connections to initiate discharging of the coupled second capacitor and the third capacitor, isolate the first capacitor from the voltage node to terminate charging of the first capacitor and discharging of the coupled second capacitor and the third capacitor, isolate one end of the coupled second capacitor and the third capacitor from one of the two ground connections, couple the first capacitor and the coupled second capacitor and the third capacitor to share the charge of the first capacitor with the coupled second capacitor and the third capacitor, and couple the input of the measurement circuit and the output of the voltage scaling circuit to generate a further voltage level at the input of the measurement circuit proportional to the voltage level at the voltage node.

[0136] Example 17: The apparatus of any one of Examples 12 to 16, wherein the measurement circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC).

[0137] Example 18: The apparatus of any one of Examples 12 to 17, comprising an analog connection for coupling the measurement circuit to the voltage scaling circuit.

[0138] Example 19: An electronic system including at least two successive approximation register (SAR) analog-to-digital converters (ADCs), a first scaling connection, a second scaling connection, a bus for routing voltage signals provided by the first scaling connection and the second scaling connection to any one of the at least two SAR ADCs, and a processor having a scaling coefficient representing a relationship between a level of the voltage signal routed by the bus and a level of a voltage signal generated by each device coupled to the respective inputs of the first scaling connection and the second scaling connection, wherein each device coupled to the respective inputs of the first scaling connection and the second scaling connection each has a voltage domain higher than the voltage domain of the SAR ADC.

[0139] While the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below along with their legal equivalents. In addition, features of one embodiment can be combined with features of other disclosed embodiments as contemplated by the inventor and still fall within the scope of the present disclosure.

Claims

1. 1. A method, comprising: providing a circuit including isolated capacitors including at least a first capacitor and a second capacitor between an input of a measurement circuit and a voltage node associated with a higher voltage domain than said measurement circuit; generating, by the measurement circuitry, a first digital value representative of a voltage level related to a voltage level at the voltage node, at least in part in response to performing a measurement process using the circuitry; generating, by a processor, a second digital value representing the voltage level at the voltage node in at least partly response to the first digital value and a scaling factor representing a pre-specified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node.

2. The measurement process comprises: coupling the first capacitor to the voltage node to initiate full charging of the first capacitor; coupling the second capacitor in series between two ground connections to initiate a full discharge of the second capacitor; isolating the first capacitor from the voltage node and the second capacitor from one of the two ground connections to terminate charging and discharging of the first capacitor and the second capacitor, respectively; coupling the first capacitor and the second capacitor in parallel to share a charge of the first capacitor with the second capacitor; and coupling the input of the measurement circuit to a circuit including the first capacitor and the second capacitor coupled in parallel to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

3. An apparatus, comprising: a measurement circuit for generating a first digital value, the first digital value representing a voltage level at an input of the measurement circuit, the measurement circuit including logic for generating control signals for a measurement process; a voltage scaling circuit for coupling the input of the measurement circuit to a voltage node associated with a high voltage domain higher than the measurement circuit; a voltage scaling circuit responsive to a control signal generated by the logic of the measurement circuit for generating a scaled voltage according to a prespecified relationship between an input voltage and an output voltage of the voltage scaling circuit; and a processor for generating a second digital value representing the voltage level at the voltage node in at least partly response to the first digital value and a scaling coefficient representing the prespecified relationship between an input voltage and an output voltage of the voltage scaling circuit.

4. The voltage scaling circuit comprises: A first capacitor; A second capacitor; and a switch for alternately coupling or isolating the first capacitor and the second capacitor at least partially in response to the control signal for the measurement process.

5. The control signal for the measurement process for controlling the voltage scaling circuitry comprises: coupling the first capacitor to the voltage node to initiate a full charge of the first capacitor; coupling the second capacitor in series across a ground connection to initiate a discharge of the second capacitor; isolating the first capacitor from the voltage node and the second capacitor from the ground connection to terminate the charging of the first capacitor and the discharging of the second capacitor; coupling the second capacitor to the first capacitor to share the charge of the first capacitor with the second capacitor; and 5. The apparatus of claim 4, further comprising: a first capacitor coupled to said input of said measurement circuit and said second capacitor coupled together to generate a voltage level at said input of said measurement circuit that is proportional to the voltage level at said voltage node.

6. The voltage scaling circuit comprises: an input for switchably coupling to the first capacitor; an output for switchably coupling to the first capacitor and to the second capacitor.

7. The apparatus of claim 3 , wherein the measurement circuit comprises a successive approximation register (SAR) analog-to-digital converter (ADC).

8. 4. The apparatus of claim 3, further comprising an analog connection coupling the measurement circuit to the voltage scaling circuit.

9. 1. A method, comprising: providing a circuit including isolated capacitors including at least a first capacitor, a second capacitor, and a third capacitor between an input of a measurement circuit and a voltage node associated with a higher voltage domain than said measurement circuit; generating, by the measurement circuitry, a first digital value representative of a voltage level related to a voltage level at the voltage node, at least in part in response to performing a first measurement process utilizing the measurement circuitry; generating, by a processor, a second digital value transiently representing the voltage level at the voltage node in response at least in part to the first digital value and a first scaling factor representing a prespecified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node; generating, by the measurement circuitry, a third digital value representative of a further voltage level related to the voltage level at the voltage node, at least in part in response to performing a second measurement process using the measurement circuitry; generating, by a processor, a fourth digital value at least partially responsive to the third digital value and the second scaling factor, the fourth digital value transiently representing the voltage level at the voltage node; generating a final digital value representative of the voltage level at the voltage node at least in part in response to the second digital value and the fourth digital value.

10. The first measurement process comprises: coupling the first capacitor to the voltage node to initiate full charging of the first capacitor; coupling the second capacitor in series between two ground connections to initiate a discharge of the second capacitor; isolating the first capacitor from the voltage node and the second capacitor from a ground connection to terminate the charging of the first capacitor and the discharging of the second capacitor, respectively; coupling the first capacitor and the second capacitor to share a charge of the first capacitor with the second capacitor; and coupling the input of the measurement circuit to the circuit including the coupled first capacitor and the second capacitor to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

11. The second measurement process comprises: coupling the second capacitor and a third capacitor; coupling the first capacitor to the voltage node to initiate full charging of the first capacitor; coupling the coupled second and third capacitors between two ground connections to initiate a discharge of the coupled second and third capacitors; isolating the first capacitor from the voltage node and isolating one end of the coupled first and second capacitors from one of the two ground connections to terminate the charging of the first capacitor and the discharging of the coupled second and third capacitors, respectively; coupling the first capacitor with the coupled second and third capacitors to share the charge of the first capacitor with the coupled second and third capacitors; and coupling the input of the measurement circuit and the circuit including the coupled first capacitor, the second capacitor, and the third capacitor to generate a further voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

12. An apparatus, comprising: a measurement circuit for generating a digital value representative of a voltage level at an input of the measurement circuit, the measurement circuit including logic for generating control signals including a control signal for a first measurement process and a control signal for a second measurement process; a voltage scaling circuit for coupling the input of the measurement circuit to a voltage node associated with a higher voltage domain than the measurement circuit; generating a first scaled voltage at the input of the measurement circuit according to a first prespecified relationship between an input voltage and an output voltage of the voltage scaling circuit in response to a control signal for the first measurement process generated by the logic of the measurement circuit; and a voltage scaling circuit for generating a second scaled voltage at the input of the measurement circuit according to a second prespecified relationship between an input voltage and an output voltage of the voltage scaling circuit in response to a control signal for the second measurement process generated by the logic of the measurement circuit; and a processor for generating a digital value transiently representative of a voltage level at the voltage node in at least partial response to a first scaling coefficient representative of the first pre-specified relationship between an input voltage and an output voltage of the voltage scaling circuit, a second scaling coefficient representative of the second pre-specified relationship between the input voltage and an output voltage of the voltage scaling circuit, and a digital value generated by the measurement circuit.

13. The digital value generated by the measurement circuitry is a first digital value representing the first scaled voltage generated by the voltage scaling circuit in response to a control signal for the first measurement process; and a second digital value representative of the second scaled voltage produced by the voltage scaling circuit in response to a control signal for the second measurement process.

14. The voltage scaling circuit comprises: A first capacitor; A second capacitor; a third capacitor; and and a switch for alternately coupling or isolating the first capacitor, the second capacitor, and the third capacitor at least partially in response to the control signal for each of the first measurement process and the second measurement process.

15. The control signal for the first measurement process for controlling the voltage scaling circuit comprises: coupling the first capacitor to the voltage node to initiate charging of the first capacitor; coupling the second capacitor between two ground connections to initiate a discharge of the second capacitor; isolating the first capacitor from the voltage node and isolating one end of the second capacitor from one of the two ground connections to terminate the charging of the first capacitor and the discharging of the second capacitor; coupling the first capacitor and the second capacitor to share the charge of the first capacitor with the second capacitor; and 15. The apparatus of claim 14, further comprising: a voltage scaling circuit output coupled to the input of the measurement circuit to generate a voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

16. The control signal for the second measurement process for controlling the voltage scaling circuit is coupling the second capacitor to the third capacitor; coupling the first capacitor to the voltage node to initiate charging of the first capacitor; coupling the second and third capacitors together between two ground connections to initiate a discharge of the second and third capacitors together; isolating the first capacitor from the voltage node and isolating one end of the coupled second and third capacitors from one of the two ground connections to terminate the charging of the first capacitor and the discharging of the coupled second and third capacitors; coupling the first capacitor with the coupled second and third capacitors to share a charge of the first capacitor with the coupled second and third capacitors; and 15. The apparatus of claim 14, further comprising: a voltage scaling circuit coupled to an input of the measurement circuit to generate a further voltage level at the input of the measurement circuit that is proportional to the voltage level at the voltage node.

17. 13. The apparatus of claim 12, wherein the measurement circuit comprises a successive approximation register (SAR) analog-to-digital converter (ADC).

18. 13. The apparatus of claim 12, further comprising an analog connection coupling the measurement circuit to the voltage scaling circuit.

19. 1. An electronic system comprising: at least two successive approximation register (SAR) analog-to-digital converters (ADCs); a first scaling connection; a second scaling connection; and a bus for routing voltage signals provided by the first scaling connection and the second scaling connection to any one of the at least two SAR ADCs; a processor having a scaling coefficient representing a relationship between a level of the voltage signal routed by the bus and a level of a voltage signal generated by each device coupled to an input of each of the first and second scaling connections; a respective device coupled to the respective inputs of the first scaling connection and the second scaling connection each having a higher voltage domain than a voltage domain of the SAR ADC.

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