Sacrificial cap layer for gate protection

Abstract

The method includes providing a substrate including metal gate stacks and source / drain contact regions interleaved along a surface of the substrate with a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack. Each source / drain region is recessed into an opening between adjacent metal gate stacks such that the source / drain contact region provides a bottom of the recess and the dielectric spacer provides a sidewall. An etch stop layer is formed on the substrate conformally covering the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and over at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source / drain contact, and then the sacrificial layer is removed from the metal gate stacks and from the sidewalls of each recess.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 179,098, filed April 23, 2021, which is incorporated by reference in its entirety.

[0002] The present invention relates generally to semiconductor device manufacturing, and more particularly to a method for forming a sacrificial cap layer for gate protection. [Background technology]

[0003] Advances in semiconductor technology depend on continuous improvements in fabrication techniques. Innovations in semiconductor technology have introduced new types of structures, such as FinFET devices, stacked structures (e.g., 3D NAND devices), and the like. However, these new structures bring the need for new fabrication schemes to overcome what could otherwise be exacerbated manufacturing challenges. The present inventors have recognized one such challenge caused by damage to cap layers and erosion of spacers on gate sidewalls as a result of semiconductor plasma processing techniques. For example, dry etching processes such as reactive ion etching (RIE) can be used to open contacts in traditional middle-of-the-line (MOL) process flows. In many cases, dry etching processes can be very aggressive to some layers in semiconductor process flows. Typically, dry etching processes have a plasma source that generates a large number of ions that accelerate in a manner that causes ion bombardment against sensitive device layers. As a result, plasma etching processes can damage the underlying materials, especially when opening high aspect ratio contact holes. This damage to the underlying materials can lead to not only yield loss, but also uncontrolled variations in the electrical performance of the devices. Summary of the Invention [Means for solving the problem]

[0004] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] Aspect (1) provides a method including providing a substrate including a plurality of metal gate stacks and a plurality of source / drain contact regions interleaved along a surface of the substrate with a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack. Each of the source / drain regions is recessed into an opening between adjacent metal gate stacks such that the source / drain contact region provides a bottom of the recess and the dielectric spacer provides a sidewall of the recess. An etch stop layer is formed on the substrate conformally covering the plurality of metal gate stacks and the sidewalls and bottom of each recess, and a sacrificial layer is formed on each of the metal gate stacks and on at least a portion of each sidewall of each recess. The etch stop layer is removed from the bottom of each recess to expose a source / drain contact, and then the sacrificial layer is removed from each of the metal gate stacks and from the sidewalls of each recess.

[0006] Example (2) includes the method of example (1), wherein forming the sacrificial layer includes forming a sacrificial layer having a first thickness on top of each metal gate stack and a second thickness on a sidewall of each recess, the first thickness being greater than the second thickness.

[0007] Example (3) includes the method of example (1), wherein forming the sacrificial layer includes forming a sacrificial layer on each sidewall such that the thickness of the sacrificial layer decreases from the top of the recess to the bottom of the recess.

[0008] Example (4) includes the method of example (1), wherein forming the sacrificial layer includes forming the sacrificial layer preferentially on the top of each metal gate stack compared to the sidewalls of each recess.

[0009] Example (5) includes the method of example (4), wherein preferentially forming the sacrificial layer includes performing an atomic layer deposition (ALD) process under processing conditions that reduce diffusion of reactant gases into the recessed portion.

[0010] Example (6) includes the method of example (5), wherein the process conditions include at least one of a concentration of a reactant gas, a gas exposure time, a substrate temperature, and a substrate rotation speed.

[0011] An embodiment (7) includes the method of embodiment (4), wherein preferentially forming a sacrificial layer includes rotating the substrate while exposing the substrate to a gas to form the sacrificial layer.

[0012] Example (8) includes the method of example (7), further including setting a rotation speed of the substrate to effect a predetermined preferential deposition of the sacrificial layer on top of each metal gate stack.

[0013] Example (9) includes the method of example (1), wherein forming the etch stop layer includes forming a layer including silicon nitride, silicon oxide, or silicon oxynitride.

[0014]

[0023] Example (10) includes the method of example (1), wherein forming the sacrificial layer includes forming a layer including a metal oxide (MOx), a metal nitride (MNx), or a metal oxynitride.

[0015] Example (11) includes the method of example (4), wherein preferentially forming the sacrificial layer includes forming a sacrificial cap layer having a thickness in the range of 0.5 nm to about 10 nm on top of each metal gate stack.

[0016] Example (12) includes the method of example (11), wherein preferentially forming the sacrificial layer includes forming a sacrificial cap layer having a thickness in the range of 2 nm to about 5 nm on top of each metal gate stack.

[0017] Another aspect (13) provides a method that includes providing a substrate including source / drain contact regions, a replacement metal gate stack, spacers on sidewalls of the replacement metal gate stack, and an etch stop layer on the spacers. A sacrificial cap layer is formed on the replacement metal gate stack, the sacrificial cap layer having a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness. The etch stop layer is removed and the sacrificial cap layer is removed using a plasma etch process.

[0018] Example (14) includes the method of example (13), wherein the etch stop layer includes silicon nitride, silicon oxide, or silicon oxynitride.

[0019] Example (15) includes the method of example (13), wherein the sacrificial cap layer includes a metal oxide (MOx), a metal nitride (MNx), or a metal oxynitride.

[0020] Example (16) includes the method of example (13), wherein the sacrificial cap layer includes AlN, TiN, or TiOx.

[0021] Example (17) includes the method of example (13), wherein the substrate is rotated during formation of the sacrificial cap layer.

[0022] Example (18) includes the method of example (13), wherein removing the sacrificial cap layer includes using a wet etching chemistry.

[0023] Another aspect (19) provides a method that includes providing a substrate including source / drain contact regions, a replacement metal gate (RMG) stack, low dielectric constant spacers on sidewalls of the replacement metal gate stack, and an etch stop layer on the spacers. A sacrificial cap layer including TiO2 is formed on the replacement metal gate stack, the sacrificial cap layer having a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness. The etch stop layer is removed using a plasma etch process and the sacrificial cap layer is removed using a wet etch chemistry.

[0024] Example (20) includes the method of example (19), wherein forming a sacrificial cap layer includes preferentially depositing on top of each RMG stack by atomic layer deposition (ALD) using sequential exposure to titanium tetrakis(dimethylamido)titanium (TDMA) and ozone (O3) at a process pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 100° C. to about 150° C., and a substrate rotation speed of about 10 RPM to about 50 RPM.

[0025] Please note that this summary section does not specify all embodiments and / or inherently novel aspects of the present disclosure described in the disclosure or claims. Rather, the summary section merely provides a preliminary description of different embodiments and points out corresponding novel aspects over the prior art. For additional details and / or possible perspectives of the present disclosure and embodiments, the reader is directed to the Detailed Description section of the present disclosure and corresponding figures, which are further described below.

[0026] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale, and in fact dimensions of various features may be expanded or reduced for clarity of discussion. [Brief description of the drawings]

[0027] [Figure 1A]1 illustrates a cross-sectional view of a fin portion of a semiconductor device during fabrication taken along the direction of the fin. [Figure 1B] 1 illustrates a gate cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention taken along a direction orthogonal to the fin direction. [Figure 1C] 1 illustrates a top view of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 2A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 2B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 3A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 3B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 4A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 4B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 5A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 5B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 6A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 6B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 7A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 7B]3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 8A] 1 shows a partial cross-sectional view of a semiconductor device 100 at a next manufacturing stage after removing a sacrificial cap layer 110, according to an exemplary embodiment of the present disclosure. [Figure 8B] 1 shows a partial cross-sectional view of a semiconductor device 100 at a next manufacturing stage after removing a sacrificial cap layer 110, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The following disclosure presents many embodiments or examples that realize various features of the presented subject matter. Specific examples of components and configurations are described below to simplify the disclosure. It should be understood that these are merely examples and are not intended to limit the present invention. For example, forming a first feature above or directly above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purposes of brevity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations described. Furthermore, spatial relationship terms such as "top," "bottom," "lower," "lower," "lower," "upper," "upper," and the like may be used herein to facilitate the description of the relationship of one element or feature to another element(s) or feature(s) as illustrated. The spatial relationship terms are intended to encompass different orientations of the device during use or operation in addition to the orientation illustrated. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein may likewise be interpreted accordingly.

[0029] The present application discloses a method for preventing damage to semiconductor regions during plasma etching. The proposed integration scheme uses a sacrificial cap layer formed directly on top of the semiconductor region to be protected. This sacrificial cap layer is designed to protect the semiconductor region during the plasma etching process that would otherwise damage the semiconductor region. This sacrificial cap layer can be removed later in the process using a mild wet cleaning process.

[0030] The embodiments of the present application can be applied to various types of devices such as fin transistors and stacked memory devices, etc. Specific embodiments of the above process are described below with reference to Figures 1 to 8.

[0031] Figure 1A shows a partial cross-sectional view of a semiconductor device under fabrication along the direction of the fins, and Figure 1B shows a cross-sectional view of the semiconductor device along a direction perpendicular to the direction of the fins. Figure 1C shows a top view showing cut lines 1A-1A and 1B-1B shown in Figure 1A and 1B, respectively, all according to an embodiment of the present invention. Figure 1A is a partial cross-sectional view and does not show the underlying fins and substrate.

[0032] 1A-1C, at this stage of processing, semiconductor device 100 has already undergone a substantial portion of front-end-of-line (FEOL) fabrication. For example, as shown in FIG. 1B, a transistor structure having a plurality of fins 109 is formed on a substrate 111.

[0033] In various embodiments, the substrate 111 may include silicon, silicon germanium, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, and others. The substrate 111 may include a semiconductor wafer, which may include a semiconductor epitaxial layer, including a heteroepitaxial layer. For example, in one or more embodiments, one or more heteroepitaxial layers including a compound semiconductor may be formed on a semiconductor substrate. In various embodiments, some or all of the substrate 111 may be amorphous, polycrystalline, or single crystalline. In various embodiments, the substrate 111 may be doped, undoped, or may include both doped and undoped regions.

[0034] The fins 109 may be formed by epitaxial growth from a substrate 111, or alternatively, using an etch-back process that leaves the fins 109. The fins 109 may be separated from one another by shallow isolation regions 112. Thus, the shallow isolation regions 112 and the fins 109 may form an alternating pattern.

[0035] In one embodiment, the shallow isolation regions 112 may be formed by depositing an oxide fill material after patterning the fins 109, which is then planarized using, for example, a chemical mechanical planarization process. After planarization, the shallow isolation regions 112 may be recessed to raise the fins 109.

[0036] The multiple dummy gates 102 are formed over the substrate 111 and the multiple fins 109. In one embodiment, the multiple dummy gates 102 may be formed by patterning a layer of amorphous silicon or polysilicon deposited over the multiple fins 109.

[0037] Next, spacers 101 are formed on sidewalls of the dummy gates 102. The spacers 101 can be formed by deposition of an insulating layer followed by an anisotropic etching process. For example, a reactive ion etching (RIE) process can be used to form the spacers 101. The material of the insulating layer is selected to be impervious to etching by chemicals such as TMAH or NH4OH that are not selectively etched during removal of the dummy gates 102 later in the process. In one example, the spacers 101 can include a low-k material.

[0038] Epitaxial regions 103 are then grown over portions of the fins 109 located between the dummy gates 102 to form raised source / drain regions. The upper surfaces of the raised source / drain regions may form facets due to the growth pattern of the corresponding epitaxial material.

[0039] In one or more embodiments, the epitaxial region 103 may be formed in a single epitaxial growth process. In other embodiments, the growth of the epitaxial region 103 may consist of a multi-step process. For example, the multi-step process may begin with growing an initial epitaxial layer having a first doping on the fins 109 to a predetermined thickness, followed by growing a second layer having a second doping. For example, the second doping may be a higher doping than the first doping. Similarly, the different layers may differ in composition, for example, of germanium or other compounds. The epitaxial growth process may use any type of epitaxial process, including molecular beam epitaxy (MBE), or various types of chemical vapor deposition (CVD).

[0040] In one or more embodiments, the epitaxial region 103 may be grown to introduce strain into the fins 109, for example due to lattice mismatch.

[0041] In one or more embodiments, source / drain (S / D) regions may be formed by doping the fin region and the epitaxial region 103, for example, in an implant / anneal process.

[0042] 2A-2B show cross-sectional views of semiconductor device 100 at a subsequent manufacturing stage after forming an etch stop layer (ESL) 105 over semiconductor device 100. Figure 2A shows a cut line similar to Figure 1A, while Figure 2B shows a cut line similar to Figure 1B.

[0043] The ESL 105 may be conformally deposited over the entire wafer surface. In various embodiments, the ESL 105 comprises silicon nitride, silicon oxide, or silicon oxynitride. In various embodiments, the ESL 105 may have a thickness in the range of 0.5 nm to about 10 nm. In one embodiment, the ESL 105 may have a thickness in the range of 2 nm to about 5 nm.

[0044] 3A-3B show partial cross-sectional views of an in-process semiconductor device 100 after depositing oxide 106, according to an embodiment of the invention. Figure 3A shows a cut line similar to Figure 1A, while Figure 3B shows a cut line similar to Figure 1B.

[0045] 3A and 3B, oxide 106 is filled between the dummy gates 102. The oxide 106 is overfilled above the top surface of the ESL 105 and on top of the dummy gates 102.

[0046] In various embodiments of the semiconductor device 100, the oxide 106 can be a flowable oxide including spin-on glass. In one example, a layer including borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), arsenic silicon glass (ArSG), or other types of glass can be deposited and heated to reflow. In one or more embodiments, the oxide 106 can also include oxides such as tetraethyloxysilane (TEOS), fluorinated TEOS (FTEOS), organosilicate glass (OSG), fluorinated silicate glass (FSG), or spin-on glass (SOG).

[0047] 4A-4B show cross-sectional views of a semiconductor device 100 in fabrication after forming a replacement metal gate (RMG) in accordance with an embodiment of the present invention. Figure 4A shows a cut line similar to Figure 1A, while Figure 4B shows a cut line similar to Figure 1B.

[0048] As shown in Figures 4A and 4B, the oxide 106 is planarized to expose the underlying ESL 105. The ESL 105 may be removed using an anisotropic etching process to expose the dummy gates 102. The dummy gates 102 are then removed using, for example, a wet etching process or alternatively a plasma process. The spacers 101 preserve the shape of the gate stack during removal of the dummy gates 102. During the etching process, the oxide 106 protects the underlying regions of the epitaxial region 103.

[0049] After removing the dummy gates 102, the inner walls of the spacers 101 are exposed leaving a cavity. The cavity is filled with a replacement gate material 107. After the replacement gate material 107 is in place, a contact cap 108 is formed. The contact cap 108 may be formed using a self-aligned process such that it is selectively formed only on the replacement gate material 107.

[0050] The replacement gate material 107 together with a contact cap 108 form a replacement metal gate (RMG) stack 102'. The RMG stack 102' serves to set the work function of the gate and forms the final gate electrode of the semiconductor device 100.

[0051] 5A-5B show partial cross-sectional views of semiconductor device 100 at a next manufacturing stage after etching oxide 106, in accordance with an embodiment of the present invention. Figure 5A shows a cut line similar to Figure 1A, while Figure 5B shows a cut line similar to Figure 1B.

[0052] As shown in FIG. 5A, etching the oxide 106 leaves behind an empty, unfilled trench or recessed feature. In various embodiments, the oxide etch process can be a wet etch process or a dry etch process such as reactive ion etching (RIE), or any process currently known in the art of semiconductor manufacturing. Etching the oxide 106 exposes the remaining ESL 105 between the spacers 101 that line the replacement gate material 107 and the contact cap 108.

[0053] 6A-6B show partial cross-sectional views of a semiconductor device 100 at a next manufacturing stage after depositing a sacrificial cap layer 110, in accordance with an embodiment of the present invention. Figure 6A shows a cut line similar to Figure 1A, while Figure 6B shows a cut line similar to Figure 1B.

[0054] The sacrificial cap layer 110 may be preferentially deposited on top of the RMG stack 102' including the contact cap 108 and the replacement gate material 107. As shown generally in Figures 6A-6B, the thickness of the sacrificial cap layer 110 may be greater on the contact cap 108 compared to on the ESL 105 on the spacer 101, and the thickness of the sacrificial cap layer 110 on the ESL 105 spacer 101 may decrease from the top of the spacer 101 to the bottom of the spacer 101. In various embodiments, the sacrificial cap layer 110 may include any of metal oxides (MOx), metal nitrides (MNx), and metal oxynitrides, such as AlOx, AlN, TiN, TiOx, where "M" represents an elemental metal, such as aluminum, titanium, tantalum, and others.

[0055] In various embodiments, the sacrificial cap layer 110 can have a thickness in the range of 0.5 nm to about 10 nm on top of the contact cap 108. In one embodiment, the sacrificial cap layer 110 can have a thickness in the range of 2 nm to about 5 nm.

[0056] In one embodiment of the semiconductor device 100, the sacrificial cap layer 110 is formed using a vapor deposition process, such as an atomic layer deposition (ALD) process, a chemical vapor deposition process such as metal-organic CVD (MOCVD), and other such processes.

[0057] In one embodiment, preferential deposition of the sacrificial cap layer 110 on top of the RMG stacks 102′ can be achieved using an ALD process and processing conditions that reduce diffusion of reactant gases into trenches or recessed features between the multiple RMG stacks 102′. Processing conditions can include concentration of reactant gas, gas exposure time, substrate temperature, and substrate rotation speed. In one example, the substrate can be rotated during gas exposure, and the rotation speed can be optimized to achieve the desired preferential deposition. In some examples, a higher rotation speed can result in increased preferential deposition on top of the RMG stacks 102′. Thus, the shape of the sacrificial cap layer 110 can be tailored, and the sacrificial cap layer 110 can have a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness.

[0058] In one example, a sacrificial cap layer 110 including TiO, preferentially deposited on top of the RMG stack 102′, can be deposited by ALD using sequential exposure to titanium tetrakis(dimethylamido)titanium (TDMAT) and ozone (O) at a process pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 100° C. to about 150° C., and a rotation speed of about 10 RPM to about 50 RPM.

[0059] 7A-7B show partial cross-sectional views of a semiconductor device 100 at a next manufacturing stage after performing an ESL etching process, in accordance with an embodiment of the present invention. Figure 7A shows a cut line similar to Figure 1A, while Figure 7B shows a cut line similar to Figure 1B.

[0060] The ESL etch process removes the remaining ESL 105 on the plurality of spacers 101 that line the replacement gate material 107 and the contact caps 108 .

[0061] In various embodiments, the remaining ESL 105 is removed using a plasma process, such as a reactive ion etching (RIE) process, which may have low etch selectivity to the contact cap 108 and spacers 101, and the sacrificial cap layer 110 protects the contact cap 108 and the underlying spacers 101 from plasma damage during the highly anisotropic RIE process.

[0062] 8A-8B show partial cross-sectional views of a semiconductor device 100 at a next manufacturing stage after removing the sacrificial cap layer 110, in accordance with an embodiment of the present invention. Figure 8A shows a cut line similar to Figure 1A, while Figure 8B shows a cut line similar to Figure 1B.

[0063] Removal of the sacrificial cap layer 110 may be performed by an etching process, such as a wet etch, that is efficient and does not damage the contact cap 108, the plurality of spacers 101, and the epitaxial region 103. In one example, the wet etch may include a mixture of sulfuric acid and hydrogen peroxide (SPM) at about 70° C. to about 110° C.

[0064] In the above description, specific details have been set forth, such as the particular configuration of the processing system and a description of the various components and processes used therein. However, it should be understood that the technology of the present invention may be implemented in other embodiments that differ from these specific details, and that such details are for the purpose of explanation and are not intended to limit the present invention. Several embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific values, materials, and configurations have been set forth to provide a thorough understanding. Nevertheless, several embodiments can be implemented without such specific details. Components having substantially the same functional structure are labeled with similar reference numerals, and therefore redundant descriptions may be omitted if any.

[0065] Various techniques have been described as multiple separate operations to facilitate understanding of various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in different orders than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0066] As used herein, "substrate" or "wafer" refers collectively to an object to be processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, such as a base substrate structure (such as a semiconductor wafer), a reticle, or a layer (such as a thin film) on or over the base substrate structure. Thus, the substrate is not limited to any particular base structure, lower or upper layer, patterned or unpatterned, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. Although the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0067] Those skilled in the art will also appreciate that many modifications may be made to the operation of the techniques described above and still achieve the same objectives of the invention. Such modifications are intended to be encompassed within the scope of the present disclosure. Accordingly, the foregoing description of embodiments of the invention is not intended to be limiting. Rather, any limitations to the embodiments of the invention are set forth in the following claims.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of: providing a substrate having a plurality of metal gate stacks and a plurality of source / drain contact regions in an alternating arrangement along a surface of the substrate with a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack, each of the source / drain regions being embedded within an opening between adjacent metal gate stacks, the source / drain contact regions providing a bottom of the recess, and the dielectric spacer providing a sidewall of the recess; forming an etch stop layer on the substrate, the etch stop layer conformally covering the plurality of metal gate stacks, the sidewalls of each recess, and the bottom of each recess; forming a sacrificial layer over each of the metal gate stacks and on at least a portion of each sidewall of each recess; removing the etch stop layer from the bottom of each recess while leaving the sacrificial layer on at least a portion of each sidewall of each recess to expose the source / drain contacts; removing the sacrificial layer from each of the metal gate stacks and from the sidewalls of each recess; The method comprising:

2. forming the sacrificial layer includes forming the sacrificial layer having a first thickness on top of each metal gate stack and a second thickness on the sidewalls of each recess; The method of claim 1 , wherein the first thickness is greater than the second thickness.

3. The method of claim 1 , wherein forming the sacrificial layer comprises forming the sacrificial layer on each sidewall such that a thickness of the sacrificial layer decreases from a top of the recess toward the bottom of the recess.

4. 2. The method of claim 1, wherein forming the sacrificial layer comprises preferentially forming the sacrificial layer on top of each metal gate stack relative to sidewalls of each recess.

5. 5. The method of claim 4, wherein preferentially forming the sacrificial layer comprises performing an atomic layer deposition (ALD) process under processing conditions that inhibit diffusion of reactant gases into the recessed features.

6. The method of claim 5 , wherein the process conditions include at least one of a concentration of the reactive gas, a gas exposure time, a substrate temperature, and a substrate rotation speed.

7. The method of claim 4 , wherein preferentially forming the sacrificial layer comprises rotating the substrate while exposing the substrate to a gas that forms the sacrificial layer.

8. 8. The method of claim 7, further comprising setting a rotation speed of the substrate to provide a predetermined preferential deposition of the sacrificial layer on top of each metal gate stack.

9. The method of claim 1 , wherein forming the etch stop layer comprises forming a layer comprising silicon nitride, silicon oxide, or silicon oxynitride.

10. 10. The method of claim 1, wherein forming the sacrificial layer comprises forming a layer comprising a metal oxide (MOx), a metal nitride (MNx), or a metal oxynitride.

11. 5. The method of claim 4, wherein preferentially forming the sacrificial layer comprises forming a sacrificial cap layer on the top of each metal gate stack having a thickness in the range of 0.5 nm to about 10 nm.

12. 12. The method of claim 11, wherein preferentially forming the sacrificial layer comprises forming a sacrificial cap layer having a thickness in the range of 2 nm to about 5 nm on the top of each metal gate stack.

13. providing a substrate having source / drain contact regions, a replacement metal gate stack, spacers on sidewalls of the replacement metal gate stack, and an etch stop layer on the spacers; forming a sacrificial cap layer on the replacement metal gate stack, the sacrificial cap layer having a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness, the sacrificial cap layer being formed on only a portion of the replacement metal gate stack such that an exposed portion of the etch stop layer is exposed; removing the exposed portion of the etch stop layer while leaving the sacrificial layer on top of the etch stop layer using a plasma etch process; removing the sacrificial cap layer; The method comprising:

14. The method of claim 13 , wherein the etch stop layer comprises silicon nitride, silicon oxide, or silicon oxynitride.

15. 14. The method of claim 13, wherein the sacrificial cap layer comprises a metal oxide (MOx), a metal nitride (MNx), or a metal oxynitride.

16. The method of claim 13 , wherein the sacrificial cap layer comprises AlN, TiN, or TiOx.

17. The method of claim 13 , wherein the substrate is rotated during the step of forming the sacrificial cap layer.

18. The method of claim 13 , wherein removing the sacrificial cap layer comprises using a wet etch chemistry.

19. providing a substrate having source / drain contact regions, a replacement metal gate (RMG) stack, low dielectric constant spacers on sidewalls of the replacement metal gate stack, and an etch stop layer on the spacers; forming a sacrificial cap layer comprising TiO2 on the replacement metal gate stack, the sacrificial cap layer having a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness, the sacrificial cap layer being formed on only a portion of the replacement metal gate stack such that an exposed portion of the etch stop layer is exposed; removing the exposed portion of the etch stop layer while leaving the sacrificial layer on top of the etch stop layer using a plasma etch process; removing the sacrificial cap layer using a wet etch chemistry; The method comprising:

20. 20. The method of claim 19, wherein forming the sacrificial cap layer comprises preferentially depositing on the top of each RMG stack by atomic layer deposition (ALD) using sequential exposures of titanium tetrakis(dimethylamido)titanium (TDMAT) and ozone (O3) at a process pressure between about 1 Torr and about 3 Torr, a substrate temperature between about 100° C. and about 150° C., and a substrate rotation speed between about 10 RPM and about 50 RPM.

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