Sacrificial cap layer for contact etching

Abstract

The method includes providing a substrate having source / drain regions and an etch stop layer over the source / drain regions. A plasma etching process is performed using an etching gas to remove the etch stop layer and form a sacrificial oxide cap layer over the source / drain regions. The sacrificial oxide cap layer is then removed from the source / drain regions.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 195,436, filed June 1, 2021, and U.S. Patent Application No. 17 / 721,620, filed April 15, 2022, which are incorporated by reference in their entireties.

[0002] The present invention relates generally to semiconductor device manufacturing, and more particularly to a method for forming a sacrificial cap layer for contact etching. [Background technology]

[0003] Advances in semiconductor technology depend on continuous improvements in fabrication manufacturing techniques. Semiconductor technology innovations have introduced new types of structures such as FinFET devices and stacked structures (e.g., 3D NAND devices). However, these new structures require new fabrication schemes to overcome traditional manufacturing challenges. For example, contacts can be opened using dry etching processes such as reactive ion etching (RIE) in traditional middle-of-line (MOL) process flows. Often, dry etching processes can be very aggressive to some layers in semiconductor process flows. Typically, dry etching processes have a plasma source that generates a huge number of ions that accelerate to cause ion bombardment against sensitive device layers. As a result, plasma etching processes can cause damage to the underlying materials, which in turn can lead to uncontrollable variations in the electrical performance of the devices, as well as reduced yields. Summary of the Invention [Means for solving the problem]

[0004] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] Aspect (1) provides a method that includes providing a substrate having source / drain regions and an etch stop layer on the source / drain regions. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide cap layer on the source / drain regions. The sacrificial oxide cap layer is then removed from the source / drain regions.

[0006] Example (2) includes the method of example (1), wherein the substrate includes a metal gate stack separated from the source / drain regions by spacers, and the etch stop layer is a conformal layer having a first portion covering the source / drain regions and a second portion covering the spacers and the metal gate stack.

[0007] Example (3) includes the method of example (2), wherein performing the plasma etching process includes completely removing a first portion of the etch stop layer to expose the source / drain regions before completely removing the second portion of the etch stop layer, and a sacrificial oxide cap layer is formed on the exposed source / drain regions during the completely removing the second portion of the etch stop layer.

[0008] Example (4) includes the method of example (1), wherein the source / drain regions include Si, Ge, or both Si and Ge.

[0009] An embodiment (5) includes the method of embodiment (1), wherein performing the plasma etching process comprises: 2 , GeO 2 , or SiGeO x forming a sacrificial oxide cap layer comprising:

[0010] An embodiment (6) includes the method of embodiment (1), wherein the etch stop layer includes a nitride layer.

[0011] An embodiment (7) includes the method of embodiment (1), wherein the etch stop layer includes SiN.

[0012] An embodiment (8) includes the method of embodiment (1), wherein performing the plasma etching process includes using an etching gas that includes a fluorocarbon-containing gas and an oxygen-containing gas.

[0013]

[0023] Example (9) includes the method of example (8), wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

[0014] An embodiment (10) includes the method of embodiment (8), wherein the oxygen-containing gas is O 2 , O 3 , CO, CO 2 , S.O. 2 , or a combination thereof.

[0015] Example (11) includes the method of example (1), wherein removing the sacrificial cap layer includes performing a wet etching process on the substrate.

[0016] Example (12) includes the method of example (1), wherein removing the sacrificial cap layer includes performing a dry etching process on the substrate.

[0017] Another aspect (13) provides a method that includes providing a substrate including source / drain regions and a SiN etch stop layer on the source / drain regions, where the source / drain regions include Si, Ge, or both Si and Ge. A plasma etching process is performed using an etching gas including a fluorocarbon-containing gas and an oxygen-containing gas that removes the SiN etch stop layer and forms a sacrificial oxide cap layer on the source / drain regions. The sacrificial oxide cap layer is removed from the source / drain regions using a wet or dry etching process.

[0018] Example (14) includes the method of example (13), wherein the substrate includes a metal gate stack separated from the source / drain regions by spacers, and the SiN etch stop layer is a conformal layer having a first portion covering the source / drain regions and a second portion covering the spacers and the metal gate stack.

[0019] Example (15) includes the method of example (14), wherein performing the plasma etching process includes completely removing a first portion of the etch stop layer to expose the source / drain regions before completely removing the second portion of the etch stop layer, and a sacrificial oxide cap layer is formed on the exposed source / drain regions during the completely removing the second portion of the etch stop layer.

[0020] Example (16) includes the method of example (13), wherein the sacrificial oxide cap layer is SiO 2 , GeO 2 , or SiGeO x Includes.

[0021]

[0023] Aspect (17) includes the method of aspect (13), wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

[0022] An embodiment (18) includes the method of embodiment (13), wherein the oxygen-containing gas is O 2 , O 3 , CO, CO 2 , S.O. 2 , or a combination thereof.

[0023] Another aspect (19) provides a method that includes providing a substrate including source / drain regions and a SiN etch stop layer on the source / drain regions, the source / drain regions including Si, Ge, or both Si and Ge. A plasma etching process removes the SiN etch stop layer and forms a sacrificial oxide cap layer on the source / drain regions. 3 F gas and O 2The etching is performed using an etching gas containing a sacrificial oxide cap layer, SiO 2 , GeO 2 , or SiGeO x The sacrificial oxide cap layer is removed from the source / drain regions using a wet or dry etching process.

[0024] Example (20) includes the method of example (19), wherein the substrate includes a metal gate stack separated from the source / drain regions by a spacer, and the SiN etch stop layer is a conformal layer having a first portion covering the source / drain regions and a second portion covering the spacer and the metal gate stack. Performing the plasma etch process includes completely removing the first portion of the etch stop layer to expose the source / drain regions before completely removing the second portion of the etch stop layer. A sacrificial oxide cap layer is formed on the exposed source / drain regions during the completely removing the second portion of the etch stop layer.

[0025] It should be noted that this "Summary" section does not specify all embodiments and / or inherently novel aspects of the disclosure or the claimed disclosure. Rather, the "Summary" merely provides a preliminary description of various embodiments and corresponding novelties over the prior art. For additional details and / or anticipated aspects of the disclosure and embodiments, the reader is directed to the "Description of Embodiments" section of the present disclosure and corresponding figures, which are discussed further below.

[0026] Aspects of the present disclosure will be better understood upon review of the following detailed description in conjunction with the accompanying drawings, in which: Note that, according to standard industry practice, various features have not been drawn to scale, and in fact the dimensions of various features may be increased or decreased for clarity of discussion. [Brief description of the drawings]

[0027] [Figure 1A]1 illustrates a cross-sectional view of a fin portion of a semiconductor device during fabrication taken along the direction of the fin. [Figure 1B] 1 illustrates a gate cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention taken along a direction orthogonal to the fin direction. [Figure 1C] 1 illustrates a top view of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 2A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 2B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 3A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 3B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 4A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 4B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 5A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 5B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 6A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 6B] 3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 7A] 4A-4D show fin cross-sectional views of a semiconductor device at subsequent manufacturing stages according to exemplary embodiments of the present disclosure. [Figure 7B]3A-3C show cross-sectional views of a gate of a semiconductor device at a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 8A] 1 shows experimental results of substrate processing according to an embodiment of the present invention compared to conventional methods. [Figure 8B] 1 shows experimental results of substrate processing according to an embodiment of the present invention compared to conventional methods. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact with each other, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not in itself address the relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of explanation, spatially relative terms such as "top," "bottom," "lower," "below," "lower," "lower," "upper," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures: the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0029] As mentioned in the background section above, damage to epitaxial source / drain materials induced by contact open etching is one of the MOL challenges in the fabrication of FinFETs for logic ICs. This type of damage leads to uncontrollable variations in electrical performance within the device. An embodiment of the present invention provides a novel approach to protect the epitaxial source / drain materials from damage by in-situ forming a thin sacrificial cap layer on the epitaxial source / drain materials during the contact open etch. The sacrificial cap layer can then be removed using a mild process that does not damage the epitaxial source / drain materials and provides high etch selectivity between the sacrificial cap layer and the epitaxial source / drain materials.

[0030] The present application discloses a method to prevent damage to semiconductor regions during plasma etching. The proposed integration scheme uses a sacrificial cap layer formed directly on top of the semiconductor region to be protected. This sacrificial cap layer is designed to protect the semiconductor region during the plasma etching process that would otherwise damage the semiconductor region. This sacrificial cap layer can be removed later in the process using a gentle dry or wet cleaning process.

[0031] The embodiments of the present application may be applied to various types of devices such as fin transistors and stacked memory devices.Specific embodiments of the above process are described below.

[0032] Figure 1A shows a partial cross-sectional view of a semiconductor device under fabrication along the direction of the fins, Figure 1B shows a cross-sectional view of the semiconductor device along a direction perpendicular to the direction of the fins, and Figure 1C shows a top view showing section lines 1A-1A and 1B-1B shown in Figure 1A and 1B, respectively, all according to embodiments of the present invention. Figure 1A is a partial cross-sectional view and does not show the underlying fins and substrate.

[0033] 1A-1C, at this stage of processing, semiconductor device 100 has already undergone a substantial portion of front-end-of-line (FEOL) fabrication. For example, as shown in FIG. 1B, a transistor structure having a plurality of fins 109 is formed on a substrate 111.

[0034] In various embodiments, the substrate 111 may include silicon, silicon germanium, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, and others. The substrate 111 may include a semiconductor wafer, which may include a semiconductor epitaxial layer, including a heteroepitaxial layer. For example, in one or more embodiments, one or more heteroepitaxial layers including a compound semiconductor may be formed on a semiconductor substrate. In various embodiments, some or all of the substrate 111 may be amorphous, polycrystalline, or single crystalline. In various embodiments, the substrate 111 may be doped, undoped, or may include both doped and undoped regions.

[0035] The fins 109 may be formed by epitaxial growth from a substrate 111, or alternatively, using an etch-back process that leaves the fins 109. The fins 109 may be separated from one another by shallow isolation regions 112. Thus, the shallow isolation regions 112 and the fins 109 may form an alternating pattern.

[0036] In one embodiment, the shallow isolation regions 112 may be formed by depositing an oxide fill material after patterning the fins 109, which is then planarized using, for example, a chemical mechanical planarization process. After planarization, the shallow isolation regions 112 may be recessed to raise the fins 109.

[0037] The multiple dummy gates 102 are formed over the substrate 111 and the multiple fins 109. In one embodiment, the multiple dummy gates 102 may be formed by patterning a layer of amorphous silicon or polysilicon deposited over the multiple fins 109.

[0038] Next, spacers 101 are formed on the sidewalls of the dummy gates 102. The spacers 101 may be formed by deposition of an insulating layer followed by an anisotropic etching process. For example, a reactive ion etching (RIE) process may be used to form the spacers 101. The material of the insulating layer is selectively etched away during removal of the dummy gates 102 later in the process, e.g., by etching with TMAH or NH 4 It is selected to be impervious to etching by chemicals such as OH, etc. In one example, the spacers 101 can include a low dielectric constant material.

[0039] Epitaxial regions 103 are then grown over portions of the fins 109 located between the dummy gates 102 to form raised source / drain regions. As shown, the upper surfaces of the raised source / drain regions may form facets due to the growth pattern of the corresponding epitaxial material. In some embodiments, the source / drain regions include Si, Ge, or both Si and Ge.

[0040] In one or more embodiments, the epitaxial region 103 may be formed in a single epitaxial growth process. In other embodiments, the growth of the epitaxial region 103 may consist of a multi-step process. For example, the multi-step process may begin with growing an initial epitaxial layer having a first doping on the fins 109 to a predetermined thickness, followed by growing a second layer having a second doping. For example, the second doping may be a higher doping than the first doping. Similarly, the different layers may differ in composition, for example, of germanium or other compounds. The epitaxial growth process may use any type of epitaxial process, including molecular beam epitaxy (MBE), or various types of chemical vapor deposition (CVD).

[0041] In one or more embodiments, the epitaxial region 103 may be grown to introduce strain into the fins 109, for example due to lattice mismatch.

[0042] In one or more embodiments, source / drain (S / D) regions may be formed by doping the fin region and the epitaxial region 103, for example, in an implant / anneal process.

[0043] 2A-2B show cross-sectional views of semiconductor device 100 at subsequent manufacturing stages after forming an etch stop layer (ESL) 105 over semiconductor device 100. Figure 2A shows a cut line similar to Figure 1A, while Figure 2B shows a cut line similar to Figure 1B.

[0044] The ESL 105 may be conformally deposited over the entire wafer surface. In various embodiments, the ESL 105 comprises silicon nitride (SiN) or silicon oxynitride (SiON). In various embodiments, the ESL 105 may have a thickness in the range of 0.5 nm to about 10 nm. In one embodiment, the ESL 105 may have a thickness in the range of 2 nm to about 5 nm.

[0045] 3A-3B show partial cross-sectional views of an in-process semiconductor device 100 after depositing oxide 106, according to an embodiment of the invention. Figure 3A shows a cut line similar to Figure 1A, while Figure 3B shows a cut line similar to Figure 1B.

[0046] 3A and 3B, oxide 106 is filled between the dummy gates 102. The oxide 106 is overfilled above the top surface of the ESL 105 and on top of the dummy gates 102.

[0047] In various embodiments of the semiconductor device 100, the oxide 106 can be a flowable oxide including spin-on glass. In one example, a layer including borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), arsenic silicon glass (ArSG), or other types of glass can be deposited and heated to reflow. In one or more embodiments, the oxide 106 can also include oxides such as tetraethyloxysilane (TEOS), fluorinated TEOS (FTEOS), organosilicate glass (OSG), fluorinated silicate glass (FSG), or spin-on glass (SOG).

[0048] 4A-4B show cross-sectional views of a semiconductor device 100 in fabrication after forming a replacement metal gate (RMG) in accordance with an embodiment of the present invention. Figure 4A shows a cut line similar to Figure 1A, while Figure 4B shows a cut line similar to Figure 1B.

[0049] As shown in Figures 4A and 4B, the oxide 106 is planarized to expose the underlying ESL 105. The ESL 105 may be removed using an anisotropic etching process to expose the dummy gates 102. The dummy gates 102 are then removed using, for example, a wet etching process or alternatively a plasma process. The spacers 101 preserve the shape of the gate stack during the removal of the dummy gates 102. During the etching process, the oxide 106 protects the underlying regions of the epitaxial region 103.

[0050] After removing the dummy gates 102, the inner walls of the spacers 101 are exposed leaving a cavity. The cavity is filled with a replacement gate material 107. After the replacement gate material 107 is in place, a contact cap 108 is formed. The contact cap 108 may be formed using a self-aligned process such that it is selectively formed only on the replacement gate material 107.

[0051] The replacement gate material 107 together with a contact cap 108 form a replacement metal gate (RMG) stack 102'. The RMG stack 102' serves to set the work function of the gate and forms the final gate electrode of the semiconductor device 100.

[0052] 5A-5B show partial cross-sectional views of semiconductor device 100 at a next manufacturing stage after etching oxide 106, in accordance with an embodiment of the present invention. Figure 5A shows a cut line similar to Figure 1A, while Figure 5B shows a cut line similar to Figure 1B.

[0053] As shown in FIG. 5A, etching the oxide 106 leaves behind an empty, unfilled trench or recessed feature. In various embodiments, the oxide etch process can be a wet etch process or a dry etch process such as reactive ion etching (RIE), or any process currently known in the art of semiconductor manufacturing. Etching the oxide 106 exposes the remaining ESL 105 between the spacers 101 that line the replacement gate material 107 and the contact cap 108.

[0054] 6A-6B show partial cross-sectional views of a semiconductor device 100 at a next manufacturing stage after performing an ESL etch process, in accordance with an embodiment of the present invention. Figure 6A shows a cut line similar to Figure 1A, while Figure 6B shows a cut line similar to Figure 1B.

[0055] The ESL etch process includes performing a plasma etch process using an etch gas that removes the ESL 105 and forms a sacrificial oxide cap layer 113 on the source / drain regions. During the plasma etch process, once the ESL 105 is removed to expose the epitaxial region 103, the presence of an oxygen-containing gas in the etch gas reacts with the epitaxial region 103 to form a thin sacrificial cap layer 113 on the epitaxial region 103. The presence of the thin sacrificial cap layer 113 protects the epitaxial region 103 from plasma damage due to other reactive gases in the etch gas. The ESL etch process is performed until the ESL 105 is completely removed from the semiconductor device 100. This requires protection of the epitaxial region 103 by the sacrificial oxide cap layer 113 since the ESL etch process may be performed to remove remaining ESL 105 from regions other than the epitaxial region 103. The sacrificial oxide cap layer 113 is resistant to other reactive gases in the etch gas. Protection of the epitaxial region 103 prevents or reduces material loss, chemical doping, and damage to the bulk crystal structure of the epitaxial region 103. In some embodiments, the sacrificial oxide cap layer 113 is SiO 2 , GeO 2 , or SiGeO x Includes.

[0056] In various embodiments, the sacrificial cap layer 113 may have a thickness ranging from 0.5 nm to about 5 nm on top of the epitaxial region 103. In one embodiment, the sacrificial cap layer 113 may have a thickness ranging from 1 nm to about 3 nm, and may be about 2 nm.

[0057] In various embodiments, the etching gas in the ESL etching process may include a fluorocarbon-containing gas and an oxygen-containing gas. The etching gas may further include argon (Ar) gas as a diluent gas. The fluorocarbon-containing gas may include a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof. The fluorocarbon gas may include C x X ywhere C and X represent carbon and halogen, respectively, and x and y are integers. Hydrofluorocarbon gases have the chemical formula: x X y H z where C, X, and H represent carbon, halogen, and hydrogen, respectively, and x, y, and z are integers. The oxygen-containing gas is, for example, O 2 , O 3 , CO, CO 2 , S.O. 2 , or a combination thereof.

[0058] In one example, the etching gas is CH 3 F, O 2 , and Ar. An exemplary gas flow is about 10-100 sccm of CH 3 F, approximately 10 to 100 sccm O 2 and about 50-200 sccm Ar. In one example, the plasma etch process may be performed in a process chamber including an upper electrode and a lower electrode, the lower electrode supporting a substrate being processed. Exemplary process conditions may include a substrate temperature of about 20-100° C., a gas pressure of about 5-100 mTorr, an RF power of about 50-500 W to the upper electrode, and an RF power of about 50-500 W to the lower electrode.

[0059] 7A-7B show partial cross-sectional views of a semiconductor device 100 at a next manufacturing stage after removing a sacrificial oxide cap layer from the source / drain regions, in accordance with an embodiment of the present invention. Figure 7A shows a cut line similar to Figure 1A, while Figure 7B shows a cut line similar to Figure 1B.

[0060] Removal of the sacrificial cap layer 113 may be performed by an etching process that is efficient and does not damage the epitaxial region 103, such as a dry etch or a wet etch. In one example, a wet etch may include exposing the substrate to dilute hydrofluoric acid (DHF). In one example, a dry etch may include exposing the substrate to HF gas and NH followed by a thermal treatment that desorbs reaction by-products from the substrate. 3This may include a chemical oxide removal process (COR) involving exposure to a gas.

[0061] 8A-8B show experimental results of substrate processing according to an embodiment of the present invention. 3 F, O 2 8A and 8B show transmission electron microscope (TEM) images after removal of the SiN ESL from the SiGe substrate using a plasma-enhanced etching gas containing CH and Ar. Following removal of the SiN ESL, a sacrificial cap layer was formed on the SiGe substrate, comprising SiGeOx, and having a thickness of about 2 nm. The TEM in FIG. 8A clearly shows that the crystal structure of the SiGe substrate is not damaged by the plasma etching process. In contrast, FIG. 8B shows that the TEM image of the SiGe substrate is obtained by etching the SiGe substrate using a plasma-enhanced etching gas containing CH and Ar. 3 F, H 2 8A-8B show TEM images after removal of the SiN ESL from a SiGe substrate using a plasma-enhanced etching gas containing Ar and Ar. Due to the absence of oxygen-containing gas in the etching gas, no sacrificial cap layer was formed on the SiGe substrate following removal of the SiN ESL. The TEM in FIG. 8B clearly shows that the crystalline structure of the SiGe substrate is severely damaged by the plasma etching process. Chemical analysis further shows high levels of hydrogen incorporation in the SiGe substrate. Thus, the results in FIGS. 8A-8B clearly show how a sacrificial cap layer can protect the crystalline structure of a SiGe substrate in a semiconductor device.

[0062] In the above description, specific details have been described, such as the specific geometry of the processing system and a description of the various components and processes used. However, it should be understood that the techniques herein may be implemented in other embodiments that differ from these specific details, and that such details are for illustrative purposes and are not intended to be limiting. Several embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific numbers, materials, and configurations have been shown to ensure understanding. However, several embodiments may be implemented without such specific details. Elements having substantially the same functional structure are indicated with similar reference numerals, and redundant descriptions may be omitted.

[0063] To facilitate understanding of various embodiments, various techniques have been described as multiple operations. The order of description should not be construed as though the operations are necessarily order dependent. In fact, the operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0064] As used herein, "substrate" or "wafer" generally refers to an object that is processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, such as a base substrate structure, such as a semiconductor wafer, a reticle, or a layer that rests or overlies a base substrate structure, such as a thin film. Thus, substrate is not limited to any particular base structure, patterned or unpatterned underlying or overlying layer, but is intended to include any such layer or base structure, and any combination of multiple layers and / or base structures. Although the description herein may refer to a particular type of substrate, this is for illustrative purposes only.

[0065] Those skilled in the art will also appreciate that many variations may be made in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Thus, the above description of the embodiments of the present invention is not intended to be limiting. Rather, limitations to the embodiments of the present invention are set forth in the following claims.

Claims

1. A method for fabricating a semiconductor device comprising the steps of: providing a substrate including epitaxial source / drain regions and an etch stop layer on the epitaxial source / drain regions; performing a plasma etching process using an etching gas that removes the etch stop layer and forms a sacrificial oxide cap layer on the epitaxial source / drain regions; removing the sacrificial oxide cap layer from the epitaxial source / drain regions using an etching process, wherein the epitaxial source / drain regions underneath the sacrificial oxide cap layer are not damaged; The method comprising:

2. the substrate includes a metal gate stack separated from the source / drain regions by spacers; 2. The method of claim 1, wherein the etch stop layer is a conformal layer having a first portion covering the epitaxial source / drain regions and a second portion covering the spacers and the metal gate stack.

3. The step of performing the plasma etching process includes: completely removing the first portion of the etch stop layer to expose the epitaxial source / drain regions before completely removing the second portion of the etch stop layer; forming the sacrificial oxide cap layer on the exposed epitaxial source / drain regions while completely removing the second portion of the etch stop layer; The method of claim 2, comprising:

4. The method of claim 1 , wherein the epitaxial source / drain regions comprise Si, Ge, or both Si and Ge.

5. The step of performing the plasma etching process includes ２ , GeO ２ , or SiGeO ｘ The method of claim 1 , further comprising forming a sacrificial oxide cap layer comprising:

6. The method of claim 1 , wherein the etch stop layer comprises a nitride layer.

7. The method of claim 1 , wherein the etch stop layer comprises SiN.

8. 10. The method of claim 1, wherein performing the plasma etching process comprises using an etching gas that includes a fluorocarbon-containing gas and an oxygen-containing gas.

9. The method of claim 8 , wherein the fluorocarbon-containing gas comprises a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

10. The oxygen-containing gas is O ２ , O ３ , CO, CO ２ , S.O. ２ or a combination thereof.

11. The method of claim 1 , wherein removing the sacrificial oxide cap layer comprises performing a wet etching process on the substrate.

12. The method of claim 1 , wherein removing the sacrificial oxide cap layer comprises performing a dry etching process on the substrate.

13. A method for fabricating a semiconductor device comprising: providing a substrate comprising epitaxial source / drain regions and a SiN etch stop layer on the epitaxial source / drain regions, the epitaxial source / drain regions comprising Si, Ge, or both Si and Ge; performing a plasma etch process with an etching gas, the etching gas including a fluorocarbon-containing gas and an oxygen-containing gas, to remove the SiN etch stop layer and form a sacrificial oxide cap layer on the epitaxial source / drain regions; removing the sacrificial oxide cap layer from the epitaxial source / drain regions using a wet or dry etching process, wherein the epitaxial source / drain regions underneath the sacrificial oxide cap layer are not damaged; The method comprising:

14. the substrate includes a metal gate stack separated from the epitaxial source / drain regions by spacers; 14. The method of claim 13, wherein the SiN etch stop layer is a conformal layer having a first portion covering the epitaxial source / drain regions and a second portion covering the spacers and the metal gate stack.

15. performing the plasma etching process includes completely removing the first portion of the etch stop layer to expose the epitaxial source / drain regions before completely removing the second portion of the etch stop layer; forming the sacrificial oxide cap layer on the exposed epitaxial source / drain regions while completely removing the second portion of the etch stop layer; 15. The method of claim 14, comprising:

16. The sacrificial oxide cap layer is made of SiO ２ , GeO ２ , or SiGeO ｘ The method of claim 13, comprising:

17. The method of claim 13 , wherein the fluorocarbon-containing gas comprises a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

18. The oxygen-containing gas is O ２ , O ３ , CO, CO ２ , S.O. ２ or a combination thereof.

19. A method for fabricating a semiconductor device comprising: providing a substrate comprising epitaxial source / drain regions and a SiN etch stop layer on the epitaxial source / drain regions, the epitaxial source / drain regions comprising Si, Ge, or both Si and Ge; CH ３ F gas and O ２ performing a plasma etch process using an etch gas containing a gas comprising a SiO 2 gas, the SiN etch stop layer being removed and a sacrificial oxide cap layer being formed on the epitaxial source / drain regions, the sacrificial oxide cap layer being formed on the epitaxial source / drain regions; ２ , GeO ２ , or SiGeO ｘ and removing the sacrificial oxide cap layer from the epitaxial source / drain regions using a wet or dry etching process, wherein the epitaxial source / drain regions underneath the sacrificial oxide cap layer are not damaged; The method comprising:

20. the substrate includes a metal gate stack separated from the epitaxial source / drain regions by spacers; the SiN etch stop layer is a conformal layer having a first portion covering the epitaxial source / drain regions and a second portion covering the spacers and the metal gate stack; The step of performing the plasma etching process includes: completely removing the first portion of the etch stop layer to expose the epitaxial source / drain regions before completely removing the second portion of the etch stop layer; forming the sacrificial oxide cap layer on the exposed epitaxial source / drain regions while completely removing the second portion of the etch stop layer; 20. The method of claim 19, having the following structure:

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