Metal-insulator-metal capacitor with top contact - Patents.com

Abstract

An example of a device and method of fabricating the device is disclosed that includes a first top contact, a second top contact adjacent to the first top contact, a first mesa disposed below the first top contact, and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and is electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and is electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and is electrically coupled to the first top contact.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices including capacitors, and more particularly, but not by way of limitation, to metal-insulator-metal (MIM) capacitors and techniques for fabricating the same. [Background technology]

[0002]

[0002] High performance computing (HPC) processors, such as those for artificial intelligence (AI), are large and use capacitors for power decoupling to improve power IR drop for high performance high frequency computations. Multiple plate MIM capacitors can be used to decouple power supply lines (Vdd) and improve processor performance. MIM capacitors may also have other applications. However, conventional MIM capacitors may provide insufficient decoupling performance for HPC processors and other high performance systems.

[0003]

[0003] Therefore, there is a need for systems, devices, and methods that overcome the shortcomings of conventional capacitor configurations, including the methods, systems, and devices provided herein. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should the following summary be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope related to any particular aspect and / or example. As such, the following summary is intended only to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0005]

[0005] In accordance with various aspects disclosed herein, at least one aspect includes an apparatus including a first top contact, a second top contact adjacent to the first top contact, a first mesa disposed below the first top contact, a second mesa disposed below the second top contact, a first plate of a metal-insulator-metal (MIM) capacitor disposed below the first top contact and electrically coupled to the first top contact, a first insulator of the MIM capacitor disposed on the first plate, a second plate of the MIM capacitor disposed on the first insulator and electrically coupled to the second top contact, a second insulator of the MIM capacitor disposed on the second plate, and a third plate of the MIM capacitor disposed on the second insulator and electrically coupled to the first top contact.

[0006] According to various aspects disclosed herein, at least one aspect includes a method of manufacturing a device, the method including forming a first mesa, forming a second mesa adjacent to the first mesa, depositing a first plate of a metal-insulator-metal (MIM) capacitor between the first mesa and the second mesa, a portion of the first plate extending to the first mesa, depositing a first insulator of the MIM capacitor on the first plate, a portion of the first insulator extending to the first mesa and the second mesa, depositing a second plate of the MIM capacitor on the first insulator between the first mesa and the second mesa, a portion of the second plate extending to the second mesa, and depositing a second insulator of the MIM capacitor on the second plate. depositing a first top contact, wherein the first mesa is disposed below the first contact, and the first and second plates are electrically coupled to the first top contact; and forming a second top contact, wherein the second mesa is disposed below the second contact, and the second plate is electrically coupled to the second contact.

[0007]

[0007] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one of ordinary skill in the art based on the accompanying drawings and detailed description. [Brief description of the drawings]

[0008]

[0008] A more complete appreciation of the same will be readily obtained as many of the aspects and attendant advantages of the present disclosure will become better understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure. [Figure 1]

[0009] 1 illustrates a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Diagram 2]

[0010] 1 illustrates a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3A]

[0011] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3B] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3C] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3D] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3E] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3F] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3G] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3H] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3I] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3J] 1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 3K]1 illustrates a portion of a process for manufacturing a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 4]

[0012] FIG. 1 illustrates a top view of a device including a MIM capacitor in accordance with one or more embodiments of the present disclosure. [Diagram 5]

[0013] 1 illustrates a portion of a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 6]

[0014] 1 illustrates a portion of a device including a MIM capacitor according to one or more embodiments of the present disclosure. [Figure 7]

[0015] 1 illustrates a mobile device in accordance with at least one aspect of the present disclosure. [Figure 8]

[0016] 1 illustrates various electronic devices in which one or more aspects of the present disclosure may be utilized. [Figure 9]

[0017] 1 shows a flow chart for manufacturing a device including a MIM capacitor in accordance with one or more embodiments of the present disclosure.

[0009]

[0018] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. According to common practice, features illustrated by the drawings may not be drawn to scale. Thus, dimensions of illustrated features may be arbitrarily expanded or reduced for clarity. According to common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not show all components of a particular apparatus or method. Moreover, like reference numerals refer to like features throughout the specification and figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0019] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific aspects. Alternative aspects may be devised without departing from the scope of the teachings in the present disclosure. In addition, well-known elements of exemplary aspects of the present disclosure may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0011]

[0020] In some described exemplary implementations, examples are identified in which some of the various component structures and operations are derived from known conventional techniques and configured in accordance with one or more exemplary aspects. In such examples, some internal details of the known conventional component structures and / or operations may be omitted to help avoid potential ambiguity of the concepts illustrated in the exemplary aspects disclosed herein.

[0012]

[0021] Additionally, it should be noted that terms or phrases such as "lower", "upper", "left", "right", "bottom", "upper", "horizontal", "vertical", "top", "bottom", "side", "sidewall", etc. are used for convenience. Unless otherwise specified, such terms / phrases are not intended to indicate an absolute orientation or direction. Also, as indicated, the terms "on" and "in contact" may be used synonymously unless specifically indicated otherwise.

[0013]

[0022] The terms used herein are for the purpose of describing particular aspects only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further to be understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014]

[0023] As explained in the background, in high performance computing integrated circuit (IC) designs, large size decoupling capacitors can be used for VDD decoupling to reduce the IR drop from the front side. Furthermore, top metal layer (TME) MIM capacitors have lower power decoupling effectiveness and larger IR drop.

[0015]

[0024] IC level power distribution network (PDN) IR drop from the front side of the BEOL presents an additional problem for IC scaling of 5 nm technology. As technology scaling continues to reduce area and improve performance, PDN IR drop reduces performance improvement from reduced scale technology. Current process integration techniques do not allow for improved PDN IR drop as technology scales. High density MIM caps with multi-plate (e.g., 3-4 plate) configurations are beneficial for decoupling, but these configurations can present increased process challenges during manufacturing. Various aspects disclosed and described in further detail herein provide MIM capacitors and manufacturing processes to facilitate the fabrication of multi-plate MIM capacitors with no limitations on the number of MIM metal plates. Metal and via processes are compatible with conventional metal modules.

[0016]

[0025] FIG. 1 illustrates a partial cross-sectional view of a device 100 including a multi-plate MIM capacitor 150 according to one or more embodiments of the present disclosure. In some embodiments, the device 100 may be a die, an integrated circuit, a package, or the like. It is further understood that the device 100 may include multiple components in an integrated device, only some of which are shown. As illustrated, the device 100 may include a first intermetal dielectric (IMD) layer 130 and a second IMD layer 135, each of which may include one or more layers of dielectric material. The first IMD layer 130 is disposed on a first metal layer Mx. The second metal layer Mx+1 is at least partially embedded in the second IMD layer 135 with one or more vias 165 or partial vias 115 and 125. The second IMD layer 135 may have a top contact formed in the Mx+1 metal layer, such as a first top contact 110 and a second top contact 120. The first top contact 110 may be coupled to a first partial via 115 to facilitate electrical connection to a first plate 152 of the MIM capacitor 150 and a third plate 156 of the MIM capacitor 150. The first partial via 115 may be disposed on a first mesa 131 formed in the first IMD layer 130. In some aspects, the first mesa 131 may be formed as a conical structure with tapered sides such that it has a generally circular shape when viewed from a top view. In some aspects, the second top contact 120 may have a similar structure to the first top contact 110. The second top contact 120 may be coupled to a second partial via 125 to facilitate electrical connection to a second plate 154 of the MIM capacitor 150. The second partial via 125 may be disposed on a second mesa 132 formed in the first IMD layer 130. In some embodiments, the second mesa 132 may be formed as a conical structure with tapered sides such that it has a generally circular shape when viewed from a top view. It will be understood that the various disclosed embodiments are not limited to this exemplary configuration and can include other geometric shapes. For example, the first mesa 131 and / or the second mesa 132 may have a trapezoidal, rectangular, square, elliptical, etc. top view of the corresponding structures forming the first mesa 131 and / or the second mesa.

[0017]

[0026] The multi-plate MIM capacitor 150 is shown in a three-plate configuration, including a second plate 154 separated from a first plate 152 by a first insulator 153 of the MIM capacitor 150. The second plate 154 is separated from a third plate 156 by a second insulator 155. As explained above, the first plate 152 and the third plate 156 are coupled to the first top contact 110 and the second plate 154 is coupled to the second top contact 120, which allows both connections to the MIM capacitor 150 to be located on the same side. Furthermore, in some aspects, the first plate 152, the first insulator 153, the second plate 154, the second insulator 155, and the third plate 156 may extend beyond the top contacts 110 and 220 and even beyond the via 165. Other configurations are described herein. Thus, the various disclosed aspects are not limited to the exemplary configurations shown.

[0018]

[0027] The second IMD layer 135 may have additional structures formed from the Mx+1 metal layer, such as metal trace 160, which may be coupled to metal trace 140 formed in metal layer Mx using via 165. Metal traces 140 and 160 and via 165 may be coupled to positive potentials, ground potentials, digital signals, analog signals, or any other suitable signals for routing within device 100.

[0019]

[0028] Further, in some embodiments, additional separate MIM capacitors are formed. For example, MIM capacitor 170 may be coupled to first top contact 110. Similarly, MIM capacitor 180 may be coupled to second top contact 120. In configurations with MIM capacitor 180, there will be physical plate separation (due to plate patterning) in the area below 125 or 115 (not shown in FIG. 1, but see, for example, the exemplary configurations partially shown in FIGS. 5 and 6). In this optional embodiment, it will be understood that another top contact (not shown) may be adjacent to top contact 110 and coupled to the plate of MIM capacitor 170. Similarly, yet another top contact (not shown) may be adjacent to the second top contact (but not visible in the cross-sectional view) and coupled to the top and bottom plates of MIM capacitor 180. In further embodiments, one or both of the other contacts may be located in another metal layer different from Mx metal layer or Mx+1. Thus, it is possible for some portions of the MIM capacitor to have top contacts on the same metal layer and other portions to have contacts on a different metal layer.

[0020]

[0029] It will be appreciated that the various plates (e.g., 152, 154, and 156) and other metal layers and structures (e.g., 110, 115, 120, 125, 140, 160, and 165) may be any highly conductive material, such as copper (Cu), aluminum (AL), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), tungsten (W), ruthenium (Ru), cobalt (Co), alloys, or combinations thereof. It will be appreciated that in some embodiments, the Mx and Mx+1 metals may be different. The insulators (e.g., 153 and 155) may be a high dielectric constant (high-k) material, such as hafnium oxide (HfOx) or a similar material. The first IMD layer 130 and the second IMD layer 135 may each be a low-k material such as doped silicon dioxide (SiO2) or its fluorine-doped, carbon-doped, and carbon-doped forms, as well as spin-on organic polymer dielectrics such as polyimide (PI), benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), and / or silicone-based polymer dielectrics. It will be understood that the illustrated configurations and example materials are provided merely to aid in the explanation of various aspects and should not be construed as limiting the various aspects disclosed. For example, although a three-plate configuration is shown, various aspects of the present disclosure allow for four or more plates in the MIM capacitor.

[0021]

[0030] In some aspects of the disclosure, the first top contact 110 may be coupled to a first power connection that may be coupled to a power source (not shown). The second top contact 120 may be coupled to a second power connection that may be coupled to a power source. In some aspects, the power source may be located remotely from the first and second power connections. In some aspects, the power source may be local to the first and second power connections or may be in direct contact with the first and second power connections. In some aspects, the first power connection may be configured to be at a positive potential (e.g., Vdd). The second power connection may be configured to be at a negative potential (e.g., Vss) or ground. In other aspects, these may be reversed, such that the first power connection is configured to be at Vss or ground and the second power connection is configured to be at Vdd. The first power connection and the second power connection may be formed, at least in part, from portions of metal layer Mx+1 or may be coupled to the top contact using a via that couples the top contact to another metal layer. It will be appreciated that having the MIM capacitor in close proximity to the power input provides improved decoupling and performance of the power distribution network. It will be appreciated that the various aspects disclosed herein are not limited to decoupling capacitor applications and may be used in any conventional capacitor application.

[0022]

[0031] FIG. 2 illustrates a partial cross-sectional view of a device 200 including a multi-plate MIM capacitor 250 according to one or more embodiments of the present disclosure. In some embodiments, the device 200 may be a die, an integrated circuit, a package, or the like. It will be further understood that the device 200 may include multiple components in an integrated device, only some of which are shown. As illustrated, the device 200 may include a first intermetal dielectric (IMD) layer 230 and a second IMD layer 235, each of which may include one or more layers of dielectric material. The first IMD layer 230 is disposed on a first metal layer Mx. The second metal layer Mx+1 is at least partially embedded in the second IMD layer 235 with one or more vias 265. The second IMD layer 235 may have MIM capacitor top contacts formed in the Mx+1 metal layer, such as the first top contact 210 and the second top contact 220. The first top contact 210 may be directly coupled to the first plate 252 of the MIM capacitor 250 and the third plate 256 of the MIM capacitor 250. The top contact 210 may be disposed on a first mesa 231 formed in the second IMD layer 235. In some aspects, the first mesa 231 may be formed as a cone structure with tapered sides such that it has an approximately circular shape when viewed from a top view. In some aspects, the second top contact 220 may have a similar structure to the first top contact 210. The second top contact 220 may be coupled to the second plate 254 of the MIM capacitor 250. The second top contact 220 may be disposed on a second mesa 232 formed in the second IMD layer 235. In some aspects, the second mesa 232 may be formed as a cone structure with tapered sides such that it has an approximately circular shape when viewed from a top view.

[0023]

[0032] The multi-plate MIM capacitor 250 is shown in a three-plate configuration, including a second plate 254 separated from a first plate 252 by a first insulator 253 of the MIM capacitor 250. The second plate 254 is separated from a third plate 256 by a second insulator 255. As explained above, the first plate 252 and the third plate 256 are coupled to the first top contact 210 and the second plate 254 is coupled to the second top contact 220, which allows both connections to the MIM capacitor 250 to be located on the same side. Furthermore, in some aspects, the first plate 252, the first insulator 253, the second plate 254, the second insulator 255, and the third plate 256 may extend beyond the top contacts 210 and 220 and even beyond the via 265. Other configurations are described herein. Thus, the various disclosed aspects are not limited to the exemplary configurations shown.

[0024]

[0033] The second IMD layer 235 may have additional structures formed from the Mx+1 metal layer, such as metal trace 260, which may be coupled to metal trace 240 formed in metal layer Mx using via 265. Metal traces 240 and 260 and via 265 may be coupled to positive potentials, ground potentials, digital signals, analog signals, or any other suitable signals for routing within device 200.

[0025]

[0034] Further, in some embodiments, additional separate MIM capacitors are formed. For example, any MIM capacitor 270 may be coupled to the first top contact 210. Similarly, any MIM capacitor 280 may be coupled to the second top contact 120. An exemplary configuration is partially shown in FIG. 5. It will be appreciated that another top contact (not shown) may be adjacent to the top contact 210 and coupled to the center plate of the MIM capacitor 270. Similarly, yet another top contact (not shown) may be adjacent to the second top contact 220 (but not visible in the cross-sectional view) and coupled to the top and bottom plates of the MIM capacitor 280. In further embodiments, one or both of the other contacts may be disposed in another metal layer different from the Mx metal layer or Mx+1. Thus, it is possible for some of the MIM capacitors to have top contacts on the same metal layer and other portions to have contacts on different metal layers.

[0026]

[0035] It will be appreciated that the various plates (e.g., 252, 254, and 256) and other metal layers and structures (e.g., 210, 215, 220, 225, 240, 260, and 265) may be any highly conductive material, such as copper (Cu), aluminum (AL), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), alloys, or combinations thereof. The insulators (e.g., 253 and 255) may be high-dielectric constant (high-k) materials. The first IMD layer 230 and the second IMD layer 235 may each be a low-dielectric constant (low-k) material, such as doped silicon dioxide (SiO2), or its fluorine-doped, carbon-doped, and carbon-doped forms, as well as spin-on organic polymer dielectrics, such as polyimide (PI), benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), and / or silicone-based polymer dielectrics. It will be understood that the illustrated configurations and example materials are provided merely to aid in the explanation of the various aspects and should not be construed as limiting the various aspects disclosed. For example, while a three-plate configuration is shown, various aspects of the present disclosure allow for four or more plates in a MIM capacitor.

[0027]

[0036] In accordance with various embodiments disclosed herein, at least one embodiment includes an apparatus including a multi-plate MIM capacitor (e.g., 150, 250). The apparatus includes a first top contact (110, 210), a second top contact (120, 220) adjacent to the first top contact, a first plate (152, 252) of the metal-insulator-metal (MIM) capacitor (150, 250) disposed below the first top contact and electrically coupled to the first top contact, a first insulator (153, 253) of the MIM capacitor (150, 250) disposed on the first plate (152, 252), and a first insulator (153, 253) of the MIM capacitor (150, 250). a second plate (154, 254) of the MIM capacitor disposed on the insulator (153, 253) and electrically coupled to the second top contact (120, 220); a second insulator (155, 255) of the MIM capacitor disposed on the second plate (154, 254); and a third plate (156, 256) of the MIM capacitor (150, 250) disposed on the second insulator and electrically coupled to the first top contact (110, 210). It will be appreciated that the various disclosed aspects provide various technical advantages. For example, in at least some aspects, having both MIM contacts adjacent and on the same side allows for improved manufacturing and is compatible with standard metal and via processes. Other technical advantages may be recognized from the various aspects disclosed herein, and these technical advantages are provided merely by way of example and should not be construed as limiting any of the various aspects disclosed herein.

[0028]

[0037] Other embodiments of this aspect include one or more of the following features: The device may include a first mesa (131, 231) disposed below the first top contact and a second mesa (132, 232) disposed below the second top contact. In some aspects, the device may include a first partial via (115) disposed between the first top contact (110) and the first mesa, where the first plate and the third plate may be electrically coupled to the first top contact (110) through the first partial via (115), and a second partial via (125) disposed between the second top contact (120) and the second mesa (132), where the second plate (154) is electrically coupled to the second top contact (120) through the second partial via. In another aspect, the first top contact (210) is disposed directly on the first mesa (231) and the second top contact (220) is disposed directly on the second mesa (232). The first top contact (110, 220) and the second top contact (120, 220) are at least partially disposed in the second IMD layer (135, 235). The first top contact (110, 210) and the second top contact (120, 220) are in the same metal layer (Mx+1) in the second IMD layer (135, 235). The first IMD layer (130, 230) is disposed on the lower metal layer (Mx). Additional aspects will be understood from the various aspects disclosed herein.

[0029]

[0038] A method of manufacture is presented to fully explain the design aspects of the present disclosure. Other methods of manufacture are possible, and the described method of manufacture is presented only to aid in understanding the concepts disclosed herein.

[0030]

[0039] 3A-3K illustrate exemplary portions of manufacturing a device 300, such as the device shown in Figures 1 and 2, in accordance with one or more embodiments of the present disclosure. Figures 3A-3K generally illustrate cross-sectional views at various stages of manufacturing.

[0031]

[0040] 3A illustrates a portion of a manufacturing process for a device 300 according to one or more embodiments of the present disclosure. As shown in FIG. 3A, the process can begin with an intermetal dielectric (IMD) layer 330 being deposited on a metal layer Mx.

[0032]

[0041] 3B illustrates a portion of a manufacturing process for the device 300 according to one or more embodiments of the present disclosure. As shown in FIG. 3B, the process can continue with an IMD layer 330 deposited on the metal layer Mx. In this portion, the IMD layer 330 is patterned and etched to form a first mesa 331 and a second mesa 332. In some embodiments, the IMD layer 330 may be formed by depositing one layer having a thickness equal to or greater than the height of the first mesa 331 and the second mesa 332. In alternative embodiments, the IMD layer 330 may be formed by depositing two or more layers, which may then be patterned and etched to form the first mesa 331 and the second mesa 332.

[0033]

[0042] FIG. 3C illustrates a portion of a fabrication process for the device 300 according to one or more aspects of the present disclosure. As shown in FIG. 3B, the process can continue with an IMD layer 330 being deposited on the metal layer Mx, forming a first mesa 331 and a second mesa 332. In this portion, a first metal 381 (not fully formed) for the MIM capacitor 350 is deposited on the IMD 330, including the first mesa 331 and the second mesa 332. The first metal 381 is patterned and etched, and a portion is used to form a first plate 352, which is still connected to another portion of the first metal 381. In some aspects, the first plate 352 and the MIM capacitor 350 can extend beyond the MIM capacitor 350 node region (e.g., to the opposite side of the first mesa 331). Further, as shown, the first metal 381 extends over the first mesa 331 but is removed from the second mesa 332. It will be appreciated that in some aspects, other plates for other MIM capacitors may be formed from the first metal 381 at this point if additional MIM capacitors are present. Further, in some aspects, the first metal 381 may be patterned to form other metal structures. Similarly, it will be appreciated that the fabrication process may proceed simultaneously for the node region (e.g., the region where the top contact of the MIM capacitor 350 is formed) and the regular via region of the MIM capacitor 350.

[0034]

[0043] FIG. 3D illustrates a portion of a fabrication process for a device 300 according to one or more embodiments of the present disclosure. As illustrated in FIG. 3D, the process can continue with an IMD layer 330 being deposited on the metal layer Mx, a first mesa 331 and a second mesa 332 being formed, and a first metal 381 being deposited. In this portion, a first insulator layer 391 (e.g., a high-k dielectric) for the MIM capacitor 350 is deposited on the first metal 381 and IMD 330, including the first mesa 331 and the second mesa 332. In some embodiments, the first insulator 353 is formed from a portion of the first insulator layer 391. It will be appreciated that in some embodiments, the various insulator (dielectric) layers (e.g., 391) and metal layers (e.g., 381) are formed by conformal deposition. Thus, the surface profile of the next layer generally follows the surface profile of the previous layer. For ease of illustration, the various surface profiles are illustrated as simple geometric shapes. However, these examples should not be construed as limiting the various embodiments disclosed herein. Moreover, it will be understood that the illustrated embodiments represent only a portion of the structure.

[0035]

[0044] FIG. 3E illustrates a portion of a manufacturing process of the device 300 according to one or more aspects of the present disclosure. As illustrated in FIG. 3E, the process can continue with the IMD layer 330 being deposited on the metal layer Mx, forming the first mesa 331 and the second mesa 332. Further, the first metal 381 and the first insulator layer 391 are deposited. In this portion, the second metal 382 (not fully formed) for the MIM capacitor 350 is deposited on the first insulator layer 391, including on the first mesa 331 and the second mesa 332. The second metal 382 is patterned and etched, and a portion is used to form the second plate 354, which is still connected to the other portion of the second metal 382. Further, as illustrated, the second metal 382 extends onto the second mesa 332, but is removed from the first mesa 331. It will be appreciated that in some aspects, if additional MIM capacitors are present, other plates for the other MIM capacitors may be formed from the second metal 382 at this point.

[0036]

[0045] FIG. 3F illustrates a portion of a manufacturing process for the device 300 according to one or more embodiments of the present disclosure. As shown in FIG. 3D, the process can continue with an IMD layer 330 being deposited on the metal layer Mx, forming a first mesa 331 and a second mesa 332. Further, a first metal 381, a first insulator layer 391, and a second metal 382 are deposited. In this portion, a second insulator layer 392 (e.g., a high-k dielectric) for the MIM capacitor 350 is deposited on the second metal 382, ​​and an exposed portion of the first insulator layer 391 is deposited on the IMD layer 330, including the first mesa 331 and the second mesa 332. In some embodiments, a second insulator 355 is formed from a portion of the second insulator layer 392. In other aspects, the second insulator layer 392 forms a second insulator and / or other insulator structures that may extend beyond the node region of the MIM capacitor 350. Additionally, it will be appreciated that sections of the diagram where the first insulator layer 391 and the second insulator 392 overlap may be referred to as 391+392, as these portions may be represented as a common insulator element for convenience of explanation.

[0037]

[0046] FIG. 3G illustrates a portion of a fabrication process for device 300 according to one or more embodiments of the present disclosure. As shown in FIG. 3G, the process can continue with an IMD layer 330 being deposited on metal layer Mx to form first mesa 331 and second mesa 332. Further, a first metal 381, a first insulator layer 391, a second metal 382, ​​and a second insulator layer 392 are deposited. In the illustrated embodiment, when first insulator layer 391 and second insulator layer 392 overlap, these sections may be referred to as 391+392. In this portion of the process, a third metal 383 for MIM capacitor 350 is deposited on second insulator layer 392, including on first mesa 331 and second mesa 332. The third metal 383 is patterned and etched, with a portion used to form the second plate 355, which is still connected to another portion of the third metal 383. Additionally, as shown, the third metal 383 extends over the first mesa 331, but is removed from the second mesa 332. It will be appreciated that in some aspects, other plates for other MIM capacitors may be formed from the third metal 383 at this point, if additional MIM capacitors are present.

[0038]

[0047] 3H illustrates a portion of a manufacturing process of the device 300 according to one or more embodiments of the present disclosure. As shown in FIG. 3H, the process can continue with an IMD layer 330 being deposited on the metal layer Mx to form a first mesa 331 and a second mesa 332. Further, a first metal 381, a first insulator layer 391, a second metal 382, ​​a second insulator layer 392, and a third metal 383 are deposited. In this portion, a second IMD layer 335 is deposited on the exposed portions of the third metal 383 and the second insulator layer 392. A chemical mechanical polishing (CMP) is performed to remove excess material and planarize the top surfaces of the first mesa and the second mesa with the rest of the device 300. As shown, the extensions of the first plate 352 and the third plate 356, along with the combined first insulator 353 and second insulator 355, are exposed adjacent to the top of the first mesa 331. The first plate 352 and the third plate 356 are separated by the first insulator 353 and the second insulator 355 at the first mesa 331. Additionally, the extension of the second plate 354 is exposed adjacent to the top of the second mesa 332. The extension of the second plate 354 is disposed between the first insulator 353 and the second insulator 355 at the second mesa 332.

[0039]

[0048] FIG. 3I illustrates a top view of a portion of the device 300 during a portion of the fabrication process illustrated in FIG. 3H, according to one or more embodiments of the present disclosure. As illustrated in FIG. 3I, the first plate 352 and the third plate 356 are exposed on the sidewall adjacent to the top of the first mesa 331. The first plate 352 and the third plate 356 are separated by the first insulator 353 and the second insulator 355 at the exposed top of the first mesa 331. The second plate 354 is exposed on the sidewall adjacent to the exposed top of the second mesa 332. The second plate 354 is exposed on the sidewall adjacent to the exposed top of the second mesa 332 and is disposed between the adjacent first insulator 353 and second insulator 355. In some aspects, the top cross-sections of first mesa 331 and second mesa 332 may have a generally circular shape, although it will be understood that the cross-sections of first mesa 331 and second mesa 332 are not limited to a circular shape and any geometric configuration may be used for first mesa 331 and / or second mesa 332. For example, the mesas may have an oval, square, or rectangular cross-section when viewed from above.

[0040]

[0049] FIG. 3J illustrates a portion of a manufacturing process for a device 300 according to one or more embodiments of the present disclosure. As illustrated in FIG. 3J, the process can continue from FIG. 3H. In some embodiments, the device 300 can be a die, an integrated circuit, a package, or the like. It will be further understood that the device 300 can include multiple components in an integrated device, only some of which are shown. As illustrated, the device 300 can include a first IMD layer 330, which can include one or more layers of a dielectric material. The first IMD layer 330 is disposed on a first metal layer Mx. In this portion of the process, a partial via 315 is deposited on the first mesa 331, thereby allowing the partial via 315 to electrically contact the first plate 352 and the third plate 356. A partial via 325 is deposited on the second mesa 332, thereby allowing the partial via 325 to electrically contact the second plate 354. Further, a via 365 is formed to electrically contact the metal trace 340 in the Mx metal layer. Further, a second metal layer Mx+1 is deposited over the partial vias 315 and 325, the via 365, and the exposed portion of the second IMD 335. The second metal layer Mx+1 is patterned and etched to form a first top contact 310, a second top contact 320, and a metal trace 360. The first top contact 310 is electrically coupled to the first plate 352 and the third plate 356 through the partial via 315. The second top contact 320 is electrically coupled to the second plate 354 through the partial via 325. One or more additional layers can be added to the second IMD layer 335, thereby allowing the first top contact 310, the second top contact 320, and the metal trace 360 ​​to be at least partially embedded in the second IMD layer 335 along with the via 365 and the partial vias 315 and 325.

[0041]

[0050] It will thus be appreciated that device 300 is similar to device 100 described above. Second IMD layer 335 has top contacts formed in the Mx+1 metal layer, such as first top contact 310 and second top contact 320. First top contact 310 may be coupled to first partial via 315 to facilitate electrical connection to first plate 352 of MIM capacitor 350 and third plate 356 of MIM capacitor 350. First partial via 315 may be disposed on first mesa 331 formed in first IMD layer 330. In some aspects, first mesa 331 may be formed as a conical structure with tapered sides such that it has a generally circular shape when viewed from a top view. In some aspects, second top contact 320 may have a structure similar to first top contact 310. The second top contact 320 may be coupled to a second partial via 325 to facilitate electrical connection to a second plate 354 of the MIM capacitor 350. The second partial via 325 may be disposed on a second mesa 332 formed in the first IMD layer 330. In some aspects, the second mesa 332 may be formed as a conical structure with tapered sides such that it has a generally circular shape when viewed from a top view.

[0042]

[0051] The multi-plate MIM capacitor 350 is shown in a three-plate configuration and includes a second plate 354 separated from a first plate 352 by a first insulator layer 353 of the MIM capacitor 350. The second plate 354 is separated from a third plate 356 by a second insulator 355. As explained above, the first plate 352 and the third plate 356 are coupled to the first top contact 310 and the second plate 354 is coupled to the second top contact 320, which allows both connections to the MIM capacitor 350 to be located on the same side.

[0043]

[0052] IMD layer 330 may have additional structures formed from the Mx+1 metal layer, such as metal trace 360, which may be coupled to metal trace 340 formed in metal layer Mx by via 365. Metal traces 340 and 360 and via 365 may be coupled to positive potentials, ground potentials, digital signals, analog signals, or any other suitable signals for routing within device 300.

[0044]

[0053] FIG. 3K illustrates a portion of a manufacturing process for a device 302 according to one or more aspects of the present disclosure. As illustrated in FIG. 3K, the process can continue from FIG. 3H. In some aspects, the device 302 can be a die, an integrated circuit, a package, etc. It will be further understood that the device 302 can include multiple components in an integrated device, only some of which are shown. As illustrated, the device 302 can include a first IMD layer 330, which can include one or more layers of a dielectric material. The first IMD layer 330 is disposed on a first metal layer Mx. In this part of the process, a via 365 is formed to electrically contact a metal trace 340 that is in the Mx metal layer. Additionally, a second metal layer Mx+1 is deposited on the first mesa 331, the second mesa 332, the via 365, and a portion of the second IMD 335. The second metal layer Mx+1 is patterned and etched to form a first top contact 310, a second top contact 320, and a metal trace 360. The first top contact 310 is electrically coupled to the first plate 352 and the third plate 356 via direct contact. The second top contact 320 is electrically coupled to the second plate 354 via direct contact. One or more additional layers can be added to the second IMD layer 335, thereby allowing the first top contact 310, the second top contact 320, and the metal trace 360 ​​to be at least partially embedded in the second IMD layer 335 along with the vias 365.

[0045]

[0054] It will thus be appreciated that device 302 is similar to device 200 described above. Second IMD layer 335 has top contacts formed in the Mx+1 metal layer, such as first top contact 310 and second top contact 320. First top contact 310 may be directly electrically coupled to first plate 352 of MIM capacitor 350 and third plate 356 of MIM capacitor 350. In some aspects, first mesa 331 may be formed as a cone structure with tapered sides such that it has a substantially circular shape when viewed from a top view. In some aspects, second top contact 320 may have a similar structure to first top contact 310. Second top contact 320 may be directly electrically coupled to second plate 354 of MIM capacitor 350. In some aspects, second mesa 332 may be formed as a cone structure with tapered sides such that it has a substantially circular shape when viewed from a top view.

[0046]

[0055] The multi-plate MIM capacitor 350 is shown in a three-plate configuration and includes a second plate 354 separated from a first plate 352 by a first insulator layer 353 of the MIM capacitor 350. The second plate 354 is separated from a third plate 356 by a second insulator 355. As explained above, the first plate 352 and the third plate 356 are coupled to the first top contact 310 and the second plate 354 is coupled to the second top contact 320, which allows both connections to the MIM capacitor 350 to be located on the same side.

[0047]

[0056] IMD layer 330 may have additional structures formed from the Mx+1 metal layer, such as metal trace 360, which may be coupled to metal trace 340 formed in metal layer Mx by via 365. Metal traces 340 and 360 and via 365 may be coupled to positive potentials, ground potentials, digital signals, analog signals, or any other suitable signals for routing within device 302.

[0048]

[0057] FIG. 4 illustrates a portion of a device 400 according to one or more aspects of the present disclosure. In some aspects, the device 400 may be a die, an integrated circuit, a package, or the like. It will be further understood that the device 400 may include multiple components in an integrated device, only some of which are shown. As illustrated, the device 400 may include a multi-plate MIM capacitor 450 that is similar in structure to the MIM capacitors previously described (e.g., 150, 250, 350). The multi-plate MIM capacitor 450 has a first plate 452, a second plate 454, and a third plate 456. The portions of metal forming the first plate 452 and the third plate 456 extend to the sidewalls of the first mesa 431 and are shown as circular rings around the first mesa 431. The first plate 452 and the third plate 456 are separated by a first insulator 453 and a second insulator 455, which are shown as interdigitated concentric circles around the first mesa 431, but are not specifically shown as layers between the perspective views of the first plate 452, the second plate 454, and the third plate 456. The portion of the metal forming the second plate 454 extends to the sidewall of the second mesa 431 and is shown as a circular ring around the first mesa 431. The second plate 454 is disposed between the first insulator 453 and the second insulator 455, which are shown as concentric circles around the second mesa 432. In some aspects, the first plate 452, the second plate 454, and the third plate 456 extend beyond the first mesa 431 and the second mesa 432, as shown, and in some aspects, around the via 465. It will be understood that the various disclosed aspects are not limited to these example dimensions.

[0049]

[0058] FIG. 5 illustrates a portion of a device 500 according to one or more aspects of the present disclosure. In some aspects, the device 500 may be a die, an integrated circuit, a package, or the like. It will be further understood that the device 500 may include multiple components in an integrated device, only some of which are shown. As illustrated, the device 500 may include a multi-plate MIM capacitor 550 that is similar in structure to the MIM capacitors previously described (e.g., 150, 250, 350). The multi-plate MIM capacitor 550 has a first plate 552, a second plate 554, and a third plate 556. The portions of metal forming the first plate 552 and the third plate 556 extend to the sidewalls of the first mesa 531 and are shown as circular rings around the first mesa 531. The first plate 552 and the third plate 556 are separated by a first insulator 553 and a second insulator 555, which are shown as interdigitated concentric circles around the first mesa 531. The portion of the metal forming the second plate 554 extends to the sidewall of the second mesa 532 and is shown as a circular ring around the first mesa 531. The second plate 554 is disposed between the first insulator 553 and the second insulator 555, which are shown as concentric circles around the second mesa 532. In some aspects, the first plate 552, the second plate 554, and the third plate 556 may be disposed between the first mesa 531 and the second mesa 532, as shown. An additional MIM capacitor (e.g., MIM capacitor 570 and MIM capacitor 580) may be coupled to one of the contacts around the mesas. For example, MIM capacitor 570 may be coupled to first plate 552 and third plate 556 at first mesa 531. Similarly, MIM capacitor 580 may be coupled to second plate 554 at first mesa 532. Additionally, contacts 585 for the first and third plates of MIM capacitor 580 may be offset from second mesa 532. Thus, it will be understood that the various disclosed aspects are not limited to the configurations shown.

[0050]

[0059] FIG. 6 illustrates a portion of a device 600 according to one or more aspects of the present disclosure. In some aspects, the device 600 may be a die, an integrated circuit, a package, or the like. It will be further understood that the device 600 may include multiple components in an integrated device, only some of which are shown. As illustrated, the device 600 may include a multi-plate MIM capacitor 650 that is similar in structure to the MIM capacitors previously described (e.g., 150, 250, 350). The multi-plate MIM capacitor 650 has a first plate 652, a second plate 654, and a third plate 656. The portions of metal forming the first plate 652 and the third plate 656 extend to the sidewalls of the first mesa 631 and are shown as semicircular rings around the first mesa 631. The first plate 652 and the third plate 656 are separated by the first insulator 653 and the second insulator 655, which are shown as interlocking concentric circles around the first mesa 631. As shown, it will be understood that the first insulator 653 and the second insulator 655 may be joined at the first mesa 631 since the second plate 654 does not extend to this portion. Alternatively, in some embodiments, only one of the first insulator 653 and the second insulator 655 may extend onto the sidewall of the first mesa 631. The portion of the metal forming the second plate 654 extends to the sidewall of the second mesa 632 and is shown as a semicircular ring around the first mesa 631. The second plate 654 is disposed between the first insulator 653 and the second insulator 655, which are shown as concentric semicircles around the second mesa 632. In some aspects, the first plate 652, the second plate 654, and the third plate 656 may be disposed between the first mesa 631 and the second mesa 632 as shown. Additional MIM capacitors (e.g., MIM capacitor 670 and MIM capacitor 680) may be coupled to one of the contacts around the mesas. For example, in the cross-sectional detail shown, MIM capacitor 670 has a first plate 672, a second plate 674, and a third plate 676.The portions of the metal forming the first plate 672 and the third plate 676 extend to the sidewalls of the first mesa 631 and are shown as semicircular rings around the first mesa 631. The portions of the first plate 672 and the third plate 676 on the sidewalls of the mesa 631 are separated by a first insulator 673 and / or a second insulator 675, which are shown as interdigitated concentric circles around the first mesa 631. In this configuration, the first plate 672 and the third plate 676 of the MIM capacitor 670 are separated from the first plate 652 and the third plate 656 of the MIM capacitor 650. It will be appreciated that the various plates and insulators of the MIM capacitor 680 may also be separated from the plates and insulators of the MIM capacitor 650. However, in alternative configurations, one or more of the plates and insulators may be common. For example, in some embodiments, the metal plates of MIM capacitor 650 and MIM capacitor 670 may be separated, but one or more of the insulators (e.g., 653 / 673 and 655 / 675) may be a continuous layer between MIM capacitor 650 and MIM capacitor 670. In further alternative embodiments, MIM capacitor 650 may be rotated 180 degrees (in the top figure) or flipped horizontally (in the bottom figure). In this configuration, instead of mesa 631 (not shown) having a first metal plate and a third metal plate on both the left and right, the left portion of mesa 631 (not shown) has a first metal plate and a third metal plate, and the right portion of mesa 631 (not shown) has a second metal plate. Thus, various configurations will be understood by those skilled in the art, and it will be understood that the various disclosed embodiments are not limited to the configurations shown.

[0051]

[0060] FIG. 7 illustrates an example mobile device according to some examples of the disclosure. Referring now to FIG. 7, a block diagram of a mobile device configured in accordance with an example aspect is depicted, generally designated as mobile device 700. In some aspects, the mobile device 700 may be configured as a wireless communication device. As shown, the mobile device 700 includes a processor 701. The processor 701 is communicatively coupled to a memory 732 via a link, which may be an inter-die link or an inter-chip link. The mobile device 700 also includes a display 728 and a display controller 726, which is coupled to the processor 701 and the display 728.

[0052]

[0061] In some aspects, FIG. 7 may include a Coder / Decoder (CODEC) 734 (e.g., an audio and / or voice codec) coupled to the processor 701, a speaker 736 and a microphone 738 coupled to the CODEC 734, and wireless circuitry 740 (which may include a modem, RF circuitry, filters, etc., and may be implemented using one or more devices including multi-plate MIM capacitors as disclosed herein) coupled to a wireless antenna 742 and the processor 701.

[0053]

[0062] In certain aspects where one or more of the above-mentioned blocks are present, the processor 701, the display controller 726, the memory 732, the codec 634, and the wireless circuitry 740 can be included in a system-in-package or system-on-chip device 722 that can be implemented using one or more devices including MIM capacitors in the backside BEOL metallization as disclosed herein. The input device 730 (e.g., a physical or virtual keyboard), the power source 744 (e.g., embedded), the display 728, the input device 730, the speaker 736, the microphone 738, the wireless antenna 742, and the power source 744 can be external to the system-on-chip device 722 or can be coupled to components of the system-on-chip device 722, such as interfaces or controllers.

[0054]

[0063] It should be noted that although FIG. 7 shows a mobile device 700, the processor 701 and memory 732 may also be integrated into a set-top box, a music player, a video player, an entertainment unit, a navigation device, a Personal Digital Assistant (PDA), a stationary data unit, a computer, a laptop, a tablet, a communications device, a mobile phone, or other similar device.

[0055]

[0064] FIG. 8 illustrates various electronic devices that may be integrated with any of the aforementioned integrated or semiconductor devices according to various examples of the present disclosure. For example, a mobile phone device 802, a laptop computer device 804, and a stationary terminal device 806 may each be generally considered user equipment (UE) and may include a device 800 including a MIM capacitor in the backside BEOL metallization as described herein. The device 800 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. The devices 802, 804, 806 illustrated in FIG. 8 are merely examples. Other electronic devices may also feature device 800 including a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0056]

[0065] From the above, it can be appreciated that there are various methods for fabricating a device including a multi-plate MIM capacitor as disclosed herein. FIG. 9 illustrates a flow chart of an example method 900 for fabricating a device including a metal-insulator-metal (MIM) capacitor according to at least one embodiment disclosed. In block 902, the fabrication process can include forming a first mesa (e.g., 131, 231). In block 904, the fabrication process can further include forming a second top contact (e.g., 120, 220) adjacent to the first top contact. In block 906, the fabrication process can include depositing a first plate (e.g., 150, 250) of the metal-insulator-metal (MIM) capacitor between the first mesa and the second mesa, with a portion of the first plate extending to the first mesa. At block 908, the fabrication process can include depositing a first insulator (e.g., 153, 253) of the MIM capacitor on the first plate, with a portion of the first insulator extending to the first mesa and the second mesa. At block 910, the fabrication process can include depositing a second plate (e.g., 154, 254) of the MIM capacitor disposed on the first insulator, with a portion of the second plate extending to the second mesa. At block 912, the fabrication process can include depositing a second insulator (e.g., 155, 255) of the MIM capacitor on the second plate, with a portion of the second insulator extending to the first mesa and the second mesa. At block 914, the fabrication process can include depositing a third plate (e.g., 156, 256) of the MIM capacitor on the second insulator between the first mesa and the second mesa, with a portion of the third plate extending to the first mesa. At block 916, the fabrication process can include forming a first top contact, with the first mesa disposed below the first contact, and the first plate and the second plate electrically coupled to the first top contact.At block 918, the manufacturing process can form a second upper contact, the second mesa being disposed below the second contact, and the second plate being electrically coupled to the second contact.

[0057]

[0066] It will be appreciated from the above disclosure that additional processes for manufacturing the various embodiments disclosed herein will be apparent to those skilled in the art, and that literal representations of the above processes have not been presented or shown in the accompanying drawings.

[0058]

[0067] It will be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may include means for performing the various functions described above. It will be understood that the foregoing aspects are provided by way of example only, and that the various aspects claimed are not limited to the specific content and / or figures cited as examples.

[0059]

[0068] One or more of the components, processes, features, and / or functions shown in FIGS. 1-9 may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from this disclosure. It is also noted that FIGS. 1-9 and their corresponding descriptions in this disclosure are not limited to dies and / or integrated circuits (ICs). In some implementations, FIGS. 1-9 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an IC package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0060]

[0069] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the described features, advantages or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0061]

[0070] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0062]

[0071] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0063]

[0072] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0064]

[0073] Nothing described, illustrated, or shown in this application is intended to disclose to the public any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0065]

[0074] In the above detailed description, it can be seen that various features are grouped together in each example. This manner of disclosure should not be understood as an intention that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the disclosure may include fewer than all features of each disclosed exemplary clause. Thus, the following clauses should be considered to be incorporated in the description, and each clause may stand alone as a separate example. Although each dependent clause may refer to a specific combination with one of the other clauses in the clause, the aspect(s) of the dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of the aspect(s) of the dependent clause with the subject matter of any other dependent clause or independent clause, or combinations of any features with other dependent clauses and independent clauses. Unless a specific combination is not intended (e.g., conflicting aspects such as defining an element as both an insulator and a conductor) is expressly expressed or can be easily inferred, the various aspects disclosed herein expressly include these combinations. It is further contemplated that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0066]

[0075] The following numbered sections explain implementation examples.

[0067]

[0076] Clause 1. An apparatus comprising: a first top contact, a second top contact adjacent to the first top contact, a first mesa disposed below the first top contact, a second mesa disposed below the second top contact, a first plate of a metal-insulator-metal (MIM) capacitor disposed below the first top contact and electrically coupled to the first top contact, a first insulator of the MIM capacitor disposed on the first plate, a second plate of the MIM capacitor disposed on the first insulator and electrically coupled to the second top contact, a second insulator of the MIM capacitor disposed on the second plate, and a third plate of the MIM capacitor disposed on the second insulator and electrically coupled to the first top contact.

[0068]

[0077] Clause 2 The device described in Clause 1, further comprising: a first partial via disposed between the first upper contact and the first mesa, wherein the first plate and the third plate are electrically coupled to the first upper contact via the first partial via; and a second partial via disposed between the second upper contact and the second mesa, wherein the second plate is electrically coupled to the second upper contact via the second partial via.

[0069]

[0078] Clause 3. The device of clause 1, wherein the first top contact is disposed directly on the first mesa and the second top contact is disposed directly on the second mesa.

[0070]

[0079] Clause 4. The device of any of clauses 1 to 3, wherein the first mesa and the second mesa are formed in a first intermetal dielectric (IMD) layer.

[0071]

[0080] Clause 5. The device of clause 4, further comprising a second intermetal dielectric (IMD) layer, the first top contact and the second top contact being at least partially disposed within the second IMD layer.

[0072]

[0081] Clause 6. The apparatus of clause 5, wherein the first top contact and the second top contact are in a same metal layer in the second IMD layer.

[0073]

[0082] Clause 7. The apparatus of clause 6, further comprising a bottom metal layer, the first IMD layer disposed on the bottom metal layer.

[0074]

[0083] Clause 8. The apparatus of any of clauses 4 to 7, wherein the first insulator comprises a high-k dielectric material and the first IMD layer comprises a low-k dielectric material.

[0075]

[0084] Clause 9. The apparatus of any of clauses 5 to 8, wherein the second IMD layer comprises a low-k dielectric material.

[0076]

[0085] Clause 10. The apparatus of any of clauses 1 to 9, wherein the first plate, the second plate, the third plate, the first insulator, and the second insulator are disposed between the first top contact and the second top contact.

[0077]

[0086] Clause 11. An apparatus according to any of clauses 1 to 10, wherein the first plate and the third plate are coupled to a first power connection and the second plate is coupled to a second power connection.

[0078]

[0087] Clause 12. The apparatus of clause 11, wherein the first power connection is configured to be at a positive potential and the second power connection is configured to be at a negative potential or ground.

[0079]

[0088] Clause 13. The apparatus of any of clauses 1 to 12, further comprising a second MIM capacitor having a second plate disposed between the first plate and the third plate, the first plate and the third plate being coupled to the first top contact.

[0080]

[0089] Clause 14. The apparatus of any of clauses 1 to 13, further comprising a third MIM capacitor, the third MIM capacitor having a second plate disposed between the first plate and the third plate, the second plate coupled to the second top contact.

[0081]

[0090] Clause 15. The apparatus of any of clauses 1 to 14, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

[0082]

[0091] Clause 16. A method of manufacturing a device, comprising: forming a first mesa; forming a second mesa adjacent to the first mesa; depositing a first plate of a metal-insulator-metal (MIM) capacitor between the first mesa and the second mesa, a portion of the first plate extending to the first mesa; depositing a first insulator of the MIM capacitor on the first plate, a portion of the first insulator extending to the first mesa and the second mesa; depositing a second plate of the MIM capacitor on the first insulator between the first mesa and the second mesa, a portion of the second plate extending to the second mesa; 13. A method for manufacturing a MIM capacitor comprising: depositing a second insulator, a portion of the second insulator extending to the first mesa and the second mesa; depositing a third plate of a MIM capacitor on the second insulator between the first mesa and the second mesa, a portion of the third plate extending to the first mesa; forming a first top contact, the first mesa being disposed below the first contact, the first plate and the second plate being electrically coupled to the first top contact; and forming a second top contact, the second mesa being disposed below the second contact, the second plate being electrically coupled to the second contact.

[0083]

[0092] Clause 17. The method of clause 16, further comprising: disposing a first partial via between the first top contact and the first mesa, where the first plate and the third plate are electrically coupled to the first top contact through the first partial via; and disposing a second partial via between the second top contact and the second mesa, where the second plate is electrically coupled to the second top contact through the second partial via.

[0084]

[0093] Clause 18. The method of clause 16, wherein the first top contact is disposed directly on the first mesa and the second top contact is disposed directly on the second mesa.

[0085]

[0094] Clause 19. The method of any of clauses 16-18, wherein the first mesa and the second mesa are formed in a first intermetal dielectric (IMD) layer.

[0086]

[0095] Clause 20. The method of clause 19, further comprising forming a second intermetal dielectric (IMD) layer, the first top contact and the second top contact being at least partially disposed within the second IMD layer.

[0087]

[0096] Clause 21. The method of clause 20, wherein the first top contact and the second top contact are in a same metal layer in the second IMD layer.

[0088]

[0097] Clause 22. The method of clause 21, further comprising disposing a bottom metal layer, the first IMD layer being on the bottom metal layer.

[0089]

[0098] Clause 23. The method of any of clauses 19-22, wherein the first insulator comprises a high-k dielectric material and the first IMD layer comprises a low-k dielectric material.

[0090]

[0099] Clause 24. The method of any of clauses 20-23, wherein the second IMD layer comprises a low-k dielectric material.

[0091]

[0100] Clause 25. The method of any of clauses 16 to 24, wherein the first plate, the second plate, the third plate, the first insulator, and the second insulator are disposed between the first top contact and the second top contact.

[0092]

[0101] Clause 26. The method of any of clauses 16 to 25, wherein the first plate and the third plate are coupled to a first power connection and the second plate is coupled to a second power connection.

[0093]

[0102] Clause 27. Apparatus according to clause 26, wherein the first power connection is configured to be at a positive potential and the second power connection is configured to be at a negative potential or ground.

[0094]

[0103] Clause 28. The method of any of clauses 16-27, further comprising forming a second MIM capacitor, the second MIM capacitor having a second plate disposed between the first plate and a third plate, the first plate and the third plate coupled to the first top contact.

[0095]

[0104] Clause 29. The method of any of clauses 16-28, further comprising forming a third MIM capacitor, the third MIM capacitor having a second plate disposed between the first plate and the third plate, the second plate coupled to the second top contact.

[0096]

[0105] Clause 30. The method of any of clauses 16 to 29, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

[0097]

[0106] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing the respective acts and / or functions of the disclosed methods.

[0098]

[0107] Further, in some instances, an individual act may be subdivided into or include one or more sub-acts, and such sub-acts may be included in and become part of the disclosure of the individual act.

[0099]

[0108] Although the above disclosure illustrates examples of the present disclosure, it should be noted that various modifications and changes can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or acts of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. An apparatus comprising: a first upper contact; a second upper contact adjacent to the first upper contact; a first mesa disposed below the first upper contact; a second mesa disposed below the second upper contact; a first plate of a metal-insulator-metal (MIM) capacitor disposed below the first upper contact and electrically coupled to the first upper contact; a first insulator of the MIM capacitor disposed on the first plate; a second plate of the MIM capacitor disposed on the first insulator and electrically coupled to the second upper contact; a second insulator of the MIM capacitor disposed on the second plate; a third plate of the MIM capacitor disposed on the second insulator and electrically coupled to the first upper contact.

2. A first partial via disposed between the first upper contact and the first mesa, and the first plate and the third plate are electrically coupled to the first upper contact via the first partial via; a second partial via disposed between the second upper contact and the second mesa, and the second plate is electrically coupled to the second upper contact via the second partial via; the apparatus according to claim 1, further comprising the above.

3. The apparatus according to claim 1, wherein the first mesa and the second mesa are formed in a first inter-metal dielectric (IMD) layer.

4. Further comprising a second inter-metal dielectric (IMD) layer, wherein the first upper contact and the second upper contact are at least partially disposed within the second IMD layer; the first upper contact and the second upper contact are within the same metal layer within the second IMD layer; further comprising a lower metal layer, wherein the first IMD layer is disposed on the lower metal layer; the apparatus according to claim 3.

5. A second MIM capacitor having a second plate disposed between a first plate and a third plate, and the first plate and the third plate are coupled to the first upper contact; the second MIM capacitor The apparatus according to claim 1, further comprising a third MIM capacitor having a second plate disposed between a first plate and a third plate, wherein the second plate is coupled to the second upper contact.

6. A method of manufacturing an apparatus, comprising: forming a first mesa; forming a second mesa adjacent to the first mesa; depositing a first plate of a metal-insulator-metal (MIM) capacitor between the first mesa and the second mesa, with a portion of the first plate extending to the first mesa; depositing a first insulator of the MIM capacitor on the first plate, with a portion of the first insulator extending to the first mesa and the second mesa; depositing a second plate of the MIM capacitor on the first insulator between the first mesa and the second mesa, with a portion of the second plate extending to the second mesa; depositing a second insulator of the MIM capacitor on the second plate, with a portion of the second insulator extending to the first mesa and the second mesa; depositing a third plate of the MIM capacitor on the second insulator between the first mesa and the second mesa, with a portion of the third plate extending to the first mesa; forming a first upper contact, with the first mesa disposed below the first contact and the first plate and the second plate being electrically coupled to the first upper contact; forming a second upper contact, with the second mesa disposed below the second contact and the second plate being electrically coupled to the second contact.

7. The apparatus according to claim 1, or the method according to claim 6, wherein the first mesa is disposed completely below the first upper contact and the second mesa is disposed completely below the second upper contact.

8. The apparatus according to claim 1, or the method according to claim 6, wherein the first upper contact is disposed directly on the first mesa and the second upper contact is disposed directly on the second mesa.

9. The method according to claim 6, wherein the first mesa and the second mesa are formed within a first inter-metal dielectric (IMD) layer.

10. The method according to claim 9, further comprising forming a second inter-metal dielectric (IMD) layer, wherein the first upper contact and the second upper contact are at least partially disposed within the second IMD layer.

11. The apparatus according to claim 3, or the method according to claim 9, wherein the first insulator comprises a high-k dielectric material and the first IMD layer comprises a low-k dielectric material.

12. The apparatus according to claim 4, or the method according to claim 10, wherein the second IMD layer comprises a low-k dielectric material.

13. The apparatus according to claim 1, or the method according to claim 6, wherein the first plate, the second plate, the third plate, the first insulator, and the second insulator are disposed between the first upper contact and the second upper contact.

14. The first plate and the third plate are coupled to a first power connection, and the second plate is coupled to a second power connection, The apparatus according to claim 1, or the method according to claim 6, wherein the first power connection is configured to be at a positive potential and the second power connection is configured to be at a negative potential or grounded.

15. The apparatus according to claim 1, or the method according to claim 6, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a cellular phone, a smartphone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

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