Metal Pillar Connection Topology in Radio Frequency Transistor Amplifier Dies for Heterogeneous Packaging

Abstract

A radio frequency ("RF") transistor amplifier die includes a semiconductor layer structure including a plurality of transistor cells and an insulating layer on a surface of the semiconductor layer structure. Conductive pillar structures protrude from the insulating layer opposite the surface of the semiconductor layer structure and are configured to provide an input signal connection, an output signal connection, or a ground connection to the transistor cells. The ground connection is disposed between the input and / or output signal connections to the transistor cells. Related devices and packages are also discussed.

Description

[Technical field]

[0001] Claiming priority This application claims priority to U.S. Patent Application No. 17 / 466,783, filed in the U.S. Patent and Trademark Office on September 3, 2021, the disclosure of which is incorporated by reference in its entirety herein.

[0002] The present disclosure is directed to integrated circuit ("IC") devices, and more particularly, to power amplifier devices, device packaging, and related manufacturing methods. [Background technology]

[0003] Electrical circuits that require the ability to handle high power while operating at high frequencies, such as 0.5-1 GHz, 3 GHz, 10 GHz, or higher, have become more prevalent in recent years. In particular, there is currently a high demand for radio frequency ("RF") power amplifiers, which are used to amplify RF signals at radio (including microwave) frequencies in a variety of applications, such as base stations for wireless communication systems. Signals amplified by RF power amplifiers often include signals with modulated carriers having frequencies in the megahertz (MHz) to gigahertz (GHz) range. These RF power amplifiers may be required to exhibit high reliability, good linearity, and handle high output power levels.

[0004] Many RF power amplifier designs utilize semiconductor switching devices as the amplifying device. Examples of these switching devices include power transistor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, and field-effect transistor (FET) devices, including HEMTs (high-electron-mobility transistors), MESFETs (metal-semiconductor field-effect transistors), and LDMOS (laterally-diffused metal-oxide-semiconductor) transistors.

[0005] RF transistor amplifiers are typically formed as semiconductor integrated circuit chips. Most RF transistor amplifiers are implemented in silicon or using wide bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and III-nitride materials. As used herein, the term "III-nitrides" refers to those semiconductor compounds formed between nitrogen and elements in group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula in which one mole of nitrogen combines with one mole of total group III elements.

[0006] An RF transistor amplifier may include one or more amplification stages, each of which is typically implemented as a transistor amplifier. To increase output power and current handling capabilities, RF transistor amplifiers are typically implemented in a "unit cell" configuration, where a number of individual "unit cell" transistor structures are placed electrically in parallel. An RF transistor amplifier may be implemented by the transistor cells of a single integrated circuit chip or "die," or may include multiple dies. A die or chip may refer to a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0007] Silicon-based RF transistor amplifiers are typically implemented using LDMOS transistors and may exhibit high levels of linearity with relatively inexpensive fabrication. III-Nitride based RF amplifiers are typically implemented using HEMTs, primarily in applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0008] In the operation of a HEMT device, a two-dimensional electron gas (2DEG) forms at the heterojunction of two semiconductor materials with different bandgap energies, with the smaller bandgap material having a higher electron affinity. The 2DEG is an accumulation layer in the smaller bandgap material and may contain a very high sheet electron concentration. In addition, electrons originating in the wider bandgap semiconductor material transfer to the 2DEG layer, allowing for high electron mobility due to reduced scattering of ionized impurities. This combination of high carrier concentration and high carrier mobility may give HEMTs a very large transconductance, which may provide a strong performance advantage over metal-oxide-semiconductor field effect transistors (MOSFETs) for high frequency applications. High electron mobility transistors fabricated in III-nitride based material systems also have the potential to generate large amounts of radio frequency (RF) power due to the combination of material properties including the aforementioned high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity.

[0009] RF transistor amplifiers often include circuits such as matching circuits, or impedance matching circuits designed to improve the impedance match between the active transistor die (e.g., including MOSFET, HEMT, LDMOS, etc.) and the transmission line connected thereto for RF signals at the fundamental operating frequency, and harmonic termination circuits designed to at least partially terminate harmonic products that may be generated during device operation, such as second and third harmonic products. Termination of harmonic products also affects the generation of intermodulation distortion products.

[0010] The impedance matching and harmonic termination circuitry along with the transistor die(s) may be enclosed within a device package. Integrated circuit packaging may refer to encapsulating one or more dies within a supporting case or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. Electrical leads may extend from the package to electrically connect the transistor die to external systems and / or circuit elements, such as input and output RF transmission lines and bias voltage sources. The input and output matching circuits within the integrated circuit device package typically include LC networks that provide at least a portion of the impedance matching circuitry, the impedance matching circuitry configured to match the impedance of the active transistor die to a fixed value. Typically, the input and output RF matching circuits employ off-die components and implementation aspects that may increase the package footprint.

[0011] Connections within the package, such as between the die and off-die components or other external circuitry, may rely on wire bonds. Wire bonds may be formed through die-level processing steps. The geometry of such traditional connections may be difficult to control and / or may limit precision for more complex RF IC designs. Also, signal routing options through wire bonds may be limited due to the relatively bulky and large die area requirements for wire bond contact pads. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent No. RE34,861 [Patent Document 2] U.S. Patent No. 4,946,547 [Patent Document 3] U.S. Patent No. 5,200,022 [Patent Document 4] U.S. Patent No. 6,218,680 [Patent Document 5] U.S. Patent No. 5,210,051 [Patent Document 6] U.S. Patent No. 5,393,993 [Patent Document 7] U.S. Patent No. 5,523,589 [Patent Document 8] U.S. Patent No. 7,030,428 [Patent Document 9] U.S. Patent No. 8,563,372 [Patent Document 10] U.S. Patent No. 9,214,352 [Patent Document 11] U.S. Patent No. 5,192,987 [Patent Document 12] U.S. Patent No. 5,296,395 [Patent Document 13] U.S. Patent No. 6,316,793 [Patent Document 14] U.S. Patent No. 6,548,333 [Patent Document 15] U.S. Patent No. 7,544,963 [Patent Document 16] U.S. Patent No. 7,548,112 [Patent Document 17] U.S. Patent No. 7,592,211 [Patent Document 18] U.S. Patent No. 7,615,774 [Patent Document 19] U.S. Patent No. 7,709,269 [Patent Document 20] U.S. Patent No. 8,049,252 [Patent Document 21] U.S. Patent No. 7,045,404 [Patent Document 22] U.S. Patent No. 8,120,064 [Patent Document 23] U.S. Patent Application Serial No. 16 / 889,432 Summary of the Invention

[0013] According to some embodiments, an integrated circuit device includes a radio frequency ("RF") transistor amplifier die, the RF transistor amplifier die including a semiconductor layer structure including a plurality of transistor cells, an insulating layer on a surface of the semiconductor layer structure, and a plurality of conductive pillar structures protruding from the insulating layer opposite the surface of the semiconductor layer structure. Each of the conductive pillar structures is configured to provide an input signal connection, an output signal connection, or a ground connection to the transistor cells. The ground connection is disposed between the input signal connections and / or the output signal connections to the transistor cells.

[0014] In some embodiments, a first subset of conductive pillar structures may be configured to provide a ground connection and may be disposed between a second and a third subset of conductive pillar structures that may be configured to provide input and output signal connections, respectively.

[0015] In some embodiments, a first subset of the conductive pillar structures may be configured to provide a ground connection and a second subset of the conductive pillar structures may be configured to provide one of an input signal connection or an output signal connection, and each conductive pillar structure of the second subset may be disposed between each conductive pillar structure of the first subset.

[0016] In some embodiments, a third subset of the conductive pillar structures may be configured to provide the other of the input signal connection or the output signal connection, and each conductive pillar structure of the third subset may be disposed between each conductive pillar structure of the first subset.

[0017] In some embodiments, a transistor cell may include a gate finger, a drain finger, and a source finger extending over a semiconductor layer structure, wherein each conductive pillar structure of a first subset may be coupled to a source finger and each conductive pillar structure of a second subset may be coupled to a gate finger or a drain finger.

[0018] In some embodiments, each conductive pillar structure in the first subset may be between opposing ends of a source finger and / or each conductive pillar structure in the second subset may be between opposing ends of a gate finger or a drain finger.

[0019] In some embodiments, each conductive pillar structure of the first subset may be coupled to a respective extension region of a source finger and / or each conductive pillar structure of the second subset may be coupled to a respective extension region of a gate finger or a drain finger.

[0020] In some embodiments, each of the gate fingers, drain fingers, and / or source fingers can include finger segments spaced apart from one another, and respective extension regions can be disposed between the finger segments.

[0021] In some embodiments, a transistor cell includes a gate finger, a drain finger, and a source finger extending over a semiconductor layer structure, and an input signal connection, an output signal connection, or a ground connection provided by each of the conductive pillar structures is released from a wire bond connection pad that electrically connects to the gate finger, the drain finger, or the source finger.

[0022] In some embodiments, at least one of the conductive pillar structures may be coupled to a plurality of gate fingers, a plurality of drain fingers, or a plurality of source fingers by one or more intervening metal layers therebetween.

[0023] In some embodiments, the conductive pillar structures may protrude from an insulating layer adjacent a top of the RF transistor amplifier die. A substrate may be provided on the semiconductor layer structure opposite a surface having an insulating layer thereon, and the conductive via structures may extend through the substrate adjacent a bottom of the RF transistor amplifier die. Each of the conductive via structures may be configured to provide another input signal connection, an output signal connection, or a ground connection to the transistor cell.

[0024] In some embodiments, each of the conductive pillar structures may be disposed within an active area that includes a transistor cell to provide an input signal connection, an output signal connection, and a ground connection.

[0025] In some embodiments, the transistor cell may include gate fingers extending along a surface of the semiconductor layer structure, and the input signal connection may be disposed between opposing ends of the gate fingers.

[0026] According to some embodiments, a radio frequency ("RF") transistor amplifier die includes a semiconductor layer structure including a plurality of transistor cells, an insulating layer on a surface of the semiconductor layer structure, and a plurality of conductive pillar structures protruding from the insulating layer opposite the surface of the semiconductor layer structure. Each of the conductive pillar structures is configured to provide an input signal connection, an output signal connection, or a ground connection to a transistor cell. The transistor cells include gate fingers extending over the semiconductor layer structure, and an input signal connection is coupled to the gate fingers between opposing ends thereof.

[0027] In some embodiments, a ground connection may be disposed between the input signal connection and the output signal connection to the transistor cell.

[0028] In some examples, a first subset of the conductive pillar structures may be configured to provide an input signal connection, and a second subset of the conductive pillar structures may be configured to provide a ground connection, and each conductive pillar structure of the first subset may be disposed between each conductive pillar structure of the second subset.

[0029] In some embodiments, a third subset of the conductive pillar structures may be configured to provide an output signal connection, and each conductive pillar structure of the third subset may be disposed between each conductive pillar structure of the second subset.

[0030] In some embodiments, the transistor cell may further include source and drain fingers extending over the semiconductor layer structure, and each conductive pillar structure of the second subset may be between opposing ends of the source fingers and / or each conductive pillar structure of the third subset may be between opposing ends of the drain fingers.

[0031] In some embodiments, each conductive pillar structure of the first subset, the second subset, and / or the third subset may be coupled to a respective extension region between respective finger segments of the gate fingers, the source fingers, and / or the drain fingers.

[0032] In some embodiments, the conductive pillar structures may protrude from an insulating layer adjacent a top of the RF transistor amplifier die. A substrate may be provided on the semiconductor layer structure opposite a surface having an insulating layer thereon, and the conductive via structures may extend through the substrate adjacent a bottom of the RF transistor amplifier die. Each of the conductive via structures may be configured to provide another input signal connection, an output signal connection, or a ground connection to the transistor cell.

[0033] In some embodiments, each of the conductive pillar structures may be disposed within an active area that includes a transistor cell to provide an input signal connection, an output signal connection, and a ground connection.

[0034] In some embodiments, the transistor cell may further include drain and source fingers extending over the semiconductor layer structure, and the input signal connection, output signal connection, or ground connection provided by each of the conductive pillar structures may be released from a wire bond connection pad electrically connecting to the gate finger, drain finger, or source finger.

[0035] According to some embodiments, a radio frequency ("RF") transistor amplifier die includes a semiconductor layer structure including a plurality of transistor cells adjacent a surface thereof and a plurality of conductive pillar structures projecting away from the surface of the semiconductor layer structure. Each of the conductive pillar structures is configured to provide an input signal connection, an output signal connection, or a ground connection to a transistor cell. The transistor cell includes a gate finger, a drain finger, and a source finger extending over the semiconductor layer structure. The input signal connection, the output signal connection, or the ground connection provided by each of the conductive pillar structures is free from a wire bond connection pad that electrically connects to the gate finger, the drain finger, or the source finger.

[0036] In some embodiments, the conductive pillar structures may include a first subset coupled to source fingers between opposing ends thereof, a second subset coupled to gate fingers between opposing ends thereof, and / or a third subset coupled to drain fingers between opposing ends thereof.

[0037] In some embodiments, the ground connection may be disposed between the input signal connection and / or the output signal connection.

[0038] In some embodiments, a first subset of conductive pillar structures may be configured to provide a ground connection and may be disposed between a second and a third subset of conductive pillar structures that may be configured to provide input and output signal connections, respectively.

[0039] In some embodiments, a first subset of the conductive pillar structures may be configured to provide a ground connection and a second subset of the conductive pillar structures may be configured to provide one of an input signal connection or an output signal connection, and each conductive pillar structure of the second subset may be disposed between each conductive pillar structure of the first subset.

[0040] In some embodiments, each conductive pillar structure of the first subset may be coupled to a respective extension region of a source finger and / or each conductive pillar structure of the second subset may be coupled to a respective extension region of a gate finger or a drain finger.

[0041] In some embodiments, each of the gate fingers, drain fingers, and / or source fingers can include finger segments spaced apart from one another, and respective extension regions can be disposed between the finger segments.

[0042] In some embodiments, at least one of the conductive pillar structures may be coupled to a plurality of gate fingers, a plurality of drain fingers, or a plurality of source fingers by one or more intervening metal layers therebetween.

[0043] In some embodiments, an insulating layer may extend over a surface of the semiconductor layer structure adjacent a top of the RF transistor amplifier die, and the conductive pillar structures may protrude from the insulating layer. A substrate may be provided on the semiconductor layer structure opposite the surface having the insulating layer thereon. Conductive via structures may extend through the substrate adjacent a bottom of the RF transistor amplifier die. Each of the conductive via structures may be configured to provide another input signal connection, an output signal connection, or a ground connection to the transistor cell.

[0044] In some embodiments, each of the conductive pillar structures may be disposed within an active area that includes a transistor cell to provide an input signal connection, an output signal connection, and a ground connection.

[0045] According to some embodiments, an integrated circuit device package includes a radio frequency ("RF") transistor amplifier die, the RF transistor amplifier die including a semiconductor layer structure including a plurality of transistor cells, an insulating layer on a surface of the semiconductor layer structure, and a plurality of conductive pillar structures protruding from the insulating layer opposite the surface of the semiconductor layer structure. The integrated circuit device package may further include a package substrate, the package substrate including a conductive connection pattern corresponding to an arrangement of the conductive pillar structures, each of the conductive pillar structures configured to attach the RF transistor amplifier die to the conductive connection pattern of the package substrate and provide an input signal connection, an output signal connection, or a ground connection to the transistor cells. The ground connection is disposed between the input signal connection and / or the output signal connection. Additionally or alternatively, the input signal connection is disposed between opposing ends of gate fingers of the transistor cells.

[0046] In some embodiments, the conductive pillar structures may protrude from an insulating layer adjacent a top of the RF transistor amplifier die, and a substrate may be provided on the semiconductor layer structure opposite a surface having the insulating layer thereon. The conductive via structures may extend through the substrate adjacent a bottom of the RF transistor amplifier die. Each of the conductive via structures may be configured to provide another input signal connection, an output signal connection, or a ground connection to the transistor cell.

[0047] In some embodiments, the input signal connection, the output signal connection, or the ground connection provided by each of the conductive pillar structures may be released from a wire bond connection pad that electrically connects to a gate finger, a drain finger, or a source finger of a transistor cell.

[0048] In some embodiments, a first subset of conductive pillar structures may be configured to provide a ground connection and may be disposed between a second and a third subset of conductive pillar structures that may be configured to provide input and output signal connections, respectively.

[0049] In some embodiments, a first subset of the conductive pillar structures may be configured to provide a ground connection and a second subset of the conductive pillar structures may be configured to provide one of an input signal connection or an output signal connection, and each conductive pillar structure of the second subset may be disposed between each conductive pillar structure of the first subset.

[0050] In some embodiments, a third subset of the conductive pillar structures may be coupled to the other of the input signal connection or the output signal connection, and each conductive pillar structure of the third subset may be disposed between each conductive pillar structure of the first subset.

[0051] In some embodiments, each of the conductive pillar structures may be disposed within an active area that includes a transistor cell to provide an input signal connection, an output signal connection, and a ground connection.

[0052] In some embodiments, the semiconductor layer structure may include one or more epitaxial layers of wide bandgap semiconductor material.

[0053] In some embodiments, the semiconductor layer structure may include III-nitride materials on a silicon carbide substrate.

[0054] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following drawings and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims. [Brief description of the drawings]

[0055] [Figure 1] 1 is a schematic plan view of an RF transistor amplifier die or device in accordance with some embodiments of the present disclosure. [Figure 2A]1A-1C are schematic cross-sectional views of RF transistor amplifier dies including transistor structures having various arrangements of front-side pillar connection structures in accordance with some embodiments of the present disclosure. [Figure 2B] 1A-1C are schematic cross-sectional views of RF transistor amplifier dies including transistor structures having various arrangements of front-side pillar connection structures in accordance with some embodiments of the present disclosure. [Figure 2C] 1A-1C are schematic cross-sectional views of RF transistor amplifier dies including transistor structures having various arrangements of front-side pillar connection structures in accordance with some embodiments of the present disclosure. [Figure 2D] 1A-1C are schematic cross-sectional views of RF transistor amplifier dies including transistor structures having various arrangements of front-side pillar connection structures in accordance with some embodiments of the present disclosure. [Figure 3A] FIG. 2 is a schematic plan view of an RF transistor amplifier die including an arrangement of front-side pillar connection structures without back-side connection pads or contacts, in accordance with some embodiments of the present disclosure. [Figure 3B] FIG. 2 is a schematic plan view of an RF transistor amplifier die including an arrangement of front-side pillar connection structures without back-side connection pads or contacts, in accordance with some embodiments of the present disclosure. [Figure 4] FIG. 2 is a schematic plan view of an RF transistor amplifier die including a front-side pillar connection structure and a back-side connection pad or contact arrangement according to some embodiments of the present disclosure. [Diagram 5] FIG. 1 is a schematic plan view of an RF transistor amplifier die including an arrangement of front side pillar connection structures coupled to source, gate, and drain fingers having interlaced input and output signal connections and a ground connection without intervening wire bond connection pads in accordance with some embodiments of the present disclosure. [Figure 6A1] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 6A2] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 6B1] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 6B2] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 6C1] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 6C2] 1A is a cross-sectional view of a front pillar connection structure in a bifurcated structure according to some embodiments of the present disclosure. [Figure 7A] FIG. 1 is a schematic plan view of an RF transistor amplifier die including an arrangement of front side pillar connection structures coupled to respective extensions at the edges of gate fingers, drain fingers, and source fingers with ground connections interlaced between the input signal connections and between the output signal connections, in accordance with some embodiments of the present disclosure. [Figure 7B] FIG. 1 is a schematic plan view of an RF transistor amplifier die including an arrangement of front side pillar connection structures coupled to respective extensions at the edges of gate fingers, drain fingers, and source fingers with ground connections interlaced between the input signal connections and between the output signal connections, in accordance with some embodiments of the present disclosure. [Figure 8A] FIG. 1 is a schematic plan view of an RF transistor amplifier die including an arrangement of front side pillar connection structures coupled to respective extensions between segments of gate fingers, drain fingers, and source fingers with ground connections interlaced between input signal connections and between output signal connections, in accordance with some embodiments of the present disclosure. [Figure 8B] FIG. 1 is a schematic plan view of an RF transistor amplifier die including an arrangement of front side pillar connection structures coupled to respective extensions between segments of gate fingers, drain fingers, and source fingers with ground connections interlaced between input signal connections and between output signal connections, in accordance with some embodiments of the present disclosure. [Figure 9A]1A-1C are cross-sectional views illustrating examples of attaching an RF transistor amplifier die to a package substrate using a front pillar connection structure according to some embodiments of the present disclosure. [Figure 9B] 1 is a plan view illustrating an example of attaching an RF transistor amplifier die to a package substrate using a front-side pillar connection structure in accordance with some embodiments of the present disclosure. [Figure 10] 1 is a cross-sectional view illustrating an example of a device package including an RF transistor amplifier die having a front-side pillar connection structure according to some embodiments of the present disclosure. [Figure 11] 1 is a cross-sectional view illustrating an example of a device package including an RF transistor amplifier die having a front-side pillar connection structure according to some embodiments of the present disclosure. [Figure 12] 1 is a cross-sectional view illustrating an example of a device package including an RF transistor amplifier die having a front-side pillar connection structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Embodiments of the present disclosure are directed to devices and manufacturing methods that can reduce or eliminate some of the disadvantages associated with wire bonds in integrated circuit device packages. For example, wire bonds can impose limitations on package size, signal routing, and assembly due to wire bulk and contact pad area requirements. In addition, wire bonds can introduce an undesirable set of inductances that can reduce or negate the effectiveness of matching circuits (including input / output impedance matching circuits and / or harmonic termination circuits), especially in higher frequency RF applications.

[0057] Some embodiments of the present disclosure provide integrated devices and manufacturing methods that use electrical connection structures on the front side or surface of an RF transistor amplifier die or device, such as conductive pillar structures (also referred to herein as front-side pillar connection structures, front-side pillar structures, or front-side pillars), alone or in combination with conductive via structures (also referred to herein as through-substrate vias or back-side vias), which provide back-side connections or contacts, thereby reducing or eliminating wire bond connections in the package. As used herein, the "front side" or "front surface" of a die or device may be adjacent to active transistor cells in a semiconductor layer structure of the device, and the "back side" or "backside" of a die or device may be opposite the front side (which in some embodiments may include a substrate on which the semiconductor layer structure is formed or otherwise provided).

[0058] The front pillars may be conductive structures (including metal plating or other metallic structures) that may be integrated on the wafer (i.e., using wafer level processing) to improve control over geometry with design flexibility for connecting the transistor die to the package, for example, using any combination of front pillars and backside connections where at least one of the input, output, or ground connections are provided by the front pillars. The front pillars may be fabricated using high resolution patterning methods, for example, stepper lithography. Defining the front pillar structures through lithography processes may enable more effective connection methods that may be used in highly integrated packaging systems, for example, heterogeneous system-on-package (SOP), 3D stacking, etc. In particular, devices including front pillars as described herein can be "flipped" with the front pillars facing downwards such that the front pillars can connect one or more terminals of the device (e.g., source, drain, and / or gate terminals of a transistor die) to other package substrates, including printed circuit boards (PCBs), redistribution layer (RDL) structures, and / or thermally enhanced packages (e.g., TEPAC or T3PAC packages), for external connections (e.g., input, output, and / or ground connections, also referred to as "off-chip" connections).

[0059] The front pillars can also be arranged to provide different routing of off-chip connections, including input and output signals routed on and off the transistor die. In particular, embodiments of the invention described herein provide methods and topologies including front pillars that can improve or optimize input / output RF signal integrity, packaging complexity, and transistor die design. Some embodiments may consider design tradeoffs regarding the transistor die surfaces (front and back), placement of grounds for proper or desired transistor function, and input and output signal routing in relation to signal integrity. For example, all three FET terminals (gate, drain, and source) may be routed to the same side of the die (e.g., front side) to provide input, output, and ground connections in some embodiments, while other embodiments may include various combinations of front pillars and backside connections. In RF IC designs that may require a backside ground plane, conductive through-substrate vias may be used for ground connections (e.g., for connections to FET source terminals). If multiple types of connections (e.g., both power and ground connections) are routed on the backside, a backside metal patterning process can be used to provide electrical isolation between the connection pads for each type of connection. In some embodiments, the front side pillar connections can eliminate the need for backside via connections.

[0060] FIG 1 is a schematic plan view of a portion of a semiconductor die 100 according to an embodiment of the present disclosure. Die 100 may include a power transistor device, e.g., a transistor cell of an RF power amplifier. FIGs 2A-2D are schematic cross-sectional views of unit cell transistor structures 200a-200d (collectively 200, also referred to herein as transistor structures or transistor cells) of device or die 100. The plan view of FIG 1 is taken along lines I-I' of FIGs 2A-2D.

[0061] As shown in Figures 1 and 2A-2D, a semiconductor layer structure 390, such as a semiconductor structure for a III-nitride or other wide bandgap semiconductor HEMT or MOSFET, may be formed on a substrate 322, such as a silicon carbide substrate or a sapphire substrate. The substrate 322 may be a semi-insulating silicon carbide substrate, which may be, for example, a 4H polytype of silicon carbide. Other silicon carbide candidate polytypes may include 3C, 6H, and 15R polytypes. The substrate 322 may be a High Purity Semi-Insulating (HPSI) substrate, available from Cree, Inc. The term "semi-insulating" is used descriptively herein and not in an absolute sense.

[0062] In some embodiments of the present disclosure, the silicon carbide bulk crystal of the substrate 322 has a crystallinity of about 1×10 5 The SiC substrate may have a resistivity of ohm-centimeters or greater. Methods for producing such SiC substrates are described, for example, in U.S. Patent No. RE34,861, U.S. Patent No. 4,946,547, U.S. Patent No. 5,200,022, and U.S. Patent No. 6,218,680, the disclosures of which are incorporated herein by reference in their entireties. Although silicon carbide may be employed as the substrate 322, it will be understood that embodiments of the present disclosure may utilize any suitable substrate for the substrate 322, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, and indium phosphide (InP).

[0063] Substrate 322 may be a silicon carbide wafer, and device 100 may be formed at least in part through wafer-level processing, which may then be diced to provide device 100 including a plurality of individual unit cell transistors (each designated herein as 200). In some embodiments, the thickness (e.g., in the vertical or Z direction in FIGS. 2A-2D ) of substrate 322 may be greater than 100 μm, greater than 200 μm, or greater than 400 μm. In some embodiments, transistor structure 200 may include a thinned substrate 322. In some embodiments, substrate 322 may be thinned to a thickness (e.g., in the vertical or Z direction) of about 100 μm or less, e.g., 75 μm or less, or 50 μm or less.

[0064] A semiconductor layer structure 390 is formed on a surface of the substrate 322 (or on an optional layer as described further herein). In the illustrated example, the semiconductor layer structure 390 is a wide bandgap semiconductor material formed by epitaxial growth and thus includes one or more epitaxial layers 324. Techniques for epitaxial growth of III-nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference in their entireties. While the semiconductor layer structure 390 is shown with reference to one or more epitaxial layers 324 for illustrative purposes, the semiconductor layer structure 390 may include additional layers / structures / elements, such as buffer and / or nucleation layer(s), on or between the substrate 322 and the one or more epitaxial layers 324, and / or a cap layer on the top surface 324A of the epitaxial layers 324. For example, an AlN buffer layer may be formed on the upper surface 322A of the substrate 322 to provide a suitable crystal structure transition between the silicon carbide substrate 322 and the remainder of the layers of the transistor structure 200. In addition, strain-balancing transition layer(s) may additionally and / or alternatively be provided, for example as generally described in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference in its entirety. The optional buffer / nucleation / transition layer may be deposited by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and / or hydride vapor phase epitaxy (HVPE).

[0065] 1 and 2A-2D, on the front side 100f of the die 100, a source contact 315 and a drain contact 305 may be formed on a surface 324A of the epitaxial layer 324 and may be laterally spaced apart from one another. A source region of the unit cell transistor 200 is the portion of the semiconductor layer structure 390 directly below the source contact 315, and a drain region of the unit cell transistor 200 is the portion of the semiconductor layer structure 390 directly below the drain contact 305. A gate contact 310 may be formed on the epitaxial layer 324 between the source contact 315 and the drain contact 305. The material of the gate contact 310 may be selected based on the composition of the epitaxial layer 324 and may be a Schottky contact in some embodiments. For example, nickel (Ni), platinum (Pt), nickel silicide (NiSi x Several materials capable of making Schottky contacts to III-nitride based semiconductor materials may be used, such as Cu, Cu, Pd, Cr, Tungsten (W), and / or Tungsten Silicon Nitride (WSiN). Gate contact 310, drain contact 305, and source contact 315 may provide the gate terminal, drain terminal, and source terminal, respectively, of each unit cell transistor 200.

[0066] The source contact 315 and / or the drain contact 305 may include a metal capable of forming an ohmic contact to a III-nitride based semiconductor material. Suitable metals include Ti, W, titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), NiSi x, titanium silicide (TiSi), titanium nitride (TiN), WSiN, and refractory metals such as Pt. Thus, the source contact 315 and / or the drain contact 305 may include an ohmic contact portion in direct contact with the epitaxial layer 324 (e.g., a barrier layer in a HEMT device). In some embodiments, the source contact 315 and / or the drain contact 305 may be formed from multiple layers to form an ohmic contact, which may be provided as described, for example, in commonly assigned U.S. Pat. Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference in their entireties.

[0067] In some embodiments, the transistor cell 200 may be a HEMT structure, and the epitaxial layer structure 324 may include a channel layer formed on the surface 322A of the substrate 322 and a barrier layer formed on the surface of the channel layer. The channel layer may have a bandgap that is less than the bandgap of the barrier layer, and the channel layer may also have a greater electron affinity than the barrier layer. The channel layer and the barrier layer may include III-nitride based materials. As discussed above, with respect to a conventional HEMT device, a 2DEG layer is induced in the channel layer at the junction between the channel layer and the barrier layer. The 2DEG layer may act as a highly conductive layer that allows electrical conduction between the source and drain regions of the device underlying the source and drain contacts 315 and 305, respectively. HEMT structures, including substrates, channel layers, barrier layers, and other layers, are illustratively discussed in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, and 7,709,269, the disclosures of which are hereby incorporated by reference in their entireties.

[0068] As will be appreciated by one of ordinary skill in the art, a transistor cell 200 (e.g., HEMT, MOSFET, LDMOS, etc.) may be defined by an active area between a source contact 315 and a drain contact 305 under control of a gate contact 310. In some embodiments, as illustrated in FIG. 1, the source contact 315, drain contact 305, and gate contact 310 may be formed as a plurality of alternating source contacts 315, drain contacts 305, and gate contacts 310 on an epitaxial layer 324 to form a plurality of transistor unit cells 200, with the gate contacts 310 being disposed between adjacent drain contacts 305 and source contacts 315. Hundreds or thousands of unit cells, such as unit cell 200, may be formed on a semiconductor substrate and electrically connected in parallel to provide an RF transistor amplifier die or device 100.

[0069] 1 and 2A-2D, die 100 may include multiple transistor cells 200, with their respective contacts connected in parallel to provide off-chip connections (e.g., input, output, or ground connections). For example, as shown in FIG. 1, each of gate 310, drain 305, and source 315 contacts may extend in a first direction (e.g., Y-direction) to define "fingers" of gate G, drain D, and / or source S, which in some embodiments may be connected by one or more optional buses (e.g., by gate bus 310b and drain bus 305b, shown in dashed lines in FIG. 1) and / or wirebond connection pads coupled thereto on or adjacent top surface 324A of semiconductor layer structure 390. The gate fingers G, drain fingers D, and source fingers S (and connection busses and wirebond connection pads) may form part of the gate, drain, and source connection electrodes, respectively, of the device 100, which in some embodiments may be defined by one or more top or front metallization layers or bus pads to which a front pillar 366 (shown in dashed lines in FIG. 1 ) described herein may be coupled. In other embodiments, the front pillar 366 may be coupled to one or more of the gate fingers G, drain fingers D, or source fingers S without an intervening bus pad or wirebond connection pad. Thus, the die 100 may be free of wirebond connection pads and / or connection busses at the edges of the die 100, such that the transistor cells 200 may occupy a larger area of ​​the die 100. The dielectric layers isolating the various conductive elements of the front metallization structure from one another are not shown in Figure 1 to simplify the illustration. It can be seen that the unit cell transistors 200 are all electrically connected together in parallel, with the gate fingers G electrically connected together, the drain fingers D electrically connected together, and the source fingers S electrically connected together.

[0070] As shown in FIGS. 2A-2D, the transistor cell 200 may further include one or more dielectric or insulating layers, illustrated as 350, 355, and 360 adjacent the front side 100f. The first insulating layer 350 may be in direct contact with the top surface of the semiconductor layer structure 390 (e.g., the top surface 324A of the epitaxial layer 324). The second insulating layer 355 may be formed on the first insulating layer 350, and the third insulating layer 360 may be formed on the second insulating layer 355. It will also be appreciated that in some embodiments, fewer or more than three insulating layers may be included. One or more of the insulating layers 350, 355, and / or 360 may serve as a passivation layer for the transistor structure 200. The insulating layers 350, 355, 360 may be formed of silicon nitride (SiN). x N y ), aluminum nitride (AlN), silicon dioxide (SiO2), silicon oxynitride, and / or other suitable protective materials, e.g., dielectric materials such as magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. More generally, insulating layer 350, 355, 360 may be a single layer or may include multiple layers of uniform and / or non-uniform composition and / or may be sufficiently thick to protect underlying epitaxial layer(s) 324 during subsequent annealing of the ohmic contacts (e.g., to provide source contact 315 and / or drain contact 305).

[0071] The source contact 315, the drain contact 305, and the gate contact 310 may be formed in a first insulating layer 350 adjacent to the front side 100f of the die 100. In some embodiments, at least a portion of the gate contact 310 may be on a surface of the first insulating layer 350. In some embodiments, the gate contact 310 may be formed as a T-gate and / or a gamma gate, the formation of which is illustratively discussed in U.S. Pat. Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated by reference herein in their entireties. A second insulating layer 355 may be formed on the first insulating layer 350 and on portions of the drain contact 305, the gate contact 310, and the source contact 315.

[0072] Each metal contact 365 may be formed extending through one or more of the insulating layer(s) 360, 355, 350 to contact one or more of the contacts 305, 310, 315. For example, the second insulating layer 355 may be patterned to form a window exposing the source contact 315 and / or the drain contact 305 for placement of the metal contact 365. The window may be etched using a patterned mask and a low damage etch process for the source contact 315 and / or the drain contact 305. A conductive metal may be formed on the exposed portions of the source contact 315 and / or the drain contact 305 to form the metal contact 365.

[0073] Metal contacts 365 may directly contact one or more of contacts 305, 310, 315 of transistor cells 200 on front side 100f of die 100. Metal contacts 365 may be used to provide connections to gate bus 310b, drain bus 305b, and / or source bus. Metal contacts 365 may comprise metal or other highly conductive materials, including, for example, copper, cobalt, gold, and / or composite metals. A third insulating layer 360 (of similar or different composition to insulating layers 350 and / or 355) may be formed over metal contacts 365 as a final passivation layer, which may be patterned to define openings exposing metal contacts 365 for electrical connections, for example, “off-chip” input and / or output signal connections to one or more external devices, and / or ground connections to electrical ground.

[0074] In particular, one of the terminals (e.g., gate contact 310) of each unit cell transistor 200 of the RF transistor amplifier die 100 may provide an input signal connection configured to be coupled to an RF input signal. One of the terminals (e.g., drain contact 305) of each unit cell transistor 200 may provide an output signal connection configured to output an RF output signal. One of the terminals (e.g., source contact 315) of each unit cell transistor 200 of the RF transistor amplifier die 100 may provide a ground connection configured to be coupled to a reference signal, such as an electrical ground. Thus, the metal contacts 365 may define input (e.g., gate), output (e.g., drain), or ground (e.g., source) contact pads or terminals that may be directly or indirectly connected to corresponding terminals (e.g., gate 310, drain 305, and / or source 315 terminals of a FET, such as a HEMT or LDMOS transistor) of one or more transistor structures 200 of the die 100.

[0075] In embodiments of the present disclosure, each conductive pillar structure 366 (also referred to herein as a front-side connection or pillar) may be formed on one or more of the metal contacts 365 on the front side 100f of the die 100. Thus, the front pillar 366 may be electrically connected to a respective terminal (e.g., a terminal of an input signal, an output signal, or a ground connection) of the unit cell transistor 200 and may protrude from the insulating layer 360 opposite and away from the surface 324A of the semiconductor layer structure 390. The front pillar 366 may have an oval or circular shape in plan view (e.g., similar to or corresponding to an opening exposing the metal contact 365). The front pillar 366 may be a relatively thick conductive plated structure in some embodiments. For example, the front pillar 366 may be a Cu or other metal plated structure. Thus, the front pillars 366 may provide respective electrical connections (e.g., input signal connections, output signal connections, or ground connections) between one or more terminals (e.g., input, output, ground) of the transistor cells 200 and one or more external devices, for example, as a "flip chip" (where the device 100 is flipped upside down and attached and electrically connected to the substrate or device(s) thereon by the pillars 366 adjacent the front side 100f of the device 100) and / or in a stacked multi-chip package. As shown in Figures 2A-2D, a solder layer 367 may be provided on the front pillars 366 for electrical connection and / or attachment.

[0076] 2A-2D illustrate non-limiting examples of various input signal connections, output signal connections, and ground connections that may be implemented using front side pillars 366 according to some embodiments of the present invention. In particular, in some embodiments as shown in FIG. 2A, front side pillars 366 are electrically coupled to all three terminals (gate 310, drain 305, and source 315) of transistor structure 200a to provide input signal connections, output signal connections, and ground connections, respectively, at front side 100f of die 100, for example.

[0077] 2B, front side pillar 366 is electrically coupled to the gate 310 and drain 305 terminals of transistor structure 200b to provide input and output signal connections, respectively, on front side 100f of die 100. Conductive via connections or structures 368 (also referred to herein as backside vias) extend through substrate 322 and epitaxial layer 324 to couple source contact 315 to metal contact 345 on back side 100b of die 100 to provide a ground connection, for example.

[0078] 2C, the front side pillar 366 is electrically coupled to the gate terminal 310 of the transistor structure 200c, for example, to provide an input signal connection on the front side 100f of the die 100. Respective conductive through-substrate via connections 368 extend through the substrate 322 and the epitaxial layer 324 to couple the source contact 315 and the drain contact 305 to respective metal contacts 345 on the back side 100b of the die 100, for example, to provide a ground connection to the source contact 315 and to provide an output signal connection to the drain contact 305. A backside metal patterning process may be used to provide electrical isolation between the respective metal contacts 345.

[0079] 2D , front-side pillar 366 is electrically coupled to drain 305 and source 315 terminals of transistor structure 200d on front side 100f of die 100 to provide, for example, an output signal connection and a ground connection, respectively. A conductive through-substrate via connection or structure 368 extends through substrate 322 and epitaxial layer 324 to couple gate 310 to metal contact 345 on backside 100b of die 100 to provide, for example, an input signal connection.

[0080] 2C and 2D, transistor structures in which input and / or output signal connections are routed through the substrate 322 may be referred to herein as "hot via" configurations. More generally, in embodiments of the invention, a front pillar 366 may provide a connection to one or more transistor terminals (e.g., input, output, ground) on the front side 100f of the device 100 in some examples in various combinations with one or more back side vias 368, which provide a connection to the other of the transistor terminals (e.g., input, output, ground) on the back side 100b of the device 100. That is, embodiments of the invention may include any combination of front pillars 366 and back side vias 368 each providing an input signal connection, an output signal connection, or a ground connection.

[0081] The front side 100f of the device 100, including the front side pillars 366 protruding from the insulating layer 360, may be "flipped" and attached (front side 100f facing down) to a wafer carrier (e.g., to provide structural support for further processing operations) or to a package substrate (e.g., a printed PCB or RDL structure) so that the front side pillars 366 are physically attached to and electrically connected, e.g., by solder layer 367, to corresponding conductive traces on the package substrate for electrical signal routing. Although the front side pillars 366 may protrude from the insulating layers 350, 355, 360 of the device 100, in some embodiments, additional support layers (e.g., additional insulating layers and / or adhesive layers) may surround or encapsulate the pillars 366 for mechanical support. An RDL structure refers to a substrate or laminate having a conductive layer pattern and / or conductive via structure (referred to herein as conductive vias). The RDL structures may be fabricated using semiconductor processing techniques, for example, by depositing conductive and insulating layers and / or patterns on a substrate and forming vias and copper routing patterns within the structures for transmitting signals through the RDL structures, thereby reducing or eliminating, in some embodiments, the need and / or use of wire bonds (which may introduce a series of inductances that may reduce or negate the effectiveness of impedance matching networks and / or harmonic termination circuits, especially in higher frequency RF applications).

[0082] Additionally, depending on the package integration, front side pillars 366 may provide some chip-chip or chip-board isolation by allowing placement of connection pads or pillars with any combination of front side and / or back side input / output / ground connections away from the edge or perimeter of die 100, may increase heat dissipation from front side 100f of device 100, may increase mechanical strength, and / or may increase design flexibility (especially in "flip chip" packages). Manufacturing operations for forming devices including placement of front side pillars 366 according to some embodiments of the present invention are described, for example, in U.S. patent application Ser. No. 16 / 889,432 to Alcorn et al., the disclosure of which is incorporated herein by reference.

[0083] Embodiments of the present invention may include any combination whereby the front pillar structures provide at least one of an input signal connection, an output signal connection, or a ground connection. For example, an arrangement of front pillars in relation to gate lines or fingers (e.g., in a linear or "strip" arrangement, or in a sparse or "dot" arrangement) may be used to reduce gate resistance and / or increase RF signal isolation. In particular, some embodiments of the present invention may provide an arrangement of front pillars coupled to one or more of the input, output, or ground connections of a transistor cell, and disposed between the input and output signal connections (to increase RF signal isolation therebetween) and / or between opposing ends of the gate fingers (to shorten the RF signal propagation path and thus reduce resistance). Various combinations of front pillars and backside connections according to embodiments of the present disclosure are described below with reference to the illustrative examples of Figures 3A-3B, 4, 5, 7, and 8.

[0084] 3A is a schematic plan view of an RF transistor amplifier die according to some embodiments of the present disclosure. As shown in FIG. 3A, the transistor amplifier die 300a includes front pillar connections 366 coupled to the gate contact 310, the drain contact 305, and the source contact 315 to provide input signal connections, output signal connections, and ground connections, respectively, at the front side 100f of the die 300a without the use of backside contacts. Thus, the front pillars 366 are electrically connected to terminals (e.g., input signal, output signal, or ground connection terminals) of the unit cell transistor 200 and protrude (in the Z-direction) from the insulating layer 360 opposite and away from the surface 324A of the semiconductor layer structure 390. In particular, front pillar 366 providing an input signal connection is coupled to wirebond connection pad 310g (electrically connected to gate bus 310b), and front pillar 366 providing an output signal connection is coupled to wirebond connection pad 305d (electrically connected to drain bus 305b). Front pillar 366 providing a ground connection is coupled to source contacts 315 between opposing ends of source fingers S with either a free or no intervening wirebond connection pad in the electrical connection path.

[0085] Front pillars 366, which provide the input, output, and ground connections, are aligned with corresponding conductive connection patterns (shown in dashed lines in FIG. 3A as “conductive strips” 321g, 321d, and 321s extending along the width of die 300a in the X-direction) on the package substrate to provide a single input RF signal path, a single output RF signal path (in the Y-direction) between opposing edges of die 300a. In other words, the package substrate (on which die 300a may be mounted) includes conductive connection strips 321g, 321d, and 321s aligned with pillars 366, which provide the input, output signal, and ground connections, respectively. A front pillar 366 providing a ground connection (e.g., coupled to source finger S) is disposed between the input signal connection and the output signal connection (e.g., as provided by front pillar 366 coupled to pads 310g and 305d), which may improve isolation between the RF input signal and the RF output signal. A package substrate to which die 300a may be attached may include connection strips 321g, 321d, and 321s correspondingly disposed as gate, drain, and source pads, respectively.

[0086] 3A with reference to two front pillars 366 connected to each source finger S, it will be understood that fewer or more front pillars 366 may be connected to each source finger S, and that more pillars 366 per finger S may reduce the source impedance. Also in FIG. 3A, the front pillar 366 providing the input signal connection is coupled to pad 310g (electrically connected to gate bus or manifold 310b), and the front pillar 366 providing the output signal connection is coupled to pad 305d (electrically connected to drain bus or manifold 305b), with wire bond connection pads 310g and 305d positioned on opposing edges of die 300a. Thus, the RF signal must propagate the entire length between the opposing edges of die 300a (along the Y-direction), and as a result, the input signal path may have a relatively high resistance, which may result in latency issues and / or losses, especially at higher operating frequencies.

[0087] 3B is a schematic plan view of an RF transistor amplifier die including an arrangement of front pillar connection structures without backside connection pads or contacts according to a further embodiment of the present disclosure. As shown in FIG. 3B, the transistor amplifier die 300b includes front pillar connections 366 coupled to the gate contact 310, the drain contact 305, and the source contact 315 at the front side 100f of the die 300b to provide input signal connections, output signal connections, and ground connections, respectively. The front pillars 366 protrude (in the Z-direction) from the insulating layer 360 opposite and away from the surface 324A of the semiconductor layer structure 390, so that the die 300b may be free from the backside contacts. In particular, the front pillar 366 providing the output signal connection is coupled to wire bond connection pad 305d (electrically connected to drain bus 305b) and the front pillar 366 providing the ground connection is coupled to wire bond connection pad 315s (electrically connected to source bus 315b). The front pillar 366 providing the input signal connection is free from the wire bond connection pad in an electrical connection path therebetween and is coupled to the gate contact 310 between the opposing ends of the gate finger G. Although shown in FIG. 3B with reference to two front pillars 366 connected to each gate finger G, it will be understood that fewer or more front pillars 366 may be connected to each gate finger G. In some embodiments, each front pillar 366 providing the input signal connection may be connected to two or more gate fingers G, which may be referred to as a "bifurcated" gate connection. For example, in a bifurcated gate connection, the front pillars 366 may be coupled to respective gate contacts 310 via a common upper level (e.g., M2) metal layer that connects respective lower level (e.g., M1) metal layers and the M1 metal layer, as shown in Figure 6A2. The front pillar 366 connection between opposing ends of the gate fingers G may increase uniformity with respect to signal timing or propagation delay, and the bifurcated gate arrangement may allow for increased density of the gate fingers G (such that multiple gate fingers G may be connected to one front pillar 366).

[0088] The front pillars 366 providing the input, output, and ground connections are aligned with corresponding conductive pad structures (shown in dashed lines in FIG. 3B as connection strips 321g, 321d, and 321s extending along the width of the die 300b in the X-direction) on the package substrate to provide a single input RF signal path and a single output RF signal path. Thus, the front pillars 366 providing the ground connection (e.g., coupled to the source finger S) are disposed at one edge of the die 300b, and the front pillars 366 providing the input signal connection (e.g., coupled to the gate finger G) are disposed between the ground and output signal connections at the opposing edge of the die. A package substrate to which the die 300b may be attached may include correspondingly disposed connection strips 321g, 321d, and 321s.

[0089] The placement of the front pillar 366 providing the input signal connection coupled to the gate finger G in the middle of the die 300b may shorten the input signal path length, thereby reducing the gate resistance Rg and improving the RF gain. However, in comparison to the die 300a of FIG. 3A, the die 300b places the front pillar 366 providing the input signal connection between the wire bond connection pads 315s and 305d providing the ground connection and the output signal connection, respectively, at the opposing edges of the die 300b. The closer proximity of the front pillar 366 providing the input signal connection to the output signal connection provided by the front pillar 366 coupled to the drain bus pad 305d may reduce the isolation between the RF input signal and the RF output signal.

[0090] Providing all of the input, output, and ground connections on the front side 100f of the transistor die using front pillars 366 as described herein can be advantageous in terms of manufacturing complexity, and further embodiments of the present disclosure can include front pillars 366 in combination with backside contacts 345. However, it will be understood that any combination of front pillars providing at least one of an input signal connection, an output signal connection, or a ground connection can be used.

[0091] 4 is a schematic plan view of an RF transistor amplifier die including a front pillar connection structure and an arrangement of backside connection pads or contacts according to some embodiments of the present disclosure. As shown in FIG. 4, a transistor amplifier die 400 includes a front pillar 366 coupled to a gate contact 310 and a drain contact 305 to provide input and output signal connections, respectively, at a front surface 100f of the die 400 in combination with a backside contact 345 coupled to a source contact 315 by a conductive through-substrate via 368 to provide a ground connection. Thus, the front pillar 366 protrudes (in the Z-direction) from the insulating layer 360 away from the surface 324A of the semiconductor layer structure 390 and opposite the surface 322B that includes the backside contact 345.

[0092] In particular, front pillar 366 providing the input signal connection is coupled to wirebond connection pad 310g, front pillar 366 providing the output signal connection is coupled to wirebond connection pad 305d, and ground connection is provided by backside contacts 345 coupled to source contacts 315 by respective through-substrate vias 368 from backside surface 100b. Through-substrate vias 368 providing ground connections are coupled to source contacts 315 between opposing ends of source fingers S and extend through semiconductor layer structure 390 and substrate 322 to provide electrical connection with backside contacts 345.

[0093] The front pillars 366 providing the input and output signal connections are aligned with corresponding conductive pad structures (shown in FIG. 4 by dashed lines as connection strips 321g and 321d extending along the width of die 400 in the X-direction) on the package substrate to provide a single input RF signal path, a single output RF signal path (in the Y-direction) between opposing edges of die 400. However, without the front pillars 366 interposing ground connections between the front pillars 366 providing the input and / or output signal connections, the series of input-output connections shown in FIG. 4 may present challenges with regard to RF signal isolation, and the proximity of the inputs to outputs may present limitations for higher power applications.

[0094] 5, 7, and 8 illustrate examples where input and / or output signal connections are interlaced with ground connections. Although illustrated in Figures 5, 7, and 8 with reference to input signal connections, output signal connections, and ground connections provided by front-side pillars without back-side contacts, it will be understood that in some embodiments, one or more of the input connections, output connections, or ground connections may be routed to the back-side of the die using respective conductive vias 368 as described herein.

[0095] 5 is a schematic plan view of an RF transistor amplifier die with interlaced ground and input and output signal connections according to some embodiments of the present disclosure. As shown in FIG. 5, the transistor die 500 includes front pillars 366 coupled to gate contacts 310, drain contacts 305, and source contacts 315 between opposing ends of gate fingers G, drain fingers D, and source fingers S, respectively, rather than external wirebond connection pads or bus pads at the edges of the die 500. The front pillars 366 provide input signal connections, output signal connections, and ground connections, and are aligned with corresponding conductive connection patterns or pad structures (shown in FIG. 5 as dashed lines extending along the width of the die 500 in the X-direction) on the package substrate to provide a single input RF signal path, a single output RF signal path (in the X-direction) between opposing edges of the die 500.

[0096] Front pillars 366 providing ground connections (e.g., coupled between opposing ends of source fingers S) are arranged in an alternating or interlaced manner with front pillars 366 providing input signal connections (e.g., coupled to opposing ends of gate fingers G) and output signal connections (e.g., coupled between opposing ends of drain fingers D), referred to herein as a GSG (ground-signal-ground) configuration. In particular, in FIG. 5 , front pillars 366 providing input signal connections (e.g., coupled to gate fingers G) are arranged between front pillars 366 providing ground connections (e.g., coupled to source fingers S) in an input GSG configuration. Similarly, front pillars 366 providing output signal connections (e.g., coupled to drain fingers D) are arranged between front pillars 366 providing ground connections in an output GSG configuration. However, it will be appreciated that in some embodiments, either the input signal connections or the output signal connections may be arranged alternately or interlaced with ground connections, i.e., RF signal connections (at the input, at the output, or both) may be provided in a GSG configuration by interlacing front pillars 366 that provide ground connections therebetween.

[0097] The package substrate (on which the transistor die 500 can be inverted and mounted with the front pillars 366 facing down or towards the surface of the package substrate) includes connection strips 321g, 321d, and 321s aligned to correspond with the arrangement of the front pillars 366 providing gate, drain, and source pads for the input, output, and ground connections, respectively. In particular, the package substrate includes input (e.g., gate) connection strips 321g interlaced or interdigitated between adjacent ground (e.g., source) connection strips 321s and output (e.g., drain) connection strips 321d interlaced or interdigitated between adjacent ground connection strips 321s. That is, the conductive routing 321g, 321d, and 321s in and / or on the package substrate are arranged to correspond to the input and / or output GSG configurations. In the example of FIG. 5, intermediate connecting strips 321s are included in both the input GSG and the output GSG.

[0098] The input and / or output GSG configurations may improve RF isolation between the input and output RF signals and improve signal integrity by effectively sandwiching the input (and / or output) signal connections between adjacent ground connections. Also, locating the front pillars 366 providing the input signal connections between opposing ends of the gate fingers G may shorten the input signal propagation path, thereby reducing resistance Rg. The respective locations of the front pillars 366 may also be positioned to address and / or smooth out signal latency issues.

[0099] 5, front side pillars 366 are coupled to gate fingers G, drain fingers D, and source fingers S without intervening wire bond connection pads or bus pads therebetween. That is, transistor die 500 may be free of wire bond connection pads, such as gate bus, drain bus, and / or source bus / bond pads, with each front side pillar extending through one or more of insulating layers 350, 355, and / or 360 to contact gate contact 310, drain contact 305, and / or source contact 315 (or an intervening metal layer 365 electrically connected to contacts 310, 305, 315). By locating the front side pillars 366 in a central area of ​​the die including the active area 502 for the transistor cells 200 (rather than at the edge of the die 500) so as to provide input, output, and / or ground connections without intervening wire bond connection pads or bus pads, the gate fingers G, drain fingers D, and / or source fingers S can extend along up to the entire length of the die 500, thereby increasing the available area on the die 500 for the transistor active area 502.

[0100] As shown in Figures 6A1, 6B1, and 6C1, a front pillar 366 providing an input signal connection, an output signal connection, or a ground connection may, in some embodiments, be coupled to a gate 310, drain 305, or source 315 contact, respectively, by one or more intervening metal layers M1, M2. Alternatively, as shown in Figures 6A2, 6B2, and 6C2, each front pillar 366 providing an input signal connection, an output signal connection, or a ground connection may be coupled to multiple (illustrated as two) gate contacts 310, drain contacts 305, or source contacts 315, respectively, in a bifurcated arrangement. For example, each front pillar 366 may be coupled to a respective gate contact 310, drain contact 305, or source contact 315 via a respective M1 metal layer and an M2 metal layer connecting the M1 metal layer. Coupling the front pillars 366 to the contacts 310, 305 in a branched structure may increase uniformity with respect to signal timing or propagation delay, such that the front pillars 366 may be arranged to provide similar input or output signal path lengths to the respective contacts 310, 305 while increasing the density of the fingers G, D, S (such that multiple narrower fingers G, D, S may be connected to one front pillar 366).

[0101] 7A and 7B are schematic plan views of an RF transistor amplifier die including an arrangement of front pillar connection structures coupled to respective extensions at the edges of the gate, drain, and source fingers with ground connections alternating or interlaced between the input signal connections and between the output signal connections, according to some embodiments of the present disclosure. As shown in FIG. 7A and 7B, the transistor die 700a, 700b includes a front pillar 366 coupled to the gate finger G, the drain finger D, and the source finger S (and thus the contacts of the gate 310, the drain 305, and the source 315) by respective extensions 310e, 305e, and 315e at the opposing edges of the fingers G, D, and S. The extensions 310e, 305e, 315e (also referred to herein as finger extensions or extension regions) and the front pillars 366 connected thereto are aligned with corresponding conductive connection patterns or pad structures (shown in dashed lines in FIGS. 7A and 7B as “connection dots” 721g, 721d, and 721s spaced apart from one another along the width or in the X-direction) on the package substrate to provide a single input RF signal path, a single output RF signal path (in the Y-direction) between the opposing edges of the dies 700a, 700b. In other words, the package substrate (on which the dies 700a, 700b may be mounted) includes a conductive connection pattern implemented by connection dots 721g, 721d, and 721s, which are aligned with the front pillars 366 that provide the input signal connection, the output signal connection, and the ground connection, respectively.

[0102] Although the transistor dies 700a, 700b include input and output signal connections with ground connections arranged in an interlaced or alternating manner in the GSG configuration, it will be understood that in some embodiments, either the input or output signal connections may be arranged interlaced with the ground connections. In particular, the front pillars 366 providing the input signal connections (e.g., coupled to the gate finger extensions 310e) are arranged between the front pillars 366 providing the ground connections (e.g., coupled to the source finger extensions 315e) in the input GSG configuration. Additionally or alternatively, the front pillars 366 providing the output signal connections (e.g., coupled to the drain finger extensions 305e) are arranged between the front pillars 366 providing the ground connections in the output GSG configuration.

[0103] The package substrate (on which the dies 700a, 700b may be mounted) may include connection dots 721g, 721d, and 721s as gate, drain, and source pads arranged corresponding to the arrangement of the front pillars 366 on the extension regions 310e, 305e, and 315e to provide input, output, and ground connections. In particular, the input (e.g., gate) connection dots 721g may be alternated or interlaced between adjacent ground (e.g., source) connection dots 721s along one edge of the package substrate, and the output (e.g., drain) connection dots 721d may be alternated or interlaced between adjacent ground connection dots 721s along an opposing edge of the package substrate. Thus, input and output GSG configurations may be provided at the gate finger level, drain finger level, and source finger level, with respective connection dots 721g, 721d, or 721s coupled to respective fingers G, D, or S by respective front pillars 366 and finger extensions 310e, 305e, or 315e. Die 700b of FIG. 7B includes additional front pillars 366 coupled to source fingers S between their opposing ends (i.e., between the input GSG and output GSG) aligned with a connection pattern of additional source pads or straps 721s' on the package substrate (shown with dashed lines in FIG. 7B) to provide additional input-output isolation in a manner similar to source pads 321s discussed above with reference to FIG. 3A.

[0104] The package substrate may further include electrical connections therein or thereon that electrically connect to the input connection dots 721g or the output connection dots 721d to route RF signals into or out of the package. For example, in the illustrated devices 700a, 700b of Figures 7A and 7B, the package substrate may include conductive traces coupling an RF input signal path and conductive traces coupling an RF output signal path for routing RF signals into and out of the package, respectively.

[0105] The input and / or output GSG configurations may reduce or avoid signal interference between parallel input connections and / or parallel output connections by providing RF signal isolation for the respective input and / or output signal paths. For example, in some conventional designs, an input or output to a die may include an input or output wire bundle containing multiple input or output wire bonds, but signals propagating within each input or output wire bundle may interfere with each other. To mitigate interference between signals propagating on adjacent input or output wires, off-pad (e.g., pad-to-pad) resistors may be used in such designs. However, the input and / or output GSG configurations described herein may include an intervening ground connection between signals propagating on adjacent input or output signal paths, thereby increasing isolation and reducing or avoiding signal interference within each input bundle 310e or output bundle 305e without using resistors between adjacent input finger extensions 310e and / or between adjacent output finger extensions 305e.

[0106] 7A , front pillar 366 is coupled to gate finger extension 310e, drain finger extension 305e, and source finger extension 315e at opposing ends of die 700a in an area outside of transistor active area 702 (including gate finger G, drain finger D, and source finger S thereon). That is, extension regions 310e, 305e, and / or 315e may be provided at opposing ends of fingers G, D, S such that active area 702 of transistor die 700a may be freed from front pillar connection 366.

[0107] 7A and 7B, a subset of gate fingers G are coupled to a common front pillar 366 by respective gate finger extensions 310e and are electrically isolated from other subsets of gate fingers G by interlaced or interdigitated source finger extensions 315e. The isolation between the subsets of gate fingers G may allow for greater gate density within the active area 702. A subset of drain fingers D are similarly coupled to each front pillar 366 by respective drain finger extensions 305e and are electrically isolated from other subsets of drain fingers D by interlaced or interdigitated source finger extensions 315e. That is, ground extension regions 315e may be provided between the input extension regions 310e on one side of the die 700a, 700b and / or between the output extension regions 305e on the other side of the die 700a, 700b to provide isolation between the respective GSG groups defined by the front pillars 366. In other words, the input and / or output signal connections may each include multiple (shown as three) GSG configurations, with isolation provided by the ground extensions 315e interlaced or interleaved between the extension regions 310e or 305e in each GSG group. In FIG. 7B, additional isolation is provided between the input and output signal connections by the pillars 366 positioned to be coupled to the source straps 721s′.

[0108] Transistor dies 700a, 700b include an illustrative pattern of extension regions 310e, 305e, 315e, with each input extension region 310e and output extension region 305e disposed opposite a ground connection 315e, although embodiments of the invention are not limited to such an arrangement. Similarly, although shown in Figures 7A and 7B with reference to one front pillar 366 connected to each extension region 310e, 305e, 315e, it will be understood that fewer or more front pillars 366 may be connected to each source finger S, and that more pillars 366 per finger S may reduce the source impedance. 7A and 7B, the front pillar 366 providing the input signal connection is coupled to the gate extension 310e, and the front pillar 366 providing the output signal connection is coupled to the drain extension 305e, where the extensions 310e and 305e are located on opposite edges of the die 700a, 700b. Thus, the RF signal must propagate the entire length between the opposite edges of the die 700a, 700b (along the Y-direction), and as a result, the input signal path may have a relatively high resistance, which may result in latency issues and / or losses, especially at higher operating frequencies.

[0109] 8A and 8B are schematic plan views of an RF transistor amplifier die including an arrangement of front pillar connection structures coupled to respective extensions between segments of gate, drain, and source fingers with ground connections interlaced between input signal connections and between output signal connections, according to some embodiments of the present disclosure. As shown in FIG. 8A and 8B, transistor die 800a, 800b includes front pillar 366 coupled to respective segments of gate finger G, drain finger D, and source finger S (and thus contacts of gate 310, drain 305, and source 315) by respective extensions 310e, 305e, and 315e. In FIG. 8A and 8B, extensions 310e, 305e, and 315e (also referred to as finger extensions or extension regions) are disposed between segments of fingers G, D, and S. The extensions 310e, 305e, 315e and their connected front pillars 366 are aligned with corresponding conductive pad structures on the package substrate (shown in dashed lines in FIGS. 8A and 8B as connection dots 821g, 821d, and 821s spaced apart from one another along the width or in the X-direction) arranged to provide a central input RF signal path or gate feed, in this example, with two output RF signal paths at opposite ends or edges of the dies 800a, 800b. However, it will be understood that the patterns shown in FIGS. 8A and 8B may be repeated in one or more directions (e.g., along the X-direction and / or Y-direction). Thus, the configuration of front pillars 366 in the transistor dies 800a, 800b of FIGS. 8A and 8B may provide respective input signal connections (RF inputs) between pairs of output signal connections (RF outputs).

[0110] The package substrate includes connection dots 821g, 821d, and 821s arranged to align with the arrangement of front pillars 366 providing input, output, and ground connections, respectively. In particular, input (e.g., gate) connection dots 821g may be interlaced between adjacent ground (e.g., source) connection dots 821s between finger segments G, D, S, and output (e.g., drain) connection dots 821d may be interlaced between adjacent ground connection dots 821s at the edges of finger segments G, D, S. Thus, input and output GSG configurations may be provided at the gate finger level, drain finger level, and source finger level, with each connection dot 821g, 821d, or 821s coupled to a respective segment of finger G, D, or S by a respective front pillar 366 and finger extension 310e, 305e, or 315e. The package substrate may further include electrical connections therein or thereon that electrically connect the input connection dots 821g or the output connection dots 821d for routing RF signals into or out of the package, respectively. For example, in the illustrated devices 800a, 800b of Figures 8A and 8B, the package substrate may include conductive traces coupling RF input signal paths in a central region of the die 800a, 800b and conductive traces coupling RF output signal paths at opposing edges of the die 800a, 800b for routing RF signals into or out of the package, respectively. In the example of Figure 8B, the package substrate may include additional conductive traces 821s' coupling ground connections between the input and output signal paths.

[0111] In the example of Figures 8A and 8B, subsets of gate fingers G are coupled to a common front pillar 366 by respective gate finger extensions 310e (positioned between segments of the gate fingers G) and are electrically isolated from other subsets of gate fingers G by interlaced source finger extensions 315e. That is, individual segments of fingers G, S, D are separated from one another by extension regions 310e, 315e that provide input GSG configurations. Ground extension regions 315e may be provided between the input extension regions 310e and between opposing pairs of output extension regions 305e in the central regions of the dies 800a, 800b to provide isolation between the respective GSG groups defined by the front pillars 366. Die 800b in FIG. 8B includes additional front-side pillars 366 coupled to source fingers S between their opposing ends (i.e., between the input GSG and output GSG) aligned with a connection pattern of additional source pads or straps 821s' on the package substrate (shown with dashed lines in FIG. 8B) to provide additional input-output isolation in a manner similar to the source pads 321s discussed above with reference to FIG. 3A.

[0112] 7A and 7B, input and / or output signal connections may be defined by multiple GSG configurations, with isolation between groups of fingers G or D carrying input and output signals provided by front pillars 366 and ground extensions 315e coupled to source fingers S interlaced between front pillars 366 and extensions 310e or 305e in each GSG group. Isolation between subsets of gate fingers G by intervening front pillars 366 and extension regions 315e may allow for higher gate density in active area 802. Additionally, in comparison to the configurations of FIGS. 7A and 7B, providing front pillars 366 and extension regions 310e for input signal connections between segments of gate fingers G may reduce gate resistance Rg, as the signal path between the RF input and RF output may be shorter (i.e., in terms of the length of each segment of gate finger G).

[0113] Thus, embodiments of the present invention may include any combination of front-side pillars and back-side connections, where at least one of the input signal connection, the output signal connection, or the ground connection is provided by the front-side pillar. Compared to the use of wirebond connections with wirebond connection pads (e.g., 310g, 305d), a topology including conductive pillar structures 366 according to embodiments of the present disclosure may shorten connection paths and / or allow for more complex input / output / ground connection patterns. For example, accessing the input path in the middle of the gate fingers in the active area may significantly reduce gate resistance and improve RF gain. Additionally or alternatively, additional isolation for input and / or output signal integrity may be achieved by interlacing conductive pillar structures 366 providing input and / or output signal connections with conductive pillar structures 366 providing ground strips or dots. Various arrangements of conductive pillar structures 366 on the front side of the die in combination with conductive via structures 368 providing connections to the back side of the die may increase package integration options.

[0114] 9A and 9B are cross-sectional and plan views, respectively, illustrating an example of substrate mounting of an RF transistor amplifier die with a front pillar connection structure according to some embodiments of the present disclosure. Referring to FIG. 9A, a transistor die 900 including a conductive front pillar structure 366 according to any of the previous embodiments may be freed from wire bond connection pads, in some embodiments, and mounted on a package substrate 920 to provide off-chip electrical connections.

[0115] 9A, the die 900 is "flipped" with the front side 100f facing the surface of the package substrate 920 such that the front pillars 366 physically attach the die 900 to the package substrate 920 and electrically connect the transistor cells (e.g., by solder layers 367) to corresponding conductive connection patterns (shown as conductive traces 921) on the package substrate 920 to provide input signal connections, output signal connections, or ground connections for electrical signal routing into and out of the device package (examples of which are shown in FIGS. 10-12). In some embodiments, the package substrate can include a thermally conductive heat sink (e.g., a conductive flange of a thermally enhanced package) for both electrical signal routing (e.g., a bond to electrical ground) and for heat transfer through the substrate (examples of which are shown in FIGS. 11-12).

[0116] Referring to FIG. 9B, a package substrate 920 includes conductive connection patterns or traces 921 that correspond to the arrangement of conductive pillar structures 366 on die 900 to provide input signal connections, output signal connections, and / or ground connections.

[0117] For example, the package substrate 920 may be a PCB or RDL structure, and the conductive pattern or trace 921 may couple RF input signal paths and conductive traces that couple RF output signal paths for routing into and out of the package. By way of example, the routing of the conductive pattern or trace shown in FIG. 9B implements interdigitated connection strips 921g, 921d, 921s that provide respective input and output GSG configurations. However, it will be understood that a package substrate according to an embodiment of the present disclosure may include conductive connection patterns therein or thereon that correspond to any arrangement of conductive pillar structures, including but not limited to those described herein.

[0118] FIG. 10 is a cross-sectional view illustrating an example of an overmolded-type integrated circuit device package including an RF transistor amplifier die 900 according to some embodiments of the present disclosure. As shown in FIG. 10, the package 1000 includes a device 900 having components and connections similar to any of the embodiments described herein, inverted and mounted by front pillars 366 and a die attach material layer (e.g., solder layer 367) to respective conductive traces 1021 on a substrate 1020, such as a PCB or RDL structure. In the example of FIG. 10, an overmolded-type packaging material 1013 may substantially surround or encapsulate the device 100 and provide access to package leads (e.g., gate and drain leads) 1011i, 1011o (collectively 1011) via wire bond connections 1025 for connection to a circuit or device outside the package 1000. The overmold 1013 may be formed from a plastic or plastic-polymer compound, thereby providing protection from the external environment. Some advantages of the overmold-type packaging material 1013 include reducing the overall height or thickness of the package 1000, as well as design flexibility for placement of the leads 1011 and / or spacing between the leads 1011.

[0119] In particular, in the example of FIG. 10, input lead 1011i is coupled to gate 310 by wire bond 1025, conductive trace 1021 on package substrate 1020, and corresponding front-side pillar 366, output lead 1011o is coupled to drain 305 by wire bond 1025, conductive trace 1021 on package substrate 1020, and corresponding front-side pillar 366, and source 315 is grounded through conductive trace 1021 on package substrate 102 and corresponding front-side pillar 366.

[0120] 11 and 12 are cross-sectional views illustrating examples of thermally enhanced integrated circuit device packages including an RF transistor amplifier die 100, according to some embodiments of the present disclosure. As shown in FIG. 11 and FIG. 12, the open-cavity packages 1100, 1200 include a device 900 having components and connections similar to any of the embodiments described herein, but mounted on a conductive base or flange 1120, 1220 and protected by a lid member 1113, 1213 of the thermally enhanced package. In particular, FIG. 11 illustrates a first implementation of the thermally enhanced package (which may be referred to as a TEPAC package 1100) and FIG. 12 illustrates a second implementation of the thermally enhanced package (which may be referred to as a T3PAC package 1200), according to embodiments of the present disclosure. In some embodiments, the flanges 1120, 1220 may provide both a mounting surface for the die 900 and the PCB or RDL structure 1020 (and / or other components of the package) as well as thermal conductivity (e.g., heat sinking) to dissipate or otherwise transfer heat generated by the components out of the package 1100, 1200. The flanges 1120, 1220 may also provide one of the terminals for the package 1100, 1200. For example, the flanges 1120, 1220 may be configured to provide an electrical ground connection.

[0121] The TEPAC package 1100 of Figure 11 may be a ceramic-based package including an upper housing defined by a lid member 1113 and a frame member (shown in cross section as sidewalls 1110f). The lid member 1113 and / or sidewalls 1110f may comprise a ceramic material (e.g., alumina) and may define an open-cavity surrounding the die 100 on a conductive base or flange 1120. The lid member 1113 may be bonded to the sidewalls 1110f using an epoxy adhesive. The sidewalls 1110f may be attached to the base 1120 via brazing.

[0122] 12 may be a ceramic-based package including a base 1220 and an upper housing having a lid member 1213 and a frame member (shown in cross section as sidewall 1210f). The lid member 1213 and sidewall 1210f may in turn define an open-cavity surrounding the die 100 on a conductive base or flange 1220. In the package 1200, the lid member 1213 may be a ceramic material (e.g., alumina) and the sidewall 1210f may be a printed circuit board (PCB).

[0123] In Figures 11 and 12, the flanges 1120, 1220 can be conductive materials, such as copper layers / laminates or alloys or metal matrix composites thereof. In some embodiments, the flanges 1120 can include copper-molybdenum (CuMo) layers, CPC (Cu / MoCu / Cu), or other copper alloys such as copper-tungsten CuW, and / or other laminate / multilayer structures. In the example of Figure 11, the flanges 1120 can be a CPC-based structure with sidewalls 1110f and / or lid member 1113 attached. In the example of Figure 12, the flanges 1220 can be a copper-molybdenum (RCM60)-based structure with sidewalls 1210f and / or lid member 1213 attached, for example, by a conductive adhesive.

[0124] In Figures 11 and 12, one of the terminals of the die 900 (e.g., source contact 315) may be attached to the flanges 1120, 1220, which may thus provide a source lead for the package 1100, 1200. The conductive leads 1111, 1211 may provide gate and drain leads for the package 1100, and are attached to the flanges 1120, 1220 and supported by the respective side walls 1110f, 1210f. In the examples of Figures 11 and 12, the respective wire bonds 1125, 1225 are thus used to connect the package leads 1111, 1211 to the die 900 for connection to a circuit or device outside the package 1100, 1200. In other embodiments, the wire bonds 1125, 1225 may be omitted and different electrical connections may be used. More generally, the packages 1000, 1100, 1200 described herein may include any combination of conductive vias, wire bonds, and / or conductive pillars for electrically connecting the terminals 310, 305, 315 to the input leads, output leads, and / or ground leads of the package.

[0125] In the figures, the conductive pillars 366 are illustrated as free-standing, without encapsulation by other non-conductive materials. Such free-standing pillars 366 may provide advantages, including but not limited to, reducing RF parasitic coupling, e.g., pillar-pillar, chip-chip / board, and / or pillar-chip / board. However, it will be understood that any of the embodiments having conductive pillars 366 as described herein may further include an encapsulation material, such as an overmold, on or covering the pillars 366, between the insulating layers 350, 355, 360 and the mounting substrate to provide additional protection (mechanical, moisture, etc.) and / or support for the pillars 366. In some embodiments, whether the pillars 366 are free-standing or supported by an encapsulation material may be variable based on design factors (e.g., power, frequency, matching circuits, packaging, etc.).

[0126] The embodiments of the present disclosure can be fabricated on a substrate or laminate (e.g., RDL laminate) and can be assembled in batches using modern enhanced wafer level packaging techniques. The die can include transistor cells of a power transistor device, for example, defining an RF power amplifier. In some embodiments, the die can include discrete multi-stage and monolithic microwave integrated circuits (MMICs) and / or multi-pass (e.g., Doherty) transistor devices.

[0127] While described primarily with reference to HEMT transistor structures, it will be understood that the fabrication processes and transistor structures according to the embodiments of the present disclosure are not limited. For example, the devices and fabrication methods described herein may be applied to other transistor structures, including but not limited to vertical or lateral MOSFET structures having a gate contact 310 separated from the surface of the epitaxial layer 324 by an oxide or other insulating layer. In devices having a lateral structure, the terminals of the device (e.g., the drain, gate and source terminals for a power MOSFET device) are on the same major surface (i.e., top or bottom) of the semiconductor layer structure. In contrast, in devices having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). Vertical power semiconductor devices, including MOSFET transistors, may have a standard gate electrode design in which the gate electrode of the transistor is formed on the top of the semiconductor layer structure, or may instead have a gate electrode buried in a trench in the semiconductor layer structure, typically referred to as a gated trench MOSFET.

[0128] Embodiments of the present disclosure may be used, for example, in various cellular infrastructure (CIFR) RF power products (including but not limited to 5W, 10W, 20W, 40W, 60W, 80W, and different frequency bands) for 5G and base station applications. Embodiments of the present disclosure may also be applied to radar and MMIC-type applications. More generally, embodiments of the present disclosure may be applied in GaN HEMT discrete and RF IC technologies, as well as power MOSFETs, Schottky, or any device that may use wire bonds for external connections.

[0129] Various embodiments have been described herein with reference to the accompanying drawings in which exemplary embodiments are shown. However, these embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. In the drawings, sizes and relative sizes of layers and regions are not shown to scale and may, in some cases, be exaggerated for clarity.

[0130] It will be understood that terms such as "first", "second" and the like may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any combination of one or more of the associated listed items. The term "at least one" likewise includes any combination of one or more of the associated listed items, but may not require each and every one of the associated listed items.

[0131] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0132] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0133] When an element, such as a layer, region, or substrate, is referred to as being "on," "attached," or extending "on" another element, it will be understood that it can be directly on the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on," or "directly attached," or extending "directly onto" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or there can be intervening elements present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0134] Relative terms such as "lower" or "upper" or "top" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0135] In this specification, embodiments of the present invention are described with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the figures are to be expected as a result of manufacturing techniques, tolerances, and the like. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include, for example, deviations in shapes that result from manufacturing. Elements shown in dotted lines may be optional in the illustrated embodiments.

[0136] Like numbers refer to like elements throughout, and thus, the same or similar numbers may be described with reference to other drawings even if not mentioned or described in the corresponding drawing, and elements without a reference number may be described with reference to other drawings.

[0137] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims

1. A radio frequency (RF) transistor amplifier die, comprising: A semiconductor layer structure including a plurality of transistor cells; An insulating layer on the surface of the semiconductor layer structure; A plurality of conductive pillar structures protruding from the insulating layer opposite to the surface of the semiconductor layer structure, each of the conductive pillar structures being configured to provide an input signal connection, an output signal connection, or a ground connection to the transistor cell; The ground connection is disposed between the input signal connection and / or the output signal connection to the transistor cell, the transistor cell includes a gate finger extending along the surface of the semiconductor layer structure, and the input signal connection is disposed between opposite ends of the gate finger. An RF transistor amplifier die.

2. A first subset of the conductive pillar structures is configured to provide the ground connection, a second subset of the conductive pillar structures is configured to provide one of the input signal connection or the output signal connection, and each conductive pillar structure of the second subset is disposed between each conductive pillar structure of the first subset. The RF transistor amplifier die according to claim 1.

3. A third subset of the conductive pillar structures is configured to provide the other of the input signal connection or the output signal connection, and each conductive pillar structure of the third subset is disposed between each conductive pillar structure of the first subset. The RF transistor amplifier die according to claim 2.

4. The transistor cell includes a gate finger, a drain finger, and a source finger extending on the semiconductor layer structure, each conductive pillar structure of the first subset is coupled to the source finger, and each conductive pillar structure of the second subset is coupled to the gate finger or the drain finger. The RF transistor amplifier die according to claim 2.

5. Each conductive pillar structure of the first subset is between opposite ends of the source finger, and / or each conductive pillar structure of the second subset is between opposite ends of the gate finger or the drain finger. The RF transistor amplifier die according to claim 4.

6. Each of the conductive pillar structures of the first subset is coupled to a respective extension region of the source finger, and / or each of the conductive pillar structures of the second subset is coupled to a respective extension region of the gate finger or the drain finger. The RF transistor amplifier die according to claim 4.

7. Each of the gate fingers, the drain fingers, and / or the source fingers includes finger segments spaced from each other, and each of the respective extension regions is disposed between the finger segments. The RF transistor amplifier die according to claim 6.

8. The input signal connection, the output signal connection, or the ground connection provided by each of the conductive pillar structures is released from a wire bond connection pad that is electrically connected to the gate finger, the drain finger, or the source finger. The RF transistor amplifier die according to claim 1 or 2.

9. At least one of the conductive pillar structures is coupled to a plurality of the gate fingers, a plurality of the drain fingers, or a plurality of the source fingers by one or more intervening metal layers therebetween. The RF transistor amplifier die according to claim 8.

10. The conductive pillar structure protrudes from the insulating layer adjacent to the top of the RF transistor amplifier die, a substrate on the semiconductor layer structure opposite to the surface having the insulating layer thereon, and a conductive via structure extending through the substrate. Each of the conductive via structures is configured to provide another input signal connection, output signal connection, or ground connection to the transistor cell. The RF transistor amplifier die according to any one of claims 1 to 7.

11. Each of the conductive pillar structures is disposed within an active region including the transistor cell so as to provide the input signal connection, the output signal connection, and the ground connection. The RF transistor amplifier die according to any one of claims 1 to 7.

12. A radio frequency (“RF”) transistor amplifier die, a semiconductor layer structure including a plurality of transistor cells, an insulating layer on the surface of the semiconductor layer structure, a plurality of conductive pillar structures protruding from the insulating layer opposite to the surface of the semiconductor layer structure, each of the conductive pillar structures being configured to provide an input signal connection, an output signal connection, or a ground connection to the transistor cell the transistor cell includes a gate finger extending on the semiconductor layer structure, and the input signal connection is coupled to the gate finger between its opposite ends RF transistor amplifier die **Claim 13** A first subset of the conductive pillar structures is configured to provide the input signal connection, a second subset of the conductive pillar structures is configured to provide the ground connection, and each conductive pillar structure of the first subset is disposed between each conductive pillar structure of the second subset. The RF transistor amplifier die according to claim 12. **Claim 14** A third subset of the conductive pillar structures is configured to provide the output signal connection, each conductive pillar structure of the third subset is disposed between each conductive pillar structure of the second subset, the transistor cell further includes a source finger and a drain finger extending on the semiconductor layer structure, and each of the conductive pillar structures of the second subset is between opposite ends of the source finger and / or each of the conductive pillar structures of the third subset is between opposite ends of the drain finger. The RF transistor amplifier die according to claim 13. **Claim 15** Each conductive pillar structure of the first subset, the second subset, and / or the third subset is coupled to an extension region between respective finger segments of the gate finger, the source finger, and / or the drain finger. The RF transistor amplifier die according to claim 14. **Claim 16** the conductive pillar structures protrude from the insulating layer adjacent to the top of the RF transistor amplifier die a substrate on the semiconductor layer structure opposite to the surface having the insulating layer thereon Further comprising a conductive via structure extending through the substrate, each of the conductive via structures being configured to provide an additional input signal connection, output signal connection, or ground connection to the transistor cell, the RF transistor amplifier die according to any one of claims 12 to 15.

17. Each of the conductive pillar structures is disposed within an active region including the transistor cell so as to provide the input signal connection, the output signal connection, and the ground connection, the RF transistor amplifier die according to any one of claims 12 to 15.

18. The transistor cell further includes drain fingers and source fingers extending on the semiconductor layer structure, and the input signal connection, the output signal connection, or the ground connection provided by each of the conductive pillar structures is released from wire bond connection pads that electrically connect to the gate fingers, the drain fingers, or the source fingers, the RF transistor amplifier die according to any one of claims 12 to 15.

19. A radio frequency ("RF") transistor amplifier die, A semiconductor layer structure including a plurality of transistor cells adjacent to its surface, A plurality of conductive pillar structures protruding away from the surface of the semiconductor layer structure, the first subset of the conductive pillar structures being configured to provide an input signal connection to the transistor cell, The transistor cell includes gate fingers, drain fingers, and source fingers extending on the semiconductor layer structure, and each of the conductive pillar structures of the first subset is configured to provide the input signal connection that is released from a connection bus that electrically connects the gate fingers and is attached to at least one device external to the radio frequency transistor amplifier die. RF transistor amplifier die.

20. A radio frequency ("RF") transistor amplifier die including a semiconductor layer structure including a plurality of transistor cells, an insulating layer on the surface of the semiconductor layer structure, and a plurality of conductive pillar structures protruding from the insulating layer opposite to the surface of the semiconductor layer structure. A package substrate including a conductive connection pattern corresponding to the arrangement of the conductive pillar structures, wherein each of the conductive pillar structures attaches the RF transistor amplifier die to the conductive connection pattern of the package substrate and is configured to provide an input signal connection, an output signal connection, or a ground connection to the transistor cell. The input signal connection is disposed between opposite ends of the gate fingers of the transistor cell. An integrated circuit device package.

21. The conductive pillar structure protrudes from the insulating layer adjacent to the top of the RF transistor amplifier die, and the RF transistor amplifier die further includes a substrate on the semiconductor layer structure opposite to the surface having the insulating layer thereon and a conductive via structure extending through the substrate, wherein each of the conductive via structures is configured to provide another input signal connection, output signal connection, or ground connection to the transistor cell. The integrated circuit device package according to claim 20. A substrate on the semiconductor layer structure opposite to the surface having the insulating layer thereon. The integrated circuit device package according to claim 20, further including a conductive via structure extending through the substrate, wherein each of the conductive via structures is configured to provide another input signal connection, output signal connection, or ground connection to the transistor cell.

22. The input signal connection, the output signal connection, or the ground connection provided by each of the conductive pillar structures is released from a wire bond connection pad that electrically connects to the gate fingers, drain fingers, or source fingers of the transistor cell. The integrated circuit device package according to claim 20 or 21.

23. A first subset of the conductive pillar structures is configured to provide the ground connection. The integrated circuit device package according to claim 20 or 21, wherein the first subset of the conductive pillar structures is disposed between a second subset and a third subset of the conductive pillar structures, each of which is configured to provide one of the input signal connection and the output signal connection.

24. A first subset of the conductive pillar structures is configured to provide the ground connection, a second subset of the conductive pillar structures is configured to provide one of the input signal connection or the output signal connection, and each of the conductive pillar structures of the second subset is disposed between each of the conductive pillar structures of the first subset. The integrated circuit device package according to claim 20 or 21.

25. The third subset of the conductive pillar structures is coupled to the other of the input signal connection or the output signal connection, and each conductive pillar structure of the third subset is disposed between each of the conductive pillar structures of the first subset, the integrated circuit device package of claim 24. **Claim 26** The integrated circuit device package of claim 20 or 21, wherein each of the conductive pillar structures is disposed within an active region including the transistor cell so as to provide the input signal connection, the output signal connection, and the ground connection. **Claim 27** The integrated circuit device package of claim 20 or 21, wherein the semiconductor layer structure includes one or more epitaxial layers of a wide bandgap semiconductor material. **Claim 28** The integrated circuit device package of claim 20 or 21, wherein the semiconductor layer structure includes a group III nitride material on a silicon carbide substrate.

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