Mitigating changes over time

Abstract

Aspects of the present disclosure control the aging of a signal path in an idle mode to mitigate aging. In one example, the input of the signal path is alternately held low and high for multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal having a low frequency) is input to the signal path during the idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is held high or low during each idle period based on the aging pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]

[0001] This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 396,046, filed in the United States Patent Office on August 6, 2021, the entire contents of which are incorporated herein by reference as if fully set forth below in their entirety, and for all applicable purposes. [Technical field]

[0002] FIELD OF THE DISCLOSURE Aspects of the present disclosure relate generally to aging, and more particularly, to mitigating aging. [Background technology]

[0003]

[0003] Circuits can suffer from aging effects such as bias temperature instability (BTI), which can degrade the performance of the circuit over time. For example, BTI stress in a signal path of a circuit during an idle mode can cause a duty-cycle shift in the signal path over time, which can lead to timing problems (e.g., timing violations) in the circuit. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, nor is it intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description presented later.

[0005]

[0005] A first aspect relates to a system. The system includes a multiplexer having a first input, a second input, a select input, and an output. The system also includes a signal path having an input and an output, where the input of the signal path is coupled to the output of the multiplexer. The system further includes a controller coupled to the second input of the multiplexer and to the select input of the multiplexer, where the controller has an indicator input. The controller is configured to receive a mode indicator signal at the indicator input, instruct the multiplexer to select a first input of the multiplexer if the mode indicator signal has a first logic value, instruct the multiplexer to select a second input of the multiplexer if the mode indicator signal has a second logic value, and output a control signal to the second input of the multiplexer, which control whether the input of the signal path is parked high or low.

[0006]

[0006] A second aspect relates to a system. The system includes a latch circuit having a signal input, a clock input, a set input, a reset input, and an output. The system also includes a signal path having an input and an output, where the input of the signal path is coupled to the output of the latch circuit. The system further includes a controller coupled to the set input and the reset input of the latch circuit, where the controller has an indicator input. The controller is configured to receive a mode indicator signal at the indicator input, deassert the set input and the reset input when the mode indicator signal has a first logic value, and use the set input and the reset input to control whether the input of the signal path remains high or low when the mode indicator signal has a second logic value.

[0007] A third aspect relates to a method for aging control, the method including: inputting a signal to an input of a signal path in an active mode; and controlling aging of the signal path in an idle mode. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A illustrates an example of a signal path including a delay circuit in accordance with certain aspects of the present disclosure. [Figure 1B]

[0009] FIG. 1B illustrates an example in which the input of a signal path is held low in idle mode, according to certain aspects of the present disclosure. [Figure 1C]

[0010] FIG. 1C illustrates an example of a duty cycle shift in a signal path due to asymmetric aging in accordance with certain aspects of the present disclosure. [Figure 1D]

[0011] FIG. 1D illustrates an example in which the input of a signal path is held high in idle mode, according to certain aspects of the present disclosure. [Figure 1E]

[0012] FIG. 1E illustrates another example of a duty cycle shift in a signal path due to asymmetric aging in accordance with certain aspects of the present disclosure. [Diagram 2]

[0013] FIG. 2 illustrates an example of a system including a multiplexer with age-varying control in accordance with certain aspects of the present disclosure. [Figure 3A]

[0014] FIG. 3A is a timing diagram illustrating an example of aging control in accordance with certain aspects of the present disclosure. [Figure 3B]

[0015] FIG. 3B is a timing diagram illustrating another example of aging control in accordance with certain aspects of the present disclosure. [Figure 4]

[0016] FIG. 4 illustrates an example of a controller including a circular shift register in accordance with certain aspects of the present disclosure. [Figure 5A]

[0017] FIG. 5A illustrates another example of a system including a multiplexer with age-varying control in accordance with certain aspects of the present disclosure. [Figure 5B]

[0018] FIG. 5B illustrates an example of the system in FIG. 5A including a clock gating circuit in accordance with certain aspects of the present disclosure. [Figure 5C]

[0019] FIG. 5C illustrates an example implementation of a clock gating circuit in accordance with certain aspects of the present disclosure. [Figure 6]

[0020] FIG. 6 illustrates another example of a system including a multiplexer with age-varying control in accordance with certain aspects of the present disclosure. [Figure 7]

[0021] FIG. 7 illustrates another example of a system including a multiplexer with age-varying control in accordance with certain aspects of the present disclosure. [Figure 8]

[0022] FIG. 8 illustrates another example of a system including a multiplexer with age-varying control in accordance with certain aspects of the present disclosure. [Figure 9A]

[0023] FIG. 9A illustrates an example of a system with time-varying control for two signal paths in accordance with certain aspects of the present disclosure. [Figure 9B]

[0024] FIG. 9B illustrates another example of a system with time-varying control for two signal paths in accordance with certain aspects of the present disclosure. [Figure 10]

[0025] FIG. 10 illustrates an example of a system including a latch circuit with aging control in accordance with certain aspects of the present disclosure. [Figure 11A]

[0026] FIG. 11A illustrates another example of a system including a latch circuit with aging control in accordance with certain aspects of the present disclosure. [Figure 11B]

[0027] FIG. 11B illustrates an example of the system in FIG. 11A including a clock gating circuit in accordance with certain aspects of the present disclosure. [Figure 12]

[0028] FIG. 12 illustrates an example of a system including a multiplexer and latch circuit with age-varying control in accordance with certain aspects of the present disclosure. [Figure 13]

[0029] FIG. 13 illustrates an example of a system including a single data rate (SDR) to double data rate (DDR) converter with aging control in accordance with certain aspects of the present disclosure. [Figure 14]

[0030] FIG. 14 illustrates an example implementation of a controller in accordance with certain aspects of the present disclosure. [Figure 15]

[0031] FIG. 15 illustrates an example of a multiplexer configured to output an aging control signal in accordance with certain aspects of the present disclosure. [Figure 16]

[0032] FIG. 16 illustrates an example of a memory interface circuit with aging control in accordance with certain aspects of the present disclosure. [Figure 17]

[0033] FIG. 17 illustrates another example of a memory interface circuit with aging control in accordance with certain aspects of the present disclosure. [Figure 18]

[0034] FIG. 18 is a flow chart illustrating a method of aging control according to certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0035] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0036] Age-related effects such as bias temperature instability (BTI) can degrade the performance of a circuit over time. For example, BTI stress in a signal path of a circuit during idle mode can cause duty cycle shifts in the signal path over time, which can lead to timing problems (e.g., timing violations) in the circuit.

[0011]

[0037] An example of a duty cycle shift caused by BTI stress will now be described with reference to FIGS. 1A-1E. FIG. 1A shows an example of a signal path 105 including a delay circuit 115 for delaying a signal in the signal path 105. The delay circuit 115 may be configured to delay a signal to adjust the timing of the signal relative to another signal. The signal may be a clock signal, a data signal, a control signal, an address signal, or another type of signal. In an example where the signal is a clock signal, the delay circuit 115 may be used to adjust the timing of the clock signal to center an edge of the clock signal between transitions of the data signal for data capture. In an example where the signal is a data signal, the delay circuit 115 may be used to adjust the timing of the data signal to align the data signal with another data signal (e.g., reduce skew between the data signals). In an example where the signal path 105 is in a memory system, the signal may be a control signal including a command for a memory device (e.g., a write command, a read command, a refresh command, etc.) and / or an address signal including an address in the memory device for writing or reading data.

[0012]

[0038] The delay circuit 115 may include delay buffers 120-1 through 120-4 coupled in series, where the delay of the delay circuit 115 is equal to the sum of the individual delays of the delay buffers 120-1 through 120-4. In the example shown in FIG. 1A, each of the delay buffers 120-1 through 120-4 is implemented with a respective complementary inverter including a respective one of the transistors 125-1 through 125-4 (e.g., n-type field effect transistors) and a respective one of the transistors 130-1 through 130-4 (e.g., p-type field effect transistors). However, it should be understood that each of the delay buffers 120-1 through 120-4 may be implemented with another type of circuit or logic gate.

[0013]

[0039] When signal path 105 is in an active mode, a signal (e.g., a data signal, a clock signal, etc.) is received at input 108 of signal path 105 and delayed by a delay in delay circuit 115. The resulting delayed signal may be output to another circuit (not shown) coupled to output 110 of signal path 105.

[0014]

[0040] When signal path 105 is in idle mode, input 108 of signal path 105 may be held high or low (i.e., held) during an idle period. In an example where the signal in active mode is a clock signal, signal path 105 may be in idle mode when the clock signal is gated. In an example where the signal in active mode is a data signal, signal path 105 may be in idle mode when there is no data traffic at input 108 of signal path 105.

[0015]

[0041] FIG. 1B shows an example where input 108 is held low (i.e., logic 0) in idle mode. FIG. 1B also shows the logic states at the inputs and outputs of each of delay buffers 120-1 through 120-4. In this example, output 110 of signal path 105 is low (i.e., logic 0) in idle mode. In this example, transistors 130-1, 125-2, 130-3, and 125-4 are turned on in idle mode, and transistors 125-1, 130-2, 125-3, and 130-4 are turned off in idle mode. In FIG. 1B, transistors 130-1, 125-2, 130-3, and 125-4 that are turned on in idle mode are shown in bold. Transistors 130-1, 125-2, 130-3, and 125-4 that are turned on in idle mode are stressed in idle mode, while transistors 125-1, 130-2, 125-3, and 130-4 that are turned off in idle mode are not stressed in idle mode. This results in asymmetric aging, where transistors 130-1, 125-2, 130-3, and 125-4 that are stressed in idle mode age faster than transistors 125-1, 130-2, 125-3, and 130-4 that are not stressed in idle mode.

[0016]

[0042] In this example, the asymmetric aging shifts the threshold voltages of stressed transistors 130-1, 125-2, 130-3, and 125-4 in idle mode, causing the falling edge delay at output 110 to increase relative to the rising edge delay at output 110. The increase in falling edge delay relative to the rising edge delay causes a duty cycle shift in signal path 105. An example of a duty cycle shift is illustrated in the timing diagram shown in FIG. 1C. In the example shown in FIG. 1C, a clock signal 150 is input to input 108 of signal path 105 in active mode. In this example, clock signal 150 at input 108 has a 50% duty cycle. FIG. 1C also shows clock signal 160 at output 110 of signal path 105 after clock signal 150 has been delayed by delay circuit 115. Delay circuit 115 delays the rising edge of clock signal 160 at output 110 by T. r , and the falling edge of the clock signal 160 is delayed by a delay T f As shown in Figure 1C, the asymmetric aging results in a delay of the falling edge T f is the delay of the rising edge T r In this example, the longer delay of the falling edge increases the duty cycle of the clock signal 160 at the output 110 (i.e., results in a duty cycle of greater than 50% at the output 110).

[0017]

[0043] In the example illustrated in Figures 1B and 1C, the input 108 of signal path 105 is held low in idle mode. Asymmetric aging also occurs in the case where the input 108 of signal path 105 is held high in idle mode. In this regard, Figure 1D shows an example where the input 108 is held high (i.e., logic 1) in idle mode. Figure 1D also shows the logic states at the inputs and outputs of each of delay buffers 120-1 to 120-4. In this example, the output 110 of signal path 105 is high (i.e., logic 1) in idle mode. In this example, transistors 125-1, 130-2, 125-3, and 130-4 are turned on in idle mode, and transistors 130-1, 125-2, 130-3, and 125-4 are turned off in idle mode. 1D, transistors 125-1, 130-2, 125-3, and 130-4 that are turned on in idle mode are shown in bold. Transistors 125-1, 130-2, 125-3, and 130-4 that are turned on in idle mode are stressed in idle mode, while transistors 130-1, 125-2, 130-3, and 125-4 that are turned off in idle mode are not stressed in idle mode, which results in asymmetric aging, where transistors 125-1, 130-2, 125-3, and 130-4 that are stressed in idle mode age faster than transistors 130-1, 125-2, 130-3, and 125-4.

[0018]

[0044] In this example, the asymmetric aging shifts the threshold voltages of stressed transistors 125-1, 130-2, 125-3, and 130-4 in idle mode, causing the rising edge delay at output 110 to increase relative to the falling edge delay at output 110. The increase in rising edge delay relative to the falling edge delay causes a duty cycle shift in signal path 105. An example of a duty cycle shift is illustrated in the timing diagram shown in FIG. 1E. In the example shown in FIG. 1E, a clock signal 150 is input to input 108 of signal path 105 in active mode. In this example, clock signal 150 at input 108 has a 50% duty cycle. FIG. 1E also shows clock signal 180 at output 110 of signal path 105 after clock signal 150 has been delayed by delay circuit 115. Delay circuit 115 delays the rising edge of clock signal 180 at output 110 by T. r , and the falling edge of the clock signal 180 is delayed by a delay T f As shown in Figure 1E, the asymmetric aging results in a delay of the rising edge T r is the delay of the falling edge T f In this example, the longer delay of the rising edge reduces the duty cycle of the clock signal 180 at the output 110 (i.e., results in a duty cycle at the output 110 that is less than 50%).

[0019]

[0045] Thus, asymmetric aging in idle mode causes a duty cycle shift (i.e., duty cycle degradation) over time. The duty cycle shift increases or decreases the duty cycle depending on whether the input 108 of the signal path 105 is held low or high in idle mode. In a system that is sensitive to duty cycle, the duty cycle shift can lead to timing issues in the system. An example of such a system is a double data rate (DDR) system where data is captured from a data signal on both the rising and falling edges of a clock signal. In this example, the duty cycle shift due to asymmetric aging can lead to timing violations in the system.

[0020]

[0046] To address this, various aspects of the present disclosure control aging in idle mode to mitigate duty cycle shift due to aging. In one example, instead of leaving the input of the signal path at the same logic value during each idle period, the input is alternately left low and high for multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path and thus mitigate duty cycle shift due to asymmetric aging. In another example, a clock signal (e.g., a slow clock signal having a low frequency) is input to the signal path during the idle period to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path may be kept high or low during each idle period based on an aging pattern (e.g., a programmable aging pattern). In certain aspects, the aging pattern may be programmed to compensate for the asymmetric aging of the signal path in active mode. In certain aspects, a multiplexer coupled to the input of the signal path is used to control the aging of the signal path in idle mode. In certain aspects, a latch circuit (e.g., a flip-flop) coupled to the input of the signal path is used to control the aging of the signal path in idle mode. In certain aspects, the logic value at the input of the signal path in idle mode can be controlled using the set and / or reset inputs of the latch circuit. The above and other exemplary features of the present disclosure are further described below.

[0021]

[0047] As used herein, a "latch circuit" includes one or more circuits configured to latch / store one or more logical values, such as latches, flip-flops, registers, etc.

[0022]

[0048] 2 illustrates an example of a system 205 with aging mitigation in accordance with certain aspects of the present disclosure. In this example, the system 205 includes a signal path 210, a multiplexer 220, and a controller 230.

[0023]

[0049] The signal path 210 has an input 212 and an output 214. The input 212 may be configured to receive a signal in an active mode. The signal may be a clock signal, a data signal, a control signal, an address signal, or another type of signal. The signal path 210 may include a delay circuit (e.g., delay circuit 115) for delaying a signal. For example, the delay circuit may be configured to delay a signal to adjust the timing of the signal relative to another signal, as described further below. It should be understood that the signal path 210 may include one or more other circuits instead of or in addition to the delay circuit. The one or more other circuits may include one or more logic gates, sequential logic circuits, etc. The output 214 of the signal path 210 may be coupled to a sequential logic circuit, a driver, a pad, or another circuit, as described further below.

[0024]

[0050] The multiplexer 220 has a first input 222, a second input 224, a selection input 226, and an output 228. The output 228 of the multiplexer 220 is coupled to the input 212 of the signal path 210. The multiplexer 220 is configured to selectively couple the first input 222 or the second input 224 to the output 228 based on a selection signal received at the selection input 226. For example, the multiplexer 220 may couple the first input 222 to the output 228 (i.e., select the first input 222) when the selection signal has a first logical value, and couple the second input 224 to the output 228 (i.e., select the second input 224) when the selection signal has a second logical value. The first logical value may be 1 and the second logical value may be 0, or vice versa. In this example, the first input 222 is configured to receive a signal for an active mode of the signal path 210. As discussed above, the signal may be a clock signal, a data signal, a control signal (also called a command signal), an address signal, or another type of signal. Although multiplexer 220 is shown in FIG. 2 as having two inputs (i.e., a first input 222 and a second input 224), it should be understood that multiplexer 220 may include more than two inputs.

[0025]

[0051] The controller 230 has an input 232, a first output 234, and a second output 236. The input 232 may be configured to receive an indicator signal that indicates to the controller 230 whether the signal path 210 is in an idle mode or an active mode. In this regard, the input 232 may be referred to as an indicator input. In one example, the indicator signal may have a first logical value to indicate an idle mode and a second logical value to indicate an active mode. The first logical value may be 1 and the second logical value may be 0, or vice versa.

[0026]

[0052] In an example where the signal input to signal path 210 is a clock signal, the clock signal may be gated in an idle mode. In this example, the indicator signal may be generated by a circuit (not shown) that controls clock gating in system 205. In this example, the idle indicating signal may indicate an active mode when the clock signal is not gated and an idle mode when the clock signal is gated. In an example where the signal input to signal path 210 is a data signal, signal path 210 may enter an idle mode when there is no data traffic arriving on signal path 210. In this example, the indicator signal may be generated by a circuit (not shown) that controls (e.g., manages) data traffic in system 205. In this example, the indicating signal may indicate an active mode when there is incoming data traffic and an idle mode when there is no incoming data traffic. In an example where the signal is a control signal (also called a command signal), signal path 210 may be idle when there is no command (e.g., read / write command) arriving on signal path 210. In this example, the indicating signal may indicate an active mode when there is an incoming command and an idle mode when there is no incoming command.

[0027]

[0053] A first output 234 of the controller 230 is coupled to the second input 224 of the multiplexer 220, and a second output 236 of the controller 230 is coupled to the select input 226 of the multiplexer 220. The controller 230 is configured to output a time-varying control signal at the first output 234. As explained further below, the time-varying control signal is a control signal that controls whether the input 212 of the signal path 210 is held high or low in idle mode. The controller 230 is configured to output a select signal at the second output 236 to control the input selection of the multiplexer 220.

[0028]

[0054] In an active mode (also referred to as a functional mode), the controller 230 uses the select signal to instruct the multiplexer 220 to select the first input 222 (e.g., set the select signal to a first logical value). As a result, the multiplexer 220 passes the signal received at the first input 222 to the input 212 of the signal path 210. In one example, the controller 230 may instruct the multiplexer 220 to select the first input 222 when the indicator signal indicates an active mode. As described above, the signal may be a clock signal, a data signal, a control signal, an address signal, or another type of signal. In an example where the signal is a data signal, the signal path 210 may be in the active mode when the signal path 210 is receiving incoming data traffic. In an example where the signal is a control signal, the signal path 210 may be in the active mode when the signal path 210 is receiving a command (e.g., a read / write command).

[0029]

[0055] In the idle mode, the controller 230 instructs the multiplexer 220 to select the second input 224 (e.g., sets the select signal to a second logical value). For example, the controller 230 may instruct the multiplexer 220 to select the second input 224 when the controller 230 receives an indicator signal indicating the idle mode. As a result, the multiplexer 220 couples the time-varying control signal output from the first output 234 of the controller 230 to the input 212 of the signal path 210. This allows the controller 230 to control the aging of the signal path 210 in the idle mode by controlling the logical value (i.e., state) that is latched at the input 212 of the signal path 210 using the time-varying control signal, as described further below.

[0030]

[0056] 3A is a timing diagram illustrating an example of controller 230 using a time-varying control signal to control aging in idle mode, according to a particular embodiment. FIG. 3A shows the logic value 305 (i.e., state) at input 212 of signal path 210 across multiple active periods 310-1 through 310-4 and multiple idle periods 320-1 through 320-4. In this example, the signal input to signal path 210 in active mode is a clock signal. However, it should be understood that the signal could be a data signal, a control signal, an address signal, or another type of signal.

[0031]

[0057] 3A, controller 230 keeps input 212 of signal path 210 alternating low and high for idle periods 320-1 through 320-4 to balance the aging of devices (e.g., transistors) in signal path 210. For example, controller 230 may keep input 212 of signal path 210 alternating low and high for successive idle periods by setting the aging control signal alternating low and high for successive idle periods. The controller 230 may keep the input 212 of the signal path 210 low during odd idle periods 320-1 and 320-3 and keep the input 212 of the signal path 210 high during even idle periods 320-2 and 320-4 (as shown in the example in FIG. 3A ), or may keep the input 212 of the signal path 210 high during odd idle periods 320-1 and 320-3 and keep the input 212 of the signal path 210 low during even idle periods 320-2 and 320-4. To do this, the controller 230 may set the age-varying control signal low during odd idle periods 320-1 and 320-3 and set the age-varying control signal high during even idle periods 320-2 and 320-4, or may set the age-varying control signal high during odd idle periods 320-1 and 320-3 and set the age-varying control signal low during even idle periods 320-2 and 320-4.

[0032]

[0058] Assuming that the cumulative duration of odd idle periods 320-1 and 320-3 is approximately equal to the cumulative duration of even idle periods 320-2 and 320-4 over a number of idle periods, controller 230 keeps input 212 of signal path 210 low and high for approximately equal durations in idle mode over time. This helps balance the aging of devices (e.g., transistors) in signal path 210, thus reducing duty cycle shifts in signal path 210 caused by asymmetric aging.

[0033]

[0059] 3B is a timing diagram illustrating another example of controller 230 using an aging control signal to control aging in idle mode, according to a particular embodiment. FIG. 3B shows the logic value 350 (i.e., state) at input 212 of signal path 210 over multiple active periods 360-1 through 360-4 and multiple idle periods 370-1 through 370-4. In this example, the signal input to signal path 210 in active mode is a clock signal. However, it should be understood that the signal could be a data signal or another type of signal.

[0034]

[0060] In the example shown in FIG. 3B, the controller 230 inputs a low-speed clock signal to the signal path 210 in the idle mode. The low-speed clock signal may have a frequency much lower than that of the clock signal used in the active mode to reduce power in the idle mode. For example, the low-speed clock signal may have a frequency of 19.2 MHz or less. The low-speed clock signal may be generated by a low-speed clock generator (not shown) coupled to the controller 230. The low-speed clock generator may be implemented using a crystal oscillator or another type of clock generator. In this example, the controller 230 may input the low-speed clock signal to the signal path 210 by outputting the low-speed clock signal in the idle mode as a time-varying control signal (i.e., outputting the low-speed clock signal at the first output 234). In this example, the low-speed clock signal helps balance the aging of devices (e.g., transistors) in the signal path 210 by alternating the input 212 of the signal path 210 between high and low in the idle mode.

[0035]

[0061] In certain aspects, the controller 230 may park the input 212 of the signal path 210 in the idle mode based on an aging pattern, which may be programmable. For example, the aging pattern may be repeated every N consecutive idle periods, where N is an integer. For each N consecutive idle period, the aging pattern may indicate a number k of N consecutive idle periods during which the input 212 of the signal path 210 is parked high, and a number of N consecutive idle periods (i.e., Nk) during which the input 212 of the signal path 210 is parked low. For example, if N is equal to 8, the aging pattern is repeated every 8 consecutive idle periods. In this aspect, the controller 230 may control the aging based on the aging pattern by setting the aging control signal high for k of the N consecutive idle periods and setting the aging control signal low for Nk of the N consecutive idle periods. N may be an integer greater than 1, k may be an integer equal to or greater than 1, and N may be greater than k. In one example, k and N may be stored as parameters in a register 235 in the controller 230. In this example, k and N may be programmable by writing values ​​of k and N to the register 235. It should be understood that the register 235 may be omitted in some implementations.

[0036]

[0062] In certain aspects, the aging pattern is specified by a sequence of N bits. In these aspects, each bit in the sequence corresponds to one of N consecutive idle periods, and each bit indicates whether the input 212 of the signal path 210 is held high or low during the corresponding one of the N consecutive idle periods. For example, a bit value of 1 may indicate that the input 212 of the signal path 210 is held high during the corresponding idle period, and a bit value of 0 may indicate that the input 212 of the signal path 210 is held low during the corresponding idle period, or vice versa. For example, the aging pattern given by the bit sequence 11100000 may indicate that the input 212 is held high for three of eight consecutive idle periods and low for five of eight consecutive idle periods.

[0037]

[0063] In certain aspects, controller 230 may control aging based on a sequence of N bits by setting the logic state (i.e., logic value) of an aging control signal based on a sequence of N bits, where each bit in the sequence corresponds to a respective one of N consecutive idle periods. For each of the N idle periods, controller 230 may set the aging control signal high if the corresponding bit in the sequence has a first logic value and set the aging control signal low if the corresponding bit in the sequence has a second logic value. The first logic value may be 1 and the second logic value may be 0, or vice versa.

[0038]

[0064] The controller 230 may store a sequence of N (e.g., 8) bits that specify the time-varying pattern in a register 235. In one example, the register 235 may include a circular shift register configured to output the bits in the sequence one by one. In this regard, FIG. 4 illustrates an example in which the register 235 includes a circular shift register 410 according to a particular embodiment. In this example, the circular shift register 410 includes storage slots 415-1 through 415-N (also referred to as storage spaces), where each of the storage slots 415-1 through 415-N may hold one bit of the sequence of N bits. The circular shift register 410 has an input 412 and an output 414. The input 412 is used to control the shifting of bits in the circular shift register 410, as described further below. The output 414 is coupled to a first output 234 of the controller 230 and configured to output the bits in the storage slots 415-N.

[0039]

[0065] In this example, the controller 230 also includes a control circuit 420. The control circuit 420 has an input 422, a first output 424, and a second output 426. The input 422 is coupled to an input 232 of the controller 230 and configured to receive the indicator signal described above. The first output 424 is coupled to an input 412 of the circular shift register 410 and used by the control circuit 420 to shift bits in the circular shift register 410, as described further below. The second output 426 is coupled to a second output 236 of the controller 230 and used by the control circuit 420 to control the input selection of the multiplexer 220.

[0040]

[0066] In operation, the control circuit 420 is configured to instruct the multiplexer 220 to select the second input 224 in the idle mode via the second output 426 (e.g., when an idle signal indicating an idle period is received at the input 422). In an example in which the multiplexer 220 selects the second input 224 when a second logical value is input to the selection input 226, the control circuit 420 may instruct the multiplexer 220 to select the second input 224 by outputting a second logical value to the selection input 225 via the second output 426. The control circuit 420 may be configured to instruct the multiplexer 220 to select the first input 222 in the active mode via the second output 426.

[0041]

[0067] In idle mode, the control circuitry 420 may be configured to shift the bits in the circular shift register 410 by one bit position per idle period via the first output 424 such that the circular shift register 410 outputs each bit in the sequence of N bits once every N idle periods. For example, the control circuitry 420 may shift the bits in the circular shift register 410 by one bit position each time the indicator signal indicates an idle mode. With each shift, the bits in each storage slot 415-1 through 415-N may be shifted up to the next storage slot 415-1 through 415-N in the circular shift register 410. For example, in one shift, the bits in storage slot 415-1 may be shifted up to storage slot 415-2, and the bits in storage slot 415-N may be shifted back to storage slot 415-1 (as indicated by the arrow looping back from storage slot 415-N to storage slot 415-1).

[0042]

[0068] Thus, in this example, the bits in the circular shift register 410 are shifted by one bit position for each idle period such that the circular shift register 410 cycles through a sequence of N bits once every N idle periods. In this example, the input 212 of the signal path 210 may be held high when the circular shift register 410 outputs a first bit value, and the input 212 of the signal path 210 may be held low when the circular shift register 410 outputs a second bit value. The first bit value may be a 1 and the second bit value may be a 0, or vice versa.

[0043]

[0069] Thus, the aging control by the controller 230 may be configured (e.g., programmed), for example, by programming bits in a sequence of N bits appropriately. In some use cases, the signal path 210 may experience asymmetric aging in the active mode. In these use cases, the aging pattern may be programmed to compensate for the asymmetric aging of the signal path 210 in the active mode, and thus mitigate the duty cycle shift caused by the asymmetric aging in the active mode. For example, if the input 212 of the signal path 210 is high for a longer duration in the active mode than low in the active mode, the aging pattern may be programmed such that the controller 230 keeps the input 212 of the signal path 210 low for more idle periods than high to compensate for the asymmetric aging in the active mode. Similarly, if the input 212 of the signal path 210 is low for a longer duration in the active mode than it is high in the active mode, the aging pattern may be programmed such that the controller 230 keeps the input 212 of the signal path 210 high for more idle periods than low to compensate for the asymmetric aging in the active mode. In this example, the durations that the input 212 of the signal path 210 is high and low in the active mode may be determined, for example, by running a simulation of the system 205 in the active mode. This information may also be obtained by monitoring the logic state at the input 212 of the signal path 210 in the active mode and determining the durations that the input 212 of the signal path 210 is high and low in the active mode based on the monitored logic state. After this information is obtained, the aging pattern may be programmed accordingly to compensate for the asymmetric aging in the active mode.

[0044]

[0070] 5A illustrates an example of a system 505 including the signal path 210, multiplexer 220, and controller 230 described above. The system 505 also includes a driver 510 and a pad 520. The driver 510 has an input 512 and an output 514. The input 512 of the driver 510 is coupled to the output 214 of the signal path 210, and the output 514 of the driver 510 is coupled to the pad 520. In certain aspects, the signal path 210, the multiplexer 220, the driver 510, and the pad 520 may be integrated on a chip (i.e., a die), and the pad 520 may be coupled to another chip via metal lines (e.g., formed on a printed circuit board (PCB)).

[0045]

[0071] In an active mode, the driver 510 may be configured to receive a signal from the signal path 210 and drive the pad 520 (and thus the metal line) based on the received signal. For example, the driver 510 may be configured to drive the pad 520 high when the received signal is high and drive the pad 520 low when the received signal is low. Alternatively, the driver 510 may be configured to drive the pad 520 low when the received signal is high and drive the pad 520 high when the received signal is low. The driver 510 may be implemented with a pull-up transistor to drive the pad 520 high and a pull-down transistor to drive the pad 520 low.

[0046]

[0072] In one example, a metal line (not shown) may be coupled between pad 520 and another chip (not shown). In this example, driver 510 may be configured to transmit a signal to the other chip via the metal line by driving pad 520 (and thus the metal line) based on a signal. In this example, signal path 210 and driver 510 may be located in a transmission path of system 505. As described above, the signal may be a data signal, a clock signal, a control signal, an address signal, or another type of signal.

[0047]

[0073] In the example of FIG. 5A, the logic state at the output 214 of the signal path 210 may toggle between high and low over multiple idle periods. This is because, as described above, the controller 230 alternately holds the input 212 of the signal path 210 high and low to balance the aging. In some use cases, it is desirable for the input 512 of the driver 510 and / or the pad 520 to be low (i.e., logic 0) in the idle mode. For example, specifications may require that the pad 520 be low in the idle mode such that a transmission line (not shown) coupled to the pad 520 is held low in the idle mode. In these cases, a clock gating circuit 540 (also called a clock gating cell) may be coupled between the output 214 of the signal path 210 and the input 512 of the driver 510 to isolate the driver 510 and the pad 520 from toggling between low and high at the output 214 of the signal path 210 in the idle mode, an example of which is shown in FIG. 5B.

[0048]

[0074] 5B, the clock gating circuit 540 has a signal input 542 coupled to the output 214 of the signal path 210, an output 546 coupled to the input 512 of the driver 510, and a control input 544 coupled to a third output 530 of the controller 230. In this example, the controller 230 may be configured to selectively gate or ungate the clock gating circuit 540 via the third output 530. For example, the clock gating circuit 540 may be configured to gate when a first logical value is input to the control input 544 and ungate when a second logical value is input to the control input 544. In this example, the controller 230 may gate the clock gating circuit 540 by outputting a first logical value to the control input 544 of the clock gating circuit 540 and ungate the clock gating circuit 540 by outputting a second logical value to the control input 544 of the clock gating circuit 540. In this example, the first logical value may be 1 and the second logical value may be 0, or vice versa. In this example, the clock gating circuit 540 may be configured to hold the output 546 low when the clock gating circuit 540 is gated.

[0049]

[0075] In this example, controller 230 may be configured to ungate clock gating circuit 540 in active mode and gate clock gating circuit 540 in idle mode (e.g., when controller 230 receives an indicator signal at input 232 indicating idle mode). In this example, clock gating circuit 540 holds output 546 low in idle mode, which isolates driver 510 and pad 520 from toggling between low and high at output 214 of signal path 210 in idle mode.

[0050]

[0076] It should be understood that the present disclosure is not limited to the example shown in Figure 5B. For example, in another example, the clock gating circuit 540 may be coupled between the output 514 of the driver 510 and the pad 520 to isolate the pad 520 from toggling in the idle mode. In this example, the controller 230 may gate the clock gating circuit 540 in the idle mode and ungate the clock gating circuit 540 in the active mode, as described above.

[0051]

[0077] The clock gating circuit 540 may be implemented using one or more logic gates. For example, FIG. 5C shows an example in which the clock gating circuit 540 includes an AND gate 570. In this example, a first input of the AND gate 570 is coupled to the signal input 542, a second input of the AND gate 570 is coupled to the control input 544, and an output of the AND gate 570 is coupled to the output 546. In this example, the AND gate 570 ungates the clock gating circuit 540 when the logic value at the control input 544 is 1. The AND gate 570 gates the clock gating circuit 540 and keeps the output 546 low when the logic value at the control input 544 is 0. In one example, the AND gate 570 may be implemented using a NAND gate and an inverter. It should be understood that the clock gating circuit 540 is not limited to the example shown in FIG. 5C and the clock gating circuit 540 may be implemented using another type of logic gate and / or combination of logic gates. It should also be understood that the clock gating circuit 540 may include additional components not shown in FIG. 5C (eg, latch circuits or synchronizers to prevent glitches).

[0052]

[0078] In the above example, the clock gating circuit 540 is configured to hold the output 546 low when the clock gating circuit 540 is gated. However, it should be understood that the present disclosure is not limited to this example. For example, in some use cases, it may be desirable for the input 512 and / or pad 520 of the driver 510 to be high (i.e., logic 1) in idle mode. In these cases, the clock gating circuit 540 is configured to hold the output 546 high when the clock gating circuit 540 is gated. In these cases, the clock gating circuit 540 may be implemented using an OR gate or a combination of logic gates.

[0053]

[0079] 6 shows an example of a system 605 that includes the signal path 210, multiplexer 220, and controller 230 described above. The system 605 also includes a latch circuit 610 (e.g., a flip-flop) having a signal input 612, a clock input 614, and an output 616. The signal input 612 is coupled to the output 214 of the signal path 210. In this example, the signal in the active mode can be a data signal, a control signal, or an address signal.

[0054]

[0080] In an active mode, latch circuit 610 is configured to receive a signal from signal path 210 at a signal input 612 and a clock signal (labeled "Clk") at a clock input 614. Latch circuit 610 is configured to latch (i.e., capture) the logical value of the signal on an edge of the clock signal and output the latched logical value at an output 616. The output 616 may be coupled to a circuit configured to receive the latched logical value. The circuit may include another latch circuit, a processor, a data buffer, etc. The edge of the clock signal used to latch the logical value may be a rising edge or a falling edge.

[0055]

[0081] 7 illustrates an example of a system 705 including the signal path 210, multiplexer 220, controller 230, and latch circuit 610 described above. The system 705 also includes a pad 720 and a receiver 710. The receiver 710 has an input 712 and an output 714. The input 712 of the receiver 710 is coupled to the pad 720, and the output 714 of the receiver 710 is coupled to a first input 222 of the multiplexer 220. In certain aspects, the pad 720, the receiver 710, the multiplexer 220, the signal path 210, and the latch circuit 610 may be integrated on a chip (i.e., a die), and the pad 720 may be coupled to another chip via metal lines (e.g., formed on a printed circuit board (PCB)).

[0056]

[0082] The receiver 710 may be configured to receive a signal from another chip (not shown) via a pad 720. The receiver 710 may amplify the received signal (e.g., to compensate for signal attenuation in the metal line) and / or perform equalization on the received signal. The receiver 710 outputs the received signal to a first input 222 of the multiplexer 220. In this example, the receiver 710 and the signal path 210 may be located in a receive path of the system 705. In this example, the signal may be a data signal (e.g., transmitted by the other chip via a metal line to the pad 720).

[0057]

[0083] 8 shows an example of a system 805 that includes the signal path 210, multiplexer 220, and controller 230 described above. The system 805 also includes a latch circuit 810 (e.g., a flip-flop) having a signal input 812, a clock input 814, and an output 816. The clock input 814 is coupled to the output 214 of the signal path 210. In this example, the signal in the active mode is a clock signal.

[0058]

[0084] In an active mode, latch circuit 810 is configured to receive a data signal at signal input 812 and a clock signal from signal path 210 at clock input 814. Latch circuit 810 is configured to latch (i.e., capture) the logical value of the data signal on an edge of the clock signal and output the latched logical value at output 816. Output 816 may be coupled to a circuit configured to receive the latched logical value. The circuit may include another latch circuit, a processor, a data buffer, etc. The edge of the clock signal used to latch the logical value may be a rising edge or a falling edge. In this example, signal path 210 may be configured to delay the clock signal to adjust the timing of the clock signal (e.g., to center an edge of the clock signal between transitions of the data signal).

[0059]

[0085] 8, the system 805 also includes a clock source 820 configured to output a clock signal at an output 822 coupled to the first input 222 of the multiplexer 220. The clock source 820 may include a phase-locked loop (PLL) or another type of clock generator. The clock source 820 may be integrated on the same chip as the multiplexer 220 or may be located on a separate chip.

[0060]

[0086] In the example described above, the signal input 812 of the latch circuit 810 is a data signal, but it should be understood that the signal could also be a control signal or an address signal. For example, the latch circuit 810 could be used to latch command bits or address bits.

[0061]

[0087] 9A shows an example of a system 905 that includes the signal path 210, multiplexer 220, controller 230, and latch circuit 810 described above. System 905 also includes a second multiplexer 920, a second signal path 910, a pad 940, and a receiver 930. In the following description of FIG. 9A, signal path 210 is referred to as the first signal path and multiplexer 220 is referred to as the first multiplexer.

[0062]

[0088] The second signal path 910 has an input 912 and an output 914, where the output 914 is coupled to the signal input 812 of the latch circuit 810. The second signal path 910 may be configured to delay a data signal, a control signal, or an address signal as described above with reference to FIG.

[0063]

[0089] The second multiplexer 920 has a first input 922, a second input 924, a select input 926, and an output 928. The output 928 of the second multiplexer 920 is coupled to the input 912 of the second signal path 910. The second multiplexer 920 is configured to selectively couple the first input 922 or the second input 924 to the output 928 based on a select signal received at the select input 926. For example, the second multiplexer 920 may couple the first input 922 to the output 928 (i.e., select the first input 922) when the select signal has a first logical value and couple the second input 924 to the output 928 (i.e., select the second input 924) when the select signal has a second logical value. In the example shown in FIG. 9A, the second input 924 is coupled to the first output 234 of the controller 230 and thus receives the time-varying control signal output from the controller 230. The selection input 926 is coupled to the second output 236 of the controller 230 and thus receives the selection signal output from the controller 230. Thus, in this example, the controller 230 controls the time-varying of the first signal path 210 and the time-varying of the second signal path 910. In this example, the idle periods of the first signal path 210 and the second signal path 910 may be the same. However, it should be understood that this is not necessarily the case, as will be further explained below with reference to FIG. 9B.

[0064]

[0090] The receiver 930 has an input 932 and an output 934. The input 932 of the receiver 930 is coupled to a pad 940, and the output 934 of the receiver 930 is coupled to a first input 922 of the second multiplexer 920. In certain aspects, the pad 940, the receiver 930, the first multiplexer 220, the second multiplexer 920, the first signal path 210, the second signal path 910, and the latch circuit 810 may be integrated on a chip (i.e., a die), and the pad 940 may be coupled to another chip via a metal line (e.g., formed on a printed circuit board (PCB)).

[0065]

[0091] Receiver 930 is configured to receive a signal (e.g., a data signal, a control signal, or an address signal) from another chip (not shown) via pad 940. Receiver 930 may amplify the received signal (e.g., to compensate for signal attenuation in metal lines) and / or perform equalization on the received signal. Receiver 930 outputs the received signal to a first input 922 of second multiplexer 920. In this example, receiver 930 and signal path 910 may be located in a receive path of system 905.

[0066]

[0092] As described above, in this example, the controller 230 controls the aging of the first signal path 210 and the aging of the second signal path 910. In an active mode, the controller 230 instructs the first multiplexers 220 to select their respective first inputs 222 and instructs the second multiplexers 920 to select their respective first inputs 922. In an idle mode, the controller 230 instructs the first multiplexers 220 to select their respective second inputs 224 and instructs the second multiplexers 920 to select their respective second inputs 924. The controller 230 then controls the aging of the first signal path 210 and the second signal path 910 using aging control signals (e.g., using any of the techniques described above with reference to FIG. 2). For example, the controller 230 may keep the input 212 of the first signal path 210 alternating low and high for multiple idle periods and the input 912 of the second signal path 910 alternating low and high for multiple idle periods. In another example, the controller 230 may control the aging of the first signal path 210 and the second signal path 910 based on an aging pattern (e.g., a sequence of N bits), as described above.

[0067]

[0093] 9B illustrates an example in which the controller 230 may independently control the aging of the first signal path 210 and the aging of the second signal path 910, according to certain aspects. In this example, the controller 230 has a second input 952, a third output 944, and a fourth output 946, which are used to control the aging of the second signal path 910. In the following description of FIG. 9B, the input 232 is referred to as the first input.

[0068]

[0094] In this example, the third output 944 is coupled to a second input 924 of the second multiplexer 920, and the fourth output 946 is coupled to a select input 926 of the second multiplexer 920. The first input 232 is configured to receive a first indicator signal indicative of an idle period of the first signal path 210, and the second input 942 is configured to receive a second indicator signal indicative of an idle period of the second signal path 910. The idle periods of the first signal path 210 and the second signal path 910 may overlap in time. In this example, the controller 230 is configured to output a first aging control signal at the first output 234 to control the aging of the first signal path 210 and a second aging control signal at the third output 944 to control the aging of the second signal path 910.

[0069]

[0095] An exemplary operation of the controller 230 according to a particular embodiment will now be described. In an active mode of the first signal path 210, the controller 230 instructs the first multiplexer 220 via the second output 236 to select the first input 222. As a result, the first multiplexer 220 passes the clock signal received at the first input 222 to the first signal path 210.

[0070]

[0096] In the idle mode of the first signal path 210, the controller 230 instructs the first multiplexer 220 to select the second input 224. As a result, the multiplexer 220 couples the first time-varying control signal output from the first output 234 of the controller 230 to the second input 224 of the multiplexer 220. This allows the controller 230 to control the aging of the first signal path 210 in the idle mode using the first time-varying control signal, as described above with reference to FIG. 2. In this example, the controller 230 determines that the first signal path 210 is idle when a first indicator signal is received at the first input 232 indicating that the first signal path 210 is in the idle mode.

[0071]

[0097] In an active mode of the second signal path 910, the controller 230 instructs the second multiplexer 920 via the fourth output 946 to select the first input 922. As a result, the second multiplexer 920 passes a signal received at the first input 922 (e.g., a data signal, a control signal, or an address signal) to the second signal path 910.

[0072]

[0098] In the idle mode of the second signal path 910, the controller 230 instructs the second multiplexer 920 to select the second input 924. As a result, the second multiplexer 920 couples the second aging control signal output from the third output 944 of the controller 230 to the second input 924 of the second signal path 910. This allows the controller 230 to control the aging of the second signal path 910 in the idle mode of the second signal path using the second aging control signal (e.g., using any one of the techniques described above with reference to FIG. 2). For example, the controller 230 may keep the input 912 of the second signal path 910 alternately low and high for multiple idle periods of the second signal path 910. In another example, the controller 230 may control the aging of the second signal path 910 based on an aging pattern (e.g., a sequence of N bits), as described above. In this example, the controller 230 determines that the second signal path 910 is idle when a second indicator signal indicating that the second signal path 910 is in an idle mode is received at the second input 942. For example, the second signal path 910 may be in an idle mode when the receiver 930 is not receiving incoming data traffic, such as a data signal.

[0073]

[0099] 10 illustrates a system 1005 using aging mitigation in accordance with certain aspects of the present disclosure. In this example, the system includes a signal path 1040, a latch circuit 1010 (e.g., a flip-flop), and a controller 1030.

[0074]

[0100] The signal path 1040 has an input 1042 and an output 1044. The input 1042 may be configured to receive a signal in an active mode. The signal may be a data signal, a control signal, an address signal, or another type of signal. The signal path 1040 may include a delay circuit (e.g., delay circuit 115) for delaying a signal. For example, the delay circuit may be configured to delay a signal to adjust the timing of the signal relative to another signal, as described further below. It should be understood that the signal path 1040 may include one or more other circuits instead of or in addition to the delay circuit. The one or more other circuits may include one or more logic gates, sequential logic circuits, etc. The output 1044 of the signal path 1040 may be coupled to a sequential logic circuit, a driver, a pad, or another circuit, as described further below.

[0075]

[0101] The latch circuit 1010 has a signal input 1012, a clock input 1014, a set input 1016, a reset input 1018, and an output 1020. The output 1020 of the latch circuit 1010 is coupled to an input 1042 of a signal path 1040. The signal input 1012 is configured to receive a signal (e.g., a data signal, a control signal, or an address signal), and the clock input 1014 is configured to receive a clock signal (labeled "Clk"). The latch circuit 1010 is configured to latch (i.e., capture) the logical value of the signal on an edge of the clock signal and output the latched logical value at the output 1020. In examples where the signal in the active mode is a data signal, the signal input 1012 may be referred to as a data input.

[0076]

[0102] The latch circuit 1010 is configured to set when the set input 1016 is asserted (e.g., a logical 1 is input to the set input 1016). When the set input 1016 is asserted, the output 1020 of the latch circuit 1010 goes high (i.e., a logical 1). The latch circuit 1010 is configured to reset when the reset input 1018 is asserted (e.g., a logical 1 is input to the reset input 1018). When the reset input 1018 is asserted, the output 1020 of the latch circuit 1010 goes low (i.e., a logical 0).

[0077]

[0103] The controller 1030 has an input 1032, a first output 1034, and a second output 1036. The input 1032 may be configured to receive an indicator signal that indicates to the controller 1030 when the signal path 1040 is in an idle mode. In an example where the signal input to the signal path 1040 is a data signal, the signal path 1040 may enter the idle mode when there is no data traffic arriving on the signal path 1040. In this example, the indicator signal may be generated by a circuit (not shown) that controls (e.g., manages) data traffic in the system 1005. The first output 1034 of the controller 1030 is coupled to the set input 1016 of the latch circuit 1010, and the second output 1036 of the controller is coupled to the reset input 1018 of the latch circuit 1010. As explained further below, the controller 1030 uses the set input 1016 and reset input 1018 of the latch circuit 1010 to control whether the input 1042 of the signal path 1040 (which is coupled to the output 1020 of the latch circuit 1010) is held high or low in idle mode.

[0078]

[0104] In an active mode (also called a functional mode), the controller 1030 deasserts the set input 1016 and the reset input 1018 of the latch circuit 1010 (e.g., inputs a logic 0 to both the set input 1016 and the reset input 1018). In this case, the latch circuit 1010 latches the logic value of a signal (e.g., a data signal, a control signal, or an address signal) on an edge of the clock signal and outputs the latched logic value on signal path 1040.

[0079]

[0105] In idle mode, the controller 1030 uses the set input 1016 and reset input 1018 of the latch circuit 1010 to control the aging of the signal path 1040. The controller 1030 may determine that the signal path 1040 is in idle mode when the input 1032 of the controller 1030 receives an indicator signal indicating idle mode. In this example, the controller 1030 may hold the input 1042 of the signal path 1040 high by asserting the set input 1016 (e.g., inputting a logic 1 to the set input 1016). The controller 1030 may hold the input 1042 of the signal path 1040 low by asserting the reset input 1018 (e.g., inputting a logic 1 to the reset input 1018). Note that in this example, one of the set input 1016 and the reset input 1018 is asserted at a time.

[0080]

[0106] In idle mode, the controller 1030 may control the aging of the signal path 1040 using any of the techniques described above with reference to FIG. 2. For example, the controller 1030 may alternately assert the set input 1016 and the reset input 1018 of the latch circuit 1010 for multiple idle periods to cause the input 1042 of the signal path 1040 to remain alternately low and high for multiple idle periods. For example, the controller 1030 may keep the input 1042 low during odd idle periods and keep the input 1042 high during even idle periods, or vice versa. In this example, the controller 1030 may assert the reset input 1018 during odd idle periods and assert the set input 1016 during even idle periods, or may assert the set input 1016 during odd idle periods and assert the reset input 1018 during even idle periods.

[0081]

[0107] In another example, the controller 1030 may control the aging of the signal path 1040 based on an aging pattern, as described above. For example, the aging pattern may be repeated every N consecutive idle periods, where N is an integer. For each N consecutive idle period, the aging pattern may indicate a number k of N consecutive idle periods during which the input 1042 of the signal path 1040 is held high, and a number of N consecutive idle periods (i.e., Nk) during which the input 1042 of the signal path 1040 is held low. For example, if N is equal to 8, then the aging pattern is repeated every 8 consecutive idle periods. In this aspect, the controller 1030 may control the aging based on the aging pattern by asserting the set input 1016 for k of the N consecutive idle periods and asserting the reset input 1018 for Nk of the N consecutive idle periods. N may be an integer greater than 1, k may be an integer equal to or greater than 1, and N may be greater than k. In one example, k and N may be stored as parameters in a register 1035 in the controller 1030. In this example, k and N may be programmable by writing values ​​of k and N to the register 1035. It should be understood that the register 1035 may be omitted in some implementations.

[0082]

[0108] In certain aspects, the aging pattern is specified by a sequence of N bits. In these aspects, each bit in the sequence corresponds to one of N consecutive idle periods, and each bit indicates whether the input 1042 of the signal path 1040 is held high or low during the corresponding one of the N consecutive idle periods. For example, a bit value of 1 may indicate that the input 1042 of the signal path 1040 is held high during the corresponding idle period, and a bit value of 0 may indicate that the input 1042 of the signal path 1040 is held low during the corresponding idle period, or vice versa. For example, the aging pattern given by the bit sequence 11100000 may indicate that the input 1042 is held high for three of eight consecutive idle periods and low for five of eight consecutive idle periods.

[0083]

[0109] In one particular aspect, the controller 1030 may control the aging based on a sequence of N bits by controlling the set input 1016 and the reset input 1018 based on a sequence of N bits, where each bit in the sequence corresponds to a respective one of N consecutive idle periods. For each of the N idle periods, the controller 230 may assert the set input 1016 to keep the input 1042 high if the corresponding bit in the sequence has a first logical value, and may assert the reset input 1018 to keep the input 1042 low if the corresponding bit in the sequence has a second logical value. The first logical value may be 1 and the second logical value may be 0, or vice versa.

[0084]

[0110] 11A illustrates an example of a system 1105 including the signal path 1040, latch circuit 1010, and controller 1030 described above. The system 1105 also includes a driver 1110 and a pad 1120. The driver 1110 has an input 1112 and an output 1114. The input 1112 of the driver 1110 is coupled to an output 1044 of the signal path 1040, and the output 1114 of the driver 1110 is coupled to a pad 1120. In certain aspects, the signal path 1040, the latch circuit 1010, the driver 1110, and the pad 1120 may be integrated on a chip (i.e., a die), and the pad 1120 may be coupled to another chip via metal lines (e.g., formed on a printed circuit board (PCB)).

[0085]

[0111] The driver 1110 may be configured in an active mode to receive a signal from the signal path 1040 and drive the pad 1120 (and thus the metal line) based on the received signal. For example, the driver 1110 may be configured to drive the pad 1120 high when the received signal is high and drive the pad 1120 low when the received signal is low. Alternatively, the driver 1110 may be configured to drive the pad 1120 low when the received signal is high and drive the pad 1120 high when the received signal is low. The driver 1110 may be implemented with a pull-up transistor to drive the pad 1120 high and a pull-down transistor to drive the pad 1120 low.

[0086]

[0112] 11A, the logic state at the output 1044 of the signal path 1040 may toggle between high and low over multiple idle periods. This is because, as described above, the controller 1030 alternately holds the input 1042 of the signal path 1040 high and low to balance the aging. In some use cases, it is desirable for the input 1112 of the driver 1110 and / or the pad 1120 to be low (i.e., logic 0) in the idle mode. For example, a specification may require that the pad 1120 be low in the idle mode such that a transmission line (not shown) coupled to the pad 1120 is held low in the idle mode. In these cases, a clock gating circuit 1140 (also called a clock gating cell) may be coupled between the output 1044 of the signal path 1040 and the input 1112 of the driver 1110 to isolate the driver 1110 and the pad 1120 from toggling between low and high at the output 1044 of the signal path 1040 in idle mode, an example of which is shown in FIG. 11B.

[0087]

[0113] 11B, the clock gating circuit 1140 has a signal input 1142 coupled to the output 1044 of the signal path 1040, an output 1146 coupled to the input 1112 of the driver 1110, and a control input 1144 coupled to a third output 1130 of the controller 1030. In this example, the controller 1030 may be configured to selectively gate or ungate the clock gating circuit 1140 via the third output 1130. For example, the clock gating circuit 1140 may be configured to gate when a first logical value is input to the control input 1144 and ungate when a second logical value is input to the control input 1144. In this example, the controller 1030 may gate the clock gating circuit 1140 by outputting a first logic value to the control input 1144 of the clock gating circuit 1140 and ungate the clock gating circuit 1140 by outputting a second logic value to the control input 1144 of the clock gating circuit 1140. In this example, the first logic value may be 1 and the second logic value may be 0, or vice versa. In this example, the clock gating circuit 1140 may be configured to hold the output 1146 low when the clock gating circuit 1140 is gated.

[0088]

[0114] In this example, the controller 1030 may be configured to ungate the clock gating circuit 1140 in the active mode (e.g., when the controller 1030 receives an indicator signal at the input 1032 indicating an idle mode) and gate the clock gating circuit 1140 in the idle mode. In this example, the clock gating circuit 1140 holds the output 1146 low in the idle mode, which isolates the driver 1110 and the pad 1120 from toggling between low and high at the output 1044 of the signal path 1040 in the idle mode.

[0089]

[0115] It should be understood that the present disclosure is not limited to the example shown in Figure 11B. For example, in another example, the clock gating circuit 1140 may be coupled between the output 1114 of the driver 1110 and the pad 1120 to isolate the pad 1120 from toggling in the idle mode. In this example, the controller 1030 may gate the clock gating circuit 1140 in the idle mode and ungate the clock gating circuit 1140 in the active mode, as described above.

[0090]

[0116] In the above example, the clock gating circuit 1140 is configured to hold the output 1146 low when the clock gating circuit 1140 is gated. However, it should be understood that the present disclosure is not limited to this example. For example, in some use cases, it may be desirable for the input 1112 and / or pad 1120 of the driver 1110 to be high (i.e., logic 1) in idle mode. In these cases, the clock gating circuit 1140 is configured to hold the output 1146 high when the clock gating circuit 1140 is gated.

[0091]

[0117] Figure 12 illustrates an example of a system 1205 in which the example system 205 shown in Figure 2 is combined with the example system 1005 shown in Figure 10, according to certain aspects. In the following description of Figure 12, signal path 210 is referred to as the first signal path, signal path 1040 is referred to as the second signal path, controller 230 is referred to as the first controller, and controller 1030 is referred to as the second controller.

[0092]

[0118] In this example, the output 214 of the first signal path 210 is coupled to the clock input 1014 of the latch circuit 1010. Thus, in this example, the clock signal used to clock the latch circuit 1010 propagates through the first signal path 210. The first controller 230 controls the aging of the first signal path 210 in the idle mode of the first signal path 210 as described above with reference to FIG. 2. The second controller 1030 controls the aging of the second signal path 1040 in the idle mode of the second signal path 1040 as described above with reference to FIG. 10. The output 1044 of the second signal path 1040 may be coupled to a driver (e.g., driver 1110), a sequential logic circuit (e.g., a flip-flop), a processor, or another type of circuit.

[0093]

[0119] 13 illustrates an example of a system 1305 including the signal path 1040 and the controller 1030 described above. The system 1305 also includes a single data rate (SDR) to double data rate (DDR) converter 1310 according to an embodiment of the present disclosure. The SDR-DDR converter 1310 includes a first latch circuit 1320, a second latch circuit 1340, and a multiplexer 1360. The SDR-DDR converter 1310 has a first input 1312, a second input 1314, and an output 1316. The first input 1312 is configured to receive a first data signal, and the second input 1314 is configured to receive a second data signal. The first data signal may include odd data bits and the second data signal may include even data bits, or vice versa. The first data signal and the second data signal may each include one data bit per period of the clock signal (labeled "Clk"). Thus, in this example, the first data signal and the second data signal each transmit data at a single data rate (i.e., one bit per period of the clock signal). The output 1316 of the SDR-DDR converter 1310 is coupled to an input 1042 of the signal path 1040.

[0094]

[0120] The first latch circuit 1320 has a signal input 1322, a clock input 1324, a set input 1326, a reset input 1328, and an output 1330. The signal input 1322 is coupled to a first input 1312 of the SDR-DDR converter 1310, and the clock input 1324 is configured to receive a clock signal. The first latch circuit 1320 is configured to latch (i.e., capture) a logical value of the first data signal on a rising edge of the clock signal and output the latched logical value at the output 1330. Thus, in this example, the first latch circuit 1320 is a rising-edge triggered latching circuit (also referred to as a positive-edge triggered latching circuit).

[0095]

[0121] The first latch circuit 1320 is configured to set when the set input 1326 is asserted (e.g., a logical 1 is input to the set input 1326). When the set input 1326 is asserted, the output 1330 goes high (i.e., a logical 1). The first latch circuit 1320 is configured to reset when the reset input 1328 is asserted (e.g., a logical 1 is input to the reset input 1328). When the reset input 1328 is asserted, the output 1330 goes low (i.e., a logical 0).

[0096]

[0122] The second latch circuit 1340 has a signal input 1342, a clock input 1344, a set input 1346, a reset input 1348, and an output 1350. The signal input 1342 is coupled to the second input 1314 of the SDR-DDR converter 1310, and the clock input 1344 is configured to receive a clock signal. The second latch circuit 1340 is configured to latch (i.e., capture) a logical value of the second data signal on a falling edge of the clock signal and output the latched logical value at the output 1350. Thus, in this example, the second latch circuit 1340 is a falling-edge triggered latching circuit (also referred to as a negative-edge triggered latching circuit).

[0097]

[0123] The second latch circuit 1340 is configured to set when the set input 1346 is asserted (e.g., a logical 1 is input to the set input 1346). When the set input 1346 is asserted, the output 1350 goes high (i.e., a logical 1). The second latch circuit 1340 is configured to reset when the reset input 1348 is asserted (e.g., a logical 1 is input to the reset input 1348). When the reset input 1348 is asserted, the output 1350 goes low (i.e., a logical 0).

[0098]

[0124] The multiplexer 1360 has a first input 1362, a second input 1364, a select input 1366, and an output 1368. The first input 1362 is coupled to the output 1330 of the first latch circuit 1320, the second input 1364 is coupled to the output 1350 of the second latch circuit 1340, the select input 1366 is configured to receive a clock signal, and the output 1368 is coupled to the output 1316 of the SDR-to-DDR converter 1310.

[0099]

[0125] The multiplexer 1360 is configured to couple the output 1330 of the first latch circuit 1320 to the output 1368 when the clock signal is high, and to couple the output 1350 of the second latch circuit 1340 to the output 1368 when the clock signal is low. Thus, for each period of the clock signal, the multiplexer 1360 outputs latched data bits (e.g., odd data bits) from the output 1330 of the first latch circuit 1320 during a portion of the period that the clock signal is high, and outputs latched data bits (e.g., even data bits) from the output 1350 of the second latch circuit 1340 during a portion of the period that the clock signal is low. Thus, the multiplexer 1360 outputs two data bits per period of the clock signal at the output 1316, and therefore outputs data bits at the output 1316 at double data rate.

[0100]

[0126] An output 1316 of the SDR-to-DDR converter 1310 is coupled to an input 1042 of the signal path 1040 such that the SDR-to-DDR converter 1310 outputs data bits at double data rate to the signal path 1040. An output 1044 of the signal path 1040 may be coupled to a driver (e.g., driver 1110), a sequential logic circuit (e.g., a flip-flop), a processor, or another type of circuit.

[0101]

[0127] In this example, a first output 1034 of the controller 1030 is coupled to a set input 1326 of the first latch circuit 1320 and to a set input 1346 of the second latch circuit 1340. A second output 1036 of the controller 1030 is coupled to a reset input 1328 of the first latch circuit 1320 and to a reset input 1348 of the second latch circuit 1340.

[0102]

[0128] In the active mode (also called the functional mode), the controller 1030 deasserts the set input 1326 and the reset input 1328 of the first latch circuit 1320 (e.g., inputs a logic 0 to both the set input 1326 and the reset input 1328) and deasserts the set input 1346 and the reset input 1348 of the second latch circuit 1340 (e.g., inputs a logic 0 to both the set input 1346 and the reset input 1348). In this case, the first latch circuit 1320 latches the logic value (i.e., data bit) of the first data signal on the rising edge of the clock signal and outputs the latched logic value to the first input 1362 of the multiplexer 1360, and the second latch circuit 1340 latches the logic value (i.e., data bit) of the second data signal on the falling edge of the clock signal and outputs the latched logic value to the second input 1364 of the multiplexer 1360.

[0103]

[0129] In the idle mode, the controller 1030 controls the aging of the signal path 1040. The controller 1030 may determine that the signal path 1040 is in the idle mode when the input 1032 of the controller 1030 receives an indicator signal indicating the idle mode. In this example, the controller 1030 may hold the input 1042 of the signal path 1040 high by asserting the set input 1326 of the first latch circuit 1320 (e.g., by outputting a logic 1 at the first output 1034) and the set input 1346 of the second latch circuit 1340. The controller 1030 may hold the input 1042 of the signal path 1040 low by asserting the reset input 1328 of the first latch circuit 1320 (e.g., by outputting a logic 1 at the second output 1036) and the reset input 1348 of the second latch circuit 1340.

[0104]

[0130] In idle mode, the controller 1030 may control the aging of the signal path 1040 using any of the techniques described above with reference to FIG. 2. For example, the controller 1030 may keep the input 1042 of the signal path 1040 alternating low and high for multiple idle periods. In this example, the controller 1030 may keep the input 1042 low during odd idle periods and high during even idle periods, or vice versa. In another example, the controller 1030 may control the aging of the signal path 1040 based on an aging pattern, as described above with reference to FIG.

[0105]

[0131] Although the SDR-to-DDR converter 1310 has been described above using the example of data signals, it should be understood that the SDR-to-DDR converter 1310 may also be used for control and address signals.

[0106]

[0132] As described above, the controller 1030 may control the aging based on the sequence of N bits stored in the register 1035. In one example, the register 1035 may include a circular shift register configured to output the bits in the sequence one by one. In this regard, FIG. 14 illustrates an example in which the register 1035 includes a circular shift register 1410 according to a particular embodiment. In this example, the circular shift register 1410 includes storage slots 1415-1 to 1415-N, where each of the storage slots 1415-1 to 1415-N may hold one bit of the sequence of N bits. The circular shift register 1410 has an input 1412 and an output 1414. The input 1412 is used to control the shifting of bits in the circular shift register 1410, as described further below. The output 1414 is configured to output the bits in the storage slots 415-N.

[0107]

[0133] In this example, the controller 1030 also includes a first multiplexer 1450, a second multiplexer 1460, and an inverter 1470. The first multiplexer 1450 has a first input 1452 coupled to the output 1414 of the circular shift register 1410, a second input 1454 configured to receive a logic 0, an output 1458 coupled to the first output 1034 of the controller 1030, and a selection input 1456. The second multiplexer 1460 has a first input 1462 coupled to the output 1414 of the circular shift register 1410 via an inverter 1470, a second input 1464 configured to receive a logic 0, an output 1468 coupled to the second output 1036 of the controller 1030, and a selection input 1466.

[0108]

[0134] The controller 1030 also includes a control circuit 1420. The control circuit 1420 has an input 1422, a first output 1424, and a second output 1426. The input 1422 is coupled to an input 1032 of the controller 1030 and configured to receive the indicator signal described above. The first output 1424 is coupled to an input 1412 of the circular shift register 1410 and is used by the control circuit 1420 to shift bits in the circular shift register 1410, as described further below. The second output 146 is coupled to a selection input 1456 of the first multiplexer 1450 and a selection input 1466 of the second multiplexer 1460.

[0109]

[0135] In operation, the control circuit 1420 is configured to instruct each of the first multiplexer 1450 and the second multiplexer 1460 via the second output 1426 to select their respective second inputs 1454 and 1464 in the active mode. This causes the first multiplexer 1450 and the second multiplexer 1460 to output a 0 to the set input 1016 and the reset input 1018 of the latch circuit 1010, which deasserts both the set input 1016 and the reset input 1018.

[0110]

[0136] In operation, the control circuit 1420 is configured to instruct each of the first multiplexer 1450 and the second multiplexer 1460 via the second output 1426 to select their respective first inputs 1452 and 1462 in idle mode. This couples the set input 1016 to the output 1414 of the circular shift register 1410 and couples the reset input 1018 to the output 1414 of the circular shift register 1410 via an inverter 1470. Thus, the reset input 1018 receives the inverse of the bit output by the circular shift register 1410 in this example.

[0111]

[0137] In idle mode, the control circuitry 1420 may be configured to shift bits in the circular shift register 410 by one bit position per idle period via the first output 1424 such that the circular shift register 410 outputs each bit in the sequence of N bits once every N idle periods. For example, the control circuitry 1420 may shift bits in the circular shift register 1410 by one bit position each time the indicator signal indicates an idle mode. With each shift, bits in each storage slot 1415-1 through 1415-N may be shifted up to the next storage slot 1415-1 through 1415-N in the circular shift register 1410. For example, in one shift, bits in storage slot 1415-1 may be shifted up to storage slot 1415-2 and bits in storage slot 415-N may be shifted back to storage slot 1415-1 (as indicated by the arrow looping back from storage slot 1415-N to storage slot 1415-1).

[0112]

[0138] Thus, in this example, the bits in the circular shift register 1410 are shifted by one bit position every idle period such that the circular shift register 1410 cycles through a sequence of N bits once every N idle periods. In this example, the output 1020 of the latch circuit 1010 may be held high when the circular shift register 1410 outputs a 1. This is because the first multiplexer 1450 outputs a 1 to the set input 1016 of the latch circuit 1010, which asserts the set input 1016, and the second multiplexer outputs a 0 (i.e., the inverse of the 1) to the reset input 1018 of the latch circuit 1010, which deasserts the reset input 1018. Also, in this example, the output 1020 of the latch circuit 1010 may be held low when the circular shift register 1410 outputs a 0. This is because the first multiplexer 1450 outputs a 0 to the set input 1016 of the latch circuit 1010, which deasserts the set input 1016, and the second multiplexer outputs a 1 (i.e., the inverse of 0) to the reset input 1018 of the latch circuit 1010, which asserts the reset input 1018.

[0113]

[0139] In the example shown in FIG. 14, the inverter 1470 is coupled between the output 1414 of the circular shift register 1410 and the first input 1462 of the second multiplexer 1460. However, it should be understood that the present disclosure is not limited to this example. In other implementations, the inverter 1470 may be coupled between the output 1414 of the circular shift register 1410 and the first input 1452 of the first multiplexer 1450. In this example, the output 1020 of the latch circuit 1010 may be held low when the circular shift register 1410 outputs a 1, and the output 1020 of the latch circuit 1010 may be held high when the circular shift register 1410 outputs a 0.

[0114]

[0140] 15 illustrates another example of a system 1505 with aging mitigation in accordance with certain aspects of the present disclosure. In this example, the system 1505 includes the signal path 210, the multiplexer 220, and the controller 230 described above. The system 1505 also includes a second multiplexer 1520. In the following description of FIG. 15, the multiplexer 220 will be referred to as the first multiplexer 220.

[0115]

[0141] The second multiplexer 1520 has a first input 1522, a second input 1524, a selection input 1526, and an output 1528. The output 1528 of the second multiplexer 1520 is coupled to the second input 224 of the first multiplexer 220, and the selection input 1526 of the second multiplexer 1520 is coupled to the first output 234 of the controller 230. The first input 1522 of the second multiplexer 1520 is configured to receive a logical 0, and the second input 1524 of the second multiplexer 1520 is configured to receive a logical 1. For example, the first input 1522 may receive a logical 0 by grounding the first input 1522, and the second input 1524 may receive a logical 1 by coupling the second input 1524 to a supply rail.

[0116]

[0142] In the idle mode, the second multiplexer 1520 is configured to receive a time-varying control signal. As described above, in certain aspects, the time-varying control signal may alternate between 1 (i.e., high) and 0 (i.e., low) over a number of idle periods, or may switch between 1 (i.e., high) and 0 (i.e., low) based on a time-varying pattern. The second multiplexer 1520 may then select a logic 0 at the first input 1522 or a logic 1 at the second input 1524 based on the logic state of the time-varying control signal, and output the selected one of the logic 0 and the logic 1 at the output 1528. For example, the second multiplexer 1520 may select a logic 0 at the first input 1522 when the time-varying control signal is 0, and select a logic 1 at the second input 1524 when the time-varying control signal is 1, or vice versa.

[0117]

[0143] In idle mode, the first multiplexer 220 is configured to receive a selected one of a logic 0 and a logic 1 from the second multiplexer 1520 at the second input 224. Because the second input 224 of the first multiplexer 220 is selected in idle mode as described above, the first multiplexer 220 passes the selected one of a logic 0 and a logic 1 to the input 212 of the signal path 210. For example, when a logic 0 is selected, the input 212 of the signal path is held low in idle mode, and when a logic 1 is selected, the input 212 of the signal path is held high in idle mode. Thus, in this example, the output of the second multiplexer 1520 provides a time-varying control signal to the second input 224 of the first multiplexer 220.

[0118]

[0144] As described above, signal path 210, signal path 910, and signal path 1040 may each include a delay circuit, respectively. For example, signal path 210, signal path 910, and signal path 1040 may each include a delay circuit 120 including delay buffers 120-1 to 120-4 connected in series. In the example of FIG. 1A, four delay buffers 120-1 to 120-4 are shown, but it should be understood that the signal paths may include a different number of delay buffers. Although FIG. 1A shows an example in which delay buffers 120-1 to 120-4 are implemented using inverters, it should be understood that delay buffers 120-1 to 120-4 are not limited to this example and delay buffers 120-1 to 120-4 may be implemented using other types of delay buffers.

[0119]

[0145] In certain aspects, a signal path (e.g., signal path 210, signal path 910, or signal path 1040) may include a delay circuit having an adjustable delay (e.g., to adjust the timing of a data signal and / or a clock signal). For example, the delay circuit may include delay buffers and a switching circuit configured to control which of the delay buffers are coupled between the input and output of the delay circuit. In this example, the delay of the delay circuit may be adjusted by using the switching circuit to control the number of delay buffers coupled between the input and output of the delay circuit. The switching circuit may include a switch, a logic gate, a multiplexer, or any combination thereof.

[0120]

[0146] 16 illustrates an example of a memory interface circuit 1600 in which aging control according to aspects of the disclosure may be used. However, it should be understood that the disclosure is not limited to the memory interface circuit 1600 and may be used in other types of circuits. The memory interface circuit 1600 may be configured to provide one or more processors (e.g., a central processing unit (CPU) core, a graphics processing unit (GPU), etc.) access to a memory device (not shown). The memory device may be a double data rate (DDR) dynamic random access memory (DRAM) or another type of memory device.

[0121]

[0147] The memory interface circuit 1600 includes a controller 1690 configured to perform aging control operations for the memory interface circuit 1600, as described further below. The memory interface circuit 1600 also includes a first pad 1610, a second pad 1612, a third pad 1614, a fourth pad 1616, a first receiver 1620, a second receiver 1624, a first driver 1622, a second driver 1626, a third driver 1627, and a fourth driver 1628. In the example of FIG. 16, a first pad 1610 is used for a data signal (labeled “DQ”), a second pad 1612 is used for a data strobe signal (labeled “DQS”), a third pad 1614 is used for a clock signal (labeled “CK”), and a fourth pad 1616 is used for a command / address signal (labeled “CA”). The first pad 1610, the second pad 1612, the third pad 1614, and the fourth pad 1616 are coupled to a memory device (not shown) via respective metal lines (not used). Although one data line corresponding to the first pad 1610 is shown in FIG. 16 for ease of illustration, it should be understood that the memory interface circuit 1600 may include multiple data lines in parallel for transmitting and / or receiving multiple data signals in parallel.

[0122]

[0148] An input of the first receiver 1620 and an output of the first driver 1622 are coupled to the first pad 1610. An input of the second receiver 1624 and an output of the second driver 1626 are coupled to the second pad 1612. An output of the third driver 1627 is coupled to the third pad 1614, and an output of the fourth driver 1628 is coupled to the fourth pad 1616. The first receiver 1620 may be configured to receive a data signal from the memory device via the first pad 1610. The first receiver 1620 may be configured to amplify the received data signal. The first driver 1622 may be configured to receive the data signal and drive the first pad 1610 with the data signal to transmit the data signal to the memory device. The second receiver 1624 may be configured to receive a data strobe signal from the memory device via the second pad 1612. The second driver 1626 may be configured to receive a data strobe signal and drive the second pad 1612 with the data strobe signal to transmit the data strobe signal to the memory device. The data strobe signal may be a clock signal used to capture data bits from a data signal. The third driver 1627 may be configured to receive a clock signal and drive the third pad 1614 with the clock signal to transmit the clock signal to the memory device. The fourth driver 1628 may be configured to receive a command / address (CA) signal and drive the fourth pad 1616 with the CA signal to transmit the CA signal to the memory device. In this example, the clock signal transmitted from the third pad 1614 may be used to capture command bits and / or address bits from the CA signal.

[0123]

[0149] The memory interface circuit 1600 also includes a first multiplexer 1630, a first signal path 1650, a second multiplexer 1640, a second signal path 1654, a second multiplexer 1640, a third signal path 1657, a third multiplexer 1675, a fourth signal path 1660, a fourth multiplexer 1680, a fifth signal path 1663, a sixth signal path 1666, a first SDR-to-DDR converter 1670, and a second SDR-to-DDR converter 1685. Each of the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 may include a delay circuit (e.g., the delay circuit 115) for delaying the respective signal.

[0124]

[0150] The first multiplexer 1630 has a first input 1632 coupled to the output of the first receiver 1620, a second input 1634 coupled to the controller 1690, a selection input 1636 coupled to the controller 1690, and an output 1638. The first signal path 1650 has an input 1651 coupled to the output 1638 of the first multiplexer 1630, and an output 1652.

[0125]

[0151] The first SDR-to-DDR converter 1670 has a first signal input 1671-1 and a second signal input 1671-2 coupled to a data source (not shown). The first SDR-to-DDR converter 1670 also has a set input 1672 coupled to the controller 1690, a reset input 1673 coupled to the controller 1690, and an output 1674. The second signal path 1654 has an input 1655 coupled to an output 1674 of the first SDR-to-DDR converter 1670 and an output 1656 coupled to an input of the first driver 1622.

[0126]

[0152] The second multiplexer 1640 has a first input 1642 coupled to the output of the second receiver 1624, a second input 1644 coupled to the controller 1690, a selection input 1646 coupled to the controller 1690, and an output 1648. The third signal path 1657 has an input 1658 coupled to the output 1648 of the second multiplexer 1640, and an output 1659.

[0127]

[0153] A third multiplexer 1675 has a first input 1676 coupled to a data strobe source (not shown), a second input 1677 coupled to a controller 1690, a select input 1678 coupled to the controller 1690, and an output 1679. A fourth signal path 1660 has an input 1661 coupled to the output 1679 of the third multiplexer 1675 and an output 1662 coupled to the input of the second driver 1626.

[0128]

[0154] The fourth multiplexer 1680 has a first input 1681 coupled to a clock source (not shown), a second input 1682 coupled to the controller 1690, a select input 1683 coupled to the controller 1690, and an output 1684. The fifth signal path 1663 has an input 1664 coupled to the output 1684 of the fourth multiplexer 1680 and an output 1665 coupled to the input of the third driver 1627.

[0129]

[0155] The second SDR-to-DDR converter 1685 has a first signal input 1686-1 and a second signal input 1686-2 coupled to a command / address source (not shown). The second SDR-to-DDR converter 1685 also has a set input 1687 coupled to the controller 1690, a reset input 1688 coupled to the controller 1690, and an output 1689. The sixth signal path 1666 has an input 1667 coupled to an output 1689 of the second SDR-to-DDR converter 1685 and an output 1668 coupled to an input of the fourth driver 1628.

[0130]

[0156] Next, an example operation of the memory interface circuit 1600 will be described in accordance with a particular aspect.

[0131]

[0157] During a write operation, the first SDR-DDR converter 1670 may receive data to be written to the memory device. For example, the first SDR-DDR converter 1670 may receive data in two or more data signals at a single data rate (SDR), where a first one of the data signals may include odd data bits and a second one of the data signals may include even bits. In this example, the first SDR-DDR converter 1670 may receive the first one of the data signals via the first signal input 1671-1 and the second one of the data signals via the second signal input 1671-2.

[0132]

[0158] The first SDR-DDR converter 1670 may convert the data signal in SDR to a data signal in double data rate (DDR) and output the data signal in DDR at output 1674. In one example, the first SDR-DDR converter 1670 may be implemented using the exemplary SDR-DDR converter 1310. The data signal in DDR propagates via the second signal path 1654 to the first driver 1622, which transmits the data signal in DDR to the memory device via the first pad 1610. In this example, the second signal path 1654 may delay the data signal (e.g., to align the data signal with one or more other data signals (not shown) on a parallel data line). As mentioned above, the other data lines are not shown in FIG. 16 for ease of illustration.

[0133]

[0159] During a write operation, the third multiplexer 1675 may receive a data strobe signal at the first input 1676. The controller 1690 instructs the third multiplexer 1675 to select the first input 1676 such that the third multiplexer 1675 outputs the data strobe signal to the fourth signal path 1660. The data strobe signal may have half the frequency of the data signal in the DDR (i.e., the data signal in the DDR includes two data bits per period of the data strobe signal). The data strobe signal propagates via the fourth signal path 1660 to the second driver 1626, which transmits the data strobe signal to the memory device via the second pad 1612. In this example, the fourth signal path 1660 may delay the data strobe signal (e.g., to adjust the timing of the data strobe signal relative to the data signal in the DDR).

[0134]

[0160] During a read operation, the first receiver 1620 may receive a data signal containing read data from the memory device via the first pad 1610. The controller 1690 may instruct the first multiplexer 1630 to select the first input 1632 to allow the data signal to propagate through the first multiplexer 1630 to the first signal path 1650. The first signal path 1650 may output the read data to a memory controller (not shown), which may buffer the data in the data signal and send the data to a processor that requested the data from the memory device.

[0135]

[0161] During a read operation, the second receiver 1624 may receive a data strobe signal from the memory device via the second pad 1612 and output the received data strobe signal to the first input 1642 of the second multiplexer 1640. The controller 1690 instructs the second multiplexer 1640 to select the first input 1642 such that the second multiplexer 1640 outputs the data strobe signal to the third signal path 1657. The data strobe signal propagates via the third signal path 1657 to a memory controller (not shown), where the memory controller may use the data strobe signal to capture read data in the data signal received from the memory device. In this example, the third signal path 1657 may delay the data strobe signal (e.g., to adjust the timing of the data strobe signal relative to the received data signal).

[0136]

[0162] The second SDR-DDR converter 1685 may receive command and / or address information for the memory device. For example, the second SDR-DDR converter 1685 may receive command and / or address information in two or more control / address (CA) signals at single data rate (SDR), where a first one of the CA signals may include odd bits and a second one of the CA signals may include even bits. In this example, the second SDR-DDR converter 1685 may receive the first one of the CA signals via the first signal input 1686-1 and the second one of the CA signals via the second signal input 1686-2.

[0137]

[0163] The second SDR-DDR converter 1685 may convert the CA signal in SDR to a CA signal in double data rate (DDR) and output the CA signal in DDR at output 1689. In one example, the second SDR-DDR converter 1685 may be implemented with the exemplary SDR-DDR converter 1310. The CA signal in DDR propagates via the sixth signal path 1666 to the fourth driver 1628, which transmits the CA signal in DDR to the memory device via the fourth pad 1616.

[0138]

[0164] The fourth multiplexer 1680 may receive a clock signal at a first input 1681. The controller 1690 instructs the fourth multiplexer 1680 to select the first input 1681 such that the fourth multiplexer 1680 outputs the clock signal to the fifth signal path 1663. The clock signal propagates via the fifth signal path 1663 to the third driver 1627, which transmits the clock signal to the memory device via the third pad 1614. The memory device may use the clock signal to capture command / address bits from the CA signal.

[0139]

[0165] For a write operation, a memory controller (not shown) may receive a request from a processor (not shown) to write data to a memory device. In response, the memory controller generates a CA signal including a write command and a write address for the data to be written. The second SDR-DDR converter 1685 receives the CA signal in SDR via a first signal input 1686-1 and a second signal input 1686-2, converts the CA signal in SDR to a CA signal in DDR, and outputs the CA signal in DDR at an output 1689. The CA signal propagates through a sixth signal path 1666 to a fourth driver 1628, which transmits the CA signal to the memory device via a fourth pad 1616.

[0140]

[0166] For a read operation, the memory controller (not shown) may receive a read request from a processor (not shown). In response, the memory controller generates a CA signal including a read command and a read address for data to be read from the memory device. The second SDR-DDR converter 1685 receives the CA signal in SDR via the first signal input 1686-1 and the second signal input 1686-2, converts the CA signal in SDR to a CA signal in DDR, and outputs the CA signal in DDR at the output 1689. The CA signal propagates through the sixth signal path 1666 to the fourth driver 1628, which transmits the CA signal to the memory device via the fourth pad 1616.

[0141]

[0167] The memory controller may also generate a CA signal including a command to perform a housekeeping operation (e.g., a refresh operation). In this case, the memory controller generates a CA signal including a housekeeping command (e.g., a refresh command) for the memory device. The second SDR-DDR converter 1685 receives the CA signal in SDR via the first signal input 1686-1 and the second signal input 1686-2, converts the CA signal in SDR to a CA signal in DDR, and outputs the CA signal in DDR at the output 1689. The CA signal propagates through the sixth signal path 1666 to the fourth driver 1628, which transmits the CA signal to the memory device via the fourth pad 1616.

[0142]

[0168] The controller 1690 may be configured to perform age-varying control operations for the memory interface circuit 1600 based on activity of the memory interface circuit 1600, as described further below. In certain aspects, the controller 1690 may receive one or more signals at an input 1692 indicative of operation of the memory interface circuit 1600. The controller 1690 may be implemented with one or more instances of the example controller 230 and / or controller 1030 described above.

[0143]

[0169] During a write operation, the first signal path 1650 and the third signal path 1657 may be idle, while the second signal path 1654, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 are active. In other words, the read data path and the read data strobe path (which include the first signal path 1650 and the third signal path 1657, respectively) may be in an idle mode during a write operation. In this case, the controller 1690 may receive a signal from the memory controller indicating a write operation. In response, the controller 1690 may perform an age-varying control operation for the first signal path 1650 and the third signal path 1657 while the second signal path 1654, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 are active.

[0144]

[0170] In this regard, the controller 1690 may instruct the first multiplexer 1630 via the selection input 1636 to select the second input 1634. The controller 1690 may then input an aging control signal to the second input 1634 of the first multiplexer 1630 to control the aging of the first signal path 1650 (e.g., using any of the example techniques described above). For example, the aging control signal may keep the input 1651 of the first signal path 1650 alternately high and low for multiple idle periods, may control the aging of the first signal path 1650 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0145]

[0171] The controller 1690 may also instruct the second multiplexer 1640 to select the second input 1644 via the selection input 1646. The controller 1690 may then input an aging control signal to the second input 1644 of the second multiplexer 1640 to control the aging of the third signal path 1657 (e.g., using any of the example techniques described above). For example, the aging control signal may keep the input 1658 of the third signal path 1657 alternately high and low for multiple idle periods, may control the aging of the third signal path 1657 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0146]

[0172] During a read operation, the second signal path 1654 and the fourth signal path 1660 may be idle, while the first signal path 1650, the third signal path 1657, the fifth signal path 1663, and the sixth signal path 1666 are active. In other words, the write data path and the write data strobe path (which include the second signal path 1654 and the fourth signal path 1660, respectively) may be in an idle mode during a read operation. In this case, the controller 1690 may receive a signal from the memory controller indicating a read operation. In response, the controller 1690 may perform an age-varying control operation for the second signal path 1654 and the fourth signal path 1660 while the first signal path 1650, the third signal path 1657, the fifth signal path 1663, and the sixth signal path 1666 are active.

[0147]

[0173] In this regard, the controller 1690 may control the aging of the second signal path 1654 using the set input 1672 and the reset input 1673 of the first SDR-DDR converter 1670 (e.g., using any of the exemplary techniques described above). For example, the controller 1690 may keep the input 1655 of the second signal path 1654 high by asserting the set input 1672 and keep the input 1655 of the second signal path 1654 low by asserting the reset input 1673. In this example, the controller 1690 may control the aging by, for example, keeping the input 1655 of the second signal path 1654 alternately high and low for multiple idle periods of the second signal path 1654. In another example, the controller 1690 may control the aging of the second signal path 1654 based on an aging pattern.

[0148]

[0174] The controller 1690 may also instruct the third multiplexer 1675 to select the second input 1677 via the selection input 1678. The controller 1690 may then input an aging control signal to the second input 1677 of the third multiplexer 1675 to control the aging of the fourth signal path 1660 (e.g., using any of the example techniques described above). For example, the aging control signal may keep the input 1661 of the fourth signal path 1660 alternately high and low for multiple idle periods, may control the aging of the fourth signal path 1660 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0149]

[0175] During a housekeeping operation (e.g., a refresh operation), the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660 associated with the read and write operations may be idle, while the fifth signal path 1663 and the sixth signal path 1666 may be active to send a housekeeping command (e.g., a refresh command) to the memory device. In other words, the write data path, the write data strobe path, the read data path, and the read data strobe path may be idle during the housekeeping operation. In this case, the controller 1690 may receive a signal indicating a housekeeping operation from the memory controller. In response, the controller 1690 may perform an aging control operation for the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660. For example, the controller 1690 may perform aging control operations for the first signal path 1650 and the third signal path 1657 in the manner described above for a write operation. The controller 1690 may also perform aging control operations for the second signal path 1654 and the fourth signal path 1660 in the manner described above for a read operation.

[0150]

[0176] During traffic idle mode or clock stop power down (CSPD) mode, the CA, CK, DQ, and DQS paths are all idle. In this case, the controller 1690 may receive a signal indicating the traffic idle mode or the CSPD mode from the memory controller. In response, the controller 1690 may perform aging control operations for the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666. The controller 1690 may perform aging control operations for the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660 in the manner described above.

[0151]

[0177] The controller 1690 may control the aging of the sixth signal path 1666 using the set input 1687 and the reset input 1688 of the second SDR-DDR converter 1685 (e.g., using any of the exemplary techniques described above). For example, the controller 1690 may keep the input 1667 of the sixth signal path 1666 high by asserting the set input 1687 and keep the input 1667 of the sixth signal path 1666 low by asserting the reset input 1688. In this example, the controller 1690 may control the aging by, for example, keeping the input 1667 of the sixth signal path 1666 alternately high and low for multiple idle periods. In another example, the controller 1690 may control the aging of the sixth signal path 1666 based on an aging pattern.

[0152]

[0178] The controller 1690 may also instruct the fourth multiplexer 1680 to select the second input 1682 via the selection input 1683. The controller 1690 may then input an aging control signal to the second input 1682 of the fourth multiplexer 1680 to control the aging of the fifth signal path 1663 (e.g., using any of the example techniques described above). For example, the aging control signal may keep the input 1664 of the fifth signal path 1663 alternately high and low for multiple idle periods, may control the aging of the fifth signal path 1663 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0153]

[0179] During the clock free running mode, the clock signal may be running in the absence of command traffic. This may be done, for example, to keep the memory device synchronized with the clock signal. In this mode, the fifth signal path 1663 remains active for the clock signal, while the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, and the sixth signal path 1666 are idle. In this case, the controller 1690 may receive a signal indicating the clock free running mode from the memory controller. In response, the controller 1690 may perform aging control operations for the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, and the sixth signal path 1666 in the manner described above.

[0154]

[0180] FIG. 17 illustrates another example of a memory interface circuit 1900 in which aging control according to aspects of the disclosure may be used. The memory interface circuit 1900 includes the first multiplexer 1630, the second multiplexer 1640, the third multiplexer 1675, the fourth multiplexer 1680, the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, the sixth signal path 1666, the first receiver 1620, the second receiver 1624, the first driver 1622, the second driver 1626, the third driver 1627, the fourth driver 1628, the first pad 1610, the second pad 1612, the third pad 1614, the fourth pad 1616, and the controller 1690 described above. The memory interface circuit 1900 also includes a fifth multiplexer 1710 and a sixth multiplexer 1720.

[0155]

[0181] The fifth multiplexer 1710 has a first input 1712 configured to receive a data signal, a second input 1714 coupled to the controller 1690, a select input 1716 coupled to the controller 1690, and an output 1718 coupled to an input 1655 of the second signal path 1654. In one example, the first input 1712 may receive a data signal from a first SDR-to-DDR converter 1670 (not shown in FIG. 17), where the first input 1712 of the fifth multiplexer 1710 is coupled to an output 1674 of the first SDR-to-DDR converter 1670. However, it should be understood that the present disclosure is not limited to this example.

[0156]

[0182] The sixth multiplexer 1720 has a first input 1722 configured to receive a CA signal, a second input 1724 coupled to the controller 1690, a select input 1726 coupled to the controller 1690, and an output 1728 coupled to an input 1667 of the sixth signal path 1666. In one example, the first input 1722 may receive a data signal from a second SDR-to-DDR converter 1685 (not shown in FIG. 17), where the first input 1722 of the sixth multiplexer 1720 is coupled to an output 1689 of the second SDR-to-DDR converter 1685. However, it should be understood that the present disclosure is not limited to this example.

[0157]

[0183] During a write operation, the controller 1690 instructs the fifth multiplexer 1710 via the selection input 1716 to select the first input 1712. This enables the fifth multiplexer 1710 to receive a data signal containing data to be written to the memory device and pass the data signal to the input 1655 of the second signal path 1654.

[0158]

[0184] During a read operation, a housekeeping operation, a traffic idle mode, or a CSPD mode, the controller 1690 may instruct the fifth multiplexer 1710 via the selection input 1716 to select the second input 1714. The controller 1690 may then input an aging control signal to the second input 1714 of the fifth multiplexer 1710 to control the aging of the second signal path 1654 (e.g., using any of the exemplary techniques described above). For example, the aging control signal may keep the input 1655 of the second signal path 1654 alternating high and low for multiple idle periods, may control the aging of the second signal path 1654 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0159]

[0185] During a read, write, or housekeeping operation, the controller 1690 may instruct the sixth multiplexer 1720 via the selection input 1726 to select the first input 1722. This enables the sixth multiplexer 1720 to receive a CA signal containing command and / or address information and pass the CA signal to an input 1667 of a sixth signal path 1666.

[0160]

[0186] During a traffic idle mode, a CSPD mode, or a clock free-running mode, the controller 1690 may instruct the sixth multiplexer 1720 via the selection input 1726 to select the second input 1724. The controller 1690 may then input an aging control signal to the second input 1724 of the sixth multiplexer 1720 to control the aging of the sixth signal path 1666 (e.g., using any of the example techniques described above). For example, the aging control signal may keep the input 1667 of the sixth signal path 1666 alternating high and low for multiple idle periods, may control the aging of the sixth signal path 1666 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0161]

[0187] FIG. 18 is a flow chart illustrating a method 1800 for aging control, according to certain embodiments.

[0162]

[0188] In block 1810, in an active mode, a signal is input to an input of a signal path. For example, the signal may include a data signal, a clock signal, a control signal, or an address signal. The signal path may correspond to any one of the signal path 210, the signal path 1040, the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, or the sixth signal path 1666. The signal path may include a delay circuit (e.g., the delay circuit 115). In some examples, the signal may be input to the signal path by a multiplexer (e.g., multiplexer 220, multiplexer 920, first multiplexer 1630, second multiplexer 1640, third multiplexer 1675, fourth multiplexer 1680, fifth multiplexer 1710, or sixth multiplexer 1720) or a latch circuit (e.g., latch circuit 1010, first latch circuit 1320, or second latch circuit 1340).

[0163]

[0189] In block 1820, aging of the signal path is controlled in the idle mode. The aging may be controlled by a controller (e.g., controller 230, 1030, or 1690).

[0164]

[0190] In certain aspects, in the idle mode, controlling the aging of the signal includes alternating high and low inputs of the signal for a number of successive idle periods. In certain aspects, the successive idle periods include odd and even idle periods. In these aspects, alternating high and low inputs of the signal path may include alternating low inputs of the signal path during each of the odd idle periods and alternating high inputs of the signal path during each of the even idle periods, or alternating high inputs of the signal path during each of the odd idle periods and alternating low inputs of the signal path during each of the even idle periods.

[0165]

[0191] In one particular aspect, in the idle mode, controlling the aging of the signal path includes keeping the input of the signal path high for k out of N consecutive idle periods and keeping the input of the signal path low for Nk out of N consecutive idle periods, where k is an integer greater than or equal to 1 and N is an integer greater than k.

[0166]

[0192] In certain aspects, the method 1800 may also include storing a sequence of bits in a register (e.g., register 235 or register 1035), each bit in the sequence of bits corresponding to a respective one of N consecutive idle periods in the idle mode. In these aspects, in the idle mode, controlling the aging of the signal path may include, for each one of the N consecutive idle periods, keeping an input of the signal path high during the idle period if the corresponding bit in the sequence of bits has a first bit value, and keeping an input of the signal path low during the idle period if the corresponding bit in the sequence of bits has a second bit value. The first bit value may be 1 and the second bit value may be 0, or the first bit value may be 0 and the second logical bit may be 1.

[0167]

[0193] In one particular aspect, in the idle mode, controlling the aging of the signal path includes inputting a clock signal to an input of the signal path. The clock signal may correspond to the slow clock signal described above with reference to FIG.

[0168]

[0194] Example implementations are described in the numbered clauses below.

[0169]

[0195] Clause 1. A system comprising:

[0196] a multiplexer having a first input, a second input, a selection input, and an output;

[0197] a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer;

[0198] a controller coupled to the second input of the multiplexer and to the selection input of the multiplexer, the controller having an indicator input, the controller comprising:

[0199] receiving a mode indicator signal at said indicator input;

[0200] instructing the multiplexer to select the first input of the multiplexer if the mode indicator signal has a first logic value;

[0201] instructing the multiplexer to select the second input of the multiplexer if the mode indicator signal has a second logic value and outputting a control signal to the second input of the multiplexer, the control signal controlling whether the input of the signal path remains high or low. A system configured to:

[0170]

[0202] Clause 2. The system of clause 1, wherein the first input of the multiplexer is configured to receive a data signal, a clock signal, a command signal, or an address signal.

[0171]

[0203] Clause 3. The system of clause 1 or 2, wherein the signal path comprises a delay circuit.

[0172]

[0204] Clause 4. The system of clause 3, wherein the delay circuit comprises serially coupled delay buffers.

[0173]

[0205] Clause 5. A system described in any one of clauses 1 to 4, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

[0174]

[0206] Clause 6. A system described in any one of clauses 1 to 5, wherein when the mode indicator signal has the second logical value, the controller is configured to alternately set the control signal high and low for a plurality of consecutive idle periods.

[0175]

[0207] Clause 7. The consecutive idle periods include an odd idle period and an even idle period, and the controller:

[0208] setting said control signal low during each of said odd idle periods;

[0209] setting the control signal high during each of the even idle periods; 7. The system of claim 6, configured to:

[0176]

[0210] Clause 8. The consecutive idle periods include an odd idle period and an even idle period, and the controller:

[0211] setting the aging control signal high during each of the odd idle periods;

[0212] setting the aging control signal low during each of the even idle periods; 7. The system of claim 6, configured to:

[0177]

[0213] Clause 9. When the mode indicator signal has the second logic value, the controller:

[0214] setting said control signal high for k of N consecutive idle periods;

[0215] setting the control signal low for Nk of the N consecutive idle periods;

[0023]

[0216] wherein k is an integer greater than or equal to 1, and N is an integer greater than k.

[0178]

[0217] Clause 10. The controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of N consecutive idle periods in an idle mode, and for each one of the N consecutive idle periods, the controller:

[0218] setting the control signal high during the idle period if the corresponding bit in the sequence of bits has a first bit value;

[0219] setting the control signal low during the idle period if the corresponding bit in the sequence of bits has a second bit value; The system of any one of clauses 1 to 5, configured to:

[0179]

[0220] Clause 11. A system according to any one of clauses 1 to 5, wherein the control signal comprises a clock signal.

[0180]

[0221] Article 12.

[0222] Pads and

[0223] a receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the first input of the multiplexer; The system of any one of clauses 1 to 11, further comprising:

[0181]

[0224] Article 13.

[0225] Pads and

[0226] a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path and the output of the driver is coupled to the pad; The system of any one of clauses 1 to 12, further comprising:

[0182]

[0227] Article 14.

[0228] 13. The system of any one of clauses 1-12, further comprising a latch circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path.

[0183]

[0229] Article 15.

[0230] 13. The system of any one of clauses 1-12, further comprising a latch circuit having a signal input, a clock input, and an output, wherein the clock input is coupled to the output of the signal path.

[0184]

[0231] Clause 16. The Controller shall:

[0232] a cyclic shift register having an input and an output, wherein the output of the cyclic shift register is coupled to the second input of the multiplexer;

[0233] a control circuit having an input, a first output and a second output, wherein the input of the control circuit is coupled to the indicator input, the first output of the control circuit is coupled to the select input of the multiplexer, and the second output of the control circuit is coupled to the input of the circular shift register; The system according to any one of clauses 1 to 10 and 12 to 15, comprising:

[0185]

[0234] Article 17.

[0235] the cyclic shift register is configured to store bits and output the bits one by one at the output of the cyclic shift register;

[0236] The control circuit includes:

[0237] receiving the mode indicator signal via the input of the control circuit;

[0238] instructing the multiplexer to select the first input if the mode indicator signal has the first logic value;

[0239] instructing the multiplexer via the first output to select the second input when the mode indicator signal has the second logic value and instructing the cyclic shift register via the second output to shift the bits in the cyclic shift register; 17. The system of claim 16, configured to:

[0186]

[0240] Clause 18. A system comprising:

[0241] a latch circuit having a signal input, a clock input, a set input, a reset input, and an output;

[0242] a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latch circuit;

[0243] a controller coupled to the set input and the reset input of the latch circuit, the controller having an indicator input, the controller comprising:

[0244] receiving a mode indicator signal at said indicator input;

[0245] deasserting the set input and the reset input when the mode indicator signal has a first logic value;

[0246] using the set input and the reset input to control whether the input of the signal path remains high or low when the mode indicator signal has a second logic value; configured to: A system comprising:

[0187]

[0247] Clause 19. The system of clause 18, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

[0188]

[0248] Clause 20. The system of clause 18 or 19, wherein the signal input of the latch circuit is configured to receive a data signal, a command signal, or an address signal.

[0189]

[0249] Clause 21. A system according to any one of clauses 18 to 20, wherein the signal path comprises a delay circuit.

[0190]

[0250] Clause 22. The system of clause 21, wherein the delay circuit comprises serially coupled delay buffers.

[0191]

[0251] Clause 23. A system as described in any one of clauses 18 to 22, wherein when the mode indicator has the second logical value, the controller is configured to alternately assert the set input and the reset input for a number of consecutive idle periods.

[0192]

[0252] Clause 24. The consecutive idle periods include an odd idle period and an even idle period, and the controller:

[0253] asserting the set input during each of the odd idle periods;

[0254] asserting the reset input during each of the even idle periods; 24. The system of claim 23, configured to:

[0193]

[0255] Clause 25. The consecutive idle periods include an odd idle period and an even idle period, and the controller:

[0256] asserting the reset input during each of the odd idle periods;

[0257] asserting the set input during each of the even idle periods; 24. The system of claim 23, configured to:

[0194]

[0258] Clause 26. When the mode indicator signal has the second logic value, the controller:

[0259] asserting the set input for k out of N consecutive idle periods;

[0260] asserting the reset input for Nk of the N consecutive idle periods;

[0023]

[0261] 23. The system of any one of clauses 18 to 22, wherein k is an integer greater than or equal to 1, and N is an integer greater than k.

[0195]

[0262] Clause 27. The controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of N consecutive idle periods in an idle mode, and for each one of the N consecutive idle periods, the controller:

[0263] asserting the set input during the idle period if the corresponding bit in the sequence of bits has a first bit value;

[0264] asserting the reset input during the idle period when the corresponding bit in the sequence of bits has a second bit value; The system of any one of clauses 18 to 22, configured to:

[0196]

[0265] Article 28.

[0266] Pads and

[0267] a receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the signal input of the latch circuit; The system of any one of clauses 18 to 27, further comprising:

[0197]

[0268] Article 29.

[0269] Pads and

[0270] a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path and the output of the driver is coupled to the pad; The system of any one of clauses 18 to 28, further comprising:

[0198]

[0271] Clause 30. A method for aging control comprising the steps of:

[0272] in an active mode, inputting a signal to an input of the signal path;

[0273] controlling aging of the signal path in an idle mode; A method for providing the above.

[0199]

[0274] Clause 31. The method of clause 30, wherein the signal comprises a data signal, a clock signal, a control signal, or an address signal.

[0200]

[0275] Clause 32. The method of clause 30 or 31, wherein the signal path comprises a delay circuit.

[0201]

[0276] Clause 33. The method of clause 32, wherein the delay circuit comprises serially coupled delay buffers.

[0202]

[0277] Clause 34. A method according to any one of clauses 30 to 33, wherein in the idle mode, controlling the time-varying nature of the signal comprises keeping the input of the signal alternately high and low for a number of successive idle periods.

[0203]

[0278] Clause 35. The successive idle periods include an odd idle period and an even idle period, and keeping the input of the signal path alternately high and low comprises:

[0279] holding the input of the signal path low during each of the odd idle periods;

[0280] holding the input of the signal path high during each of the even idle periods; 35. The method of claim 34, comprising:

[0204]

[0281] Clause 36. The successive idle periods include an odd idle period and an even idle period, and keeping the input of the signal path alternately high and low comprises:

[0282] holding the input of the signal path high during each of the odd idle periods;

[0283] holding the input of the signal path low during each of the even idle periods; 35. The method of claim 34, comprising:

[0205]

[0284] Clause 37. In the idle mode, controlling the aging of the signal path includes:

[0285] maintaining the input of the signal path high for k out of N consecutive idle periods;

[0286] holding the input of the signal path low for Nk of the N consecutive idle periods; Equipped with

[0287] 34. The method of any one of clauses 30 to 33, wherein k is an integer equal to or greater than 1, and N is an integer greater than k.

[0206]

[0288] Clause 38. The method further comprising storing a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of N consecutive idle periods in the idle mode, and wherein controlling aging of the signal path in the idle mode includes, for each one of the N consecutive idle periods:

[0289] keeping the input of the signal path high during the idle period if the corresponding bit in the sequence of bits has a first bit value;

[0290] holding the input of the signal path low during the idle period if the corresponding bit in the sequence of bits has a second bit value; 34. The method according to any one of clauses 30 to 33, comprising:

[0207]

[0291] Clause 39. A method according to any one of clauses 30 to 33, wherein controlling the aging of the signal path comprises inputting a clock signal to the input of the signal path.

[0208]

[0292] It should be understood that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, a delay circuit may be referred to as a delay line, a delay chain, a delay element, or another term. In another example, a pad may be referred to as a pin, or another term. It should also be understood that an indicator signal may be referred to as a mode indicator signal.

[0209]

[0293] The controller 230, the controller 1030, and the controller 1690 may each be implemented using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor may perform the functions described herein by executing software comprising codes for performing the functions. The software may be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0210]

[0294] Within this disclosure, the term "exemplary" is used to mean "serving an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all of the aspects of the disclosure include the described feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to a DC ground or an AC ground, and thus the term "ground" covers both possibilities.

[0211]

[0295] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal; A signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; A controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to: Receive a mode indicator signal at the indicator input; When the mode indicator signal has a first logical value, instruct the multiplexer to select the first input of the multiplexer; When the mode indicator signal has a second logical value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, and alternately set the control signal high and low over a plurality of consecutive idle periods; And is configured to perform the above operations. A system comprising the above components.

2. A system comprising: A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal; A signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; A controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to: Receive a mode indicator signal at the indicator input; When the mode indicator signal has a first logical value, instruct the multiplexer to select the first input of the multiplexer, and when the mode indicator signal has a second logical value, instruct the multiplexer to select the second input of the multiplexer and output a control signal to the second input of the multiplexer, and set the control signal high during k of the N consecutive idle periods, and set the control signal low during N - k of the N consecutive idle periods, and is configured to perform, where k is an integer greater than or equal to 1 and N is an integer greater than k, A system comprising.

3. The controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to one of each of the N consecutive idle periods in the idle mode, and for each one of the N consecutive idle periods, the controller when the corresponding bit in the sequence of bits has a first bit value, set the control signal high during the idle period, and when the corresponding bit in the sequence of bits has a second bit value, set the control signal low during the idle period, and is configured to perform, the system according to claim 2.

4. A pad, and a receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the first input of the multiplexer, The system according to claim 1, further comprising.

5. The controller is A cyclic shift register having an input and an output, wherein the output of the cyclic shift register is coupled to the second input of the multiplexer, A control circuit having an input, a first output, and a second output, wherein the input of the control circuit is coupled to the indicator input, the first output of the control circuit is coupled to the selection input of the multiplexer, and the second output of the control circuit is coupled to the input of the cyclic shift register, The system according to claim 2, comprising: **Claim 6** The cyclic shift register is configured to store bits, each of the bits corresponding to one of the N consecutive idle periods, and to output the bits one by one at the output of the cyclic shift register, The control circuit is Receiving the mode indicator signal via the input of the control circuit; When the mode indicator signal has the first logical value, instructing the multiplexer to select the first input; When the mode indicator signal has the second logical value, instructing the multiplexer to select the second input via the first output, and instructing the cyclic shift register to shift the bits in the cyclic shift register via the second output; The system according to claim 5, configured to perform: **Claim 7** A system, A latch circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latch circuit is configured to latch the logical value at the signal input at the edge of the clock signal input to the clock input when the set input and the reset input are deasserted, and to output the latched logical value at the output of the latch circuit. A signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latch circuit, A controller coupled to the set input and the reset input of the latch circuit, wherein the controller has an indicator input, and the controller Receives a mode indicator signal at the indicator input, When the mode indicator signal has a first logical value, deasserts the set input and the reset input, When the mode indicator signal has a second logical value, alternately asserts the set input and the reset input over a plurality of consecutive idle periods, And is configured to perform, A system comprising.

8. The system according to claim 1 or 7, wherein the first logical value indicates that the system is in an active mode, and the second logical value indicates that the system is in an idle mode.

9. The system according to claim 7, wherein the signal input of the latch circuit is configured to receive a data signal, a command signal, or an address signal.

10. The system according to claim 1 or 7, wherein the signal path comprises a delay circuit, and the delay circuit comprises delay buffers coupled in series.

11. A system, A latch circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latch circuit latches the logical value at the signal input at the edge of the clock signal input to the clock input when the set input and the reset input are deasserted, and outputs the latched logical value at the output of the latch circuit. A signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latch circuit, A controller coupled to the set input and the reset input of the latch circuit, wherein the controller has an indicator input, and the controller Receives a mode indicator signal at the indicator input, When the mode indicator signal has a first logic value, deasserts the set input and the reset input, When the mode indicator signal has a second logic value, Assert the set input during k of the N consecutive idle periods, Assert the reset input during N - k of the N consecutive idle periods, Is configured to perform, Where k is an integer greater than or equal to 1, and N is an integer greater than k, A system comprising.

12. The controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to one of each of the N consecutive idle periods in the idle mode, and for each one of the N consecutive idle periods, the controller When the corresponding bit in the sequence of bits has a first bit value, assert the set input during the idle period, When the corresponding bit in the sequence of bits has a second bit value, assert the reset input during the idle period, The system according to claim 11, which is configured to perform.

13. A pad, A receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the signal input of the latch circuit. The system according to claim 11, further comprising.

14. A pad, A driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path and the output of the driver is coupled to the pad. The system according to claim 1 or 11, further comprising.

15. A method for controlling the change over time of the system according to claim 1 or claim 11, comprising: Inputting a signal to the input of the signal path in the active mode; Controlling the change over time of the signal path in the idle mode; Comprising, in the idle mode, controlling the change over time of the signal by alternately setting the control signal high and low over a plurality of consecutive idle periods, or Setting the control signal high for k of the N consecutive idle periods; Setting the control signal low for N - k of the N consecutive idle periods; Comprising, where k is an integer greater than or equal to 1 and N is an integer greater than k. Method.

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