Method for forming a bottom dielectric insulating layer - Patents.com

Abstract

Embodiments of the present disclosure relate to methods for removing dummy material from beneath a superlattice structure, in some embodiments, the dummy material is removed and then replaced with a bottom dielectric insulating layer beneath the superlattice structure.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure generally relate to a method for forming a bottom dielectric insulating layer, and more particularly, to a method for removing dummy material from beneath a superlattice structure and forming a bottom dielectric insulating layer beneath the superlattice structure. [Background technology]

[0002]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so faster transistors generally require larger gate widths. As such, there is a tradeoff between transistor size and speed, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs also have drawbacks.

[0003]

[0003] As transistor device feature sizes continue to shrink to achieve increased circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, horizontal gate-all-around (hGAA) structures, etc. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure provides good electrostatic control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004]

[0004] The presence of a bottom dielectric insulating (BDI) layer is becoming a key layer for improving the performance of nanosheet devices. The BDI layer provides many advantages, including suppressing subchannel leakage and preventing process variations (e.g., punch-through stopper (PTS)). Therefore, there is a need for an improved method for forming the bottom dielectric insulating layer for gate-all-around devices. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a process method for removing dummy material. The method includes forming a trench through a superlattice structure having a plurality of stacked pairs of alternating channel layers and corresponding layers of semiconductor material on the dummy material. The trench exposes a surface of the plurality of channel layers, the plurality of layers of semiconductor material, and the dummy material. A liner is formed on the exposed surface. The liner is removed from the dummy material. The dummy material is removed without substantially affecting the channel layers and the layers of semiconductor material covered by the liner.

[0006]

[0006] An additional embodiment of the present disclosure is directed to a processing method that includes forming source and drain trenches through a plurality of stacked paired superlattice structures with alternating channel layers and corresponding semiconductor material layers on a dummy material. The source and drain trenches expose a surface of the plurality of channel layers, the plurality of semiconductor material layers, and the dummy material. The exposed surfaces of the plurality of channel layers are recessed to remove a depth of channel material and form a plurality of recessed channel layers. A liner is formed on the exposed surfaces of the plurality of recessed channel layers, the plurality of semiconductor material layers, and the surface of the dummy material. The liner is conformal and has a thickness. The liner is trimmed to expose the dummy material without exposing the plurality of channel layers or the plurality of semiconductor material layers. The dummy material is removed. The liner is trimmed to expose the semiconductor material layers. A bottom dielectric insulating layer is deposited beneath the superlattice structure. To fill the superlattice structure, a silicon material is deposited over the bottom dielectric insulating layer.

[0007]

[0007] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure briefly summarized above may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates an exemplary substrate prior to processing in accordance with one or more embodiments of the present disclosure. [Diagram 2]

[0009] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Diagram 3]2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 4] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Diagram 5] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 6] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 7] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 8] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 9] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 10] 2 illustrates a close-up view of the bottom of a trench region of the exemplary substrate shown in FIG. 1 during processing in accordance with one or more embodiments of the present disclosure. [Figure 11]

[0010] 1 illustrates a flow diagram of an exemplary method for forming a bottom dielectric insulating layer in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0011] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0010]

[0012] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0013] The term "substrate" as used herein and in the appended claims refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of the substrate unless the context clearly indicates otherwise. Additionally, a reference to depositing on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0012]

[0014] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps can also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface. What a given substrate surface includes depends on what film is being deposited and the particular chemistry used.

[0013]

[0015] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably and refer to any gas species capable of reacting with the substrate surface.

[0014]

[0016] A transistor is a circuit component or element that is often formed on a semiconductor device. In some circuit designs, transistors are formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located over the channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0015]

[0017] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which controls the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and source is denoted as VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0016]

[0018] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage on the insulated gate determines the conductivity of the device. This ability to change conductivity depending on the amount of voltage applied is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to an individual highly doped region separated by a body region. These regions can be p-type or n-type, but both are the same type, opposite to the body region. The source and drain are highly doped (unlike the body) and are denoted by a "+" sign after the type of doping.

[0017]

[0019] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel, and similarly, the drain is so named because it is where the charge carriers leave the channel.

[0018]

[0020] As used herein, the term "Fin Field Effect Transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate in which the gates are located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the collective name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0019]

[0021] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire or nanoslab or nanosheet, a rod-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0020]

[0022] As used herein, the term "nanowire" refers to a wire that is 1 nanometer (10 -9 Nanowires refer to nanostructures having diameters on the order of 1000 nm (meters). Nanowires may also be defined as having a length to width ratio of more than 1000. Alternatively, nanowires may be defined as structures whose thickness or diameter is constrained to tens of nanometers or less, and whose length is unconstrained. Nanowires are used in transistors and some laser applications, and in one or more embodiments are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to two-dimensional nanostructures having a thickness ranging from about 0.1 nm to about 1000 nm.

[0021]

[0023] One or more embodiments of the present disclosure are directed to a method of forming a bottom dielectric insulating layer. In some embodiments, the bottom dielectric insulating layer is formed by removing dummy material from an hGAA transistor. In some embodiments, the hGAA transistor is "built" on the dummy material, which is removed and replaced with the bottom dielectric insulating layer.

[0022]

[0024] Although the disclosed dummy material is not limited to a particular material composition, the inventors have found that the disclosed embodiments advantageously allow for the use of both silicon and silicon germanium as the dummy material, and thus, integration of the disclosed embodiments into existing processing schemes is advantageously straightforward.

[0023]

[0025] Some embodiments of the present disclosure are described with reference to figures illustrating devices (e.g., transistors) and processes for forming the transistors in accordance with one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible applications of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0024]

[0026] 1-10 show stages in the fabrication of a bottom dielectric insulating layer according to some embodiments of the present disclosure. Figure 11 shows a flow diagram of a method 1100 for processing a substrate according to some embodiments of the present disclosure. Method 1100 is described below with reference to Figures 1-10.

[0025]

[0027] 1-10 are cross-sectional views of an electronic device (e.g., GAA) according to one or more embodiments. Method 1100 may be part of a multi-step manufacturing process of a semiconductor device. Thus, method 1100 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0026]

[0028] 2-10 show variations of steps 1110-1190 of FIG. 11. Referring to FIG. 11, method 1100 begins in optional step 1105 by providing a substrate 102. In some embodiments, substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely made of a semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which the substrate may be formed are described, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed is within the spirit and scope of the present disclosure.

[0027]

[0029] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration that is greater than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0028]

[0030] A dummy material 103 is formed on a surface of the substrate 102. In some embodiments, the dummy material 103 comprises or consists essentially of silicon (Si). In some embodiments, the dummy material 103 comprises or consists essentially of silicon germanium (SiGe). In some embodiments, the dummy material 103 is a semiconductor material layer 110 or a channel layer 108 of a superlattice structure 106, described below.

[0029]

[0031] In some embodiments, the dummy material 103 is doped with one or more of boron, phosphorous, arsenic, or germanium. In those embodiments in which the dummy material 103 is doped, the dummy material 103 comprises a dopant concentration in the range of about 2 atomic % to about 10 atomic %. In some embodiments, the dummy material is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition.

[0030]

[0032] In some embodiments, a superlattice structure 106 is formed on top of the dummy material 103. In some embodiments, the superlattice structure 106 is formed directly on the surface of the substrate 102, with a bottom layer of the superlattice structure 106 acting as the dummy material 103. In some embodiments, the superlattice structure 106 is formed directly on the surface of the substrate 102, with a second layer of the superlattice structure 106 acting as the dummy material 103. For the avoidance of doubt, the "second layer" is the layer that is vertically adjacent to the "bottom layer," and the "bottom layer" is the layer that is in contact with the substrate 102.

[0031]

[0033] The superlattice structure 106 includes a plurality of stacked pairs of alternating semiconductor material layers 110 and corresponding channel layers 108. In some embodiments, the stacked layers include silicon (Si) and silicon germanium (SiGe). In some embodiments, the semiconductor material layers 110 include silicon germanium (SiGe) and the channel layers 108 include silicon (Si). In other embodiments, the channel layers 108 include silicon germanium (SiGe) and the semiconductor material layers include silicon (Si).

[0032]

[0034] In some embodiments, the layers of semiconductor material 110 and the corresponding layers of channel 108 may include any number of pairs of lattice-matched materials suitable for forming a superlattice structure 106. In some embodiments, the layers of semiconductor material 110 and the corresponding layers of channel 108 include from about 2 pairs to about 50 pairs, or from about 3 pairs to about 5 pairs of lattice-matched materials. In some embodiments, the superlattice structure includes 3 or 4 pairs of lattice-matched materials.

[0033]

[0035] In one or more embodiments, the thickness t1 of each of the plurality of semiconductor material layers 110 and the plurality of channel layers 108 is the same and is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 4 nm to about 10 nm. In some embodiments, each of the plurality of semiconductor material layers 110 is in the range of about 6 nm to about 10 nm. In some embodiments, each of the plurality of channel layers 108 is in the range of about 4 nm to about 10 nm. Thus, in some embodiments, a single pair of a channel layer and a semiconductor material layer has a thickness in the range of about 10 nm to about 20 nm. Furthermore, in embodiments where the superlattice structure includes three or four pairs of lattice-matched materials, the total thickness of the superlattice structure is in the range of about 30 nm to about 80 nm.

[0034]

[0036] In some embodiments, a replacement gate structure (e.g., dummy gate structure 105) is formed on the superlattice structure 106. The dummy gate structure 105 defines a channel region of a transistor device. The dummy gate structure 105 may be formed using any suitable conventional deposition and patterning process known in the art. In one or more embodiments, the dummy gate structure 105 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

[0035]

[0037] In some embodiments, sidewall spacers are formed along the outer sidewalls of the dummy gate structure 105. The sidewall spacers may include any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low pressure chemical vapor deposition.

[0036]

[0038] At step 1110, a channel region or trench is formed separating the superlattice structure 106 from an adjacent superlattice structure 106. In one or more embodiments, a source trench 113 and a drain trench 114 are formed adjacent (i.e., on either side of) the superlattice structure 106. In some embodiments, the source trench 113 and the drain trench are spaced apart by about 20 nm to about 60 nm. The trenches expose surfaces of the plurality of channel layers 108, the plurality of layers of semiconductor material 110, and the dummy material 103.

[0037]

[0039] The source trench 113 and the drain trench 114 may be formed by any suitable process. In some embodiments, the trenches are formed by a source / drain vertical etch. In some embodiments, the etch process is highly directional, allowing for vertical etching of narrow (high aspect ratio) trenches.

[0038]

[0040] After forming the trenches in step 1110, in some embodiments, the method 1100 continues to optional step 1120. In step 1120, the plurality of channel layers 108 are recessed to remove a depth D of material of the plurality of channel layers 108 and form a plurality of recessed channel layers 109. In some embodiments, the recessed depth D from each side of the superlattice structure 106 is in the range of about 5 nm to about 10 nm.

[0039]

[0041] Recessing the channel layer 108 may be performed by any suitable process. In some embodiments, step 1120 is performed by a selective etching process that selectively removes material of the plurality of channel layers 108 over material of the plurality of semiconductor material layers 110. In some embodiments, recessing the plurality of channel layers 108 is performed by a selective etching process that preferentially removes silicon over silicon germanium.

[0040]

[0042] After optionally recessing the plurality of channel layers 108, the method 1100 continues at step 1130 by forming a liner 120 on the exposed surfaces of the plurality of (recessed) channel layers 108, the plurality of semiconductor material layers 110, and the dummy material 103 at step 1120. The liner 120 comprises silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonate (SiCON), or combinations thereof. The liner 120 has a thickness L sufficient to fill any recessed portions of the plurality of recessed channel layers 108. In some embodiments, the thickness of the liner is in the range of about 3 nm to 5 nm. In some embodiments, the liner 120 is conformal and has a thickness that varies by no more than ±10% across the surface of the trench. In some embodiments, the liner 120 is deposited by atomic layer deposition.

[0041]

[0043] The method 1100 continues at step 1140 by trimming the liner 120. Trimming the liner 120 at step 1140 removes the liner 120 from the surface of the dummy material 103. Removal of the liner 120 from the surface of the dummy material 103 does not expose the plurality of channel layers 108 or the plurality of layers of semiconductor material 110. In some embodiments, the liner remains continuous across the surfaces of the plurality of channel layers 108 and the plurality of layers of semiconductor material 110. In some embodiments, the plurality of channel layers 108 and the plurality of layers of semiconductor material 110 remain at least 1 nm or at least 2 nm thick.

[0042]

[0044] In some embodiments, removal of the liner 120 is performed by a directional etching process. In some embodiments, the liner 120 on the surfaces of the plurality of channel layers 108 and the plurality of semiconductor material layers 110 is not affected by step 1140. In some embodiments, the liner on the surfaces of the plurality of channel layers 108 and the plurality of semiconductor material layers 110 is thinned without exposing the surfaces of the plurality of channel layers 108 or the plurality of semiconductor material layers 110.

[0043]

[0045] The method 1100 continues at step 1150 by removing the dummy material 103. Step 1150 can be performed by a selective etching process that is selective to the dummy material 103 on the liner 120. In some embodiments, the selective etching process is also selective to the dummy material 103 on the bottom material of the superlattice structure 106.

[0044]

[0046] In some embodiments, the selective etching process includes a wet etching process using one or more of trimethylammonium hydroxide (TMAH) or ammonium hydroxide, hi some embodiments, the wet etching process includes oxidation and removal cycles each including ozone and water.

[0045]

[0047] In some embodiments, the method 1100 continues to optional step 1160. In step 1160, the liner 120 is removed from the surface of the plurality of layers of semiconductor material 110. In those embodiments in which the plurality of channel layers 108 are recessed, as shown in Figure 7, discrete portions of the liner 120 may remain in the recessed spaces. Step 1160 may include a wet etching process including one or more of phosphoric acid or acetic acid.

[0046]

[0048] Next, in step 1170, the bottom dielectric insulating layer 104 is deposited through the trench and beneath the superlattice structure 106. In some embodiments, step 1170 is performed by a flowable deposition process, allowing the bottom dielectric insulating layer 104 to fill the spaces vacated by the dummy material 103.

[0047]

[0049] The bottom dielectric insulation (BDI) layer 104 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the bottom dielectric insulation (BDI) layer 104 comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), combinations thereof, or a high-k material. In some embodiments, the high-k material is selected from one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), and the like. In one or more particular embodiments, the bottom dielectric insulation (BDI) layer 104 comprises silicon oxide.

[0048]

[0050] 8, in some embodiments, the bottom dielectric insulating layer 104 extends outside the space previously occupied by the dummy material 103. As shown, in some embodiments, the material of the bottom dielectric insulating layer 104 is also deposited on the sidewalls of the trench.

[0049]

[0051] In these embodiments, the method 1100 removes excess bottom dielectric insulating layer material at step 1180. The excess material may be removed in any suitable manner.

[0050]

[0052] Finally, the method 1100 ends with optional step 1190. At step 1190, a silicon material 130 is deposited on the bottom dielectric insulating layer 104 to fill the superlattice structure 106. In some embodiments, the silicon material 130 is epitaxially deposited. In some embodiments, the silicon material 130 may be doped with phosphorus or boron.

[0051]

[0053] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0052]

[0054] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure includes modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A processing method for removing dummy material, comprising: forming a trench through a superlattice structure including a plurality of channel layers and a plurality of layers of semiconductor material alternating over a dummy material, the trench exposing the plurality of channel layers, the plurality of layers of semiconductor material, and the dummy material; forming a liner over the plurality of channel layers, the plurality of semiconductor material layers, and the dummy material; removing the liner from the dummy material; removing the dummy material without substantially affecting the channel layer and the semiconductor material layer covered by the liner; Including, The dummy material includes silicon (Si) or silicon germanium (SiGe) and is doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, and the concentration of the dopant is in the range of 2 atomic % to 10 atomic %; method.

2. The method of claim 1 , wherein the dummy material consists essentially of silicon (Si).

3. The method of claim 1 , wherein the dummy material consists essentially of silicon germanium (SiGe).

4. 2. The method of claim 1, wherein the semiconductor material layer and the channel layer are different materials and consist essentially of silicon (Si) and silicon germanium (SiGe), respectively.

5. The method of claim 1 , wherein the liner comprises silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), or a combination thereof.

6. The method of claim 1 , wherein removing the liner comprises a directional etching process.

7. The method of claim 1 , wherein removing the dummy material comprises a selective etching process that is selective to the dummy material over the liner.

8. The method of claim 1 , wherein removing the dummy material comprises a selective etching process that is selective to the dummy material over the channel layer or the semiconductor material layer adjacent to the dummy material.

9. The method of claim 1 , further comprising depositing a bottom dielectric insulating layer beneath the superlattice structure after removing the dummy material.

10. The method of claim 9 , wherein the bottom dielectric insulating layer is deposited by a flowable deposition process.

11. 10. The method of claim 9, wherein the bottom dielectric insulating layer comprises silicon oxide.

12. forming source and drain trenches through a superlattice structure including a plurality of channel layers and a plurality of layers of semiconductor material alternating over a dummy material, the source and drain trenches exposing the plurality of channel layers, the plurality of layers of semiconductor material, and the dummy material; removing a depth of channel material and recessing the plurality of channel layers to form a plurality of recessed channel layers; forming a liner over the plurality of recessed channel layers, the plurality of semiconductor material layers, and the dummy material, the liner being conformal and having a thickness; removing the liner from the dummy material without exposing the recessed channel layers or the layers of semiconductor material; removing the dummy material; etching the liner to expose the plurality of layers of semiconductor material; depositing a bottom dielectric insulating layer beneath the superlattice structure; depositing a silicon material over the bottom dielectric insulating layer to fill the superlattice structure; Including, The dummy material includes silicon (Si) or silicon germanium (SiGe) and is doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, and the concentration of the dopant is in the range of 2 atomic % to 10 atomic %; method.

13. The method of claim 12, wherein the total thickness of the superlattice structure is in the range of about 30 nm to about 80 nm.

14. The method of claim 12, wherein the superlattice structure comprises 3 to 5 pairs of a channel layer and a semiconductor material layer.

15. The method of claim 12, wherein the channel layer and the semiconductor material layer each have a thickness in the range of about 4 nm to about 10 nm.

16. The method of claim 12, wherein a lateral distance between the source trench and the drain trench is in a range from about 20 nm to about 60 nm.

17. The method of claim 12 , wherein the depth of the channel material removed from the plurality of channel layers is in a range from about 5 nm to about 10 nm.

18. The method of claim 12, wherein the thickness of the liner is in a range from about 3 nm to about 5 nm.

19. The method of claim 12 , wherein the dummy material consists essentially of silicon (Si).

20. The method of claim 12 , wherein the dummy material consists essentially of silicon germanium (SiGe).

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