Low capacity memory in sense amplifiers.

Abstract

A memory is provided that includes a number of memory banks, each associated with a read multiplexer. The first read multiplexer couples a first number of bit lines to a first sense node pair, and the second read multiplexer couples a second number of bit lines to a second sense node pair. The first sense amplifier is coupled to the first sense node pair. The second sense node pair can be coupled to the same sense amplifier or a different sense amplifier.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of U.S. patent application Ser. No. 17 / 446,195, filed Aug. 27, 2021, the disclosure of which is incorporated by reference herein in its entirety for all applicable purposes as if fully set forth below.

[0002] This application relates to memories, and more particularly to low capacity multi-bank memories in sense amplifiers. [Background technology]

[0003] In conventional static random-access memory (SRAM), a bitcell connects to a pair of bitlines during a read operation. Prior to a read operation, the bitlines are precharged to the power supply voltage used for the bitcell. Depending on the binary content of the bitcell, the bitcell slightly discharges either the true or complementary bitline in the bitline pair from its precharged state. For example, assume that a bitcell stores a binary 1. During a read operation, the wordline is asserted such that the bitcell is coupled to its bitline pair. Due to the value of the binary 1, the complementary bitline is discharged from its precharged state. However, the bitcell maintains the true bitline in its precharged state.

[0004] Thus, a read operation develops a voltage difference across the bit line pair. This bit line voltage difference is not full rail, but is equal to a fraction of the power supply voltage. In order to respond to this relatively small voltage difference and make a bit decision as to what was stored in the bit cell, the sense amplifier can use a relatively large amount of gain.

[0005] A charge transfer sense amplifier (CTSA) can provide a relatively large amount of gain to enable bit decisions with a relatively small voltage difference. A CTSA can provide gain in part by transferring charge between a bit line (or a complementary bit line) and a sense node (or a complementary sense node). However, several bit lines may share a sense node, and the greater the number of bit lines per sense node, the higher the parasitic capacitance may be, which may be an obstacle to fast and reliable bit decisions.

[0006] Therefore, there is a need in the art for a memory with reduced parasitic capacitance. Summary of the Invention

[0007] In one implementation, the circuit includes a first read multiplexer coupling a first plurality of bit lines to a first sensing node and a first complementary sensing node, a second read multiplexer coupling a second plurality of bit lines to a second sensing node and a second complementary sensing node, and a first sense amplifier coupled to the first sensing node and the first complementary sensing node, where the first read multiplexer is associated with a first bank of memory bit cells and the second read multiplexer is associated with a second bank of memory bit cells.

[0008] In another implementation, a method includes multiplexing a first plurality of bit line pairs with a first sense node pair in a first read operation, the multiplexing including coupling a first bit line pair of the first plurality of bit line pairs to the first sense node pair; charge sharing between the first bit line pair and the first sense node pair; inputting a value from the first sense node pair to a logic circuit; causing the logic circuit to make a bit decision based on the value from the first sense node pair; and multiplexing a second plurality of bit line pairs with a second sense node pair in a subsequent read operation, the multiplexing including coupling a second bit line pair of the second plurality of bit line pairs to the second sense node pair, the first plurality of bit line pairs being associated with a first bank of memory bit cells and the second plurality of bit line pairs being associated with a second bank of memory bit cells.

[0009] In another implementation, a memory device includes a plurality of memory banks, each including a plurality of bit line pairs, a plurality of sense node pairs, each associated with a respective one of the memory banks, means for multiplexing the bit line pairs with the sense node pairs, and means for making bit decisions based on voltages associated with the sense node pairs during a plurality of read operations targeted to the plurality of memory banks.

[0010] In yet another implementation, a memory includes a first memory bank including a first plurality of bit cells arranged in a first plurality of columns, a second memory bank including a second plurality of bit cells arranged in a second plurality of columns, a first sense node pair coupled to the first plurality of columns by a first read multiplexer, a second sense node pair coupled to the second plurality of columns by a second read multiplexer, and a first sense amplifier coupled to the first sense node pair.

[0011] These and additional advantages may be more fully understood through the following detailed description of the invention. [Brief description of the drawings]

[0012] [Figure 1] 1 illustrates a multi-bank memory having multiple sense node pairs according to one aspect of the present disclosure. [Diagram 2] 2 illustrates an exemplary sense amplifier in the memory of FIG. [Diagram 3] 2 illustrates a timing diagram for the exemplary sense amplifier of FIG. 1. [Figure 4] 2 illustrates an exemplary sense amplifier in the memory of FIG. [Diagram 5] 1 illustrates a multi-bank memory having multiple sense node pairs according to one aspect of the present disclosure. [Figure 6] 6 illustrates an exemplary sense amplifier in the memory of FIG. 5; [Figure 7] 1 illustrates an example interface between a bit line pair and a sense node pair according to one aspect of the disclosure. [Figure 8] 6 shows a flowchart of an example method that may be performed by the multi-bank memory of FIGS. [Figure 9] 1 illustrates an exemplary system on chip (SOC) that may incorporate memory, according to one aspect of the present disclosure.

[0013] Implementations of the present disclosure and their advantages are best understood by referring to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] A memory such as an SRAM is provided in which there are multiple memory banks, each associated with a read multiplexer. For example, a first read multiplexer may couple a first plurality of bit lines to a first sense node and a first complementary sense node. A second read multiplexer may couple a second plurality of bit lines to a second sense node and a second complementary sense node. The multiple bit lines may include multiple bit line pairs (bit line and bit line complement). Each bit line pair may correspond to a column of bit cells. Thus, each memory bank may include multiple bit cell columns traversed by multiple word lines.

[0015] In contrast to other examples where multiple read multiplexers may couple to the same sense node pair (sense node and sense node complement), the implementations discussed herein may include an architecture where a first read multiplexer couples to a first sense node and a first complementary sense node, and a second read multiplexer couples to a second sense node and a second complementary sense node. As mentioned above, as the number of bit lines sharing a sense node and a complementary sense node increases, the parasitic capacitance also increases. However, the implementations discussed herein increase the number of sense node pairs by providing at least one pair for each of the memory banks. Thus, the ratio of bit lines to sense nodes is reduced, thereby reducing the parasitic capacitance seen by each sense amplifier. Lower parasitic capacitance may increase the voltage achieved by charge sharing, thereby providing faster and more reliable bit decisions.

[0016] In one example, there is a first sense amplifier coupled to a first sense node and a first complementary sense node, and a second sense amplifier coupled to a second sense node and a second complementary sense node. In other words, each memory bank is associated with its own sense amplifier. The sense amplifiers may be implemented in any suitable manner, including each of the sense amplifiers being constructed as a cross-coupled pair of NAND gates, with each of the cross-coupled pairs being coupled to a push-pull circuit.

[0017] In another implementation, multiple memory banks are coupled to a single sense amplifier. In other words, the sense amplifier is coupled to both pairs of sense nodes and thus to each of the multiplexers. The sense amplifier may include a cross-coupled pair of AND-OR-invert (AOI) gates, where a first AOI gate is coupled to a first complementary sense node, a second complementary sense node, and an output from the second AOI gate, and a second AOI gate is coupled to the first sense node, the second sense node, and an output from the first AOI gate. The cross-coupled pair of AOI gates may share a push-pull circuit.

[0018] An advantage of an implementation using cross-coupled AOI gates is that the number of transistors can be reduced compared to an implementation using two cross-coupled pairs of NAND gates. Reducing the number of transistors can reduce the amount of silicon area used on a chip, possibly reducing manufacturing costs as well as potentially saving dynamic power and leakage power.

[0019] The sense amplifiers may be implemented as charge sharing sense amplifiers (CTSA). In one example, each bit line of a group of multiplexed columns is coupled to a sense node through its own charge transfer transistor. The source of each charge transfer transistor is coupled to its bit line, and the drain of each charge transfer transistor is coupled to its sense node. Thus, the gate-source voltage of each charge transfer transistor is determined by its gate voltage and its bit line voltage. In the following discussion, it is assumed that each charge transfer transistor is a p-type metal-oxide semiconductor (PMOS) transistor, although it will be understood that charge transfer can also be achieved with n-type metal-oxide semiconductor (NMOS) transistors.

[0020] Prior to word line assertion for a read operation, the bit lines are precharged to the power supply voltage and the sense nodes are discharged. The word lines are then asserted for a word line assertion period during which a bit line voltage difference develops for each bit line pair depending on the bit stored in each bit cell at the intersection of the word line and the bit line pair of the multiplexed column group. In response to this bit, either the true or complementary bit line in each bit line pair is slightly discharged from the precharged state (power supply voltage, VDD). Charge transfer occurs during a charge transfer period that begins near the end of the word line assertion period. Prior to the charge transfer period, the gate voltage of each charge transfer transistor is maintained at the power supply voltage so that each charge transfer transistor is off. The charge transfer period is delayed relative to the assertion of the word line so that the bit line voltage difference can develop for each bit line pair. During the charge transfer period, the gate voltage of the charge transfer transistor falls from the power supply voltage towards ground at some slew rate. For example, a relatively small inverter or dummy bit line voltage may be used to control the gate voltage of the charge transfer transistor. Depending on the bit value, either the true or complementary bit line in each bit line pair drops slightly from its precharged state (the power supply voltage). This bit line is referred to as the partially charged bit line in the following discussion. However, the remaining bit line of each bit line pair remains charged to the power supply voltage. This bit line is referred to as the fully charged bit line in the following discussion.

[0021] During the charge transfer period, the gate voltage of each charge transfer transistor in the group of multiplexed columns is lowered so that the gate-source voltage (gate-bitline voltage) of the charge transfer transistor of the fully charged bitline meets its threshold voltage. However, the voltage drop of the partially charged bitline is such that this same gate voltage does not meet the threshold voltage of the charge transfer transistor of the partially charged bitline. Thus, only the charge transfer transistor of the fully charged bitline in the bitline pair initially conducts charge to its sense node. Since the capacitance of the sense node is relatively small compared to the capacitance of the bitline, the resulting charge transfer causes the sense node to be charged to approximately the power supply voltage. In contrast, the sense node for the partially discharged bitline remains in its discharged default state, so the voltage difference between the sense nodes for the accessed bitline pair is approximately full rail (the voltage difference is approximately equal to the power supply voltage). Thus, the charge transfer amplifies the relatively small bitline voltage difference to approximately the full rail voltage difference on the sense node. Sensing by the sense amplifier occurs during the sensing corresponding period.

[0022] 1 is a diagram of a memory system 100 according to one implementation. The memory system 100 is a multi-bank memory system, in this case using two memory banks, bank b0 195 and bank b1 196. Each of the memory banks 195, 196 includes a number of columns of bit cells, each column having a bit line and a complementary bit line, and each of the memory banks is traversed by a number of word lines. The bit lines and complementary bit lines 190, 191 are shown as having two pairs each, it being understood that a given memory bank may include any suitable number of bit line pairs corresponding to any suitable number of columns.

[0023] Turning to multiplexer 110, it corresponds to bank b0 195 and multiplexes bit line pair 190 to sense nodes q_b0 and qb_b0. Similarly, multiplexer 120 corresponds to bank b1 196 and multiplexes bit line pair 191 to sense nodes q_b1, qb_b1. In this example, multiplexers 110, 120 each receive three signals including pre_n (bit line precharge), rm[0:3] (read multiplexing signal), and wm[0:3] (write multiplexing signal). Note that here signals rm and wm are shown as selecting among four columns, and as discussed above, a range of implementations support any number of columns that may be multiplexed.

[0024] The sense node (q_b0, q_b1) and the complementary sense node (qb_b0, qb_b1) are inputs to the sense amplifier 130. Furthermore, in this example, the memory system 100 performs either a read or a write operation to one of the memory banks 195, 196 at a given time, but not simultaneously to both memory banks 195, 196. The sense amplifier 130 bases a bit decision on the difference in voltage between a given pair of sense nodes corresponding to one of the memory banks 195, 196 in response to a read operation to that respective bank.

[0025] The interface between the bit line pairs and the sense node pairs is described in more detail with respect to Figure 7. Additionally, an exemplary architecture for the sense amplifier 130 is described in more detail with respect to Figures 2 and 4.

[0026] Figure 7 is a diagram of an example interface of a single bit line and a bit line pair (bl and blb) with a sense node and a complementary sense node (q and qb). Figure 7 has been generalized for ease of explanation, and it will be understood that the concepts described in Figure 7 are applicable to both the sense amplifier architectures of Figures 1-4 and 5-6. It will be understood that Figure 7 shows only a single bit line pair, and that other bit line pairs may be coupled to the sense nodes q and qb and selected using the appropriate multiplexer signals rm[0:3].

[0027] The bit line pair, bit line bl and complementary bit line blb, forms a column. Bit cell 705 is located at the intersection of the column and word line wl. In this example, bit cell 705 is formed by a pair of cross-coupled inverters. The output node of a first one of the inverters is the true (Q) output of bit cell 705. This output node is coupled to bit line bl through an NMOS access transistor M4. Similarly, the output node of the remaining second one of the inverters is the complementary (QB) output of bit cell 705, which is coupled to complementary bit line blb through an NMOS access transistor M3. Word line wl is coupled to the gate of the access transistor such that the Q and QB nodes drive the respective bit line during word line assertion.

[0028] In an exemplary read operation, a clock cycle triggers the assertion of a voltage on the word line wl. Prior to this word line assertion, the bit lines bl and blb have been precharged to a power supply voltage by the bit line precharge circuit 750. The bit line bl is coupled to a corresponding sense node q through a PMOS charge transfer transistor M1. Similarly, the complementary bit line blb is coupled to a corresponding sense node qb through a PMOS charge transfer transistor M2. Prior to the word line assertion, the gate voltage rm of the charge transfer transistors M1, M2 is asserted to a power supply voltage to prevent charge transfer to the sense node. The controller 745 asserts a sense node pre-charge signal (pch) prior to the word line assertion. The asserted sense node pre-charge signal drives the gates of NMOS transistors (e.g., N1, N2 in FIG. 4). The sources of these NMOS transistors are coupled to ground and the drains are coupled to q and qb, respectively. Thus, assertion of the sense node precharge signal discharges both q and qb. The same applies to transistors N3, N4, for example, which discharge q and qb of other memory banks.

[0029] The voltage on word line wl can then be asserted, which switches on access transistors M3 and M4 such that the true and complement output nodes of bit cell 705 are connected to bit lines bl and blb, respectively. Word line assertion causes a bit line voltage difference to develop between the bit lines in each bit line pair. One bit line in each bit line pair is reduced slightly from the power supply voltage (the bit line is partially discharged), while the remaining bit lines in each bit line pair remain in their precharged state (the bit line is fully charged).

[0030] With the word line still asserted and the bit line voltage difference developed, a charge transfer period is triggered by discharging the gate voltage rm. For example, the gate voltage rm may be controlled by a dummy bit line. Due to the discharge of the gate voltage rm less than this instant, the gate voltage rm discharges to the threshold voltage of the charge transfer transistor (e.g., M2) whose source is coupled to the fully charged bit line, but still exceeds the threshold voltage of the charge transfer transistor (e.g., M1) whose source is coupled to the partially discharged bit line. Thus, the charge transfer transistor of the fully charged bit line conducts charge to its sense node before the charge transfer transistor conducts charge from the partially discharged bit line. Thus, the sense node voltage qb increases prior to the increase in the complementary sense node voltage q.

[0031] The architectures shown in both Figures 1-4 and 5-6 use this voltage difference to make bit decisions. For example, Figure 2 is a diagram of an exemplary sense amplifier 130 for the implementation of Figure 1. The sense amplifier 130 in this example is implemented using a cross-coupled pair of AOI gates 131, 132. The truth table for AOI gate 131 is shown below.

[0032] [Table 1]

[0033] The truth table for AOI gate 132 is shown below.

[0034] [Table 2]

[0035] Figure 3 provides an example timing diagram of signals applied to the sense amplifier 130 of Figure 2, according to one implementation. This example follows from the discussion of Figure 7 (above), where bl and blb correspond to a bit line pair in bank 195, starting at VDD, and bl is eventually discharged to read a stored 0.

[0036] The top signal (b0_bl_pre) is the precharge signal, as discussed above with respect to Figure 7. Precharge is turned off at time t1, and then the wordline wl signal is asserted at time t2. The bitline (bl) is discharged, but the bitline complement (blb) remains at VDD.

[0037] When bl and blb have a sufficient voltage difference, pch_b0 is deasserted at time t3, which means that the discharge NMOS transistors N3, N4 are turned off while transistors N1, N2 remain on. Transistor P14 is turned on, but signals SROP, SRON are both high, which turns off transistors P1-P4, as well as N11 and P12. Transistors P1 and P3 couple VDD to q_b0 and q_b1, and transistors P2 and P4 couple VDD to qb_b0 and qb_b1.

[0038] Then, the read mux signal (b0_rm) goes on at time t4, which couples the sense node pair to the bit line pair. Bit line bl is coupled to sense node q, and blb is coupled to the complementary sense node qb. The bit line complement blb has a higher potential, which causes qb to rise faster compared to q at time t5. (Note that q_b1 and qb_b1 remain low so that transistors P5, P6 are on and transistors N7, N8 are off.) This causes the SRON signal to go low at time t6. With SRON low, transistors P9, P2, P4, and N11 are on and transistor N9 is off. Meanwhile, the high value of SROP causes transistors P1, P3, P11 to be off and N10 to be on. Transistor N11 pulls the output (sa_out) to 0 (i.e., ground) while transistor P12 is off, and therefore the output complement (sa_out_n) is 1. At time t7, word line wl is deasserted, followed by pch and rm. As a result, an output value of 0 can be sensed by sense amplifier 130 and sent to an output circuit, such as an output latch (not shown).

[0039] In contrast, a read operation of a digital 1 value will cause bl to remain high and blb to be discharged, which will result in q_b0 going high and qb_b0 going low, outputting sa_out as a digital 1. Of course, this example is for a read operation performed on memory bank 195. It will be understood that a read operation performed on memory bank 196 will be performed similarly.

[0040] FIG. 4 is a diagram of an exemplary sense amplifier 430 according to one implementation. The example of FIG. 4 is provided to demonstrate that the scope of implementations is not limited to any particular number of memory banks. Rather, the sense amplifier 430 can be scaled to accommodate a greater number of memory banks up to N memory banks, where N is an integer greater than 2, with each memory bank having a sense node and a complementary sense node (i.e., q_b0 to q_bn-1 and qb_b0 to qb_bn-1). The sense amplifier 430 can be scaled by increasing the number of series PMOS transistors PX and PX-b and the number of parallel NMOS transistors NX and NX_b.

[0041] FIG. 5 illustrates an exemplary memory system 500 according to one implementation. The implementation of FIG. 5 uses two sense amplifiers 510, 520 to accommodate multiple memory banks 195, 196. The sense amplifiers 510 and 520 may be implemented in a similar manner relative to each other. In this implementation, memory bank 195 corresponds to sense node pair q_b0, qb_b0, and memory bank 196 corresponds to sense node pair q_b1, qb_b1. The sense amplifier 510 is coupled to multiplexer 110 by sense node pair q_b0, qb_b0, and the sense amplifier 520 is coupled to multiplexer 120 by sense node pair q_b1, qb_b1.

[0042] In this example, only one of the memory banks 195, 196 is written to or read from at a particular time. In other words, only one of the sense amplifiers 510, 520 is expected to make a bit decision during any particular read operation. Furthermore, the sense amplifiers 510, 520 are not used during write operations. Once a bit decision is made, that bit may be applied to downstream circuitry, such as a latch (not shown).

[0043] 6 is a diagram of sense amplifiers 510, 520 according to one implementation. Specifically, sense amplifier 510 may include a cross-coupled pair of NAND gates 631, 632, and sense amplifier 520 may include a cross-coupled pair of NAND gates 633, 634. Each cross-coupled pair of NAND gates makes a bit decision based on a voltage difference between the sense nodes in the sense node pair, similar to the examples of FIGS. 1-4.

[0044] This example follows from the discussion of Figure 7 (above), where bl and blb correspond to a bit line pair in bank 195, starting at power supply voltage VDD, and bl finally being discharged to read the stored 0. The table below is a truth table for cross-coupled NAND gates 631, 632, it being understood that the same logic is provided by cross-coupled NAND gates 633, 634.

[0045] [Table 3]

[0046] The sense node q_b is connected to the input of NAND gate 631, and the sense node qb_b0 is coupled to the input of NAND gate 632. NAND gates 631 and 632 are cross-coupled to form an RS latch. In this example, the sense node pair is precharged to 0 volts, causing the outputs of both NAND gates 631 and 632 to be asserted high relative to the power supply voltage VDD, and bit cell 705 stores a digital one. Precharging the sense node pair to 0 volts turns on transistors P24, P26. Both SRON_b0 and SROP_b0 are high, which turns off transistors P21, P22, P23, P25, P27, and N27, and turns on transistors N23, N25. The parasitic capacitance of the sense node, conceptually represented by capacitor C (FIG. 7), is relatively small compared to the bit line capacitance, conceptually represented by capacitor Cbl (FIG. 7). The short amount of time that charge transfer transistor M1 (FIG. 7) begins to conduct before charge transfer transistor M2 (FIG. 7) therefore causes a significant increase in the voltage of sense node q_b0 compared to sense node qb_b0. Because this increase in voltage exceeds the threshold voltage of NAND gate 631, its output is discharged to 0. In other words, the increase in voltage of sense node q_b0 turns on transistors N24, N26, which pulls SROP_b0 to a 0 value. The 0 output of NAND gate 631 reinforces the high binary output of NAND gate 632 by turning on transistor P26 and turning off transistor N25. Transistor P27 turns on and transistor N27 remains off so that the binary 1 value stored in bit cell 705 is detected.

[0047] In the example where a 0 is stored in bit cell 705, the value output by NAND gate 632 becomes 0 by turning on transistors N25, N26, and the value output by NAND gate 631 becomes 1. In different read operations, the same process may be performed in sense amplifier 520. In other words, the arrangement of transistors in sense amplifier 520 results in the same logic provided by the arrangement of transistors in sense amplifier 510, by the cross-coupled NAND gates 633, 634.

[0048] Another difference between the embodiment of Figures 1-4 and the implementation of Figures 5-6 is that the implementation of Figures 5-6 includes two push-pull circuits including transistors P27, N27, P37, and N37, whereas the implementation of Figures 1-4 includes a single push-pull circuit including transistors P12 and N11. This is one example where the implementation of Figures 1-4 reduces the number of transistors compared to the implementation of Figures 5-6. Also, as mentioned above, a single set of cross-coupled AOI gates has fewer transistors than two sets of cross-coupled NAND gates, which is another example where the implementation of Figures 1-4 reduces the number of transistors. Nevertheless, both implementations described herein provide reliable operation and may be implemented in a given application as needed. As mentioned above, the implementations herein may reduce the number of bit line pairs per sense node pair, thereby reducing the parasitic capacitance seen by the sense amplifier, thus allowing smaller voltage differences to be detected faster.

[0049] An exemplary method for a read operation will be discussed with reference to the flow chart shown in Figure 8. Method 800 may be performed by a memory such as those shown in Figures 1 and 5. In other words, method 800 may be performed by a multi-bank memory system having multiple read multiplexers and one or more sense amplifiers to make bit decisions for a given read operation.

[0050] At action 810, the method includes multiplexing a first plurality of bit line pairs with a first sense node pair. Action 810 may include coupling a first bit line pair of the plurality of bit line pairs with the first sense node pair. An example in which the bit line pair and the sense node pair are coupled by transistor pairs and share charge when the transistors are turned on is described above with respect to FIG.

[0051] In action 820, the method includes charge sharing between the first bit line pair and the first sense node pair. In the example of FIG. 7, when the transistors are turned on, the bit line pair is electrically coupled to the sense node pair. In an example where the transistors are PMOS transistors, the gate source voltage determines when a particular transistor turns on. For example, when the magnitude of the gate source voltage reaches a higher voltage faster, the transistor turns on faster, and when the magnitude of the gate source voltage reaches a higher voltage slower, the transistor turns on slower. Thus, the bit line or the complementary bit line may charge or discharge the sense node or the complementary sense node faster or slower depending on the charge sharing architecture. However, the time lag in the charge sharing may result in a voltage that is a fraction of the rail voltage but can be detected to make a bit decision.

[0052] At action 830, the method includes inputting values ​​from the sense node pairs into a logic circuit. In one example, the logic circuit may include cross-coupled AOI gates, as in the implementation of FIG. 2. In another example, the logic circuit may include cross-coupled NAND gates, as in the implementation of FIG. 6.

[0053] At action 840, the method includes causing a logic circuit to make a bit decision based on the values ​​from the first pair of sense nodes. For example, the logic circuit may provide a logic function that provides a digital one or digital zero output in response to a voltage difference detected between the sense node and the complementary sense node.

[0054] As described above, the method may be performed in a memory system having multiple memory banks, each of which is coupled to a read multiplexer, and each read multiplexer is coupled to a sense node pair. In some examples, only one memory bank may be accessed during a read or write operation. Thus, a subsequent read operation may be performed on the same memory bank or a different memory bank. Actions 850-870 show a subsequent read operation performed on a second memory bank using a second bit line pair and a second sense node pair. However, it is understood that in other examples, actions 850-870 may be performed on the same memory bank using a first bit line pair and a second sense node pair.

[0055] The scope of implementations is not limited to the sequence of actions described with respect to Figure 8. Rather, other implementations may add, omit, rearrange, or modify one or more actions. For example, during operation of the memory system, a read operation may be performed to a first memory bank or to a second memory bank, and then a subsequent read operation may be performed to either the first memory bank or the second memory bank, etc. Read operations may or may not be interspersed with write operations, and operations may be repeated as necessary.

[0056] 9 is a diagram of an exemplary SOC 900 according to one implementation. In this example, the SOC 900 is implemented on a semiconductor die and includes multiple system components 910-990. Specifically, in this example, the SOC 900 includes a CPU 910, which is a multi-core general-purpose processor having four processor cores, core 0-core 3. Of course, the scope of the implementation is not limited to any particular number of cores, as other implementations may include two cores, eight cores, or any other suitable number of cores in the CPU 910. The SOC 900 further includes other system components, such as a first digital signal processor (DSP) 940, a second DSP 950, a modem 930, a GPU 920, a video subsystem 960, a wireless local area network (WLAN) transceiver 970, and a video-front-end (VFE) subsystem 980. The SOC 900 also includes a RAM memory unit 990 that can operate as a system RAM for any of the components 910-980. For example, the RAM memory unit 990 can receive data and instructions from any of the components 910-980.

[0057] The RAM memory unit 990 may include a sense amplifier architecture that services a multi-bank arrangement, such as that described above with respect to Figures 1-7. Additionally, the RAM memory unit 990 may perform the actions of Figure 8 to perform a read action.

[0058] As will be appreciated by those skilled in the art at present, depending on the particular application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, apparatus, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the specific embodiments shown and described herein are merely for the sake of some examples thereof, and the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be entirely within the scope of the following appended claims and their functional equivalents.

[0059] Implementations are described in the following numbered clauses. 1. A first read multiplexer coupling a first plurality of bit lines to a first sense node and a first complementary sense node; a second read multiplexer coupling the second plurality of bit lines to the second sense node and the second complementary sense node; a first sense amplifier coupled to the first sense node and the first complementary sense node, the first read multiplexer being associated with the first bank of memory bit cells and the second read multiplexer being associated with the second bank of memory bit cells; The circuit includes:

[0060] 2. A second sense amplifier coupled to the second sense node and the second complementary sense node, the output of the second sense amplifier being coupled to the output of the first sense amplifier. The circuit of clause 1 further comprises:

[0061] 3. A circuit comprising: a first sense amplifier including a first cross-coupled pair of NAND gates; a second sense amplifier including a second cross-coupled pair of NAND gates; and a first push-pull circuit coupled to the first cross-coupled pair of NAND gates; and a second push-pull circuit coupled to the second cross-coupled pair of NAND gates. Further comprising: an output of the first sense amplifier and an output of the second sense amplifier are coupled via a first push-pull circuit and a second push-pull circuit; Clause 2 Circuit.

[0062] 4. The circuit of clause 3, wherein a first cross-coupled pair of NAND gates is coupled to a first sensing node and a second cross-coupled pair of NAND gates is coupled to a first complementary sensing node.

[0063] 5. The circuit of clause 1, wherein the first sense amplifier is further coupled to the second sense node and the second complementary sense node.

[0064] 6. A first sense amplifier comprising: Cross-coupled pairs of AND-OR-inversion (AOI) gates Including, a first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sensing node, the second complementary sensing node, and an output from the second AOI gate of the cross-coupled pair of AOI gates; a second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sensing node, the second sensing node, and to an output from the first AOI gate of the cross-coupled pair of AOI gates; Article 5 Circuit.

[0065] 7. A first sense amplifier comprising: a cross-coupled pair of AND-OR-inversion (AOI) gates; a push-pull circuit coupled to an output of a first AOI gate of the cross-coupled pair of AOI gates and to an output of a second AOI gate of the cross-coupled pair of AOI gates; Including, the Circuit of Clause 5.

[0066] 8. A first sense amplifier is coupled to the N further sense nodes and the N further complementary sense nodes, the first sense amplifier comprising: a cross-coupled pair of AND-OR-inversion (AOI) gates; a first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sensing node, the second complementary sensing node, and N further complementary sensing nodes; a second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sensing node, the second sensing node, and N further sensing nodes, where N is an integer greater than 1; Article 5 Circuit.

[0067] 9. multiplexing a first plurality of bit line pairs with a first sense node pair in a first read operation, the multiplexing including coupling a first bit line pair of the first plurality of bit line pairs with the first sense node pair; charge sharing between a first pair of bit lines and a first pair of sense nodes; inputting values ​​from a first pair of sensing nodes into a logic circuit; causing the logic circuit to make a bit decision based on the values ​​from the first pair of sensing nodes; multiplexing a second plurality of bit line pairs with a second sense node pair during a subsequent read operation, the multiplexing including coupling a second bit line pair of the second plurality of bit line pairs to the second sense node pair, the first plurality of bit line pairs being associated with a first bank of memory bit cells and the second plurality of bit line pairs being associated with a second bank of memory bit cells; A method comprising:

[0068] 10. Charge sharing between a second pair of bit lines and a second pair of sense nodes; causing the logic circuit to make a subsequent bit decision based on inputs from the second pair of sense nodes; The method of clause 9 further comprises:

[0069] 11. The method of clause 10, wherein the logic circuit includes a first sense amplifier associated with the first pair of sense nodes and a second sense amplifier associated with the second pair of sense nodes.

[0070] 12. The method of clause 10, wherein the logic circuit includes a sense amplifier coupled to the first pair of sense nodes and the second pair of sense nodes.

[0071] 13. The method of clauses 9-10, wherein the logic circuit includes a plurality of cross-coupled pairs of NAND gates.

[0072] 14. The method of clause 9 or 10, wherein causing the logic circuit to make the bit decision includes pushing up or pulling down the output of a first cross-coupled NAND pair of gates using a first push-pull circuit coupled to a second push-pull circuit associated with an additional cross-coupled pair of NAND gates.

[0073] 15. The method of clause 9 or 10, wherein the logic circuit comprises a cross-coupled pair of AND-OR-invert (AOI) gates.

[0074] 16. A plurality of memory banks, each including a plurality of bit line pairs; a plurality of sensing node pairs, each associated with a respective one of the memory banks; means for multiplexing the bit line pairs with the sense node pairs; means for making bit decisions based on voltages associated with pairs of sense nodes during a plurality of read operations directed to a plurality of memory banks; a memory device.

[0075] 17. The memory device of clause 16, wherein the means for making a bit decision includes a cross-coupled pair of AND-OR-invert (AOI) gates, the cross-coupled pair of AOI gates being coupled to a plurality of sensing node pairs.

[0076] 18. The memory device of clause 17, further comprising a push-pull circuit coupled to an output of a first AOI gate of the cross-coupled pair of AOI gates and to an output of a second AOI gate of the cross-coupled pair of AOI gates.

[0077] 19. The memory device of clause 16, wherein the means for making a bit decision includes a plurality of cross-coupled NAND gate pairs, a first one of the NAND gate pairs being coupled to a first pair of sense nodes, and a second one of the NAND gate pairs being coupled to a second pair of sense nodes.

[0078] 20. A first memory bank including a first plurality of bit cells arranged in a first plurality of columns; a second memory bank including a second plurality of bit cells arranged in a second plurality of columns; a first pair of sense nodes coupled to a first plurality of columns by a first read multiplexer; a second pair of sense nodes coupled to a second plurality of columns by a second read multiplexer; a first sense amplifier coupled to the first pair of sense nodes; Including, memory.

[0079] 21. The memory of clause 20, wherein the first sense amplifier includes a cross-coupled pair of AND-OR-invert (AOI) gates further coupled to a second pair of sense nodes.

[0080] 22. A first sense amplifier is coupled to N further sense node pairs; a first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sensing node, the second complementary sensing node, and N further complementary sensing nodes; a second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sensing node, the second sensing node, and N further sensing nodes, where N is an integer; Article 21 Memory.

[0081] 23. The memory of clause 20, wherein the first sense amplifier includes a first cross-coupled pair of NAND gates, and the memory further includes a second sense amplifier including a second cross-coupled pair of NAND gates and coupled to the second sense node pair.

[0082] 24. The memory of any of clauses 20-23, wherein a first sensing node pair is coupled to a first plurality of columns by a plurality of bit line pairs, and a first read multiplexer is configured to turn on a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor to couple a first one of the bit line pairs to the first sensing node pair.

Claims

1. A first read multiplexer that couples a first plurality of bit lines to a first sense node and a first complementary sense node; A first transistor having a source coupled to ground and a drain coupled to the first sense node; A second transistor having a source coupled to ground and a drain coupled to the first complementary sense node; A second read multiplexer that couples a second plurality of bit lines to a second sense node and a second complementary sense node; A third transistor having a source coupled to ground and a drain coupled to the second sense node; A fourth transistor having a source coupled to ground and a drain coupled to the second complementary sense node; A first sense amplifier coupled to the first sense node and the first complementary sense node, wherein the first read multiplexer is associated with a first bank of memory bit cells and the second read multiplexer is associated with a second bank of memory bit cells, the first sense amplifier; comprising; the first sense amplifier is further coupled to the second sense node and the second complementary sense node; circuit.

2. The first sense amplifier is including a cross-coupled pair of AND-OR-invert (AOI) gates; The first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sense node, the second complementary sense node, and the output from the second AOI gate of the cross-coupled pair of AOI gates; The second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sense node, the second sense node, and the output from the first AOI gate of the cross-coupled pair of AOI gates; The circuit according to claim 1.

3. The first sense amplifier is coupled to N additional sense nodes and N additional complementary sense nodes, and the first sense amplifier is further including a cross-coupled pair of AND-OR-invert (AOI) gates; The first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sense node, the second complementary sense node, and the N additional complementary sense nodes; The second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sense node, the second sense node, and the N further sense nodes, where N is an integer greater than 1. The circuit according to claim 1.

4. In a first read operation, multiplexing a first plurality of bit line pairs with a first pair of sense nodes, including coupling a first bit line pair of the first plurality of bit line pairs to the first pair of sense nodes; Performing charge sharing between the first bit line pair and the first pair of sense nodes; Inputting a value from the first pair of sense nodes into a logic circuit; Causing the logic circuit to perform a bit determination based on the value from the first pair of sense nodes; In a subsequent read operation, multiplexing a second plurality of bit line pairs with a second pair of sense nodes, including coupling a second bit line pair of the second plurality of bit line pairs to the second pair of sense nodes, wherein the first plurality of bit line pairs are associated with a first bank of memory bit cells and the second plurality of bit line pairs are associated with a second bank of memory bit cells; A method comprising: The logic circuit includes a first sense amplifier (130, 430) coupled to the first pair of sense nodes and the second pair of sense nodes; The method further includes discharging the first pair of sense nodes by a first transistor having a source coupled to ground and a drain coupled to the first sense node, and a second transistor having a source coupled to ground and a drain coupled to the first complementary sense node; The method further includes discharging the second pair of sense nodes by a third transistor having a source coupled to ground and a drain coupled to the second sense node, and a fourth transistor having a source coupled to ground and a drain coupled to the second complementary sense node. Method.

5. Performing charge sharing between the second bit line pair and the second pair of sense nodes; Causing the logic circuit to perform a subsequent bit determination based on an input from the second pair of sense nodes; The method according to claim 4, further comprising:

6. The method according to claim 5, wherein the logic circuit includes a sense amplifier coupled to the first pair of sense nodes and the second pair of sense nodes.

7. The method according to claim 4, wherein the logic circuit includes a cross-coupled pair of AND-OR-invert (AOI) gates.

8. A memory including the circuit according to claim 1, wherein the memory includes a first memory bank including a first plurality of bit cells arranged in a first plurality of columns, a second memory bank including a second plurality of bit cells arranged in a second plurality of columns, a first pair of sense nodes coupled to the first plurality of columns by the first read multiplexer, and a second pair of sense nodes coupled to the second plurality of columns by the second read multiplexer. A memory comprising:

9. The memory according to claim 8, wherein the first pair of sense nodes is coupled to the first plurality of columns by a plurality of bit line pairs, and the first read multiplexer is configured to turn on a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor to couple a first bit line pair of the bit line pairs to the first pair of sense nodes.

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