Managing voltage regulator units in field programmable arrays.

Abstract

The electronic device has power rails driven by voltage regulators to provide a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail for supplying up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and the voltage regulator controller and operates in a standby mode or an operating mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not supply current to the power rail, while in the operating mode, the bypass unit does not bypass the feedback path and the respective voltage regulator supplies up to a predefined regulator current to the power rail.

Description

[Technical field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 237,485, entitled “Management of Voltage Regulator Units in Field Programmable Arrays,” filed August 26, 2021, which is incorporated by reference in its entirety.

[0002] This application also claims priority to U.S. patent application Ser. No. 17 / 684,215, entitled "Management of Voltage Regulator Units in Field Programmable Arrays," filed Mar. 1, 2022, which is incorporated by reference in its entirety herein. [Background technology]

[0003] Electronic devices often incorporate a system-on-chip (SoC) with a power management integrated circuit (PMIC), communication ports, external memory or storage, and other peripheral modules on a main logic board. The SoC includes one or more microprocessors or central processing unit (CPU) cores, memory, input / output ports, and secondary storage in a single package. The PMIC is typically disposed adjacent to the SoC on the main logic board and provides multiple direct current (DC) power supply rails to the SoC through conductors formed on the main logic board. For each type of SoC, the PMIC and the conductors leading to the SoC must be custom designed based on at least the microprocessor or CPU cores included in this type of SoC. Summary of the Invention

[0004] Various embodiments of systems, methods, and devices within the scope of the appended claims each have several aspects, no single aspect of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and in particular the section entitled "Description of Embodiments," it will be understood how aspects of the various embodiments are used to provide a semiconductor device configured to provide a semiconductor device or system having a generic PMIC that can adaptively support a variety of different types of SoCs having different microprocessors or CPU cores. The generic PMIC provides multiple power rails to power one or more clusters of processors of the SoC. The semiconductor device includes multiple voltage regulators disposed in a field programmable array and controlled to output power to the multiple power rails of the SoC based on load information and power state policies associated with the one or more clusters of processors coupled to the power rails. In some embodiments, each voltage regulator in the field programmable array can be electrically isolated from multiple power rails and become a redundant or standby voltage regulator without being completely powered down when a bypass unit (of the redundant or standby voltage regulator) operates in standby mode to disable the feedback path between the output interface and the input of the redundant or standby voltage regulator.

[0005] Specifically, in one aspect, an electronic device includes a power rail configured to provide a rail voltage, and a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, one or more drive paths, a voltage regulator controller, and a bypass unit. The output interface is coupled to the power rail and configured to provide the rail voltage and to supply up to a predetermined regulator current to the power rail. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path and is configured to control the one or more drive paths. The bypass unit is coupled to the one or more drive paths and the voltage regulator controller. Each respective voltage regulator of the plurality of voltage regulators is configured to operate in either a standby mode or an operating mode according to a control setting. In the standby mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the respective voltage regulator does not supply current to the power rail. In the operating mode, the bypass unit is disabled to bypass the feedback path and each voltage regulator supplies up to a default regulator current to the power rail.

[0006] In another aspect, a method of driving a power rail in an electronic device having a plurality of voltage regulators electrically coupled to the power rail is implemented. The method includes generating a rail voltage and a rail current to drive the power rail. Each respective voltage regulator has an output interface coupled to the power rail and is configured to provide the rail voltage and supply up to a predefined regulator current to the power rail when the respective voltage regulator is in an operational mode. The method further includes obtaining a control setting for each respective voltage regulator of the plurality of voltage regulators. The control setting of each respective voltage regulator determines whether the respective voltage regulator is a standby voltage regulator operating in a standby mode or an operational voltage regulator operating in an operational mode. The method further includes enabling, at each standby voltage regulator, a bypass unit of the standby voltage regulator to bypass a feedback path from the output interface to an input of the voltage regulator controller such that the standby voltage regulator does not supply current to the power rail. The method further includes disabling, at each operational voltage regulator, the bypass unit from bypassing the feedback path such that the respective voltage regulator supplies current to the power rail.

[0007] These exemplary embodiments and implementations are described not to limit or define the disclosure, but to provide examples to aid in its understanding. Additional embodiments are described in the detailed description and further description is provided therein. Other implementations and advantages may become apparent to those skilled in the art in light of the description and drawings herein. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 2 is a block diagram of exemplary system modules in a typical electronic device, according to some embodiments. [Figure 1B] 1 is a cross-sectional view of an integrated semiconductor device according to some embodiments. [Diagram 2] 1 is a block diagram of a power management system according to some embodiments. [Diagram 3] 1 is a simplified block diagram of an integrated semiconductor device including multiple voltage regulators for providing one or more power rails to an SoC, according to some embodiments. [Figure 4A] 1 illustrates a process of providing a rail current I R at a rail voltage V R using a subset of voltage regulators according to some embodiments. [Figure 4B] 1 illustrates a process for providing a rail current IR at a rail voltage VR based on one or more redundant voltage regulators in accordance with some embodiments. [Figure 5A] 1 is a block diagram of a voltage regulator, one of the voltage regulators in a field programmable array, in accordance with some embodiments. [Figure 5B] FIG. 2 is a block diagram of a voltage regulator having a bypass unit according to some embodiments. [Figure 6] FIG. 2 is a circuit diagram of a voltage regulator having an auxiliary loop for controlling redundancy according to some embodiments. [Figure 7] 1 is a circuit diagram of an example voltage regulator having a filter-based auxiliary loop in accordance with some embodiments. [Figure 8] 1 is a circuit diagram of a plurality of voltage regulators of a field programmable array of voltage regulators configured to drive a power rail in accordance with some embodiments. [Figure 9A] FIG. 2 is a circuit diagram of a multi-phase driver in a voltage regulator having multiple drive paths while operating in an operational mode according to some embodiments. [Figure 9B] FIG. 2 is a circuit diagram of a voltage regulator having multiple bypass paths while operating in bypass mode according to some embodiments. [Figure 9C] 1A-1D are circuit diagrams of equivalent circuits of a voltage regulator operating in operating mode and bypass mode, respectively, according to some embodiments. [Figure 9D] 1A-1D are circuit diagrams of equivalent circuits of a voltage regulator operating in operating mode and bypass mode, respectively, according to some embodiments. [Figure 10] 1 is a flow diagram of a method for driving power rails of an electronic device according to some embodiments.

[0009] For a better understanding of the various implementations described, reference should be made to the following Detailed Description of the Invention in conjunction with the following drawings, in which like reference numerals refer to corresponding parts throughout: DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details.

[0011] 1 is a block diagram of an exemplary system module 100 in a typical electronic device, according to some embodiments. The system module 100 in this electronic device includes at least a system on chip (SoC) 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces, such as a network interface 108, and one or more communication buses 130 for interconnecting these components. In some embodiments, the I / O controller 106 enables the SoC 102 to communicate with I / O devices (e.g., a keyboard, a mouse, or a touch screen) via a Universal Serial Bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each of which allows the electronic device to exchange data with an external source, such as a server or another electronic device. In some embodiments, the communication bus 130 includes circuitry (sometimes referred to as a chipset) that interconnects and controls communication between various system components included in the system module 100.

[0012] In some embodiments, memory module 104 includes high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, memory module 104, or alternatively a non-volatile memory device within memory module 104, includes a non-transitory computer-readable storage medium. In some embodiments, a memory slot is reserved on system module 100 to accept memory module 104. When inserted into the memory slot, memory module 104 is integrated into system module 100.

[0013] In some embodiments, the system module 100 further includes one or more components selected from the following: A memory controller 110 that controls communication between the SoC 102 and memory components, including the memory module 104, in the electronic device; Applying integrated circuit assemblies for storing data in electronic devices, in many embodiments solid state drives (SSDs) 112 based on NAND or NOR memory configurations; · a hard drive 114, which is a conventional data storage device based on electromechanical magnetic disks used to store and retrieve digital information; a power supply connector 116 including one or more direct current (DC) power supply interfaces each configured to receive a separate DC supply voltage; a power management integrated circuit (PMIC) 118 that regulates a separate DC supply voltage received via the DC power supply interface to other desired internal supply voltages (also called rail voltages), e.g., 5V, 3.3V, or 1.8V, as required by various components or circuits within the electronic device (e.g., a processor core within the SoC 102); a graphics module 120 that generates output image feeds to one or more display devices according to their desired image / video format; and · A sound module 122 that facilitates the input and output of audio signals to and from electronic devices under the control of a computer program.

[0014] Also, note that communication bus 130 interconnects and controls communications between various system components, including components 110-122.

[0015] Furthermore, those skilled in the art will appreciate that other non-transitory computer readable storage media may be used as new data storage technologies are developed for storing information on the non-transitory computer readable storage media in memory module 104 and in SSD 112. These new non-transitory computer readable storage media include, but are not limited to, those made from biological materials, nanowires, carbon nanotubes, and individual molecules, although each of these data storage technologies is currently under development and has not yet been commercialized.

[0016] In some embodiments, the SoC 102 is implemented in a semiconductor package that includes one or more integrated circuits, each of which incorporates a subset of one or more microprocessors or CPU cores, memory, input / output ports, and secondary storage on a single substrate. The PMIC 118 is also implemented in a semiconductor package that includes one or more integrated circuits, each formed on a single substrate. The SoC 102 is configured to receive one or more internal supply voltages (also referred to as rail voltages) provided by the PMIC 118 via one or more power rails. In some embodiments, both the SoC 102 and the PMIC 118 are mounted on a main logic board, e.g., on two separate areas of the main logic board, and are electrically coupled to each other via conductive lines formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that may impair the performance of the SoC, e.g., cause voltage drops in the internal supply voltages. 1B, the semiconductor dies of the SoC 102 and the PMIC 118 are packaged vertically in an integrated semiconductor device such that they are electrically coupled to each other through electrical connections that are not formed on the main logic board. Such a vertical arrangement of the semiconductor dies of the SoC 102 and the PMIC 118 can reduce the length of the electrical connections between the SoC 102 and the PMIC 118 and can avoid performance degradation caused by routing conductors on the main logic board.

[0017] In some embodiments, the general-purpose PMIC 118 is configured to drive different types of SoCs 102 in different types of electronic devices. Whether the PMIC 118 and the SoC 102 are arranged side-by-side or vertically, the PMIC 118 occupies the same footprint with respect to the main circuit board, but the SoC 102 may have a separate footprint based on the electronic modules incorporated therein. The PMIC 118 includes multiple voltage regulator units (e.g., regulator 320 in FIG. 3 ) arranged in a field programmable array (e.g., array 330 in FIG. 3 ). The multiple voltage regulator units may be identical to each other or alternatively include two or more types of voltage regulator units. In a particular electronic device, the control settings are determined based on the rail voltages and rail currents of the power rails required to power the SOC 102 and other electronic modules, if any. For each of these power rails, a corresponding control setting is used to select a subset of voltage regulator units in the field programmable array of PMIC 118, which collectively provide rail current at the rail voltage for the respective power rail. Thus, PMIC 118 is reconfigured by these control settings to provide rail voltages and currents for the power rails of SoC 102, with each voltage regulator unit in the multiple configurable voltage regulators in PMIC 118 either being redundant or being selected to drive one of the power rails by one of the control settings.

[0018] 1B is a cross-sectional view of an integrated semiconductor device 180 with a SoC 102 and a PMIC 118 arranged vertically, according to some embodiments. The semiconductor device 180 incorporates at least one SoC die 102 and at least one PMIC die 118 in a semiconductor package and includes at least a package substrate 124 having a first side 124A and a second side 124B opposite the first side 124A. The SoC die 102 is disposed on the first side 124A of the package substrate 124, and the PMIC die 118 is mechanically coupled to the second side 124B of the package substrate 124.

[0019] The package substrate 124 further includes a plurality of first via interconnects 126 that pass through the body of the package substrate 124 and are exposed on both the first side 124A and the second side 124B. The PMIC die 118 is electrically coupled to the SoC die 102 through the plurality of first via interconnects 126 of the package substrate 124. In particular, the PMIC die 118 is coupled to a plurality of rail voltages V R 2 ) to the SoC die 102 via the DC connections 128 of the PMIC die 118, the power connections 132 of the SoC die 102, and the first via interconnects 126 of the package substrate 124. In some embodiments, the SoC die 102 includes a plurality of power connections 132 configured to receive a plurality of rail voltages. When the SoC die 102 is mounted on the first side 124A of the package substrate 124, the power connections 132 of the SoC die 102 are electrically coupled to the plurality of first via interconnects 126 of the package substrate 124. Thus, the PMIC die 118 is configured to provide DC power (i.e., rail voltages and rail currents of the power rails 206 of FIG. 2 ) to the SoC die 102 via the DC connections 128 of the PMIC die 118, the power connections 132 of the SoC die 102, and the first via interconnects 126 of the package substrate 124. Furthermore, by using the extremely low impedance DC connection 128, the quality of the DC power provided by the PMIC die 118 to the SoC die 102 is significantly improved over a system in which the PMIC die 118 and the SoC die 102 are packaged separately and placed side-by-side on a main circuit board.

[0020] In some embodiments, the power management interface 208 on the PMIC die 118 is controlled by the master power management interface of the SoC die 102 and is configured to receive digital power control signals (carrying the load information 314 of FIG. 3 ) from the SoC die 102. A subset of the first via interconnects 126 is configured to transfer the digital power control signals from the SoC die 102 to the PMIC die 118.

[0021] The SoC die 102 has a first footprint on the package substrate 124, and the PMIC 118 has a second footprint on the package substrate 124. In some embodiments, the first and second footprints at least partially overlap for purposes of directly coupling the DC connections 128 of the PMIC die 118 and the power connections 132 of the SoC die 102 using a plurality of first via interconnects 126. In some circumstances, the first footprint of the SoC die 102 is larger than and completely surrounds the second footprint of the PMIC die 118. Alternatively, in some circumstances, the first footprint of the SoC die 102 is offset from the second footprint of the PMIC die 118 but at least partially overlaps with the second footprint of the PMIC die 118. The DC connection 128 of the PMIC die 118, the power connection 132 of the SoC die 102, and the first via interconnect 126 of the package substrate 124 are aligned and surrounded within the overlap area of ​​the first and second footprints.

[0022] In addition, the PMIC die 118 includes a number of thin-film inductors 150 corresponding to the number of DC connections 128. The number of thin-film inductors 150 are located adjacent to or opposite the second side 124B of the package substrate 124, for example, on the top surface of the PMIC die 118 facing the second side 124B of the package substrate 124. In other words, the number of thin-film inductors 150 are disposed between the top surface of the PMIC die 118 and the second side 124B of the package substrate 124. In some embodiments, the PMIC die 118 is mechanically coupled to the package substrate 124, for example, via an adhesive. The height of the number of thin-film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) to maintain robustness of the mechanical coupling between the PMIC die 118 and the package substrate 124. Nevertheless, the vertical arrangement of the semiconductor dies of the SoC 102 and the PMIC 118 is facilitated, in part, by the incorporation of the thin film inductor 150 in the limited space between the dies of the SoC 102 and the PMIC 118. The thin film inductor is formed and incorporated on the substrate of the PMIC 118 such that the thin film inductor can fit into the limited space between the semiconductor dies of the SoC 102 and the PMIC 118, and has an inductor height that is controlled to be less than the height of the limited space. When the thin film inductor is formed on the substrate of the PMIC 118, the thin film inductor can be directly connected to an internal node or an output node of the PMIC 118, and no traces of the main logic board are used to connect the thin film inductor to the internal node or the output node of the PMIC 118.

[0023] In some embodiments, the integrated semiconductor device 180 further includes a cover 134 coupled to the first surface 124A of the package substrate 124. The cover 134 is configured to conceal the SoC die 102 and at least a portion of the first surface 124A of the package substrate 124, thereby protecting the SoC die 102 and at least a portion of the first surface 124A. Additionally, in some embodiments, the cover 134 is made from a conductive material and configured to be grounded to provide electrostatic shielding to the SoC die 102 and any other circuitry on the first surface 124A when completely concealed by the cover 134, or to provide electrostatic shielding to the portion of the first surface 124A concealed by the cover 134 when the first surface 124A is only partially concealed by the cover 134. In some circumstances, the cover 134 is made from a thermally conductive material configured to dissipate heat generated by the SoC die 102. In some embodiments, a heat spreader 136, or a layer of heat spreader, is used to couple the SoC die 102 to the inner surface of the cover 134 to evenly spread heat generated by the SoC die 102 from the SoC die 102 to the cover 134.

[0024] In some embodiments, the semiconductor device 180 further includes a socket substrate 138. The socket substrate 138 has a third surface 138A opposite to the second surface 124B of the package substrate 124. The package substrate 124 is electrically coupled to the socket substrate 138 via a plurality of electrical connectors 140. In particular, in some embodiments, the second surface 124B of the package substrate 124 includes a first area (e.g., a central area) to which the PMIC die 118 is mechanically coupled and a second area (e.g., a peripheral area) in which the plurality of electrical connectors 140 are located. In one example, the second area is adjacent to or surrounds the first area. It should be noted that under some circumstances, the semiconductor device 180 is provided with the socket substrate 138. However, under some circumstances, the socket substrate 138 is fixed onto the circuit board of the electronic device of FIG. 1A and is not part of the integrated semiconductor device 180. Rather, semiconductor device 180 is an interchangeable part that is provided to accommodate the combined functionality of PMIC die 118 and SoC die 102 .

[0025] In some embodiments, the third side 138A of the socket substrate 138 is substantially flat, and the PMIC die 118 is disposed between the second side 124B of the package substrate 124 and the third side 138A of the socket substrate 138. The height of the plurality of thin film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) determined by the difference between the length of the electrical connector 140 and the thickness of the PMIC die 118. Alternatively, in some embodiments, the socket substrate 138 includes a concave portion 142, sometimes referred to as a cavity, configured to receive the PMIC die 118 when the PMIC die 118 is mechanically and electrically coupled to the second side 124B of the package substrate 124. The depth of the concave portion 142 is less than the thickness of the socket substrate 138. In some circumstances, the PMIC die 118 is suspended within the concave portion 142, i.e., separated from a bottom surface of the concave portion 142 by an air gap. Alternatively, in some situations, the PMIC die 118 contacts the bottom surface of the concave portion 142, either directly or through an intermediate layer (e.g., an adhesive layer, a heat spreader layer, or a layer that is both an adhesive and a heat spreader).

[0026] 1B, the depth of recessed portion 142 is equal to the thickness of socket substrate 138, and recessed portion 142 is an opening or cutoff in socket substrate 138. When socket substrate 138 is mounted on a circuit board (e.g., a main logic board), PMIC die 118 is suspended within recessed portion 142 (also referred to as an opening or cutoff) and is at least partially surrounded by package substrate 124, socket substrate 138, and the circuit board.

[0027] In some embodiments, the power connections 132 of the SoC die 102 are not directly coupled to the first via interconnects 126 of the package substrate 124. Rather, a first interposer 144 is disposed between the SoC die 102 and a first side 124A of the package substrate 124. The first interposer 144 further includes a plurality of second via interconnects 146 configured to at least electrically couple the power connections 132 of the SoC die 102 to the first via interconnects 126 of the package substrate 124. Similarly, in some embodiments, the DC connections 128 of the PMIC die 118 are not directly coupled to the first via interconnects 126 of the package substrate 124. Rather, a second interposer 148 is disposed between the PMIC die 118 and a second side 124B of the package substrate 124. The second interposer 148 further includes a plurality of third via interconnects 152 configured to at least electrically couple the DC connection 128 of the PMIC die 118 and the first via interconnect 126 of the package substrate 124. Thus, the power rail 206 of the SoC 102 includes at least the power connection 132 of the SoC die 102, the first via interconnect 126 of the package substrate 124, and the DC connection 128 of the PMIC die 118, and in some circumstances further includes the second via interconnect 146 of the first interposer 144 and / or the third via interconnect 152 of the second interposer 148.

[0028] In some embodiments, the semiconductor device 180 further includes one or more discrete electronic modules 160 (e.g., resistors, capacitors, inductors, transistors, and logic chips). The discrete electronic modules 160 may be electrically coupled in an input / output interface circuit of the SoC die 102 to control input / output coupling of the SoC die 102. Optionally, a subset of the discrete electronic modules 160 (e.g., components 160A) are disposed on a first side 124A of the package substrate 124. Each component 160A may be contained within the cover 134 or located outside the cover 134. Optionally, a subset of the discrete electronic modules 160 (e.g., components 160B) are mechanically coupled to a second side 124B of the package substrate 124. If each component 160B has a low profile (e.g., thinner than the length of the electrical connector 140), the component 160B can fit into the gap between the second side 124B of the package substrate 124 and the third side 138A of the socket substrate 138. Otherwise, if the component 160B does not have a low profile (e.g., thicker than the length of the electrical connector 140), the each component 160B may be received by the recessed portion 142 of the socket substrate 138 and disposed adjacent to the PMIC die 118.

[0029] The SoC die 102 and the PMIC die 118 are arranged vertically in the semiconductor device 180. The power connections 132 of the SoC die 102 and the DC connections 128 of the PMIC die 118 are aligned and located close to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail 206 that provides the rail voltage to the SoC die 102. Note that in some implementations, multiple PMIC dies 118 may be disposed in the recessed portion 142 of the socket substrate 138 and electrically coupled to one or more SoC dies 102 disposed on the first side 124A of the package substrate 124. For example, two PMIC dies 118 are disposed in the recessed portion 142 of the socket substrate 138 to collectively power four SoC dies 102. One of the SoC dies 102 optionally corresponds to a microprocessor or CPU core, or a cluster of microprocessors or CPU cores.

[0030] Additionally, in some embodiments, the PMIC die 118 includes a field programmable array of voltage regulators that are configurable by control settings to drive different types of SoC die 102. In some situations, multiple instances of the same PMIC die 118, package substrate 124, and socket substrate 138 are used to support different types of SoC die 102. The recessed portion 142 formed on the socket substrate 138 has a fixed size to accommodate the same PMIC die 118, and the first via interconnect 126 passing through the body of the package substrate 124 has a fixed position. Alternatively, in some situations, the footprint size of the package substrate 124 and the socket substrate 138 differs for different types of SoC die 102, but the same PMIC die 118 allows the recessed portion 142 and the first via interconnect 126 of the package substrate 124 to remain unchanged, thereby avoiding the need for custom design of the PMIC die 118 and the entire package for each individual type of SoC die 102. Therefore, the application of a field programmable array of voltage regulators in the PMIC die 118 simplifies the assembly process of the semiconductor device 180 and improves cost efficiency.

[0031] 2 is a block diagram of a power management system 200 configured to provide power to one or more power rails 206 of an SoC, such as SoC 102, according to some embodiments. Power management system 200 receives one or more input DC supply voltages 202 and digital power control signals 204 and converts the input DC supply voltages 202 to one or more rail voltages that are output by one or more power rails 206A, 206B-206N and provided to SoC 102. Power management system 200 includes a power management interface 208, one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B...210N), and one or more output filters 212 (e.g., output filters 212A, 212B,...212N). Power management interface 208 receives input DC supply voltages 202 and digital power control signals 204. In some embodiments, the power management interface 208 is controlled by a master power management interface of a central processor unit (e.g., on the SoC 102) and is configured to receive digital power control signals 204 from the SoC 102. A DC-DC converter 210 is coupled to the power management interface 208 and to the power rails 206 and converts one or more rail voltages V 202 provided on the power rails 206 from the input DC supply voltage(s) 202. R 212. The output filter 212 is coupled to the DC-DC converter 210 and is configured to reduce noise and maintain stability in the power rails 206 provided to the SoC 102. In some embodiments, the output filter (e.g., any of 212A, 212B, ... 212N) includes one or more respective output resistors 214 and one or more output capacitors 216 (e.g., 216A, 216B, ... 216N). In some embodiments, the output filter (e.g., 212B) includes the inductor 150 and one or more output capacitors (e.g., capacitor 216B).

[0032] In some embodiments, the power management system 200 is implemented on one or more PMIC dies 118, with each PMIC die 118 having a single substrate. In some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on the substrate of a single PMIC die 118, e.g., reside in the same integrated circuit fabricated on the substrate of the PMIC die 118. Conversely, in some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on multiple substrates of multiple PMIC dies 118. In some embodiments, in addition to the power management interface 208 and the DC-DC converter 210, each PMIC die 118 further includes multiple thin film inductors fabricated on or attached to a top surface of the substrate of the PMIC die 118. Optionally, the multiple thin film inductors include one or more inductors 150 used in the output filter 212. Optionally, the multiple thin film inductors include one or more inductors 150′ used in the DC-DC converter 210A. In some embodiments, in addition to the power management interface 208, the converter 210, and the inductors 150 / 150′, the PMIC die 118 further incorporates a subset of the output resistors 214 and capacitors 216 of the output filter 212. Alternatively, in some embodiments, the PMIC 118 and SoC 102 are vertically disposed within an integrated semiconductor device 180, with a subset or all of the capacitive and resistive components of the output filter 212 formed using discrete electronic modules 160 disposed on either surface of the package substrate 124.

[0033] In some embodiments, the power management system 200 includes a field programmable array of voltage regulator units, an output filter 212, one or more output resistors 214, one or more output capacitors 216, and one or more inductors 150. The digital power control signals 204 are determined, for example, by the SoC 102 based on the target power capabilities (e.g., rail voltage and rail current) required for the power rails 206. In other words, the digital power control signals 204 are determined by the load information and power state policies of the power rails 206. The power state policies require the power rails to meet at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency). For example, each power rail 206 is configured to power a CPU cluster, a cache, or a functional block of the SoC 102, with respective power demands that are used by the SoC 102 to indicate the target power capabilities of the respective power rails 206 controlled by the corresponding power state policies. In one embodiment, the power state policy of a particular power rail 206 calls for the corresponding rail current of the particular power rail 206 to be controlled to maximize one of power conversion efficiency and rail voltage response speed. In accordance with the control signals 204, the voltage regulator units in the field programmable array are partitioned and configured to form one or more DC-DC converters 210, e.g., DC-DC converters 210A, 210B, ... 210N, to drive the power rail 206 in accordance with the load information and power state policy associated with the power rail 206. For each DC-DC converter 210, additional components 212-216 and 150 may also be selected and controlled by a respective subset of the control signals 204 to enable a desired noise performance for the corresponding power rail 206.

[0034] 3 is a simplified block diagram of an integrated semiconductor device 300 including multiple voltage regulators 320 for providing one or more power rails 206 to a SoC 102, according to some embodiments. The multiple voltage regulators 320 are arranged in a field programmable array 330. A power array controller 302 includes multiple electronic modules (e.g., one or more of an SoC interface, an oscillator, a microcontroller, an LDO, and a reference generator) and is coupled to the multiple voltage regulators 320. The power array controller 302 is configured to control the multiple voltage regulators 320 to output power to the multiple power rails 206. Each power rail 206 has a respective rail voltage V R In each rail current I R In the embodiment shown in FIG. 3, a field programmable array 330 of voltage regulators 320 powers four power rails 206-1, 206-2, 206-3, and 206-4, providing rail voltages V R1 , V R2 , V R3 , and V R4 In each case, the rail current I R1 , I R2 , I R3 , and I R4 For each of the plurality of power rails 206, the power array controller 302 provides a respective rail current I associated with the respective power rail 206. R and determine at least the respective rail current I R and selecting a subset of voltage regulators 320 according to R and generate the respective rail currents I R Thus, the power array controller 302 and the voltage regulator 320 implement a power management system for the SOC 102 on one or more PMIC dies 118.

[0035] The SoC 102 includes multiple electronic components, such as one or more microprocessors or CPU cores 304, memory 306, a communication module 308, timing sources, peripherals (e.g., clocks, counter timers), analog interfaces, input / output ports, and / or secondary storage. The microprocessors or CPU cores 304 are optionally arranged in clusters. The SoC 102 is implemented by one or more integrated circuits (e.g., SoC dies 102). Each SoC die 102 incorporates a subset of the electronic modules of the SoC 102 on a respective semiconductor substrate. In one embodiment, the SoC 102 has a main SoC die that includes one or more processor cores 304 and a companion SoC die that includes the memory 306, analog interfaces, or other components separate from the processor cores 304.

[0036] For each power rail 206, the respective rail voltage V R are determined by the operation of each subset of the electronic components of the SoC102, and the respective rail currents I R is determined by the load information and power state policies associated with each subset of electronic components of the SoC 102. The power array controller 302 controls at least each of the rail voltages V R and determining a control value 310 based on at least each rail current I R and providing the determined control values ​​310 to the selected subset of voltage regulators 320 corresponding to the respective power rails 206, such that the subset of voltage regulators 320 regulates the respective rail voltages V R and generate the respective rail currents I R Additionally, in some embodiments, the power array controller 302 is configured to collectively provide each of the rail voltages V R and generate the respective rail currents I R3. Accordingly, the power array controller 302 provides a control setting, including a control value 310 and an operation enable signal 312, to each voltage regulator 320 to collectively provide the rail voltage V R and rail current I R to each power rail 206.

[0037] In some embodiments, the power array controller 302 includes one or more processors and a memory having instructions stored thereon that, when executed by the one or more processors, cause the processors to control the voltage regulators 320 to output power to the multiple power rails 206. Optionally, a VRU grouping configuration is stored in a memory of the power array controller 302, in an off-chip non-volatile memory (NVM) of the system module 100, or in a basic input / output system (BIOS) of the system module 100 to associate control values ​​310 and enable signals 312 with a subset of the voltage regulators for each of the power rails 206. In some circumstances, the VRU grouping configuration is loaded and implemented by the power array controller 302 when the PMIC 118 is powered up.

[0038] Each of the multiple power rails 206 is configured to power a subset of the electronic modules of the SOC 102, which are loads for the respective power rail 206. For each power rail 206, the power array controller 302 determines load information 314 corresponding to an expected or actual load for the respective power rail 206, and calculates a respective rail current I associated with each power rail according to the load information 314 and the power state policy. RThe power state policy includes at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency), and the device 300 is configured to operate according to the power state policy for each power rail. In some embodiments, a power rail 206 is coupled to a main SoC die having one or more processor cores 304 arranged in clusters, and the load information 314 for that power rail 206 corresponds to processor load information for one or more clusters of processors 304 of the main SoC die 102 coupled to that power rail 206. Examples of processor load information include the total number and types of operations performed by one or more clusters of processors 304. Conversely, in some embodiments, one of the power rails 206 is coupled to a companion SoC die having memory 306 and configured to power write and read operations on the memory 306. The load information for that power rail 206 corresponds to memory load information for memory accesses of the memory 306 on the companion SoC die. Examples of memory load information include the memory type of the memory 306, the frequency of memory write operations, and the frequency of memory read operations. Thus, the rail current I R is adaptively determined based on the load information 314 (e.g., processor or memory load information) of each power rail 206. Furthermore, in some embodiments, given the load information of each power rail 206, the power state policy of each of the power rails 206 may be determined by adjusting the corresponding rail current I of the power rail 206. R is controlled to maximize one of power conversion efficiency and rail voltage response speed. In one embodiment, according to the power state policy, the power rail 206 provides a maximum rail current at start-up of the power rail 206 to allow the rail voltage to reach the rail voltage VR within a transient load response time.

[0039] Additionally, in some embodiments, each of the plurality of voltage regulators 320 in the field programmable array 330 corresponds to a respective voltage regulator type selected from a plurality of predefined voltage regulator types. For each power rail 206, a selected subset of the voltage regulators 320 is configured to meet at least one performance criterion (e.g., maximum rail current I RLM , maximum regulator current I RGM , output ripple voltage, power supply rejection ratio, load transient response, output noise, and power efficiency).

[0040] 3, after a respective subset of voltage regulators 320 is selected for each power rail 206, each voltage regulator 320 in the subset is uniquely associated with a respective power rail 206 at a time. For example, at a first time, power rails 206-1, 206-2, 206-3, and 206-4 are associated with four separate sets of voltage regulators 320 as shown in FIG. 3. Each voltage regulator 320 in a first row is uniquely associated with power rail 206-1 at a first time, and may not be associated with any of power rails 206-2, 206-3, or 206-4 at the same first time. However, at a second time, distinct from the first time, the voltage regulators 320 in the field programmable array 330 may be reconfigured to power separate power rails 206. Each voltage regulator 320 in the first row is uniquely associated with power rail 206-1 at a first time, but can be reconfigured to drive any of power rails 206-2, 206-3, and 206-4 at a second time. More generally, in some embodiments, at least a plurality of voltage regulators 320 in the field programmable array 330 can be configured to provide power to a selected power rail 206 of the plurality of power rails at any one time. Thus, in some embodiments, a subset of the voltage regulators 320 are permanently assigned to some power rails 206, while others are configurable as to which power rails 206 they are connected to. In some other embodiments, all of the voltage regulators 320 in the field programmable array 330 are configurable as to which power rails 206 they are connected to.

[0041] Each respective voltage regulator 320 has at least two modes, including an operating mode and a standby mode. In the operating mode, each respective voltage regulator 320 supplies the rail voltage V R to one of the associated power rails 206 and provide up to a predefined regulator current I Rto the associated power rail 206. Conversely, the standby mode applies when a respective voltage regulator 320 (e.g., 320RA-320RD) is not assigned to drive any power rail 206 and when a respective voltage regulator 320 (e.g., 320E) is temporarily disabled from supplying current to the power rail 206 to which the respective voltage regulator 320 is assigned. Specifically, in the embodiment shown in FIG. 3, voltage regulators 320RA-320RD in field programmable array 330 are redundant and not associated with any power rail 206. Such voltage regulators 320RA-320RD operate in the standby mode and do not exit the standby mode until voltage regulators 320RA-320RD are reassigned to drive one or more power rails 206. For each voltage regulator 320 assigned to a respective power rail 206, the respective voltage regulator 320 may be disabled from supplying current to the respective power rail 206 at a first duty cycle corresponding to a standby mode. At a second duty cycle different from the first duty cycle and corresponding to an operational mode, the respective voltage regulator 320 may be activated to provide power and supply current to the respective power rail 206. For example, the voltage regulator 320E associated with power rail 206-1 may operate at alternating duty cycles corresponding to a standby mode in which the voltage regulator 320 does not supply current to the power rail 206-1 and an operational mode in which the voltage regulator 320 is enabled to supply current to the power rail 206-1.

[0042] More specifically, in some embodiments, each voltage regulator 320 (e.g., voltage regulators 320RA-320RD and 320E) includes a bypass unit configured to provide a dummy load component. In the standby mode, the bypass unit is enabled (e.g., under control of operation enable signal 312) to bypass the feedback path from the output interface to the input of voltage regulator 320, thereby preventing each voltage regulator 320 from deriving any rail current I via the output interface.R In the operating mode, the bypass unit is disabled from bypassing the feedback path and the voltage regulator is disabled so that the output interface is at the rail voltage V R and rail current I R to a corresponding power rail 206. Further details regarding the bypass unit are provided below with reference to Figures 5B and 6-10.

[0043] In some embodiments, the semiconductor device 300 further includes one or more direct current (DC) power supply interfaces 316. Each DC power supply interface 316 receives a separate DC supply voltage V IN 202. Each voltage regulator 320 is coupled to a respective subset of one or more DC power supply interfaces 316 and is configured to receive a corresponding DC supply voltage V IN 202 and corresponding DC supply voltage V IN 202 to each rail voltage V R The method is configured to generate

[0044] FIG. 4A illustrates a block diagram of a voltage regulator 320 for regulating a rail voltage V R At the rail current I R 4B illustrates a process 400 for providing a rail voltage V based on one or more redundant voltage regulators 320 in accordance with some embodiments. R At the rail current I R 4 shows a process 450 for providing a rail current I R is 0 and the maximum rail current I RLM Each of the subset of voltage regulators 320 can vary between a maximum regulator current I RGM A subset of voltage regulators 320 is configured to provide a regulator current up to a maximum rail current I RLM and the maximum regulator current I RGM For example, in FIG. 3, the first power rail 206-1 has a maximum rail current IRLM and each voltage regulator 320 is required to output a maximum regulator current I RGM Each regulator can provide a maximum rail current I RLM (e.g., 0.6A) and the maximum regulator current I RGM (e.g., 80mA) and the eight voltage regulators supply a maximum rail current I RLM Rail current up to I R are required to provide

[0045] In some embodiments, the maximum rail current I RLM is the rail voltage V within the transient load response time. R , and the power rail 206 then reaches a maximum rail current I RLM The power rail 206 operates at an operating current less than the rail voltage V R The rail voltage V R Providing enough power to the power rails to reach the maximum regulator current I during startup RGM and the maximum rail current I RLM and thus the first number of voltage regulators 320 is determined in part based on the transient load response time required for start-up of the power rails 206. However, in some embodiments, when ramping up the voltage on each power rail 206 at power rail start-up, the current provided by power management system 500 is significantly less than the maximum rail current for that power rail to reduce system stress, avoid overshoot, etc.

[0046] During operation (sometimes referred to herein as normal operation, as opposed to startup) of the power rail 206, the operating current I R fluctuates and the maximum rail current I RLM Conversely, in some embodiments, the rail current I RWhen is used, the maximum rail current I RLM is reached at least occasionally during normal operation of the power rail 206. The operating current is between 0 and the maximum rail current I RLM In contrast to power rail 206 start-up, during normal operation, the first number of voltage regulators 320 is determined based on the operating current of the power rail 206, rather than the transient load response time of the power rail 206 at each start-up. The transient load response time of the power rail 206 is determined based on the maximum rail current I RLM This can be achieved with a smaller transient rail current than

[0047] 4A, at each instant, the power rail 206 has an instantaneous rail current I R In some embodiments, the power array controller 302 may be configured to adjust all of the subset of voltage regulators 320 to the instantaneous rail current I R In other words, in some embodiments, the instantaneous rail I R is 0 and the maximum rail current I RLM For example, the first power rail 206-1 (FIG. 3) may vary between 0.5I at any one time, and none of the subset of voltage regulators 320 may operate in standby mode. RLM Instantaneous rail current I, which is equal to R and the maximum rail current I RLM All eight voltage regulators are configured to provide 0.5I RLM 3. The voltage regulators 320 are enabled while being controlled by the power array controller 302 to collectively provide only a portion of the power capability of each voltage regulator 320. Thus, in this embodiment, only a portion of the power capability of each voltage regulator 320 is utilized. In some situations, the instantaneous rail current I R Relative to the rail voltage V R is the maximum rail current I RLM Relative to the rail voltage V RThe power array controller 302 and / or the voltage regulator 320 may divide the first rail voltage error by the rail drift tolerance V RT The device is configured to maintain (e.g., limit or control) within

[0048] Further, in some embodiments, a subset of the voltage regulators 320 may be configured to substantially equally distribute the instantaneous rail currents I R For example, each voltage regulator 320 is controlled to contribute a respective portion to the instantaneous rail current I R , which varies by less than 5% (or 10%, 20%, or other predefined margin) between voltage regulators 320 configured to provide power to the same power rail 206. Each voltage regulator 320 provides a respective rail current I provided by the respective voltage regulator 320. R , which is a portion of each rail current I provided by a separate voltage regulator 320 in the subset of voltage regulators 320. R In some implementations, the inter-regulator balancing circuit is internal to each voltage regulator 320 and balances the respective rail currents I provided by each voltage regulator 320 with at least another portion of the rail currents I. R , internally and independently of other voltage regulators configured to provide power to the same power rail 206, R Use it as negative feedback to control the part of

[0049] 4B , in some embodiments, one or more of the voltage regulators 320 are disabled and operate in a standby mode, e.g., within a subset of the voltage regulators 320, under the control of the operational enable signal 312, while the remainder of the subset of the voltage regulators 320 are controlled by the instantaneous rail current I R The one or more voltage regulators 320 may include a second number of voltage regulators 320, the second number being enabled to collectively provide an instantaneous rail current I R and the maximum regulator current I RGMor, equivalently, the instantaneous rail current I R and the maximum rail current I RLM For example, the subset of voltage regulators 320 has eight voltage regulators, and the second number is equal to a value between 1 and 7. R is the first range, e.g.

[0050]

number

[0051]

number

[0052] In some circumstances, when one or more voltage regulators 320 operate in standby mode, the instantaneous rail current I R The rail voltage V associated with R is the maximum rail current I RLM The rail voltage V associated withR The second rail voltage error differs from the first rail voltage error by the rail drift tolerance V RT The rail current I R When is provided with at least one redundant regulator (FIG. 4B) or without a redundant regulator (FIG. 4A), the second rail voltage error is smaller than the first rail voltage error, and the involvement of the redundant regulator(s) 320 allows for a more accurate rail voltage V to be obtained using more complex regulator control. R is provided.

[0053] As explained above, each power rail 206 corresponds to a respective first number of voltage regulators 320, and a respective second number of voltage regulators 320 are enabled at a time to operate in standby mode, and each second number has an instantaneous rail current I R The second number is dynamically varied according to the load information 314 and the power state policy configured to meet at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency). In one example, the second number of voltage regulators 320 is dynamically adjusted to maximize power conversion efficiency for driving the power rails. Stated differently, in some embodiments, at any time while the electronic device is powered on and providing power to one or more other semiconductor devices (e.g., SoC 102) via the power rails 206, a first subset of the voltage regulators 320 are in an operational mode and a second subset of the voltage regulators 320 are in a bypass mode, as specified by the control settings (e.g., operational enable signals 312) of the respective voltage regulators. The control settings are determined by the power array controller 302 based on the load information 314 and the power state policy.

[0054] During regulator regulation process 402, additional voltage regulators 320D and 320E are switched from a standby mode to an operational mode. The internal voltage regulator controllers of voltage regulators 320A-320E that drive power rail 206 regulate the instantaneous rail current I R The rail voltage V associated with R In order to correct for rail voltage errors in the power rail 206, the operating points of these voltage regulators 320A-320E are dynamically adjusted. This regulator adjustment process 402 is relatively slow due to the time constants of the loop control filters included in the voltage regulators 320A-320E. In particular, the control loops of the additional voltage regulators 320D and 320E switching between modes disrupt the operation of the remaining control loops of the voltage regulators 320A-320C that drove the power rail 206 in the operating mode, causing the rail voltage V R Therefore, in some embodiments, any of the redundant voltage regulators 320B-320H operating in standby mode may operate at the same operating point (e.g., rail voltage V R ) when the redundant voltage regulator(s) 320 join the active voltage regulator(s) 320 in driving the power rail 206. R ) in the power rail 206. Given the same operating point, each respective voltage regulator 320 associated with a power rail 206 is configured to transition from a standby mode to an operating mode and provide a predefined regulator current to the power rail 206 within a predefined period of time, for example, within 1, 2, 5, or 10 microseconds.

[0055] 5A is a block diagram of a voltage regulator 320, one of the voltage regulators in a field programmable array 330, according to some embodiments. In the field programmable array 330, a power rail 206 is connected to a rail voltage V Ris electrically coupled to a plurality of voltage regulators 320 configured to collectively provide. Each voltage regulator 320 includes an output interface 502, one or more drive paths 504, and a voltage regulator controller 506. The output interface 502 is electrically coupled to the power rail 206 to output a rail voltage V R One or more drive paths 504 are coupled in parallel between the voltage regulator controller 506 and the output interface 502, and each drive path 504 is configured to operate at an operating frequency in each phase to provide a respective path current I P to. Each respective path current I P is a part of the rail current I R introduced into the power rail 206. The voltage regulator controller 506 is configured to receive control settings (e.g., control value 310 and operation enable signal 312) from the power array controller 302 and generate a path control signal 508 for controlling one or more drive paths 504.

[0056] The voltage regulator 320 includes a feedback path 522 that couples the output interface 502 to the voltage regulator controller 506. That being said, the voltage regulator controller 506 has a feedback input 540 configured to receive the output voltage of the output interface 502. The voltage regulator controller 506 dynamically adjusts the path control signal 508 based on the output voltage of the output interface 502 and is configured to generate a rail voltage V R as defined by the control value 310. In particular, in some embodiments, the path control signal 508 defines a duty cycle that is dynamically adjusted by the voltage regulator controller 506 according to a comparison of the output voltage of the output interface 502 with the rail voltage V R defined by the control value 310.

[0057] In some embodiments, the voltage regulator 320 includes a buck converter, i.e., a DC-DC switch mode converter, that operates based on an embedded switch. Each drive path 504 includes a switch component 510 and a pulse width modulation (PWM) driver 512. The PWM driver 512 is coupled between the voltage regulator controller 506 and the switch component 510. The PWM driver 512 receives a periodic signal 514 (e.g., having a sinusoidal, square, triangular, or sawtooth waveform) and a path control signal 508 to control the switch component 510. In particular, the path control signal 508 defines a duty cycle, and the periodic signal 514 has a frequency equal to an operating frequency of one or more drive paths 504. The PWM driver 512 is configured to modify the periodic signal 514 with the path control signal 508 to generate a switching signal 516. The switch component 510 is controlled by the switching signal 516 to be turned on and off according to the duty cycle at the operating frequency. The switch component 510 is also coupled to the DC power supply interface 316 and provides a corresponding DC supply voltage V IN It is configured to be powered by a DC supply voltage V IN is thereby output to the switch output 518 of the switch component 510 at the operating frequency according to the duty cycle. R The rail voltage V R is output to the power rail 206 via the output interface 502. In some implementations, the rail voltage V R is substantially constant (e.g., has an output ripple voltage less than the ripple tolerance) and the DC supply voltage V IN and has an average magnitude equal to the product of the duty cycle and the conversion efficiency of the switch component 510.

[0058] 5B is a block diagram of a voltage regulator 320 that further includes a bypass unit 528 internal to the voltage regulator 320. In some embodiments, each individual voltage regulator 320 uses the bypass unit 528 to control the current output independently of any other voltage regulators 320 configured to drive the same power rail 206. The bypass unit 528 controls the rail current I R 3 , is used to enable a standby mode in which the power rails 206 are disabled from contributing to the standby mode. The standby mode is optionally applied when a voltage regulator 320 (e.g., 320E of FIG. 3 ) is applied to drive a power rail 206 or when a voltage regulator 320 (e.g., 320RA-320RD of FIG. 3 ) is not applied to drive any of the power rails 206. The bypass unit 528 is coupled to one or more drive paths 504 and to the voltage regulator controller 506, and configured to provide a dummy load component (e.g., including a passive RC filter or an active filter) in place of a load coupled to the power rails 206 when the voltage regulator 320 is in the standby mode.

[0059] In the standby mode, the bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the input of the voltage regulator controller 506, thereby allowing the voltage regulator 320 to reduce the respective rail current I R5B, a first switch 530A is inserted in the interconnect carrying the switching signal 516 in each drive path 504 and blocks it, and a switch 530B is inserted in the feedback path 522 and blocks it. In some implementations, each of the switches 530A and 530B includes a multiplexer and is controlled by an operation enable signal 312 received by the voltage regulator 320. The bypass unit 528 is coupled between the switch 530A and the switch 530B of each drive path 504 and is configured to intercept the switching signal 516 and isolate the power rail 206 and the feedback path 522 from the voltage regulator controller 506. Thus, the bypass unit 528 enables the auxiliary path 532 to bypass the feedback path 522 in the standby mode. An example of an implementation of the bypass unit 528 is shown in FIG. 6, described below.

[0060] FIG. 6 is a circuit diagram of a voltage regulator 320 having an auxiliary loop 602 for facilitating a fast transition between operation of the voltage regulator in a bypass mode and operation of the voltage regulator in an active mode, according to some embodiments. A voltage regulator controller 506 is coupled to each of the drive paths 504A-504B and provides a path control signal 508 thereto. A feedback path 522 connects the output interface 502 of the drive paths 504A-504B to a feedback input 540 of the voltage regulator controller 506. In some embodiments, the voltage regulator controller 506 includes a digital-to-analog converter (DAC) 608, an error amplifier 610, and an amplifier feedback circuit and is configured to enable pulse width modulation for the drive paths 504A-504B. The control value 310 is applied by the DAC 608 to generate a reference voltage (e.g., reference voltage 704, FIG. 7) that is received at an input of the error amplifier 610. The amplifier feedback circuit and feedback path 522 adjust the rail voltage V output at the output interface 502 to match the reference voltage. RIn particular, the path control signal 508 dynamically controls the rail voltage V R In some circumstances, the power array controller 302 also controls the duty cycle of the drive paths 504A-504B to match the respective rail voltages V R and the respective rail currents I R and an operation enable signal 312 is provided to each voltage regulator 320 to enable it to generate an error amplifier 610 and an DAC 608. In some embodiments, the operation enable signal 312 is optionally applied to control (e.g., enable and disable) the error amplifier 610 and / or the DAC 608, thereby disabling the entire voltage regulator 320 when the voltage regulator 320 is a redundant voltage regulator (e.g., 320RA-320RD in FIG. 3) that is not associated with any power rail 206.

[0061] As explained above, voltage regulator 320 may be configured to supply power to any of power rails 206 when voltage regulator 320 (e.g., 320RA-320RD) is not enabled to supply power to any of power rails 206, or when voltage regulator 320 (e.g., 320H in FIG. 4B) is coupled to a power rail 206 but does not supply a corresponding rail current I R5. In some embodiments, regardless of whether the voltage regulator 320 is coupled to any power rail 206, the voltage regulator 320 includes one or more drive paths 504 and a bypass unit 528. A voltage regulator controller 506 of the voltage regulator 320 has an output 508 coupled to the one or more drive paths 504 and a feedback input 540 coupled to the output interface 502 by a feedback path 522. The bypass unit 528 is coupled to the one or more drive paths 504 and the voltage regulator controller 506 and configured to provide a dummy load component 604. In the standby mode, when the bypass unit 528 is enabled, an auxiliary loop 602 is formed, bypassing the feedback path 522 from the output interface 502 to the input of the voltage regulator controller 506 and driving the dummy load component 604 with one or more switching components 606. Thus, the auxiliary loop 602 includes a bypass unit 528 such that in standby mode, the voltage regulator 320 reduces the corresponding rail current I R 5. When the auxiliary loop 602 is enabled, the feedback path 522 is disabled because the voltage regulator 320 is in standby mode.

[0062] In particular, in the standby mode, the bypass unit 528 is enabled to bypass the switch component 510 and the passive load component 520 of each drive path 504. Each drive path 504 further includes a multiplexer 530A coupled to the PWM driver 512, the switch component 510, and the bypass unit 528. The multiplexer 530A is configured to select the bypass unit 528, deselect the switch component 510, and electrically couple the PWM driver 512 to the bypass unit 528 in the standby mode. The voltage regulator 320 further includes a multiplexer 530B coupled between the feedback input 540 of the voltage regulator controller 506 and the output interface 502. The multiplexer 530B is configured to operate simultaneously with the multiplexer 530A of each drive path 504 to select the bypass unit 538 and deselect the output interface 502 for the input of the voltage regulator controller 506. In some embodiments, the operational enable signal 312 is used to simultaneously control the multiplexers 530A and 530B to enable the standby mode. By these means, in the standby mode, the switch components 510 and the passive load components 520 of each drive path 504 are skipped by the bypass unit 528, while the voltage regulator controller 506 and the PWM driver 512 of each drive path 504 continue to operate with the dummy load components 604 and switching components 606 in the bypass unit 528.

[0063] In summary, when the voltage regulator 320 is in standby mode, the auxiliary loop 602 is formed (or enabled) to isolate the output interface 502 without completely shutting down the voltage regulator 320. The voltage regulator controller 506 and the PWM driver 512 of the drive path 504 remain operational in standby mode, allowing the voltage regulator 320 to wake up quickly and maintain a desirable transient response time when it recovers from standby mode and resumes operation in operational mode. For example, in some circumstances, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 may operate at the same operating point (e.g., the rail voltage V at the feedback input 540) in both standby mode and operational mode. R ) to enable quick switchover to the operating mode. Moreover, the switching components 510 of the drive path 504 are isolated and disabled, and the dummy load components 604 and switching components 606 are designed to consume less power than the switching components 510 and load components 520 of the drive path 504. In one embodiment, the voltage regulator 320 drives the power rail 206 with a rail current of 1.5 A in the operating mode and consumes less than 100 mA while driving the dummy load components 604 and switching components 606 in the standby mode, thereby effectively saving the power consumption of the voltage regulator 320 in the standby mode.

[0064] Conversely, in some embodiments or circumstances, a respective voltage regulator 320 (e.g., any of voltage regulators 320RA-320RD in FIG. 3) may not be assigned to drive any power rail 206 and may be shut down entirely, or operate in a standby mode. In the standby mode, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 are operational, and the bypass unit 528 is enabled to bypass the switching components 510 and load components 520 of the drive path 504. When coupled to a power rail 206, such a redundant voltage regulator 320 may, upon transition from the standby mode to the operational mode, reduce the rail voltage V R and the corresponding rail current I R However, when a voltage regulator 320 is shut down, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 are disabled under the control of the operational enable signal 312. When coupled to a power rail 206, such a redundant voltage regulator 320 can contribute current quickly (e.g., with a transient response time) to the corresponding rail current I of the power rail 206. R The voltage regulator 320 must be restarted when transitioning from standby mode to operational mode before it can contribute to the load. Although the restart process is often slow and compromises the relatively long transient response time when the voltage regulator 320 recovers from a completely shut down condition, the application of the bypass unit 528 with the operational voltage regulator controller 506 and PWM driver 512 allows for both fast mode switching and low power consumption.

[0065] 7 is a circuit diagram of an example voltage regulator 320 with a filter-based auxiliary loop 602, according to some embodiments. A compensator 702 is coupled to a drive path 504 and provides a path control signal 508 thereto. A feedback path 522 connects an output interface 502 of the voltage regulator 320 to a feedback input 540 of the compensator 702. The compensator 702 is coupled to a DAC 608 and configured to enable pulse width modulation of the drive path 504. A control value 310 is applied by the DAC 608 to generate a reference voltage 704 that is received at a reference input of the compensator 702. The compensator 702 generates a rail voltage V R to match the reference voltage 704 output by the DAC 608. In particular, the path control signal 508 dynamically controls the rail voltage V R and a reference voltage 704. In some circumstances, the power array controller 302 also controls the duty cycle of the drive path 504 to match the respective rail voltage V R and the respective rail currents I R To enable generating the feedback loop 602, an operation enable signal 312 is provided to each voltage regulator 320, which controls a switch 530 to enable one of a standby mode and an operation mode for the respective voltage regulator 320. In some embodiments, the compensator 702 is one of a Type II compensator and a Type III compensator. In some embodiments, a Type III compensator is used in implementations where a phase margin that exceeds a threshold phase margin is required to keep both the feedback loop corresponding to the feedback path 522 and the auxiliary loop 602 stable, for example.

[0066] The switch component 510 of the drive path 504 includes an upper switching transistor 706A and a lower switching transistor 706B. The upper switching transistor 706A is coupled to a DC supply voltage V IN202 and the passive load component 520 and is controlled by an upper level shifter 708A that receives and converts the switching signal 516 generated by the PWM driver 512. The lower switching transistor 706B is coupled between a low DC supply voltage (e.g., ground, sometimes referred to as circuit ground) and the passive load component 520 and is controlled by a lower level shifter 708B that receives and converts the switching signal 516 generated by the PWM driver 512.

[0067] Voltage regulator 320 further includes a bypass unit 528 coupled to switches 530A and 530B at the input and output of bypass unit 528. Switch 530A' is inserted in the interconnection carrying switching signal 516 in drive path 504 to interrupt it, and switch 530A' is inserted in feedback path 522 to interrupt it. Bypass unit 528 is coupled in parallel to switch component 510 and passive load component 520 of drive path 504 via switches 530A, 530A', 530B, and 530B'. Switches 530A and 530A' are two separate switches, optionally coupled together or combined into a single-input, two-output multiplexer. Switches 530B and 530B' are two separate switches, optionally coupled together or combined into a two-input, one-output multiplexer. In the standby mode, switches 530A and 530B are enabled and switches 530A′ and 530B′ are disabled such that auxiliary path 532 is enabled to bypass feedback path 522 from output interface 502 to the feedback input of compensator 702. Thus, voltage regulator 320 regulates the rail current I R In the operational mode, switches 530A′ and 530B′ are enabled and switches 530A and 530B are disabled, thereby disabling auxiliary path 532, and switch component 510 and passive load component 520 are enabled to supply rail voltage V Rto the power rail 206. Each of the switches 530A, 530A', 530B, and 530B' is controlled by an operational enable signal 312 or its complement.

[0068] The bypass unit 528 includes a bypass switching component 606 having an upper switching transistor 714A and a lower switching transistor 714B. The upper switching transistor 714A is coupled to a DC supply voltage V IN 202 and the dummy load component 604, and is controlled by an upper level shifter 716A that receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. A lower switching transistor 714B is coupled between a low DC supply voltage (e.g., ground) and the dummy load component 604, and is controlled by a lower level shifter 716B that receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. In some embodiments not shown, the dummy load component 604 includes an inductor-capacitor (LC) tank. In some embodiments, the dummy load component 604 includes an active filter 720 to mimic the LC tank. The active filter 720 is coupled to a bypass output 722 of the bypass unit 528 and includes an operational amplifier and passive feedback components. In one example, the active filter 720 is a second order Sallen-Key filter. By these means, the auxiliary loop 602 is established based on a replicated power stage and active filter 720 , allowing closed-loop control of the voltage regulator 320 without involving the output interface 502 of the voltage regulator 320 .

[0069] In the operating mode, switches 530A and 530B are disabled and switches 530A′ and 530B′ are enabled. The control loop control is formed by the feedback path 522 from the output interface 502 to the feedback input of the compensator 702. The compensator 702 receives the rail voltage V R7. In the standby mode, the path control signal 508 is configured to replicate the power stage while scaling down the power stage to reduce power consumption. When driven by the switching signal 516, the active filter 720 can serve the purpose of scaling down the power stage to save power consumption. In particular, when the reference voltage 704 is given, the output voltages at the output interface 502 and the bypass output 722 are low-pass filtered by the compensator 702.

[0070] In some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in the standby mode is the rail voltage V R Alternatively, in some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in standby mode is substantially equal to the rail voltage V R and less than the threshold voltage difference, V R In some embodiments, the output interface 502 and the bypass output 722 of the voltage regulator 320 are located in close physical proximity to one another on the PMIC die 118. By these means, when the standby mode is changed to the operational mode, the voltage regulator 320 will achieve a predetermined regulator current I within a predetermined period of time (e.g., within 10 microseconds). R and rail voltage V R may be provided to the power rail 206.

[0071] 7, in some embodiments, the voltage regulator 320 includes only one drive path 504 and the bypass unit 528 includes only one bypass path 724 configured to bypass a portion of the one drive path 504 of the voltage regulator 320 in a standby mode. Alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504 and the bypass unit 528 includes multiple bypass paths 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320. The bypass paths 724 may have the same number of paths as the drive paths 504, or a different number of paths. Additionally and alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504 and the bypass unit 528 includes only one bypass path 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320 in a standby mode.

[0072] FIG. 8 is a circuit diagram of a plurality of voltage regulators 800 of a field programmable array of voltage regulators configured to drive power rail 206, according to some embodiments. The plurality of voltage regulators 800 includes a first voltage regulator 800A, a second voltage regulator 800B, and a third voltage regulator 800C. The voltage regulators 800A-800C are identical to one another. In this example, each voltage regulator 800 has the same circuit configuration as voltage regulator 320 described above with reference to FIG. 7. Specifically, each voltage regulator 800 includes a compensator 702 coupled to drive path 504 and a bypass path 724. Compensator 702 provides a path control signal 508 to drive path 504. Feedback path 522 connects output interface 502 coupled to drive path 504 to a feedback input 540 of compensator 702. A reference input of the compensator 702 is coupled to the DAC 608 and configured to receive a reference voltage 704 generated by the DAC 608 according to the control value 310. The compensator 702 is configured to convert the rail voltage V R to match the reference voltage 704 by enabling pulse width modulation of the drive path 504. In particular, the path control signal 508 controls the rail voltage V Rand a reference voltage 704. A bypass unit 528 is coupled on the bypass path 724, and a switch 530 is adapted to couple the bypass unit 528 in parallel with the PWM driver 512 and the compensator 702, thereby allowing a portion of the drive path 504, including the output interface 502 coupled to the power rail 206, to be bypassed in standby mode.

[0073] The output interfaces 502 of the voltage regulators 800A-800C are electrically coupled to the same power rail 206. However, each of the voltage regulators 800A-800C is independently controlled to drive the power rail 206 by a separate corresponding operation enable signal 312. In each voltage regulator 800, that voltage regulator's operation enable signal 312 controls a switch 530 to selectively enable only one of the feedback path 522 and the auxiliary path 532. Furthermore, the voltage regulators 800A-800C are connected to the same DC supply voltage V V , which is coupled to the switch component 510 and the bypass switching component 606. IN 202 and a low DC supply voltage (e.g., ground). In some embodiments, control values ​​310 of voltage regulators 800A-800C are identical to one another such that PWM drivers 512 of voltage regulators 800A-800C generate switching signals 516 having the same duty cycle in the different voltage regulators 800A-800C. Alternatively, in some embodiments, control values ​​310 of voltage regulators 800A-800C are independently controlled by operation enable signals 312 of voltage regulators 800A-800C.

[0074] In some circumstances, each of the first and second voltage regulators 800A and 800B operates to drive the power rail 206 in an operational mode. The feedback path 522 of each of the voltage regulators 800A and 800B is enabled between the output interface 502 and the feedback input 540 of their respective voltage regulators 800A and 800B in the operational mode. Conversely, the third voltage regulator 800C is electrically isolated from the power rail 206 in a standby mode in which the bypass unit 528 of the third voltage regulator 800C is enabled to bypass the feedback path 522 of the third voltage regulator 800C.

[0075] Alternatively, in some circumstances, each of first and second voltage regulators 800A-800B operates in a standby mode and bypass unit 528 of each voltage regulator 800A-800B is enabled to bypass feedback path 522 between output interface 502 and feedback input 540 of each voltage regulator 800A-800B. Conversely, third voltage regulator 800C operates in an operation mode in which feedback path 522 of voltage regulator 800C is enabled between output interface 502 and feedback input 540 of voltage regulator 800C in the operation mode. Alternatively and additionally, in some circumstances, all three voltage regulators 800A-880C operate in an operation mode in which feedback path 522 of each and every voltage regulator 800A-800C is enabled between output interface 502 and feedback input 540 of each voltage regulator 800A-800C.

[0076] Referring to FIG. 8, multiple voltage regulators 800 are configured to drive power rails 206 in a configurable manner. In some embodiments, each voltage regulator 800 is trimmed to minimize relative mismatch (e.g., offset error, gain error, and / or bandwidth error) with the other voltage regulators 800. An in-situ and parallel trimming mechanism is optionally applied to a fully integrated or assembled SoC 102 and PMIC 118 as shown in FIG. 1B. During in-situ and parallel trimming, each voltage regulator 800 enables its respective auxiliary loop 602 and disables its respective feedback path 522. By these means, the gain and offset error of each voltage regulator 800 is adjusted without causing power sequencing issues.

[0077] In some circumstances, multiple voltage regulators 800 are powered up. When a DC supply voltage (e.g., voltage 202) is first applied, the rail voltage V output by the feedback-based voltage regulator 800 is R The voltage difference between the voltage regulators 800 is large, pitting the voltage regulators 800 against each other and slowing down the power-up process of the voltage regulators 800. This is undesirable for rapid power state transitions. To avoid this condition, in some embodiments, the voltage regulators 800 coupled to the same power rail are pre-regulated with analog signal levels before being coupled to the power rail 206. Specifically, in some situations, the output interface 502 of the voltage regulator 800 is electrically isolated from the power rail 206 when the DC supply voltage is first applied. The standby mode and the operational mode are applied sequentially during the power-up process of each voltage regulator 800. The auxiliary loop 602 of each voltage regulator 800 is configured to operate in a standby state until the respective voltage regulator 800 is stabilized and outputs the rail voltage V at the bypass output 722. R , and feedback path 522 is subsequently enabled to couple each voltage regulator 800 to the power rail 206.

[0078] Alternatively, during a power-on operation, each voltage regulator 800 begins in an operational mode. The output voltage at output interface 502 of each voltage regulator 800 is monitored and compared to a threshold start voltage. For each voltage regulator 800, upon a determination that the output voltage exceeds the threshold start voltage, output interface 502 of voltage regulator 800 is electrically coupled to power rail 206. More specifically, in one embodiment, the threshold start voltage is 1V and the rail voltage V R is 1.8V. Voltage regulators 800A-800C are each powered up separately to avoid reaction between the regulators. Separately for each voltage regulator 800A-800C, upon determining that the output voltage reaches 1V at output interface 502 of that voltage regulator (e.g., 800A), output interface 502 of that voltage regulator (e.g., 800A) is electrically coupled to power rail 206, for example, using a switch coupled between output interface 502 of the voltage regulator (e.g., 800A) and power rail 206.

[0079] During power-on testing, the normal loop of each voltage regulator 800 on the PMIC 118 supplies the rail voltage V R 5. In some circumstances, one of the SoC 102 and the PMIC 118 may fail, causing a hardware fault condition. For field fault diagnosis, the fault location needs to be identified among the different voltage regulators 800 of the SoC 102 and the PMIC 118. Therefore, each of the SoC 102 and the voltage regulators 800 may be isolated and monitored separately, i.e., each SoC 102 or voltage regulator 800 can operate separately from any other SoC 102 or voltage regulator 800. In one embodiment, each voltage regulator 800 is isolated from the SoC 102 or other voltage regulator(s) 800 by entering a standby mode in which the bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the feedback input 540 of the compensator 702.

[0080] 9A is a circuit diagram of a portion 900, herein referred to as a multi-phase drive section 900, of a voltage regulator 320 having multiple drive paths 504, according to some embodiments, and FIG. 9B is a circuit diagram of another portion 920, herein referred to as a multi-phase bypass section 920, of a voltage regulator 320 having multiple bypass paths 724, according to some embodiments. The drive section 900 corresponds to a portion of two parallel drive paths 504A and 504B, and the bypass section 920 corresponds to two parallel bypass paths 724A and 724B. A portion of each drive path 504A or 504B of the drive section 900 and each bypass path 724 of the bypass section 920 are coupled in parallel to each other via a switch 530. Referring to FIG. 5B, the switch 530 selects either the drive section 900 or the bypass section 920 (e.g., one of them) to be electrically coupled to the PWM driver 512 and the feedback input 540 of the voltage regulator controller 506. In addition to the drive paths 504, the drive section 900 further includes an output interface 502 to which each drive path 504 is coupled. As shown in the complete voltage regulator schematic (e.g., FIG. 6 ), the output interface 502 is coupled to a feedback input 540 of a voltage regulator controller 506. The output interface 502 is also coupled to the power rail 206 and outputs the rail voltage V R and is configured to supply up to a predefined regulator current to the power rail 206.

[0081] Each drive path 504 (e.g., 504A or 504B) includes a switch component 510 (as shown in FIG. 6), a passive load component 520, and a PWM driver 512, and is arranged in parallel with other drive path(s) 504 within the same voltage regulator 320. Each drive path 504 has a respective path current I P to the power rail 206. Each of the path currents I P is the rail current I induced in the power rail 206 R9A . Drive section 900 ( FIG. 9A ) includes a first number of drive paths 504, and bypass section 920 ( FIG. 9B ) has a second number of bypass paths 724. Optionally, the second number is equal to the first number, such that each bypass path 724 is configured to bypass the switch component 510 and the passive load component 520 of a respective single drive path 504. The same PWM driver 512 that drives each single drive path 504 in the operating mode is configured to drive the corresponding bypass path 724 in the standby mode. Thus, in the standby mode, each bypass path 724 is configured to operate at the operating frequency during a respective phase, with different bypass paths 724, optionally, having different phases under the control of different PWM drivers 512.

[0082] In some embodiments, the bypass section 920 functions as the bypass unit 528 of the voltage regulator 320 (e.g., of FIG. 5B). In some embodiments, the bypass section 920 includes multiple bypass switching components (e.g., component 606 of FIG. 6, or components 714A and 714B of FIGS. 9B and 9D) and a single dummy load component 604 coupled between the multiple bypass switching components 606 and a bypass output 722 of the bypass unit 528. In this example, the dummy load component 604 includes an active filter 720 (e.g., a second order Sallen-Key filter), and multiple bypass paths 724 of the bypass unit 528 share the same active filter 720. From this perspective, the active filter 720 functions as a summing filter with multiple inputs from the parallel bypass switching components 606. 9B and 9D , the bypass unit 528 has multiple bypass paths 724, each having a separate bypass switch component 606 coupled to a separate active filter 720. The bypass outputs 722 of the different active filters 720 are, optionally, coupled to each other or isolated from each other.

[0083] Each bypass switching component 606 corresponds to a respective drive path 504 and is configured to bypass a portion of the corresponding respective drive path 504 in standby mode. Specifically, the switch component 510 of the drive path 504 is connected to a DC supply voltage V IN 202 and a lower switching transistor 706B configured to generate a current path to a low DC supply voltage (e.g., ground). The bypass switching component 606 of the bypass path 724 also includes a DC supply voltage V IN 202 and a lower switching transistor 714B configured to generate a low DC supply voltage (e.g., ground). In some embodiments, the upper switching transistor 714A of the bypass path 724 has a smaller transistor size than the upper switching transistor 706A of the drive path 504, and the lower switching transistor 714B of the bypass path 724 has a smaller transistor size than the lower switching transistor 706B of the drive path 504.

[0084] 9C and 9D are circuit diagrams of equivalent circuits 940 and 960 of the voltage regulator 320 operating in an operating mode and a bypass mode, respectively, according to some embodiments. The voltage regulator 320 is a two-phase buck converter. In the standby mode (FIG. 9D), the bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the feedback input 540 of the voltage regulator controller 506 (specifically, the compensator 702 therein), and the voltage regulator 320 does not source current to the power rail 206. The voltage regulator 320 has a first alternating current (AC) loop response in the standby mode. The first AC loop response has a first low frequency gain, a first cutoff frequency, and a first phase margin. In the operating mode (FIG. 9C), the bypass unit 528 is disabled to bypass the feedback path 522, and the voltage regulator 320 sources up to a default regulator current to the power rail 206. The voltage regulator 320 has a second AC loop response in the operating mode. The second AC loop response has a second low frequency gain, a second cutoff frequency, and a second phase margin. The first and second low frequency gains are substantially equal to each other and have a first gain difference, e.g., less than a first threshold. The first and second cutoff frequencies are substantially equal to each other and have a second frequency difference, e.g., less than a second threshold (e.g., 5 kHz). The first and second phase margins are substantially equal to each other and have a third phase margin difference, e.g., less than a third threshold (e.g., 5°).

[0085] The voltage regulator 320 applies an active filter 720 in the bypass unit 528. The active filter 720 provides an LC filter frequency response with a sufficient quality factor (e.g., greater than a quality factor threshold). In the standby mode, the auxiliary loop 602 is stabilized based on the phase margin and the gain margin. The phase margin is greater than a phase margin threshold and the gain margin is greater than a gain margin threshold. The active filter 720 includes an operational amplifier 902 that has sufficient driving capability for a large load (e.g., greater than a threshold load). In addition, in the operating mode, the bypass output 722 is isolated from the power rail 206 and therefore does not disturb the operation of the SoC 102 coupled to the power rail 206.

[0086] In some embodiments (e.g., of FIG. 9C ), a bypass unit 528 with one or more bypass paths 724 is applied to bypass the feedback path 522 in a buck converter. It should be noted that in some embodiments, a bypass unit 528 with one or more bypass paths 724 is similarly applied to bypass the feedback path 522 in a boost converter or a buck-boost converter.

[0087] 10 is a flow diagram of a method 1000 for driving a power rail 206 of an electronic device, according to some embodiments. In some embodiments, the electronic device includes an integrated semiconductor device 180 that vertically integrates a SoC 102 and a PMIC 118. In some embodiments, the electronic device includes a SoC 102 and a PMIC 118 mounted on a circuit board. The power rail 206 is provided by the PMIC 118 to drive the operation of the SoC 102. The electronic device is electrically coupled to the power rail 206 and receives a rail voltage V R and rail current I R to one of the power rails 206.

[0088] The electronic device is connected to a rail voltage V R and rail current I Rto the power rail 206 (1002). Each respective voltage regulator 320 has an output interface coupled to the power rail 206 and generates and provides a rail voltage V R , configured to supply at most a default regulator current to the power rail 206 (1004). The electronic device obtains (1006) a control setting for each respective voltage regulator 320 of the plurality of voltage regulators. The control setting of each respective voltage regulator 320 determines (1008) whether the respective voltage regulator 320 is a standby voltage regulator operating in a standby mode or an operational voltage regulator operating in an operational mode. Each standby voltage regulator 320 (e.g., regulator 800C of FIG. 8 ) enables (1010) a bypass unit 528 of the standby voltage regulator to bypass a feedback path 522 from the output interface 502 to an input 540 of the voltage regulator controller 506 such that the standby voltage regulator 320 does not supply current to the power rail 206. Each working voltage regulator 320 (e.g., regulator 800A or 800B in FIG. 8) disables (1012) bypass unit 528 from bypassing feedback path 522 so that the respective voltage regulator 320 supplies current to power rail 206.

[0089] In some embodiments, each respective voltage regulator 320 of the plurality of voltage regulators is configured to transition from a standby mode to an operating mode in accordance with a change in control setting and provide a predetermined regulator current to the power rail 206 within a predetermined period of time (e.g., within 1, 2, 5, or 10 microseconds). That said, in some circumstances, the predetermined period of time is within a range of 0.1 to 10 microseconds. If each voltage regulator 320 is not completely shut down in the standby mode, each voltage regulator 320 may quickly switch from the standby mode to the operating mode and provide a predetermined regulator current to the power rail 206.

[0090] In some embodiments, for each respective voltage regulator 320, the control settings include a control value 310 and an operation enable signal 312. The control value 310 is a rail voltage V R , and the operational enable signal 312 is configured to control each voltage regulator 320 to operate in either a standby mode, in which the bypass unit 528 is enabled to bypass the feedback path 522, or an operational mode, in which the bypass unit 528 is disabled to bypass the feedback path 522, thereby controlling the rail voltage V R 5. In relation to the voltage regulator controller 506 and the PWM driver 512, the operation enable signal 312 controls the total current injected into the power rail 206. Specifically, the operation enable signal 312 is applied to a control switch 530 to select one of the bypass units 528 and feedback paths 522 that are electrically coupled to the voltage regulator controller 506 and the PWM driver 512.

[0091] In some embodiments, each respective voltage regulator 320 includes one or more drive paths 504 coupled to an output interface 502 and is configured to operate at an operating frequency. A voltage regulator controller 506 of each voltage regulator 320 has an output 508 coupled to the one or more drive paths 504 and an input 540 coupled to the output interface 502 by a feedback path 522. The voltage regulator controller 506 is configured to control the one or more drive paths 504 and the bypass unit 528.

[0092] In some embodiments, the electronic device dynamically determines (1014) control settings for each respective voltage regulator 320 coupled to the power rail 206 based on the load conditions and power state policies associated with the power rail 206 in real time.

[0093] 5B , in some embodiments, each voltage regulator includes one or more drive paths 504 coupled to an output interface 502 and a voltage regulator controller 506. Each drive path 504 further includes a passive load component 520 coupled to the output interface 502, a driver 512 configured to receive a periodic signal 514 having an operating frequency and modulate the periodic signal 514 to provide a distinct phase in a switching signal 516, and a power switch component 510 coupled to the driver 512 and the passive load component 520. The power switch component 510 couples the passive load component 520 to one or more DC supply voltages V under control of the switching signal 516. IN 5. Additionally, in some embodiments, in the standby mode, the bypass unit 528 is enabled to bypass the power switch component 510 and the passive load component 520 of each drive path 504, and each drive path 504 further includes a first multiplexer 530A coupled to the driver 512, the power switch component 510, and the bypass unit 528. The first multiplexer 530A is configured to be controlled by a control setting (specifically, the operation enable signal 312) to enable the standby mode, i.e., to select access to the bypass unit 528 and to deselect access to the power switch component 510 electrically coupled to the driver 512 of the drive path 504. Additionally, each voltage regulator 320 further includes a second multiplexer 530B coupled to the input 540 of the voltage regulator controller 506, the output interface 502 of the power rail 206, and the bypass output 722 of the bypass unit 528. The second multiplexer 530B is configured to be controlled by a control setting (specifically, the operation enable signal 312) simultaneously with the first multiplexer 530A to enable the standby mode, i.e., to select the bypass output 722 of the bypass unit 528 and to deselect the output interface 502 of the power rail 206 that is coupled to the input 540 of the voltage regulator controller 506.

[0094] 6 and 7 , in some embodiments, the bypass unit 538 includes one or more bypass paths 724, each of which includes a respective bypass switching component 606 having a bypass switching transistor 714 of a first size. The switch component 510 of each driver path 504 includes a path switching transistor 706 having a second size. The second size of the path switching transistor 706 is larger than the first size of the bypass switching transistor 714.

[0095] In some embodiments, the multiple voltage regulators 320 are electrically coupled to a power array controller 506. The power array controller 506 is configured to determine a control setting for each voltage regulator 320 coupled to a power rail 206. Further, in some embodiments, for each voltage regulator 320, the control setting is dynamically adjusted in real-time by the power array controller 506 based on the load condition and a power state policy associated with the power rail 206. For example, a power state policy may require that the control setting maximize the power conversion efficiency of the multiple voltage regulators or that the quality factor of the voltage regulator 320 be greater than a quality factor threshold.

[0096] In various embodiments of the present application, the PMIC has a field programmable array of voltage regulators configured to provide rail voltages to multiple power rails. Each power rail is associated with multiple identical voltage regulators in the field programmable array, while in some embodiments the field programmable array further includes one or more redundant voltage regulators that are not used to drive any power rail. For each power rail, all of the identical voltage regulators may, in some circumstances, be coupled to drive the respective power rail to provide maximum drive capability, while a subset of standby voltage regulators may, in some other circumstances, be isolated from the respective power rail during the standby duration. During the standby duration, a standby mode is enabled to convert a voltage regulator that drives the power rail in the operational mode into a redundant or standby voltage regulator. In this standby mode, a bypass unit of the voltage regulator is enabled to bypass a feedback path from an output interface to an input of the voltage regulator controller, and the voltage regulator does not supply current to the corresponding power rail. The voltage regulator is not completely shut down in standby mode, but can transition to operational mode to provide a default regulator current to the power rail quickly (eg, within a few microseconds).

[0097] At a minimum, the following numbered clauses describe implementation examples. Clause 1: An electronic device comprising: a power rail configured to provide a rail voltage; and a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage, each of the plurality of voltage regulators including an output interface coupled to the power rail and configured to provide the rail voltage to supply up to a predetermined regulator current to the power rail; one or more drive paths coupled to the output interface and configured to operate at an operating frequency; a voltage regulator controller having an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path and configured to control the one or more drive paths; and a bypass unit coupled to the one or more drive paths and to the voltage regulator controller, wherein each respective voltage regulator of the plurality of voltage regulators is configured to operate according to a control setting in either a standby mode, where the bypass unit is enabled to bypass a feedback path from the output interface to an input of the voltage regulator controller and the respective voltage regulator does not supply current to the power rail, or an operating mode, where the bypass unit is disabled to bypass the feedback path and the respective voltage regulator supplies up to the predetermined regulator current to the power rail.

[0098] Clause 2: The electronic device of clause 1, wherein each respective voltage regulator of the plurality of voltage regulators is configured to transition from a standby mode to an operating mode in accordance with a change in control setting and provide a predetermined regulator current to the power rail within a predetermined period of time.

[0099] Clause 3: The electronic device of clause 1, wherein, for each respective voltage regulator, the control settings include a control value and an operation enable signal, the control value defining a magnitude of the rail voltage, and the operation enable signal is configured to control the respective voltage regulator to operate in either a standby mode in which the bypass unit is enabled to bypass the feedback path, or an operation mode in which the bypass unit is disabled to bypass the feedback path.

[0100] Clause 4: The electronic device of clause 1, wherein each of the one or more drive paths further comprises a passive load component coupled to the output interface, a driver configured to receive a periodic signal having an operating frequency and modulate the periodic signal to provide a distinct phase to a switching signal, and a power switching component coupled to the driver and the passive load component, the power switching component configured to couple the passive load component to one or more DC supply voltages under control of the switching signal.

[0101] Clause 5: The electronic device of clause 4, wherein in a standby mode, the bypass unit is enabled to bypass the power switching components and passive load components of each drive path, each of the one or more drive paths further comprising a first multiplexer coupled to the driver, the power switching components, and the bypass unit, the first multiplexer being configured to be controlled by a control setting to enable a standby mode in which the first multiplexer selects access to the bypass unit and deselects access to the power switching components electrically coupled to the driver of the drive path.

[0102] Clause 6: The electronic device of clause 5, wherein each respective voltage regulator further comprises a second multiplexer coupled to an input of the voltage regulator controller, an output interface of the power rail, and an output of the bypass unit, the second multiplexer configured to be controlled by a control setting simultaneously with the first multiplexer to enable a standby mode in which the second multiplexer selects the output of the bypass unit and deselects the output interface of the power rail coupled to the input of the voltage regulator controller.

[0103] Clause 7: The electronic device of clause 4, wherein the bypass unit includes one or more bypass paths, each bypass path including a respective bypass switching component having a bypass switching transistor of a first size, and the power switching component of each driver path has a path switching transistor having a second size, the second size of the path switching transistor being greater than the first size of the bypass switching transistor.

[0104] Clause 8: An electronic device described in any one of clauses 1 to 7, wherein a plurality of voltage regulators are electrically coupled to a power array controller, the power array controller being configured to determine control settings for each voltage regulator coupled to a power rail.

[0105] Clause 9: The electronic device of clause 8, wherein for each voltage regulator, the control settings are dynamically and real-time adjusted by the power array controller based on load conditions and power state policies associated with the power rail.

[0106] Clause 10: An electronic device described in any one of clauses 1 to 6, wherein the bypass unit includes one or more bypass paths, each bypass path having a respective bypass switching component and a respective dummy load component coupled between the bypass switching component and an output of the bypass unit, and each bypass path is configured to bypass a respective drive path of the feedback path in standby mode.

[0107] Clause 11: The electronic device of clause 10, wherein for each bypass path, the respective dummy load component includes an active filter.

[0108] Clause 12: The electronic device of clause 11, wherein the active filter is a second-order Sallen-Key filter.

[0109] Clause 13: An electronic device as described in any one of clauses 1 to 12, wherein for each respective voltage regulator, the bypass unit is configured to be electrically isolated from the power rail in standby mode, to output a rail voltage in standby mode, and to provide the rail voltage to an input of the voltage regulator controller, such that when the standby mode is changed to an operating mode, each voltage regulator is capable of providing a predetermined regulator current to the power rail within a predetermined period of time.

[0110] Clause 14: The electronic device of clause 1, wherein the bypass unit includes one or more bypass switching components and a dummy load component coupled between the one or more bypass switching components and an output of the bypass unit, each bypass switching component being coupled to a respective drive path in standby mode.

[0111] Clause 15: The electronic device of clause 14, wherein the dummy load components include one of an active filter, the active filter being a Sallen-Key filter.

[0112] Clause 16: The electronic device of any one of clauses 1 to 15, wherein the multiple voltage regulators include a first voltage regulator, a second voltage regulator, and a third voltage regulator, each of the first and second voltage regulators operating to drive a power rail in an operation mode, a feedback path of each voltage regulator being enabled between an output interface and an input of each voltage regulator in the operation mode, and the third voltage regulator being electrically isolated from the power rail in a standby mode in which a bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator.

[0113] Clause 17: An electronic device according to any one of clauses 1 to 16, wherein the multiple voltage regulators coupled to the power rail are identical to each other.

[0114] Clause 18: The electronic device of any one of clauses 1 to 17, wherein each voltage regulator has a first alternating current (AC) loop response in a standby mode, the first AC loop response having a first low frequency gain, a first cut-off frequency, and a first phase margin, each voltage regulator has a second AC loop response in an operating mode, the second AC loop response having a second low frequency gain, a second cut-off frequency, and a second phase margin, a first difference between the first low frequency gain and the second low frequency gain is less than a first threshold, a second difference between the first cut-off frequency and the second cut-off frequency is less than a second threshold, and a third difference between the first phase margin and the second phase margin is less than a third threshold.

[0115] Clause 19: A method for driving a power rail, in an electronic device having a plurality of voltage regulators electrically coupled to the power rail, generating a rail voltage and a rail current to drive the power rail, wherein each respective voltage regulator has an output interface coupled to the power rail and is configured to provide the rail voltage and supply up to a default regulator current to the power rail when the respective voltage regulator is in an operational mode; obtaining control settings for each respective voltage regulator of the plurality of voltage regulators, the control settings for each respective voltage regulator determining whether the respective voltage regulator is a standby voltage regulator operating in a standby mode or an operational voltage regulator operating in an operational mode; enabling, at each standby voltage regulator, a bypass unit of the standby voltage regulator to bypass a feedback path from the output interface to an input of the voltage regulator controller such that the standby voltage regulator does not supply current to the power rail; and disabling, at each operational voltage regulator, the bypass unit from bypassing the feedback path such that the respective voltage regulator supplies current to the power rail.

[0116] Clause 20: The method of clause 19, wherein each respective voltage regulator includes one or more drive paths coupled to an output interface and configured to operate at an operating frequency, a voltage regulator controller of each voltage regulator has an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path and is configured to control the one or more drive paths, and a bypass unit is coupled to the one or more drive paths and the voltage regulator controller.

[0117] Clause 21: The method of clause 19, further comprising dynamically and in real-time determining control settings for each respective voltage regulator coupled to the power rail based on load conditions and power state policies associated with the power rail.

[0118] Clause 22: A non-transitory computer-readable storage medium storing one or more programs configured to be executed by an electronic device having a plurality of voltage regulators electrically coupled to a power rail, the one or more programs including instructions that, when executed by the electronic device, cause the electronic device to perform a method according to any one of clauses 19 to 22.

[0119] Clause 23: An apparatus for driving a power rail in an electronic device having a plurality of voltage regulators electrically coupled to the power rail, the apparatus comprising at least one means for performing the method of any one of clauses 19 to 22.

[0120] The above description has been provided in terms of specific implementations. However, the above illustrative description is not intended to be exhaustive or to be limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The implementations have been chosen and described to best explain the disclosed principles and their practical applications, thereby enabling others to best utilize the present disclosure and various implementations with various modifications suited to the particular uses contemplated.

[0121] The terms used in the description of the various described implementations herein are merely for the purpose of describing the particular implementations and are not intended to be limiting. The singular forms "a," "an," and "the," used in the description of the various described implementations and in the appended claims, are intended to include the plurals unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will further be understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will further be understood that terms such as "first," "second," and the like, may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0122] As used herein, the term "if" is interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" or "following a determination that," optionally depending on the context. Similarly, the phrase "if determined to be" or "if a 'stated condition or event' is detected" is interpreted to mean "upon determining" or "in response to determining" or "upon detecting a 'stated condition or event'" or "in response to detecting a 'stated condition or event'" or "following a determination that a 'stated condition or event' is detected," optionally depending on the context.

[0123] Although various figures depict some logical stages in a particular order, stages that are not order dependent may be reordered and other stages may be combined or split. While some reorderings or other groupings are specifically mentioned, others will be apparent to those of ordinary skill in the art, and thus the ordering and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that the stages may be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. An electronic device, comprising: A power rail configured to provide a rail voltage; A plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage, each of the plurality of voltage regulators comprising: An output interface coupled to the power rail and configured to provide the rail voltage and supply a maximum of a predetermined regulator current to the power rail; One or more drive paths coupled to the output interface and configured to operate at an operating frequency, each of the one or more drive paths comprising: A passive load component coupled to the output interface; A driver configured to receive a periodic signal having an operating frequency, modulate the periodic signal, and provide a separate phase to a switching signal; A power switching component coupled to the driver and the passive load component and configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal; One or more drive circuits comprising the foregoing; A voltage regulator controller having an input coupled to the output interface by an output and feedback path coupled to the one or more drive paths and configured to control the one or more drive paths; A bypass unit coupled to the one or more drive paths and the voltage regulator controller; A plurality of voltage regulators including the foregoing; Wherein each voltage regulator of the plurality of voltage regulators is configured to operate in either a standby mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller and to bypass the power switching component and the passive load component of each drive path, and in which each voltage regulator does not supply current to the power rail, or an operating mode in which the bypass unit is disabled to bypass the feedback path and to bypass the power switching component and the passive load component of each drive path, and in which each voltage regulator supplies a maximum of the predetermined regulator current to the power rail. An electronic device.

2. ​ The electronic device according to claim 1, wherein each of the plurality of voltage regulators is configured to transition from the standby mode to the operating mode in accordance with a change in the control setting and provide the predetermined regulator current to the power rail within a predetermined period.

3. For each voltage regulator, the control setting includes a control value and an operation enable signal, the control value defines the magnitude of the rail voltage, and the operation enable signal is configured to control each of the voltage regulators to operate in either the standby mode in which the bypass unit is enabled to bypass the feedback path or the operating mode in which the bypass unit is disabled to bypass the feedback path. The electronic device according to claim 1.

4. Each of the one or more drive paths further includes a first multiplexer coupled to the driver, the power switching component, and the bypass unit, and the first multiplexer is configured to be controlled by the control setting to enable the standby mode in which the first multiplexer selects access to the bypass unit and deselects access to the power switching component electrically coupled to the driver of the drive path. Each voltage regulator further includes a second multiplexer coupled to the input of the voltage regulator controller, the output interface of the power rail, and the output of the bypass unit, and the second multiplexer is configured to be controlled by the control setting to enable the standby mode in which the second multiplexer selects the output of the bypass unit and deselects the output interface of the power rail coupled to the input of the voltage regulator controller, in parallel with the first multiplexer. The electronic device according to claim 1.

5. The bypass unit includes one or more bypass paths, each bypass path including a respective bypass switching component having a bypass switching transistor of a first size. The power switching component of each driver path has a path switching transistor having a second size. The second size of the path switching transistor is larger than the first size of the bypass switching transistor. The electronic device according to claim 1.

6. The plurality of voltage regulators are electrically coupled to a power array controller configured to determine the control settings of each voltage regulator coupled to the power rail. For each voltage regulator, the control settings are adjusted dynamically and in real time by the power array controller based on a load state and a power state policy associated with the power rail, for the electronic device according to claim 1.

7. The bypass unit includes one or more bypass paths, each bypass path having a respective bypass switching component and a respective dummy load component coupled between the bypass switching component and the output of the bypass unit, each bypass path being configured to bypass a respective drive path of the feedback path in the standby mode. For each bypass path, the respective dummy load component includes an active filter. The active filter is a second-order Sallen-Key filter, for the electronic device according to claim 1.

8. For each voltage regulator, the bypass unit is electrically isolated from the power rail in the standby mode, outputs the rail voltage in the standby mode, and is configured to provide the rail voltage to the input of the voltage regulator controller, such that when the standby mode is changed to the operating mode, each voltage regulator is capable of providing the predetermined regulator current to the power rail within a predetermined period, for the electronic device according to claim 1.

9. The bypass unit includes one or more bypass switching components and a dummy load component coupled between the one or more bypass switching components and the output of the bypass unit. Each bypass switching component is coupled to a respective drive path in the standby mode. The dummy load component includes one of the active filters, and the active filter is a Sallen-Key filter, for the electronic device according to claim 1.

10. The plurality of voltage regulators includes a first voltage regulator, a second voltage regulator, and a third voltage regulator, each of the first and second voltage regulators operates to drive the power rail in the operation mode, and the feedback path of each of the respective voltage regulators is enabled between the output interface and the input of each of the respective voltage regulators in the operation mode, the third voltage regulator is electrically isolated from the power rail in the standby mode in which the bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator, The electronic device according to claim 1.

11. The electronic device according to claim 1, wherein the plurality of voltage regulators coupled to the power rail are identical to each other.

12. Each voltage regulator has a first alternating current (AC) loop response in the standby mode, and the first AC loop response has a first low-frequency gain, a first cut-off frequency, and a first phase margin, each voltage regulator has a second AC loop response in the operation mode, and the second AC loop response has a second low-frequency gain, a second cut-off frequency, and a second phase margin, a first difference between the first low-frequency gain and the second low-frequency gain is less than a first threshold value, a second difference between the first cut-off frequency and the second cut-off frequency is less than a second threshold value, a third difference between the first phase margin and the second phase margin is less than a third threshold value, The electronic device according to claim 1.

13. A method of driving a power rail, an electronic device having a plurality of voltage regulators electrically coupled to the power rail, each of the plurality of voltage regulators including one or more drive paths configured to be coupled to an output interface and operate at an operating frequency, each of the one or more drive circuits including a passive load component coupled to the output interface, a driver configured to receive a periodic signal having an operating frequency and modulate the periodic signal to give a separate phase to a switching signal, A power switching component coupled to the driver and the passive load component, configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal. In an electronic device comprising Generating a rail voltage and a rail current to drive the power rail, each voltage regulator having an output interface coupled to the power rail, and configured to provide the rail voltage and supply a maximum predetermined regulator current to the power rail when each respective voltage regulator is in an operating mode. Obtaining control settings for each respective voltage regulator of the plurality of voltage regulators, wherein the control settings for each respective voltage regulator determine whether the respective voltage regulator is a standby voltage regulator operating in a standby mode or an operating voltage regulator operating in the operating mode. In each standby voltage regulator, enabling a bypass unit of the standby voltage regulator to bypass a feedback path from the output interface to the input of the voltage regulator controller and to bypass the power switching component and the passive load component of each drive path so that the standby voltage regulator does not supply current to the power rail. In each operating voltage regulator, disabling the bypass unit from bypassing the feedback path and bypassing the power switching component and the passive load component of each drive path so that each respective voltage regulator supplies current to the power rail. A method comprising According to claim 14, the voltage regulator controller of each respective voltage regulator has an output coupled to the one or more drive paths and an input coupled to the output interface by the feedback path, and is configured to control the one or more drive paths, and the bypass unit is coupled to the one or more drive paths and the voltage regulator controller. The method of claim 13, further comprising dynamically and in real time determining the control settings for each voltage regulator coupled to the power rail based on a load state and a power state policy associated with the power rail. **Claim 15** A computer-readable storage medium storing one or more programs configured to be executed by an electronic device having a plurality of voltage regulators electrically coupled to a power rail, the one or more programs including instructions that, when executed by the electronic device, cause the electronic device to perform the method of any one of claims 13 or 14.

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