Active filter and gyrator including cascaded inverters

Abstract

An aspect relates to a filter or first gyrator including a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method including applying an input signal to an input of a first of the set of cascaded inverters coupled to the set of one or more passive devices and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Yet another aspect relates to a transceiver including a filter having a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters and a mixer coupled to the filter.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 400,991, filed Aug. 12, 2021, and assigned to the assignee of this application, which is incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure generally relate to filters and gyrators for use in devices that communicate using wireless signals. [Background technology]

[0003]

[0003] Active filters and gyrators in devices that communicate with radio signals typically use operational amplifiers coupled to one or more passive devices such as capacitors, resistors, and inductors. An operational amplifier is typically a complex device. For example, an operational amplifier may include an input pair of differential field effect transistors (FETs), one or more current sources or sinks coupled between the sources of the differential FET pair and ground (or a negative voltage rail), passive and / or active output impedance components, a current mirror for controlling the current through the differential FET pair, a common mode voltage control circuit, and other circuits depending on the gain and / or other requirements. Thus, an operational amplifier typically has a relatively large circuit or integrated circuit (IC) footprint, may consume a significant amount of power, and may have a relatively narrow bandwidth characteristic. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005]

[0005] An aspect of the present disclosure relates to an apparatus including a filter or first gyrator including a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters.

[0006] Another aspect of the disclosure relates to a method that includes applying an input signal to an input of a first of a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal.

[0007] Another aspect of the present disclosure relates to a transceiver including a filter including a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters, and a mixer coupled to the filter.

[0008]

[0008] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0009] [Figure 1A] 1A-1C each show a schematic diagram of an exemplary set of cascaded inverters and a corresponding exemplary operational amplifier according to an aspect of the present disclosure. [Figure 1B] 1A-1C each show a schematic diagram of an example set of cascaded inverters and a corresponding example operational amplifier, in accordance with an aspect of the present disclosure. [Figure 2A]

[0010] 1A and 1B show schematic diagrams of an example Rauch filter having a set of cascaded inverters and a corresponding example Rauch filter having an operational amplifier, respectively, according to another aspect of the present disclosure. [Figure 2B] 1A and 1B show schematic diagrams of an example Rauch filter having a set of cascaded inverters and a corresponding example Rauch filter having an operational amplifier, respectively, according to another aspect of the present disclosure. [Figure 3A]

[0011] 1A and 1B show schematic diagrams of an example Tow-Thomas biquad filter having a set of cascaded inverters and a corresponding example Tow-Thomas biquad filter having an operational amplifier, respectively, according to another aspect of the present disclosure. [Figure 3B]1A and 1B show schematic diagrams of an example Tow-Thomas biquad filter having a set of cascaded inverters and a corresponding example Tow-Thomas biquad filter having an operational amplifier, respectively, according to another aspect of the present disclosure. [Figure 4A]

[0012] 1A-1C show schematic diagrams of an example Sallen-Key filter having a set of cascaded inverters and a corresponding example Sallen-Key filter having an operational amplifier, respectively, in accordance with another aspect of the present disclosure. [Figure 4B] 1A-1C show schematic diagrams of an example Sallen-Key filter having a set of cascaded inverters and a corresponding example Sallen-Key filter having an operational amplifier, respectively, in accordance with another aspect of the present disclosure. [Figure 5A]

[0013] 1A-1C each show a schematic diagram of an example gyrator having a set of cascaded inverters and a corresponding example shunt inductor, according to another aspect of the present disclosure. [Figure 5B] 1A-1C each show a schematic diagram of an example gyrator having a set of cascaded inverters and a corresponding example shunt inductor, according to another aspect of the present disclosure. [Figure 6A]

[0014] 10A-10C show schematic diagrams of another example gyrator having a set of cascaded inverters and a corresponding example shunt inductor-resistor, respectively, in accordance with another aspect of the present disclosure. [Figure 6B] 10A-10C show schematic diagrams of another example gyrator having a set of cascaded inverters and a corresponding example shunt inductor-resistor, respectively, in accordance with another aspect of the present disclosure. [Figure 7A]

[0015] 1 illustrates a schematic diagram of an example baseband filter having a set of cascaded inverters and alternative details of an inductor of the baseband filter in accordance with another aspect of the present disclosure. [Figure 7B] 1 illustrates a schematic diagram of an example baseband filter having a set of cascaded inverters and alternative details of an inductor of the baseband filter in accordance with another aspect of the present disclosure. [Figure 8]

[0016] 1 illustrates a block diagram of an exemplary receiver according to another aspect of the present disclosure. [Figure 9]

[0017] 2 illustrates a schematic diagram of an example power supply voltage generator for a set of cascaded inverters in accordance with another aspect of the present disclosure. [Figure 10]

[0018] 1 shows a schematic diagram of an exemplary transmitter according to another aspect of the present disclosure. [Figure 11]

[0019] 1 shows a schematic diagram of another exemplary transmitter according to another aspect of the present disclosure. [Figure 12]

[0020] 4 shows a flow chart diagram of an exemplary method for filtering a signal according to another aspect of the present disclosure. [Figure 13]

[0021] 2 illustrates a block diagram of an exemplary pseudo-differential filter in accordance with another aspect of the present disclosure. [Figure 14]

[0022] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0023] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0011]

[0024] A baseband (BB) filter is typically used at the output of a mixer in a receiver. The mixer receives a radio frequency (RF) signal previously received by at least one antenna (e.g., an antenna array) and amplified by a low noise amplifier (LNA). The mixer mixes the RF signal with a local oscillator (LO) signal to generate a mixed signal. The mixed signal includes a received signal of interest (a "target received signal") and an unwanted signal. For example, the unwanted signal may be, for example, an upper frequency component of the mixed signal, an external interference signal (sometimes called an RF jammer or blocker) near or within the passband of the target received signal, or a leakage of a transmission signal from an associated transmitter near or within the passband of the target received signal. The mixer may downconvert the RF signal to a signal at (or near) baseband, or may downconvert the RF signal to an intermediate frequency (IF) signal, and an additional mixer may downconvert the IF signal to a signal at (or near) baseband.

[0012]

[0025] A combination of a baseband (BB) filter and an analog-to-digital converter (ADC), followed by an anti-aliasing filter, has been used to substantially filter out the unwanted signals in a receiver. The BB filter filters out a portion of the unwanted signals. The ADC, which is typically operated at a sampling rate significantly higher than the Nyquist rate to provide significant frequency spacing between the image signals, and the anti-aliasing filter may be able to filter out most of the image and unwanted signals from the frequency band of the target received signal. However, the high sampling rate causes the ADC to consume significant power to spread the image signal in frequency to allow the BB filter and the anti-aliasing filter to effectively filter out the unwanted signals.

[0013]

[0026] FIN field effect transistors (FINFETs) are devices that provide efficient transconductance gain (g) that can be used in filters and gyrators, especially at scales below 14 nanometers (nm). m More specifically, a set of cascaded inverters implemented using FINFETs and tightly controlled by a complementary metal-oxide semiconductor (CMOS) process can provide wideband transconductance gain (g) sufficient for use in filters and gyrators. m In some examples, the FINFETs or transistors of the inverter may be biased near their transition regions of their voltage transfer characteristics (VTC), and the output voltage of the inverter may be a substantially linear function of its input voltage.

[0014]

[0027] Specific examples of inverters are described below. However, inverters other than those shown and / or described (and / or using process technologies and / or nodes other than those explicitly listed) may be implemented. For example, active load, passive load, and / or tuned load inverters may be used. In some examples, biasing may be used to stabilize one or more inverters. For example, biasing may be used in conjunction with a DC feedback loop to stabilize the operation of at least one of the inverters. In some examples, biasing may limit the gain from input to output to remain in a well-controlled region. Furthermore, cascaded inverters may allow the overall gain to be increased to a desired value or range. In some examples, coupling a resistor between the output of one stage and the input of another stage (e.g., between the output of an inverter that forms the output of a gyrator equivalent circuit and the input of an inverter that forms the input of a gyrator equivalent circuit, as described below) may stabilize the DC node of the output inverter. In some examples, a circuit such as that described with respect to FIG. 9 may be used to stabilize the DC node of the output inverter, for example, by reducing the transconductance gain (g) of the inverter (as described in more detail below). m ) may be used to control the gain of the inverter such that it is inversely proportional to its associated resistance. Additionally, other biasing schemes and / or loops (e.g., DC feedback loops) may be used.

[0015]

[0028] Thus, the operational amplifiers typically used in active filters and gyrators may be replaced by a set of cascaded inverters to achieve a desired filter frequency response, as provided by a filter, or impedance inversion, as provided by a gyrator, as described in more detail herein. A filter may use a gyrator to perform its filtering action.

[0016]

[0029] Although the above-mentioned examples of filters (and gyrators) have been described with reference to a (baseband) receiver application, it should be understood that the filters and gyrators described herein may be used in other applications, including transmitter applications.

[0017]

[0030] FIG. 1A illustrates a schematic diagram of an example set of cascaded inverters 100 according to an embodiment of the present disclosure. The set of cascaded inverters 100 receives an input signal S i The set of cascaded inverters 100 may include an input inverter 110-1 configured to receive a signal, which may be a downconverting mixer output signal in the case of a receiver application, or an input signal for an upconverting mixer in the case of a transmitter application. The set of cascaded inverters 100 may further include one or more intermediate inverters 110-2 to 110-N-1 between the input inverter 110-1 and the output inverter 110-N. It should be understood that the set of cascaded inverters 100 need not include an intermediate inverter, as in the case of a pair of cascaded inverters. In such an embodiment, the set of cascaded inverters 100 includes two inverters. In other embodiments, the set of cascaded inverters 100 includes three inverters as shown, or includes four or more inverters. As shown, the inverters are coupled in series, with the output of the input inverter 110-1 coupled to the input of the next inverter, which is coupled to the input of the subsequent inverter, and so on up to the output inverter 110-N.

[0018]

[0031] As described further herein, for filtering and / or gyrator applications, one or more other passive components (which may include, for example, one or more reactance and / or other passive components) may be coupled to the set of cascaded inverters 100. In this regard, the output inverters 110-N may be coupled to the output signal S obased on the application in which the set of cascaded inverters 100 is used, the input signal S i For example, to implement a Rauch filter, the filter may include at least one feedback capacitor and at least one resistor coupled to a set of cascaded inverters 100. To implement a Tow-Thomas biquad filter, the filter may include multiple sets of cascaded inverters, each set of cascaded inverters including at least one feedback capacitor, at least one feedback resistor, or both. To implement a Sallen-Key filter, the filter may include at least one capacitor and at least one resistor coupled to a set of cascaded inverters. To implement a gyrator, the gyrator may include at least one capacitor and / or at least one resistor coupled to a set of cascaded inverters. Sets of cascaded inverters may be used to implement more complex filters that may be used in receiver and / or transmitter applications.

[0019]

[0032] 1B illustrates a schematic diagram of an exemplary operational amplifier 150 according to another embodiment of the present disclosure. The operational amplifier 150 may be used in filter and gyrator applications. As an example, an input signal S i may be applied to a first input terminal (e.g., the negative input terminal as shown, or the positive input terminal) of operational amplifier 150. Operational amplifier 150 includes a second input terminal (e.g., the positive input terminal as shown, or the negative input terminal) that is often coupled to a voltage rail such as ground (or some reference voltage) in many filter applications. As with the set of cascaded inverters 100, one or more additional components may be coupled to operational amplifier 150 to implement a particular filter or gyrator application.

[0020]

[0033] In filtering and gyrator applications, the operational amplifier 150 provides the transconductance gain (g m In this regard, the operational amplifier 150 may act as a sine wave amplifier (S i The output signal S can be a filtered version of o As will be described in more detail below, the set of cascaded inverters 100 also provides a transconductance gain (g m ) component. Thus, the set of cascaded inverters 100 may be implemented in a filter or gyrator application in place of an operational amplifier 150. There are several advantages to using the set of cascaded inverters 100 rather than an operational amplifier 150 in a filtering or gyrator application.

[0021]

[0034] As mentioned above, the operational amplifier 150 is typically a complex circuit at the transistor level. For example, the operational amplifier 150 may include a differential FET pair, one or more current sources or sinks coupled between the sources of the differential FET pair and ground (or a negative voltage rail), passive and / or active output impedance components, a current mirror for controlling the current through the differential FET pair, and / or a common mode voltage control circuit, and other circuits depending on the gain and / or other requirements. In contrast, the set of cascaded inverters may be a set of CMOS FINFETs, which may be significantly less complex, require less circuitry or integrated circuit (IC) footprint, consume significantly less power, and have wider bandwidth characteristics. In some embodiments, the set of cascaded inverters may be single ended, having both single ended input and single ended output, with single ended signals being transferred between the inverters in the set. In some embodiments, the power supply coupled to the inverters may be lower than the power supply required by the operational amplifier. In some embodiments, the power supply coupled to the inverters is about 0.8V. The following is a summary of the transconductance (g) for filter and gyrator applications: m We describe several filter and gyrator applications that use a set of cascaded inverters as components.

[0022]

[0035] 2A illustrates a schematic diagram of an exemplary Rauch filter 200 according to another aspect of the present disclosure. The Rauch filter may be a low-pass filter that has characteristics that are less sensitive to component variations compared to other filters. The Rauch filter may include one zero pole and a complex pole to provide a steeper roll-off compared to a single-pole filter.

[0023]

[0036] In this example, the Rauch filter 200 includes a set of cascaded inverters 210-1 to 210-3 (e.g., three in this example, but may be configured with other numbers of cascaded inverters). The Rauch filter 200 is configured to receive an input signal S iThe Rauch filter 200 may further include a first resistor R1 coupled between an input (node) of the Rauch filter 200 (wherein a signal from the Rauch filter 200 may be received) and an input of the first cascaded inverter 210-1 of the set. The Rauch filter 200 may further include a feedback capacitor C connected between an output of the last cascaded inverter 210-3 of the set and an input of the first cascaded inverter 210-1. Additionally, the Rauch filter 200 may include a feedback resistor R2 connected between the output of the last cascaded inverter 210-3 and an input (node) of the Rauch filter 200. Thus, a first terminal of the first resistor R1 may be directly connected to the feedback resistor R2 (and the input of the Rauch filter 200), and a second terminal of the first resistor R1 may be directly connected to the feedback capacitor C (and the input of the first cascaded inverter 210-1).

[0024]

[0037] The output of the last inverter 210-3 is fed to the input signal S according to the filter frequency response of the Rauch filter 200. i The output signal S is a filtered version of o The filter frequency response of the Rauch filter 200 depends on the resistance values ​​of the input resistor R1 and the feedback resistor R2, and the capacitance of the feedback capacitor C. The Rauch filter 200 may also function as a transimpedance amplifier (TIA). In such a case, the input signal S i may be the input current and the output signal S o may be the output voltage. Furthermore, in this example, the number of cascaded inverters in the set is three, which is an odd number (this may also be characterized as the number of cascaded inverters between the first and last being an odd number). In this case, the feedback through feedback capacitance C and feedback resistor R2 is negative feedback due to cascaded inverting action.

[0025]

[0038] 2B illustrates a schematic diagram of an exemplary Rauch filter 250 according to another aspect of the present disclosure. In this example, the Rauch filter 250 is implemented using an operational amplifier 260. The Rauch filter 250 is i The Rauch filter 250 includes an input resistor R1 connected between the input (node) of the Rauch filter 250 (where the input is received) and the negative input terminal of the operational amplifier 260. The Rauch filter 250 includes a feedback capacitor C connected between the output and the negative input of the operational amplifier 260. Additionally, the Rauch filter 250 further includes a feedback resistor R2 connected between the output of the operational amplifier 260 and the input (node) of the Rauch filter 250. Although the resistors R1 and R2 and the capacitor C are identified as being identical in both filters 200 and 250, it should be understood that the resistance of the resistors R1 and R2 and the capacitance of the capacitor C may be different in both filters 200 and 250. This shall apply to all other comparisons of inverter-based filters to operational amplifier-based filters as described further herein. As explained, the set of cascaded inverters 210-1 to 210-3 may be significantly less complex than the operational amplifier 260, require less circuitry or IC footprint, consume significantly less power, and have wider bandwidth characteristics.

[0026]

[0039] 3A illustrates a schematic diagram of an exemplary Tow-Thomas biquad filter 300 according to another aspect of the present disclosure. The Tow-Thomas biquad filter 300 can be configured as a low-pass filter (LPF) and / or a band-pass filter (BPF). The Tow-Thomas biquad filter 300 can include a first output configured to generate a first output signal related to a band-pass filtered input signal and a second output configured to generate a second output signal related to a low-pass filtered input signal.

[0027]

[0040] More specifically, the Tow-Thomas biquad filter 300 includes a first filter stage 310 including an input resistor R0, a first set of cascaded inverters 312-1 to 312-3, a feedback capacitor C1, and a feedback resistor R1, both of which are coupled in parallel between the output of the last cascaded inverter 312-3 and the input of the first cascaded inverter 312-1. The input resistor R0 is connected to the input signal S i The output of the last cascaded inverter 312-3 is coupled between the input of the Tow-Thomas biquad filter 300 (wherein the input signal S is received) and the input of the first cascaded inverter 312-1. The output of the last cascaded inverter 312-3 is coupled between the input signal S i A first output signal S that may be related to o1 The first filter stage 310 is configured to generate a first output signal S o1 Based on the resistance and capacitance of resistors R0 and R1 and capacitor C1, an input signal S i may be configured to apply a band pass filter (BPF) frequency response to

[0028]

[0041] In this example, the Tow-Thomas biquad filter 300 includes a second filter stage 320 that includes an input resistor R2, a second set of cascaded inverters 322-1 to 322-3, and a feedback capacitor C2. The input resistor R2 is coupled between the output of the first filter stage 310 and the input of the first cascaded inverter 322-1 of the second filter stage 320. The second filter stage 320 thus receives at its input the output signal S from the first filter stage 310. o1 The second filter stage 320 is configured to receive the intermediate signal or the second output signal S. A feedback capacitor C2 is connected between the output of the last cascaded inverter 322-3 and the input of the first cascaded inverter 322-1. o2, the output signal S of the first filter stage 310 is filtered according to the resistance and capacitance of the input resistor R2 and the feedback capacitor C2 to generate o1 In other words, the signal S o2 may be applied to another device external to the Tow-Thomas biquad filter 300, in which case it is the second output signal. o2 may not be applied to another device, in which case it acts only as an intermediate signal for the Tow-Thomas biquad filter 300.

[0029]

[0042] Further according to this example, Tow-Thomas biquad filter 300 includes a third filter stage 330 including an input resistor R3, a third set of cascaded inverters 332-1 to 332-3, and a feedback resistor R4. Input resistor R3 is coupled between the output of second filter stage 320 and the input of a first cascaded inverter 332-1 of third filter stage 330. Thus, third filter stage 330 receives at its input the output signal S from second filter stage 320. o2 A feedback resistor R4 is connected between the output of the last cascaded inverter 332-3 and the input of the first cascaded inverter 332-1. The third filter stage 330 is configured to receive the second or third output signal S o3 The output signal S of the second filter stage 320 is adjusted according to the resistance values ​​of the input resistor R3 and the feedback resistor R4 to generate o2 The cascaded filter stages 310, 320, and 330 are configured to filter the second and / or third output signals S o3 Based on the resistance of resistors R0 to R4 and the capacitance of capacitors C1 to C2, an input signal S iA feedback resistor R5 is connected between the output of the last cascaded inverter 332-3 of the Tow-Thomas biquad filter 300 and the input of the first cascaded inverter 312-1.

[0030]

[0043] 3B illustrates a schematic diagram of an exemplary Tow-Thomas biquad filter 350 according to another aspect of the disclosure. In this example, Tow-Thomas biquad filter 350 includes three cascaded filter stages 360, 370, and 380 including operational amplifiers 365, 375, and 385 having resistors R0-R5 and capacitors C1-C2, as shown. As described, the first, second, and third sets of cascaded inverters 312-1-312-3, 322-1-322-3, and 332-1-332-3 may be significantly less complex, require less circuitry or IC footprint, consume significantly less power, and have wider bandwidth characteristics than the three operational amplifiers 365, 375, and 385 of Tow-Thomas biquad filter 350.

[0031]

[0044] FIG. 4A illustrates a schematic diagram of an exemplary Sallen-Key filter 400 according to another aspect of the present disclosure. The Sallen-Key filter 400 may be used to implement a second-order active filter operation. In particular, the Sallen-Key filter 400 includes a first input resistor R1, a second input resistor R2, an input capacitor C1, a set of cascaded inverters 410-1 to 410-4, a feedback capacitor C2, and a voltage divider including resistors R3 and R4. The first and second resistors R1 to R2 are connected to a resistor R1 (input signal S iA feedback capacitor C2 is connected between the output of the last cascaded inverter 410-4 of the set and the node n1. Resistors R3 and R4 are connected in series between the output of the last cascaded inverter 410-4 and a voltage rail (e.g., ground). A node n2 between resistors R3 and R4 is coupled to the output of the first inverter 410-1 of the set. An input capacitor C1 may be connected between node n1 (between resistors R1 and R2) and a voltage rail (e.g., ground). A feedback capacitor C2 is connected between the output of the last cascaded inverter 410-4 of the set and the node n1. Resistors R3 and R4 are connected in series between the output of the last cascaded inverter 410-4 and a voltage rail (e.g., ground). A node n2 between resistors R3 and R4 is coupled to the output of the first inverter 410-1 of the set.

[0032]

[0045] The output of the last cascaded inverter 410-4 is the output signal S o which is a filter frequency response of the Sallen-Key filter 400 that depends on the resistance of the resistors R1-R4 and the capacitance of the capacitors C1 and C2. i Since Sallen-Key filter 400 involves positive feedback via capacitor C2, the number of cascaded inverters in the set is four, but may be another even number (the number of cascaded inverters between the first and last may be characterized as being even or zero (0)). For stability purposes, the coupling of node n2 to the output of the first cascaded inverter 410-1 involves negative feedback since it spans an odd number (e.g., three) of cascaded inverters 410-2 through 410-4.

[0033]

[0046] In some embodiments, a set of cascaded inverters includes a configuration in which two inverters in the set are directly connected to each other with no other elements connected between them or to the node between them. For example, such a configuration is shown in FIG. 4A, where the output of inverter 410-2 is directly connected to the input of inverter 410-3. No other elements are connected between inverters 410-2 and 410-3, and no other elements are connected to the node or connection between these inverters. Meanwhile, the node between inverters 410-1 and 410-2 is connected to other elements (e.g., resistors R3 and R4).

[0034]

[0047] 4B illustrates a schematic diagram of an exemplary Sallen-Key filter 450 according to another aspect of the disclosure. In this example, Sallen-Key filter 450 includes an operational amplifier 460 including input resistors R1 and R2, an input capacitor C1, a feedback capacitor C2, and a voltage divider including resistors R3 and R4, as shown in FIG. 4B. As described, the set of cascaded inverters 410-1 through 410-4 may be significantly less complex, require less circuitry or IC footprint, consume significantly less power, and have wider bandwidth characteristics than operational amplifier 460 of Sallen-Key filter 450.

[0035]

[0048] FIG. 5A illustrates a schematic diagram of an exemplary gyrator 500 according to another embodiment of the disclosure. A gyrator may be used to invert the impedance of one or more passive devices. For example, a gyrator may be used to invert the impedance of a capacitor to create the impedance of an inductor. Conversely, a gyrator may be used to invert the impedance of an inductor to create the impedance of a capacitor. In this example, the gyrator 500 is configured to invert the impedance of a capacitor more generally to create the impedance of an inductor more generally. Because inductors are generally more difficult to implement in an IC and / or consume additional space, the gyrator 500 may be used in a filter to implement inductors as needed to achieve a desired frequency response of the filter.

[0036]

[0049] The gyrator 500 includes a set of cascaded inverters 512-1 to 512-3, a shunt capacitor C, and a conductive feedback path 514 (e.g., substantially zero (0) or negligible resistance) connecting the output of the last cascaded inverter 512-3 to the input of the first cascaded inverter 512-1. The capacitor C is connected between the output of the first cascaded inverter 512-1 and a voltage rail (e.g., ground). A signal may be applied to an input of the gyrator 500, for example, the input of the first cascaded inverter 512-1. Due to impedance inversion, the input sees the impedance of the shunt inductor L550, as shown in FIG. 5B.

[0037]

[0050] 6A illustrates a schematic diagram of another exemplary gyrator 600 according to another aspect of the disclosure. The gyrator 600 can be configured to implement the impedance of a resistive load inductor. As described further herein, an inductor in series with a capacitor between a signal node and a voltage rail (e.g., ground) can be used to create a relatively narrow frequency notch in the filter frequency response. To create a wider frequency notch in the filter frequency response, a capacitor can be used between the signal node and a voltage rail (e.g., ground), where the width is related to the resistance of the resistor.

[0038]

[0051] The gyrator 600 includes a set of cascaded inverters 612-1 to 612-3, a capacitor C, a resistor R, and a conductive feedback path 614 (e.g., substantially zero (0) or negligible resistance) connecting the output of the last cascaded inverter 612-3 to the input of the first cascaded inverter 612-1. The capacitor C and the resistor are coupled in series between the output of the first cascaded inverter 612-1 and a voltage rail (e.g., ground). A signal may be applied to the input of the gyrator 600, for example, the input of the first cascaded inverter 612-1. Due to impedance inversion, the input sees the impedance of a resistive load shunt inductor L650, as shown in FIG. 6B.

[0039]

[0052] 7A shows a schematic diagram of an example filter 700 according to another aspect of the present disclosure. The filter 700 may be used in baseband (BB) filtering or other applications. The filter 700 includes a first filter stage 710 cascaded with a second filter stage 720. An input signal S, which may be an input current, is i is applied to the input of the first filter stage 710. As described in more detail herein, the first filter stage 710 filters the input signal S i The second filter stage 720 performs a specific filtering operation on the filtered input signal S iis low-pass filtered (LPF) to produce the output signal S o The second filter stage 720 may be configured as a Rauch filter (as described above with reference to FIG. 2A) to generate the input current signal S i The output voltage signal S o In another embodiment, multiple filter stages having a current input and a voltage output may be coupled together via resistors to convert the voltage output from one stage to a current for input to a subsequent stage.

[0040]

[0053] The first filter stage 710 couples an input signal current source S between node n1 and a voltage rail (e.g., ground). i (Input signal S i The first filter stage 710 includes a shunt capacitor C0 coupled in parallel with a node n1 (representing a source of a current), a first resonator including a first capacitor C1 coupled in series with a first gyrator L1 (providing an inductive impedance) between a node n1 and a voltage rail (e.g., ground), a second resonator including a second capacitor C2 coupled in series with a second gyrator L2 (providing an inductive impedance) between the node n1 and the voltage rail (e.g., ground), and a third resonator including a third capacitor C1 coupled in series with a third gyrator L3 (providing an inductive impedance) between the node n1 and the voltage rail (e.g., ground). The first filter stage 710 includes a frequency response having three notches determined by the capacitances and inductances of C1-L1, C2-L2, and C3-L3.

[0041]

[0054] The second filter stage 720 includes an input resistor R1, a set of cascaded inverters 722-1 to 722-3 (e.g., three in this example, but may be configured with a different number of cascaded inverters as previously described), a feedback capacitor C4, and a feedback resistor R2. The first resistor R1 is connected between the output of the first filter stage 710 (node ​​n1) and the input of the first cascaded inverter 722-1 of the set. The feedback capacitor C4 is connected between the output of the last cascaded inverter 722-3 of the set and the input of the first cascaded inverter 722-1. The feedback resistor R2 is connected between the output of the last cascaded inverter 722-3 and the output of the first filter stage 710 (node ​​n1).

[0042]

[0055] The output of the last inverter 722-3 is a filter that is amplified by the input signal S according to the filter frequency responses of the cascaded first and second filter stages 710 and 720. i The output signal S is a filtered version of o For baseband filtering or other applications, the filter frequency response of the second filter stage 720 may provide a low pass filter that includes zeros (0) substantially at the edges of the passband of the signal of interest and a pole that provides a roll-off above the frequency of zero (0) to remove unwanted signals. The resistance of resistors R1-R2 and the capacitance of capacitor C4 may be set to achieve a desired filter frequency response of the second filter stage 720.

[0043]

[0056] As described, the first filter stage 710 may be configured to provide frequency notches at frequencies where jammers / blockers and transmitter (Tx) leakage to the receiver may occur. For example, such jammers / blockers and Tx leakage may be located in the roll-off portion of the filter frequency response of the second filter stage 720. If higher rejection of these jammers / blockers and Tx leakage is desired, the notches of the first filter stage 710 may be placed at the frequencies of these jammers / blockers and Tx leakage or at expected frequencies. Thus, the rejection of these jammers / blockers and Tx leakage is the cumulative rejection provided by the roll-off of the frequency response of the second filter stage 720 and the corresponding notches in the frequency response of the first filter stage 710. Although three notches (e.g., corresponding to capacitances and inductances of C1-L1, C2-L2, and C3-L3, respectively) are shown in Figure 7A, it will be understood that a greater number (e.g., four or more) or a lesser number (0-2) of notches may be implemented in filter 700. In some embodiments, multiple notch filters in series in the signal path (e.g., as shown in Figure 7A) may be used to implement a stopband.

[0044]

[0057] FIG. 7B shows a schematic diagram of two gyrators 750 and 760, each of which can replace any of the inductors L1, L2, and L3 of the first filter stage 710, according to another embodiment of the present disclosure.

[0045]

[0058] The gyrator 750 includes a set of cascaded inverters 752-1 through 752-3, a capacitor C5 connected between the output of the first cascaded inverter 752-1 and a voltage rail (e.g., ground), and a conductive feedback path 754 coupling the output of the last cascaded inverter 752-3 to the input of the first cascaded inverter 752-1. The gyrator 750, acting as an inductive element, may be configured with a series capacitor (e.g., C1, C2, or C3 of the first filter stage 710) to generate a higher Q or a relatively narrow frequency notch due to the substantial absence of a resistive load of the capacitor C5.

[0046]

[0059] The gyrator 760 includes a set of cascaded inverters 762-1 through 762-3, a capacitor C5 coupled in series with a resistor R between the output of the first cascaded inverter 762-1 and a voltage rail (e.g., ground), and a conductive feedback path 764 coupling the output of the last cascaded inverter 762-3 to the input of the first cascaded inverter 762-1. The gyrator 760 acting as an inductive element may be configured with a series capacitor (e.g., C1, C2, or C3 of the first filter stage 710) to generate a lower Q or a relatively wide frequency notch when the resistor R loads the capacitor C5. The frequency width of the notch may be controlled by the resistance value of the resistor R.

[0047]

[0060] In some embodiments, each of the inverters 752 or 762 are identical to one another. In some embodiments, each of the inverters 722 are identical to one another. In some embodiments, each of the inverters 752 or 762 are composed of transistors configured similarly to the transistors in each of the inverters 722. For example, each of the inverters 752 or 762 may include a PMOS transistor coupled to an NMOS transistor, and each of the inverters 722 may include a PMOS transistor coupled to an NMOS transistor. All of the PMOS transistors in the inverters 752 or 762 and 722 may have the same size and the same layout, and all of the NMOS transistors in the inverters 752 or 762 and 722 may have the same size and the same layout.

[0048]

[0061] 7A and 7B, the (baseband) filters described herein may be implemented using only inverters, capacitors, and resistors. For example, such filters may be implemented without operational amplifiers (and some elements thereof, such as current sources) and / or inductors.

[0049]

[0062] 8 shows a block diagram of an example receiver 800 according to another aspect of the present disclosure. The receiver 800 may be an application of one of the above-mentioned filters. The receiver 800 includes a mixer 810, a baseband (BB) filter 820, an in-band blocker 830, a bypass switching device SW, an analog-to-digital converter (ADC) 840, and a digital filter 850.

[0050]

[0063] The mixer 810 includes a first input configured to receive an RF signal and a second input configured to receive a local oscillator (LO) signal. The mixer 810 includes an output for providing a mixed signal. A baseband (BB) filter 820, which may be configured per filter 700 or any other filter previously described, is configured to substantially remove unwanted signals, including upper frequency components, out-of-band jammers / blockers, transmit signal leakage, etc., from the mixed signal generated by the mixer 810. In some embodiments, the receiver 800 comprises a cellular receiver, and the filter 820 is configured to remove unwanted signals to improve coexistence with a WiFi system or subsystem included in the device in which the receiver 800 is implemented. As previously described, the two-pole frequency response of the filter 820, including notches carefully placed in frequency to coincide with out-of-band jammers / blockers and transmit signal leakage, may result in substantial removal of unwanted signals from the mixed signal at the output of the mixer 810.

[0051]

[0064] The in-band blocker 830 may perform additional filtering to reduce unwanted signals that may be present within the passband of the received signal of interest. The in-band blocker 830 may be selectively bypassed using a bypass switching device SW coupled in parallel with the in-band blocker 830. The ADC 840 is a 1 / 2-channel 1 / 2-channel 1 / 4 ... s, the filtered signal at the output of the baseband filter 820 (when the bypass switching device SW is closed) or the output of the in-band blocker 830 (when the bypass switching device SW is open) is converted to a digital signal based on the sampling rate f s The requirement for the RX filter 820 may be relaxed and good isolation may be maintained at this frequency (e.g., if the filter 820 is configured as single-ended and not as pseudo-differential, as may be required in configurations including operational amplifiers). Furthermore, such operation of the baseband filter 820 may allow for a larger RX input signal in the presence of a jammer, for example, due to a reduced need to attenuate such input signal to account for the dynamic range of the jammer and the ADC 840. This may result in a better SNR under blocking and / or use of adjacent channel scenarios. The digital filter 850 may further remove high frequency noise and interference from the digital signal generated by the ADC 840 to generate an output baseband (BB) signal.

[0052]

[0065] FIG. 9 illustrates a schematic diagram of an example bias voltage generator 900 configured to generate a supply voltage Vdd_inv for the set of cascaded inverters described above, according to another aspect of the disclosure. An example inverter 910, which may be an example of any inverter shown in and / or described with respect to FIGS. 1A-7B, is shown receiving a supply voltage Vdd_inv from the bias voltage generator 900. The bias voltage generator 900 is configured to generate the supply voltage Vdd_inv to compensate for variations in the resistance of one or more resistors present in the aforementioned filter. In particular, the bias voltage generator 900 varies the supply voltage Vdd_inv to adjust the transconductance gain (g) of the cascaded inverters, which is inversely proportional to the resistance of one or more resistors present in the filter. m) can be varied. Thus, the variation in transconductance gain (gm) of the cascaded inverters compensates for the variation in resistance of resistors in the aforementioned filter with process and / or temperature.

[0053]

[0066] More specifically, the bias voltage generator 900 includes a bias voltage rail V bias1 The input / output amplifier includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) M1 and an n-channel metal oxide semiconductor field effect transistor (NMOS FET) M3 coupled in series between a differential bandgap voltage (V) and a lower voltage rail (e.g., ground). The PMOS FET M1 and the NMOS FET M3 include gates coupled to each other and configured to receive a first component of a voltage, the first component being a differential bandgap voltage kV as shown. bg where k is the Boltzmann constant. The PMOS FET M1 and the NMOS FET M3 include drains that are coupled together.

[0054]

[0067] Additionally, the bias voltage generator 900 includes a bias voltage rail V bias1 The PMOS FET M2 and the NMOS FET M4 are coupled together and provide a differential bandgap voltage kV as shown. bg The PMOS FET M2 and the NMOS FET M4 include a gate configured to receive a second component of the voltage, which may be: PMOS FET M2 and NMOS FET M4 include drains coupled to each other.

[0055]

[0068] The bias voltage generator 900 includes an NMOS FET M5 including a drain and a gate configured to receive a bias current Ibias, which is a bandgap voltage V divided by the resistance of a resistor R associated with the aforementioned filter. bg may be related to (V bg / R). NMOS FET M5 is coupled between the source of bias current Ibias and a low voltage rail (eg, ground).

[0056]

[0069] The bias voltage generator 900 further includes a PMOS FET M6, an NMOS FET M7, and an NMOS FET M8 coupled in series between the first upper voltage rail Vdd1 and a lower voltage rail (e.g., ground). The bias voltage generator 900 further includes a PMOS FET M9, an NMOS FET M10, and an NMOS FET M11 coupled in series between the first upper voltage rail Vdd1 and a lower voltage rail (e.g., ground). The PMOS FETs M6 and M9 include a gate coupled to each other and to the drain of the PMOS FET M6. The NMOS FETs M7 and M10 generate a second bias voltage V bias2 NMOS FETs M7 and M10 also include sources coupled to the drains of NMOS FETs M3 and M4, respectively. NMOS FETs M8 and M11 include gates coupled to the gate of NMOS FET M5.

[0057]

[0070] The bias voltage generator 900 further includes an NMOS FET M12 coupled in series with an NMOS FET M13 between a second upper voltage rail Vdd2 and a lower voltage rail (e.g., ground). The first upper voltage rail Vdd1 may have a different supply voltage than the second upper voltage rail Vdd2. In some aspects, Vdd1 may be higher than Vdd2. For example, Vdd1 may be about 1.2V, while Vdd2 may be about 0.8V. The bias voltage generator 900 further includes an NMOS FET M14 coupled in series with an NMOS FET M15 between the second upper voltage rail Vdd2 and a lower voltage rail (e.g., ground). The NMOS FETs M12 and M14 include gates coupled to the drain of the PMOS FET M9. The NMOS FETs M13 and M15 include gates coupled to the gates of the NMOS FETs M5, M8, and M11. V bias1 The bias voltage V associated with the voltage rail bias1is generated at the source of NMOS FET M12 which is coupled to the sources of PMOS FETs M1 and M2.

[0058]

[0071] The bias voltage generator 900 includes a first capacitor C1 connected between the drain of the PMOS FET M9 and a low voltage rail (e.g., ground). Additionally, the bias voltage generator 900 includes a second capacitor C2 coupled between the source of the NMOS FET M14 and a lower voltage rail (e.g., ground). A supply voltage Vdd_inv is generated at the source of the NMOS FET M14 (i.e., across the second capacitor C2). When the control loop of the bias voltage generator 900 is stable, the bias voltage Vdd_inv scales with the transconductance gain (g) of the inverter 910 inversely proportional to the resistance of a resistor associated with the filter, with process and / or temperature variations. m ) to adjust the

[0059]

[0072] 10 shows a schematic diagram of an example transmitter 1000 according to another aspect of the disclosure. Although the filters and / or gyrators described herein have been described with reference to a receiver application, such as in the case of receiver 800, it should be understood that the filters and / or gyrators may also be used in a transmitter application. Transmitter 1000 is an example of one transmitter application employing the filters described herein.

[0060]

[0073] More specifically, the transmitter 1000 includes a digital carrier aggregator (CA) 1010 configured to generate a digital baseband transmit signal (BBTX), and a digital carrier aggregator (CA) 1020 configured to convert the digital baseband transmit signal BBTX into an analog baseband transmit signal S. i and a digital-to-analog converter (DAC) 1020 configured to convert the analog baseband transmit signal S into a digital signal S. However, it will be appreciated that in other configurations, the BBTX signal does not include a carrier aggregated signal, and the source of the BBTX signal may include circuitry other than the digital CA 1010 (e.g., in a modem of a mobile device). The transmitter 1000 receives an analog baseband transmit signal S ito filter out signal images, noise and / or other unwanted signals, resulting in a filtered analog baseband transmit signal S o In a transmitter application, the filtered analog baseband transmit signal S o may be upconverted directly to a radio frequency (RF) signal or may be upconverted to an RF signal via upconversion to an intermediate frequency (IF) signal. Thus, the output of the filter stage 1040 may be coupled to a mixer (not shown), and the filter stage 1040 may output a filtered analog baseband transmit signal S o to the mixer. In other embodiments, filter stage 1040 is omitted and filter stage 1030 is coupled to the mixer and configured to provide a filtered analog baseband signal to the mixer. In other embodiments, one or both of first filter stage 1030 and second filter stage 1040 may be replaced by a different type of filter (e.g., as described above, which may include a notch filter) and / or one or more additional filters may be coupled between the output of second filter stage 1040 and the mixer.

[0061]

[0074] The first filter stage 1030 may be configured as a Rauch filter, such as the Rauch filter 200 described above. The first filter stage 1030 includes an input capacitor C1, an input resistor R1, a set of cascaded inverters 1032-1 to 1032-3, a feedback capacitor C2, and a feedback resistor R2. The input capacitor C1 is connected to the input of the signal S iThe first cascaded inverter 1032-3 is connected between an input (node) of the first filter stage 1030 (wherein the first cascaded inverter 1032-3 is received) and a lower voltage rail (e.g., ground). An input resistor R1 is connected between the input (node) of the first filter stage 1030 and the input of the first cascaded inverter 1032-1. A feedback capacitor C2 is connected between the output of the last cascaded inverter 1032-3 and the input of the first cascaded inverter 1032-1. A feedback resistor R2 is connected between the output of the last cascaded inverter 1032-3 and the input (node) of the first filter stage 1030.

[0062]

[0075] The second filter stage 1040 may also be configured as a Rauch filter, such as the Rauch filter 200 described above. The second filter stage 1040 includes a first input resistor R3, an input capacitor C3, a second input resistor R4, a set of cascaded inverters 1042-1 to 1042-3, a feedback capacitor C4, and a feedback resistor R5. The first input resistor R3 is coupled between the output of the first filter stage 1030 and a node n1. The input capacitor C3 is connected between the node n1 and a low voltage rail (e.g., ground). The second input resistor R4 is connected between the node n1 and the input of the first cascaded inverter 1042-1. The feedback capacitor C4 is connected between the output of the last cascaded inverter 1042-3 and the input of the first cascaded inverter 1042-1. A feedback resistor R5 is connected between the output of the last cascaded inverter 1042-3 and node n1. The output of the last cascaded inverter 1042-3 is the filtered output signal S o The method is configured to generate

[0063]

[0076] 11 illustrates a schematic diagram of another example transmitter 1100 according to another aspect of the disclosure. The transmitter 1100 is another example in which the filters described herein may be used to perform filtering of a signal generated by a digital-to-analog converter (DAC).

[0064]

[0077] More specifically, the transmitter 1100 includes a first channel carrier component (CC) signal generator 1110-1, a first channel DAC 1120-1, a first channel baseband filter (BBF) 1130-1, and a first channel mixer 1140-1. The transmitter 1100 may further include a second channel carrier component (CC) signal generator 1110-2, a second channel DAC 1120-2, a second channel baseband filter (BBF) 1130-2, and a summer 1145. Furthermore, the transmitter 1100 may further include a third channel carrier component (CC) signal generator 1110-3, a third channel DAC 1120-3, a third channel baseband filter (BBF) 1130-3, and a third channel mixer 1140-3. Any of the baseband filters (BBFs) 1130-1, 1130-2, and 1130-3 may be configured with any of the filters including a set of cascaded inverters described herein. In other embodiments, one or more of the BBFs 1130 are configured using operational amplifiers or without a set of cascaded inverters. Thus, although the transmitter 1100 may include a filter described herein that uses a set of cascaded inverters, the transmitter 1100 is not limited to such a configuration. In such other embodiments, the BBFs 1130 may use any other known configuration of a baseband filter.

[0065]

[0078] The transmitter 1100 includes a phase-locked loop (PLL) 1160 configured to generate a reference oscillator signal REF, and a local oscillator (LO) signal LO based on the reference oscillator signal VREF (e.g., by dividing the frequency of the reference oscillator signal VREF). 1 and L.O. 2The frequency divider 1170 is coupled to the inputs of the mixers 1140-1 and 1140-3, respectively (LO 1 and L.O. 2 The first mixer 1140-1 includes an LO output, at which a LO signal is generated. 1 The second mixer 1140-3 frequency-converts the signal generated by the BBF 1130-1 based on the LO 2 The BBF 1130-2 frequency converts the signal generated by the BBF 1130-3 based on the LO signal. The mixed signals from the mixers 1140-1 and 1140-3 are applied to an input of a summer 1145, and a signal from the output of the BBF 1130-2 is also applied to another input of the summer 1145. The summer 1145 sums the signals from the mixers 1140-1 and 1140-3 and the BBF 1130-2 to generate a carrier aggregated (CA) baseband signal. In some embodiments, the LO signal is 1 and L.O. 2 The signals have approximately equal frequencies of opposite polarity centered around zero. For example, LO 1 and L.O. 2 The LO may have a frequency of several hundred MHz (e.g., 300 to 500, or about 400). 1 and L.O. 2 The BBF 1130 may have an operating frequency greater than the frequency of the LO signal (e.g., greater than 500 MHz, e.g., about 600 MHz). 1 and L.O. 2 It may have a bandwidth that is smaller than the frequency of the signal (eg, smaller than 300 MHz, eg, about 200 MHz).

[0066]

[0079] Mixer 1150 includes a first input coupled to the output of summer 1145 (wherein the CA baseband signal is generated) and a second input for receiving an intermediate frequency LO. Mixer 1150 mixes the CA baseband signal with the IF LO to generate an IF signal S if In some embodiments, the IF LO signal generates a LO 1 and L.O. 2The IF LO signal has a frequency at least one order of magnitude greater than the frequency of the LO signal. 1 and L.O. 2 The IF signal S may have a frequency that is about 20 to 30 times the frequency of the IF signal S if may then be filtered, for example, by any of the filters described herein or by another filter. if may be further upconverted to generate an RF signal for transmission.

[0067]

[0080] 12 illustrates a flow diagram of an example method 1200 for filtering an input signal according to another aspect of the disclosure. The method 1200 includes applying an input signal to an input of a first cascaded inverter of a set of cascaded inverters coupled to a set of one or more passive devices (block 1210) and outputting an output signal from the set of cascaded inverters that is a filtered version of the input signal (block 1220).

[0068]

[0081] 13 illustrates a block diagram of an exemplary pseudo differential filter 1300 according to another aspect of the disclosure. The pseudo differential filter 1300 includes a positive filter differential component 1310 and a negative filter differential component 1320. Each of the positive and negative filter differential components 1310 and 1320 may be configured as any of the previously described filters including a set of cascaded inverters, such as filters 200, 300, 400, and 700. Both the positive and negative filter differential components 1310 and 1320 may be configured in the same manner, with substantially the same resistances and capacitances of the resistors and capacitors that make up the positive and negative filter differential components 1310 and 1320.

[0069]

[0082] Input differential signal S i+ and S iare applied to the inputs of positive and negative filter differential components 1310 and 1320, respectively. The positive and negative filter differential components 1310 and 1320 filter the input differential signal S i+ and S i is filtered to produce the output differential signal S o and S o+ and , respectively. The polarity between the input and output differential signals may be reversed since most of the filters described herein use negative feedback. However, the polarity may be the same for a positive feedback filter such as the Sallen-Key filter 400 described above.

[0070]

[0083] FIG. 14 illustrates a block diagram of an exemplary wireless communication device 1400 according to another aspect of the present disclosure. Examples of the wireless communication device 1400 include cellular or mobile phones (e.g., smartphones), user terminals, personal computers, laptops, tablet devices, customer premises equipment (CPE), smart watches and other personal wireless devices, wireless medical devices, vehicle (automotive) wireless devices, and the like. The wireless communication device 1400 includes an integrated circuit (IC) 1410 that may be configured as a system on chip (SOC). The SOC 1410 may include a set of one or more digital signal processing cores 1420. The set of one or more digital signal processing cores 1420 may be configured to generate and / or process a baseband (BB) signal that may be received from or provided to a filter having a set of cascaded inverters as described herein, for example.

[0071]

[0084] The wireless communication device 1400 further includes a transceiver 1450 that may include a filter and / or gyrator 1460 having a set of cascaded inverters, as described herein. The filter and / or gyrator 1460 may be used (with other circuitry) to convert a BB signal received from the SOC 1410 to a radio frequency (RF) signal to be applied to an antenna 1470 for transmission to one or more remote devices. Alternatively, the filter and / or gyrator 1460 may be used (with other circuitry) to convert an RF signal received via the antenna 1470 to a BB signal to be applied to the SOC 1410 for further processing by a set of one or more digital signal processing cores 1420.

[0072]

[0085] In some embodiments, the filter and / or gyrator 1460 may have a relatively wide bandwidth (e.g., hundreds of MHz, such as 500-600 MHz or about 800 MHz or more), which may be beneficial when the transceiver 1450 operates with signals having millimeter wave (mmW) frequencies. In some such embodiments, channels at mmW frequencies may have wider bandwidths compared to channels established in older communication standards. These wide bandwidths may be realized in low noise, low power, and / or high linearity configurations.

[0073]

[0086] As a more specific receiver application example, wireless cellular networks such as Long Term Evolution (LTE) and New Radio 5th Generation (5G) include channel B25, which extends from 1930 MHz to 1995 MHz for downlink operation. Thus, the baseband receive bandwidth is −32.5 MHz to +32.5 MHz. The associated transmit signal may extend from 1850 MHz to 1915 MHz. To prevent leakage of the transmit signal into the receiver baseband circuitry, the receiver baseband filter may be configured to have a stopband starting at 47.5 MHz below the low side of the passband for the B25 channel in the baseband. For example, the filter 700, including the second stage 720 of the Rauch configuration and the notches created by the capacitor-inductor shunt resonances (C1-L1, C2-L2, and C3-L3), may be configured to provide a desired frequency response that accommodates the B25 channel passband and stopband. For example, the filter may be configured to place zeros to obtain a stopband larger than 20 dB. This causes the filtered signal to be at substantially the same level as the in-band blocker signal.

[0074]

[0087] The following provides a summary of aspects of the disclosure.

[0088] Aspect 1: An apparatus comprising a filter or a first gyrator comprising a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters.

[0075]

[0089] Aspect 2: The apparatus of aspect 1, wherein a first set of one or more passive devices of the filter is connected between an input of a first one of the first set of cascaded inverters and an output of a second one of the first set of cascaded inverters.

[0076]

[0090] Aspect 3: The apparatus of aspect 1 or 2, wherein the number of one or more cascaded inverters between a first and a second of the first set of cascaded inverters is odd.

[0077]

[0091] Example 4: The apparatus of any one of Examples 1 to 3, wherein the first set of one or more passive devices comprises a capacitor.

[0078]

[0092] Aspect 5: An apparatus described in any one of aspects 1 to 4, wherein the first set of one or more passive devices comprises a first resistor connected between an input of the filter and an input of a first one of the first set of cascaded inverters, and a second resistor connected between the input of the filter and an output of a second one of the first set of cascaded inverters.

[0079]

[0093] Aspect 6: The apparatus of any one of aspects 1 to 5, wherein the filter is configured to provide a filter frequency response of a Rauch filter.

[0080]

[0094] Aspect 7: The apparatus of aspect 1, wherein the filter comprises a first filter stage comprising a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters, the first set of one or more passive devices comprising a first resistor connected between an input of the first filter stage and a first input of the first set of cascaded inverters, and a second resistor coupled in parallel with the first capacitor between the first input of the first set of cascaded inverters and a second output of the first set of cascaded inverters.

[0081]

[0095] Aspect 8: The apparatus of Aspect 7, wherein the filter further comprises a second filter stage comprising a second set of cascaded inverters and a second set of one or more passive devices coupled to the second set of cascaded inverters, the second set of one or more passive devices comprising: a third resistor connected between an output of the second set of the first set of cascaded inverters of the first filter stage and an input of the first set of the second set of cascaded inverters, and a second capacitor connected between an input of the first set of the second set of cascaded inverters and an output of the second set of the second set of cascaded inverters.

[0082]

[0096] Aspect 9: The apparatus of aspect 7 or 8, wherein the filter further comprises a third filter stage comprising a third set of cascaded inverters and a third set of one or more passive devices coupled to the third set of cascaded inverters, the third set of one or more passive devices comprising a fourth resistor connected between an output of the second set of cascaded inverters of the second filter stage and an input of the first set of the third set of cascaded inverters, and a fifth resistor connected between an input of the first set of the third set of cascaded inverters and an output of the second set of the third set of cascaded inverters.

[0083]

[0097] Aspect 10: The apparatus of aspect 9, further comprising a sixth resistor connected between an input of a first one of the first set of cascaded inverters of the first filter stage and an output of a second one of the third set of cascaded inverters of the third filter stage.

[0084]

[0098] Aspect 11: The apparatus of aspect 9 or 10, wherein the first filter stage provides a band-pass filter (BPF) frequency response, and the first, second, and third filter stages collectively provide a low-pass filter (LPF) frequency response.

[0085]

[0099] Example 12: The apparatus of any one of Examples 7 to 11, wherein the filter is configured to provide a filter frequency response of a Tow-Thomas biquad filter.

[0086]

[0100] Aspect 13: The apparatus of aspect 1, wherein the first set of one or more passive devices of the filter comprises: a first resistor connected between an input of the filter and a first node; a second resistor connected between the first node and an input of a first one of the first set of cascaded inverters; a first capacitor connected between the first node and a voltage rail; and third and fourth resistors connected in series between an output of a second cascaded inverter of the first set of cascaded inverters and the voltage rail, wherein a second node between the third and fourth resistors is coupled to the output of the first cascaded inverter of the first set of cascaded inverters.

[0087]

[0101] Aspect 14: The apparatus of any one of aspects 1 to 13, wherein the number of cascaded inverters between a first and a second of the first set of cascaded inverters is either zero (0) or an even number.

[0088]

[0102] Aspect 15: The apparatus of aspect 1, 13, or 14, wherein the filter is configured to provide a filter frequency response of a Sallen-Key filter.

[0089]

[0103] Aspect 16: The apparatus of aspect 1, wherein a first set of one or more passive devices of the first gyrator is connected between an output of a first inverter of the first set of cascaded inverters and a voltage rail, and the first gyrator further comprises a conductor connected between an input of a first one of the first set of cascaded inverters and an output of a second one of the first set of cascaded inverters.

[0090]

[0104] Aspect 17: The apparatus of aspect 13 or 16, wherein the voltage rail comprises ground.

[0091]

[0105] Example 18: The apparatus of any one of Examples 1, 10, 11, or 17, wherein the first set of one or more passive devices comprises a capacitor.

[0092]

[0106] Example 19: An apparatus described in any one of examples 1 to 18, wherein the first set of one or more passive devices comprises a capacitor in series with a resistor.

[0093]

[0107] Example 20: An apparatus described in any one of Examples 1 to 10, wherein the filter comprises a first filter stage comprising a first gyrator connected between the node and the voltage rail.

[0094]

[0108] Aspect 21: The apparatus of aspect 20, wherein the voltage rail comprises ground.

[0095]

[0109] Aspect 22: The apparatus of any one of aspects 1 to 21, wherein the first gyrator comprises: a first set of cascaded inverters, where an input of a first one of the first set of cascaded inverters acts as a node; a first conductor connected between the input of the first one of the first set of cascaded inverters and an output of a second one of the first set of cascaded inverters; and a first set of one or more passive devices connected between the output of the first one of the cascaded inverters and a voltage rail.

[0096]

[0110] Example 23: The apparatus of any one of Examples 20 to 22, wherein the first filter stage further comprises a second gyrator connected between the node and the voltage rail.

[0097]

[0111] Aspect 24: The apparatus of any one of aspects 20 to 23, wherein the second gyrator comprises: a second set of cascaded inverters, where an input of a first set of the second set of cascaded inverters acts as a node; a second conductor connected between an input of a first one of the second set of cascaded inverters and an output of a second one of the second set of cascaded inverters; and a second set of one or more passive devices connected between the output of the first one of the second set of cascaded inverters and the voltage rail.

[0098]

[0112] Example 25: The apparatus of any one of Examples 20 to 24, wherein the first filter stage further comprises a third gyrator connected between the node and the voltage rail.

[0099]

[0113] Aspect 26: The apparatus of any one of aspects 20 to 25, wherein the third gyrator comprises: a third set of cascaded inverters, where an input of a first set of the third set of cascaded inverters acts as a node; a third conductor connected between an input of a first one of the third set of cascaded inverters and an output of a second one of the third set of cascaded inverters; and a third set of one or more passive devices connected between the output of the first one of the third set of cascaded inverters and the voltage rail.

[0100]

[0114] Aspect 27: The apparatus of any one of aspects 20-26, wherein the filter comprises a second filter stage comprising a first set of cascaded inverters and a first set of one or more passive devices, the first set of one or more passive devices comprising: a first resistor connected between the node and an input of a first one of the first set of cascaded inverters; a second resistor connected between the node and an output of a second inverter of the first set of cascaded inverters; and a capacitor connected between the input of the first one of the first set of cascaded inverters and the output of the second one of the first set of cascaded inverters.

[0101]

[0115] Aspect 28: The apparatus of any one of aspects 1 to 27, wherein the first set of one or more passive devices comprises a resistor, and further comprising a voltage generator configured to generate a supply voltage for the first set of cascaded inverters configured to vary a transconductance gain of the first set of cascaded inverters inversely proportional to a resistance of the resistor in response to process and / or temperature variations associated with the filter or the first gyrator.

[0102]

[0116] Example 29: The apparatus of any one of examples 1 to 28, wherein the filter comprises a positive filter differential component and a negative filter differential component, the positive filter differential component comprising a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters, and the negative filter differential component comprising a second set of cascaded inverters and a second set of one or more passive devices coupled to the second set of cascaded inverters.

[0103]

[0117] Aspect 30: The apparatus of any one of aspects 1 to 29, further including: a mixer configured to mix a radio frequency (RF) signal with a local oscillator (LO) signal to generate a mixed signal, wherein the filter is configured to filter the mixed signal to generate an analog baseband signal; a bypassable in-band blocker configured to reduce unwanted signals within a passband of a received signal of interest from the analog baseband signal; an analog-to-digital converter (ADC) configured to digitize the analog baseband signal or an analog signal generated by the in-band blocker; and a digital filter configured to filter the digital signal from the ADC to generate a baseband digital signal.

[0104]

[0118] Example 31: The apparatus of any one of Examples 1 to 30, wherein the filter does not include an inductor or an operational amplifier.

[0105]

[0119] Example 32: A device described in any one of examples 1 to 31, wherein the filter consists of an inverter, a capacitor, and a resistor.

[0106]

[0120] Example 33: The apparatus of any one of Examples 1 to 32, wherein the filter is configured to filter an analog baseband signal.

[0107]

[0121] Aspect 34: An apparatus described in any one of aspects 1 to 33, wherein a first inverter and a second inverter in the first set of cascaded inverters are directly connected to each other with no other elements connected between them or to a node between them.

[0108]

[0122] Example 35: An apparatus described in any one of Examples 1 to 34, wherein the first set of one or more passive devices comprises one or more reactances.

[0109]

[0123] Aspect 36: A method comprising: applying an input signal to an input of a first inverter of a set of cascaded inverters coupled to a set of one or more passive devices; and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal.

[0110]

[0124] Aspect 37: A transceiver comprising: a filter comprising a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters; and a mixer coupled to the filter.

[0111]

[0125] Aspect 38: The transceiver of aspect 37, further comprising: a first signal generator configured to generate a first digital signal; and a first digital-to-analog converter (DAC) configured to generate a first analog signal based on the first digital signal, wherein the first filter is configured to filter the first analog signal to generate a first filtered analog signal, and the first mixer is configured to mix the first filtered analog signal with a first local oscillator (LO) signal to generate a first transmit signal.

[0112]

[0126] Aspect 39: The transceiver of aspect 38, further comprising: a second filter comprising a second set of cascaded inverters and a second set of one or more passive devices coupled to the second set of cascaded inverters; a second mixer coupled to the second filter; and a second digital-to-analog converter (DAC) configured to generate a second analog signal based on the second digital signal, wherein the second filter is configured to filter the second analog signal to generate a second filtered analog signal, and the second mixer is configured to mix the second filtered analog signal with a second local oscillator (LO) signal to generate a second transmit signal.

[0113]

[0127] Aspect 40: The transceiver of any one of aspects 37 to 39, further comprising: a third filter comprising a third set of cascaded inverters and a third set of one or more passive devices coupled to the third set of cascaded inverters; a third signal generator configured to generate a third digital signal; a third digital-to-analog converter (DAC) configured to generate a third analog signal based on the third digital signal, the third filter configured to filter the third analog signal to generate a third transmit signal; and an adder that adds the first, second, and third transmit signals to generate a carrier aggregated transmit signal.

[0114]

[0128] Aspect 41: The transceiver of any one of aspects 37 to 40, further comprising a third mixer configured to mix the carrier aggregated transmit signal with a third local oscillator (LO) signal to generate an intermediate frequency (IF) or radio frequency (RF) transmit signal.

[0115]

[0129] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising a filter, wherein the filter comprises a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters, wherein the first set of one or more passive devices of the filter is connected between an input of a first one of the first set of cascaded inverters and an output of a second one of the first set of cascaded inverters, and the first set of one or more passive devices comprises a capacitor.

2. The apparatus according to claim 1, wherein the number of one or more cascaded inverters between the first one and the second one of the first set of cascaded inverters is odd.

3. The first set of one or more passive devices further comprises a first resistor connected between the input of the filter and the input of the first one of the first set of cascaded inverters, and a second resistor connected between the input of the filter and the output of the second one of the first set of cascaded inverters. The apparatus according to claim 1.

4. The apparatus according to claim 1, wherein the filter is configured to provide a filter frequency response of a Sallen - Key filter.

5. The filter comprises a first filter stage, and the first filter stage comprises the first set of cascaded inverters, one or more first sets of passive devices coupled to the first set of cascaded inverters, the first set of one or more passive devices being a first resistor connected between the input of the first filter stage and the input of the first one of the first set of cascaded inverters, a second resistor coupled in parallel with a first capacitor between the input of the first one of the first set of cascaded inverters and the output of the second one of the first set of cascaded inverters, the apparatus of claim 1. **Claim 6** the filter further comprising a second filter stage, the second filter stage being a second set of cascaded inverters, one or more second sets of passive devices coupled to the second set of cascaded inverters, the second set of one or more passive devices being a third resistor connected between the output of the second one of the first set of cascaded inverters of the first filter stage and the input of the first one of the second set of cascaded inverters, a second capacitor connected between the input of the first one of the second set of cascaded inverters and the output of the second one of the second set of cascaded inverters, the apparatus of claim 5. **Claim 7** the filter further comprising a third filter stage, the third filter stage being a third set of cascaded inverters, one or more third sets of passive devices coupled to the third set of cascaded inverters, the third set of one or more passive devices being The fourth resistor connected between the output of the second one of the second set of cascaded inverters of the second filter stage and the input of the first one of the third set of cascaded inverters, The apparatus according to claim 6, further comprising a fifth resistor connected between the input of the first one of the third set of cascaded inverters and the output of the second one of the third set of cascaded inverters.

8. The apparatus according to claim 7, further comprising a sixth resistor connected between the input of the first one of the first set of cascaded inverters of the first filter stage and the output of the second one of the third set of cascaded inverters of the third filter stage.

9. The apparatus according to claim 8, wherein the first filter stage provides a band-pass filter (BPF) frequency response, and the first, second, and third filter stages collectively provide a low-pass filter (LPF) frequency response.

10. The first set of one or more passive devices of the filter comprises A first resistor connected between the input of the filter and the first node, A second resistor connected between the first node and the input of the first one of the first set of cascaded inverters, A first capacitor connected between the first node and the voltage rail, A second capacitor connected between the first node and the output of the second one of the first set of cascaded inverters, A third and a fourth resistor connected in series between the output of the second one of the first set of cascaded inverters and the voltage rail, comprising, wherein a second node between said third and fourth resistors is coupled to an output of a first one of said first set of cascaded inverters, the apparatus of claim 1. **Claim 11** wherein a number of said cascaded inverters between a first one and a second one of said first set of cascaded inverters is either zero (0) or an even number, the apparatus of claim 10. **Claim 12** wherein said filter comprises a positive filter differential component and a negative filter differential component, wherein said positive filter differential component comprises a first set of cascaded inverters and a first set of one or more passive devices coupled to said first set of cascaded inverters, wherein said negative filter differential component comprises a second set of cascaded inverters and a second set of one or more passive devices coupled to said second set of cascaded inverters, the apparatus of claim 1. the apparatus of claim 1. **Claim 13** wherein said filter does not include an inductor or an operational amplifier, or wherein said filter is configured to filter an analog baseband signal, the apparatus of claim 1. **Claim 14** A feedback resistor is connected between said output of a last cascaded inverter and said input of a first cascaded inverter, wherein said apparatus further comprises a mixer coupled to said filter, said mixer optionally including a first input configured to receive an RF signal and a second input configured to receive a local oscillator (LO) signal, the apparatus of claim 1. **Claim 15** A method, Applying an input signal to the input of a first one of a set of cascaded inverters coupled to a set of one or more passive devices; Receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal; Comprising, a first set of one or more passive devices being coupled to the first set of cascaded inverters; The first set of one or more passive devices of the filter being connected between an input of a first one of the first set of cascaded inverters and an output of a second one of the first set of cascaded inverters; The method, wherein the first set of one or more passive devices comprises a capacitor.

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