Dynamic repartitioning of memory physical address mapping

Abstract

A system and method for dynamic repartitioning of physical memory address mapping includes relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, and then reloading the relocated data onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of physical memory address mapping does not require the processing system to be rebooted and has various applications in conjunction with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Description

[Background technology]

[0001] To improve overall processing efficiency, processing systems typically employ multi-channel high bandwidth memories, such as multi-channel Dynamic Random Access Memory (DRAM). For example, such multi-channel memories are often implemented within a processing system such that multiple memory dies are accessible in parallel by a host processor in the system. This multi-channel parallel access typically increases the amount of data that the system can read or write in a given period of time, allowing for reduced processing delays, thereby improving system performance.

[0002] Typically, the manner in which data is written to a memory device, such as a DRAM, is defined by a system's physical address mapping, which maps physical addresses to corresponding physical blocks of memory in the memory device. In conventional systems, the system must be rebooted to change the physical address mapping associated with one or more memory devices. However, rebooting typically takes time and risks boot errors or interruption of in-band mechanisms for system monitoring, which are of particular concern in high performance processing systems. Summary of the Invention [Means for solving the problem]

[0003] The following examples, either individually or in combination, may provide further context for the embodiments and implementations described herein.

[0004] Example 1. A method comprising: relocating first data from the first set of memory blocks of a first memory device of the processing system to a selected one of the second memory device or the mass storage device in response to receiving an indicator identifying the first set of memory blocks of the first memory device; repartitioning at least one physical memory map associated with the first set of memory blocks of the first memory device to generate at least one subdivided physical memory map representing a relocation of the first data to the second set of memory blocks; and storing the first data in a second set of memory blocks based on the at least one subdivided physical memory map.

[0005] Example 2. The method of example 1, wherein repartitioning the at least one physical memory map is performed in conjunction with changing a system configuration of the processing system.

[0006] Example 3. The method of example 2, wherein the change in the system configuration corresponds to a change in an error correcting code (ECC) configuration of the processing system, the ECC configuration identifying ECC memory blocks that are reserved for storing ECC data.

[0007] Example 4. The method of example 2, wherein the change in the system configuration corresponds to a change in an interleaving configuration of the processing system, the interleaving configuration defining at least one interleaving pattern according to which the data is to be stored on at least the first set of memory blocks.

[0008] Example 5. Repartitioning at least one physical memory map includes: The method of any of embodiments 1 to 4, further comprising modifying a mapping defined by at least one physical memory map for a first physical address, wherein the at least one physical memory map maps the first physical address to a first memory block of the first set of memory blocks and the at least one subdivided physical memory map maps the first physical address to a second memory block of the second set of memory blocks.

[0009] Example 6. The method of any of Examples 1-5, wherein repartitioning the at least one physical memory map is performed without requiring a reboot of the processing system that includes the first memory device.

[0010] Example 7. A processing system comprising: at least one processor couplable to at least a first memory device; the processor is configured to execute instructions; The command is, rearranging first data from a first set of memory blocks of a first memory device according to an indicator identifying the first set of memory blocks; repartitioning at least one physical memory map associated with the first set of memory blocks of the first memory device to generate at least one subdivided physical memory map representing a relocation of the first data to the second set of memory blocks of the first memory device; and operating at least one processor to store the first data in a second set of memory blocks of the plurality of memory devices based on the at least one subdivided physical memory map.

[0011] Example 8. The processing system of example 7, wherein the instructions include operating at least one processor to repartition at least one physical memory map in conjunction with a change in a system configuration of the processing system.

[0012] Example 9. The processing system of example 8, wherein the change in the system configuration corresponds to a change in an error correcting code (ECC) configuration of the processing system, the ECC configuration identifying ECC memory blocks of the plurality of memory devices that are reserved for storing ECC data.

[0013] Example 10. The processing system of Example 8, wherein the change in the system configuration corresponds to a change in an interleaving configuration of the processing system, the interleaving configuration defining at least one interleaving pattern according to which the data is to be stored on memory blocks of the plurality of memory devices, the memory blocks including at least a first set of memory blocks.

[0014] Example 11. The processing system of example 10, wherein the change in the interleaving configuration corresponds to replacing the first interleaving pattern with a second interleaving pattern, and the at least one subdivided physical memory map reflects the second interleaving pattern.

[0015] Example 12. The processing system of any of Examples 7 to 11, wherein the instructions include operating at least one processor to modify a mapping defined by the at least one physical memory map for a first physical address to subdivide the at least one physical memory map, wherein the at least one physical memory map maps the first physical address to a first memory block of the first set of memory blocks, and the at least one subdivided physical memory map maps the first physical address to a second memory block of the second set of memory blocks.

[0016] Example 13. a first memory device and a second memory device; a mass storage device, The processing system of any of Examples 7 to 11, wherein the instructions include operating at least one processor to relocate the first data to a selected one of a second memory device of the plurality of memory devices or a mass storage device.

[0017] Example 14. The processing system of any of Examples 7 to 13, wherein the instructions include operating at least one processor to repartition at least one physical memory map without requiring a reboot of the processing system.

[0018] Example 15. A system comprising: at least one processor; at least one processor is couplable to at least the first memory device and configured to execute instructions; The command is, transferring first data from a first memory block of a first memory device in response to an indicator identifying at least the first memory block; repartitioning a physical memory map associated with the first memory block to generate a repartitioned physical memory map representing a relocation of the first data to a second memory block of the first memory device without requiring a reboot of the system; and operating at least one processor to store the first data in the second memory block based on the subdivided physical memory map.

[0019] Example 16. The system of example 15, wherein the instructions further include operating the at least one processor to repartition the physical memory map in conjunction with a change in a system configuration of the system.

[0020] Example 17. The system of example 16, wherein the change in the system configuration corresponds to a change in an error correcting code (ECC) configuration of the system, the ECC configuration identifying ECC memory blocks of the plurality of memory devices that are reserved for storing ECC data.

[0021] Example 18. The system of Example 16, wherein the change in the system configuration corresponds to a change in an interleaving configuration of the system, the interleaving configuration defining at least one interleaving pattern according to which data is to be stored on a plurality of memory blocks including a first memory block and a second memory block.

[0022] Example 19. The system of example 15, wherein the instructions include operating at least one processor to modify a mapping defined by the physical memory map for a first physical address to subdivide the physical memory map, where the physical memory map associates the first physical address with a first memory block, and where the subdivided physical memory map associates the first physical address with a second memory block.

[0023] Example 20. a first memory device and a second memory device; a mass storage device, 16. The system of example 15, wherein the instructions include operating at least one processor to relocate the first data to a selected one of the second memory device or the mass storage device.

[0024] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by reference to the following drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0025] [Figure 1] 1 is a block diagram of a processing system employing a dynamic physical address map, according to some embodiments. [Diagram 2] FIG. 2 is a flow diagram illustrating a method for dynamically repartitioning memory physical address mapping in accordance with some embodiments. [Diagram 3]FIG. 2 is a block diagram illustrating a fine-grained interleaving pattern used to store data across a memory device, according to some embodiments. [Figure 4] FIG. 2 is a block diagram illustrating a coarse-grained interleaving pattern used to store data across a memory device, according to some embodiments. [Diagram 5] FIG. 1 is a flow diagram illustrating a method for dynamically repartitioning memory physical address mappings for one or more memory devices and modifying an interleaving configuration of one or more memory devices, according to some embodiments. [Figure 6] 1 is a block diagram illustrating a memory device having memory blocks reserved for storing error correcting codes (ECCs) for each ECC configuration, according to some embodiments. [Figure 7] FIG. 1 is a flow diagram illustrating a method for dynamically repartitioning memory physical address mappings for one or more memory devices and modifying ECC configurations associated with the one or more memory devices, according to some embodiments. [Figure 8] FIG. 2 is a block diagram illustrating fine-grained based dynamic repartitioning of multiple memory devices of a processing system in accordance with some embodiments. [Figure 9] FIG. 1 is a flow diagram illustrating a method for dynamically repartitioning memory physical address mappings for only a portion of memory blocks in a given memory device, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Repartitioning of the physical address mapping of a memory device, such as a multi-channel DRAM, is traditionally performed only upon reboot (i.e., "boot time") of an associated processing system. In the present context, repartitioning of the physical address mapping of one or more memory devices at boot time is referred to as "static" repartitioning. Embodiments of the present disclosure relate to "dynamic" repartitioning of the physical address mapping of one or more memory devices, where a reboot of at least a portion of the system is not required. Such dynamic repartitioning is performed in some embodiments by rearranging at least a portion of the data stored in a given memory block or set of memory blocks of one or more memory devices, repartitioning the physical address mapping associated with those memory blocks according to a new partitioning scheme, and then moving the rearranged data back onto the memory device in an arrangement that complies with the new partitioning scheme. Dynamic repartitioning is performed without requiring a reboot of the processing system, which reduces or eliminates system downtime caused by the reboot process required by traditional static repartitioning.

[0027] Because "critical" data, such as, for example, operating system (OS) data and page table data, are often stored in memory devices of a processing system, attempting to repartition such memory devices without rebooting the processing system may lead to errors or other instabilities in conventional processing systems. However, in embodiments of the present disclosure, "critical" memory locations (e.g., memory locations identified as storing critical data) within a given memory device are identified and dynamic repartitioning is disabled for these memory locations, which helps ensure that critical data is not lost during dynamic repartitioning. Because the risk of losing such critical data is mitigated or avoided entirely by disabling dynamic repartitioning for the critical memory locations, memory devices storing such critical data may be dynamically repartitioned without requiring a reboot. The dynamic repartitioning scheme described herein thus facilitates repartitioning of the physical address mapping of a memory device, and in some embodiments, facilitates such repartitioning on a per-workload basis.

[0028] A processing system typically includes one or more memory devices, such as DRAMs, that include a plurality of memory cells, where a contiguous group of memory cells is referred to as a memory block. Typically, a memory controller (e.g., a memory management unit (MMU)) of such a processing system maintains a physical address map that defines a mapping between physical addresses and physical locations (e.g., memory blocks) within one or more memory blocks of one or more memory devices of the processing system, such that the physical address map associates a given physical address with a particular physical location within the memory device of the processing system. The association between physical addresses and physical memory locations within a processing system may be referred to herein as a "physical address mapping" or a "physical memory address mapping" of the processing system. It may be desirable to modify the physical address map, and such modification is performed in conjunction with a reconfiguration of the processing system in some embodiments. Modifying the physical address map is referred to herein as a repartitioning of the physical address map. According to various examples, the physical address map for one or more memory devices of a given processing system is repartitioned when modifying an interleaving configuration associated with a memory device, when modifying an error correction code (ECC) configuration associated with a memory device, or when enabling or disabling a redundancy mode (e.g., dual module redundancy mode or triple module redundancy mode) for the processing system. It should be understood that as used herein, physical address mapping does not refer to a mapping between a virtual address and a physical address, but rather to a mapping between a physical address and a physical memory location of a processing system.

[0029] In some cases, data such as "critical" data (e.g., OS data or page table data) stored in a given memory device cannot be relocated without interrupting the operation of the processing system. Thus, in some embodiments described herein, dynamic repartitioning of the physical address map is disabled for at least some of the memory blocks of the memory devices, meaning that data stored in such memory blocks is not relocated during dynamic repartitioning of the physical address map of the corresponding memory device. As an example, when dynamically repartitioning the physical address map of the processing system, first data stored on one or more memory devices in a first set of memory blocks is identified as eligible to be relocated to another memory device or storage device, and then, in some embodiments, is reloaded on the one or more memory devices according to the new physical address mapping if dynamic repartitioning is enabled for the first set of memory blocks. In contrast, second data stored on one or more memory devices in a second set of memory blocks cannot be relocated to another memory device or storage device due to dynamic repartitioning if dynamic repartitioning is disabled for the second set of memory blocks.

[0030] 1 illustrates a processing system 100 configured for dynamic repartitioning of physical address mappings to one or more memory devices. The processing system 100 includes one or more processors 102 having cores 104, one or more memory management units (MMUs) 106, memory devices 108 (e.g., DRAM devices, direct-mapped non-volatile memory devices, phase-change memory devices, any Compute Express Link (CXL) attached memory devices, etc.), and one or more mass storage devices 110. As shown, the processor 102 is communicatively coupled to the memory devices 108 via two MMUs 106-1, 106-2.

[0031] Each of the MMUs 106 services memory access requests provided by the processors 102, provides read / write access to the memory devices 108, and translates physical memory addresses provided in memory access requests into physical memory locations (e.g., memory blocks) in one or more corresponding memory devices of the memory devices 108. To translate physical memory addresses provided in such memory access requests, each MMU 106 maintains one or more physical memory maps 112 that define associations between physical memory addresses and physical memory locations within the memory devices 108. In some cases, one or more of the physical memory maps 112 are modified or otherwise subdivided to accommodate changes in the configuration of the processing system 100.

[0032] Traditionally, in order to repartition a physical memory map for one or more memories of a processing system, the physical memory map must be repartitioned at boot time, thus requiring the corresponding processing system to be rebooted. However, having to reboot a processing system every time its physical memory map is modified or otherwise repartitioned is typically undesirable because it takes an excessive amount of time (e.g., up to several minutes for more complex processing systems such as servers or supercomputers) and risks causing interruptions or errors in in-band mechanisms for monitoring such processing systems.

[0033] In this example, processing system 100 is configured such that processor 102, in conjunction with MMU 106, causes one or more of physical memory maps 112 to be dynamically repartitioned, i.e., in a manner that avoids the need for a system reboot. In some embodiments, processor 102 causes physical memory map 112 to be dynamically repartitioned in response to processor 102 receiving or otherwise detecting dynamic repartitioning indicator 118. For illustration, dynamic repartitioning indicator 118 may be asserted to indicate that dynamic repartitioning should be performed on all or a portion of one or more of physical memory maps 112 in response to a manual (i.e., user-initiated) or automated request for dynamic repartitioning of physical memory map 112. For example, such an automated request may be generated in response to processor 102 determining that a reconfiguration of processing system 100 (also referred to herein as a “system reconfiguration”) should be performed, the reconfiguration entailing a reorganization of the manner in which data is stored across one or more physical locations of memory device 108 without changing the physical addresses corresponding to the data. That is, a system reconfiguration requires that all or a portion of one or more of physical memory maps 112 be modified to change the existing physical address mappings defined by physical memory map 112 (sometimes referred to herein as "repartitioning" physical memory address map 112). As used herein, the terms "physical address" and "physical memory address" are used interchangeably to refer to an address that refers to or is otherwise associated with a particular physical memory location of a memory device. For example, such system reconfigurations include changes to the ECC configuration of processing system 100 and changes to the interleaving configuration of processing system 100, as described in more detail below.

[0034] In one example, the processing system 100 includes ECC configuration data 114 (e.g., stored in one or more of the mass storage devices 110) that defines certain physical memory locations of the memory devices 108 as reserved for storage of ECC. Typically, ECC is redundant information stored in association with other data to allow soft errors (typically corresponding to data corruption caused, for example, by radiation strikes, signal noise, etc.) in the other data to be detected and, in some cases, corrected. For example, a block code such as a Reed-Solomon code or a Hamming code can be used as the ECC to provide error detection and correction for the memory devices 108. In some embodiments, the ECC configuration data 114 defines the presence or absence of ECC for one or more of the memory devices 108, which determines whether memory blocks are reserved for ECC in those memory devices. For example, if the processing system 100 is reconfigured to enable or disable ECC or to change the ECC scheme used for one or more selected memory devices of the memory devices 108, the ECC configuration data 114 is updated to indicate that ECC is enabled or disabled for the selected memory devices or that the ECC scheme implemented in the selected memory devices is changed, and a dynamic repartitioning indicator is generated that identifies the selected memory devices for which the ECC configuration is to be changed. Such a change in the ECC configuration of the processing system 100 is referred to herein as an "ECC reconfiguration." The processor 102 then temporarily relocates data stored in some or all of the memory locations of the selected memory devices to one or more other memory devices (i.e., not the selected memory device), one or more of the mass storage devices 110 (e.g., including one or more hard disk drives, solid state drives, flash memory, etc.), or both.In some embodiments, if only a subset of memory locations of a given memory device 108 are affected by the ECC reconfiguration and sufficient other memory locations are available (i.e., do not currently store data and are effectively “empty”), the relocated data is moved to a subset of other available memory locations on the same memory device 108. This relocation of data from memory locations affected by the ECC reconfiguration is considered part of a dynamic repartitioning of the physical memory map 112.

[0035] It should be noted that the physical address mappings associated with the memory locations of the memory device 108 to which data is relocated are typically repartitioned as part of the dynamic repartitioning and ECC reconfiguration. For example, when enabling ECC for a given memory device 108, the processor 102 determines one or more memory locations to be reserved for storing ECC data (e.g., as defined in the updated ECC configuration data 114, the dynamic repartitioning indicator, or both), and any data currently stored in those locations is temporarily relocated as described above. As another example, when disabling ECC for a given memory device 108, the processor 102 determines one or more memory locations of the given memory device that are currently reserved for storing ECC data (e.g., as defined in the updated ECC configuration data 114, the dynamic repartitioning indicator, or both), but will no longer be used to store ECC data after the ECC reconfiguration, and any data currently stored in those locations is deleted.

[0036] In some embodiments, after disabling ECC for a given memory device 108, the memory device 108 is defragmented to rearrange the data stored in the physical memory locations of the memory device 108 such that the "gaps" of empty memory caused by removing the ECC data are grouped together. As an example, consider two logically contiguous sets of physical memory addresses A and B of a given memory device 108, where each set A and B includes eight data pages (represented by physical memory addresses A0, A1, A2, A3, A4, A5, A6, A7 and B0, B1, B2, B3, B4, B5, B6, B7, respectively) and one ECC page (represented by physical memory addresses Aecc and Becc, respectively). In this example, data associated with physical memory addresses in sets A and B are stored in a set of sequential memory blocks (e.g., according to a predetermined interleaving pattern) in the following order: A0, A1, A2, A3, A4, A5, A6, A7, Aecc, B0, B1, B2, B3, B4, B5, B6, B7, Becc, where Aecc and Becc first store ECC data for sets A and B, respectively. In this example, when an ECC reconfiguration is performed on memory device 108 to disable ECC, the ECC data stored in the physical memory locations (memory blocks) associated with physical memory locations Aecc and Becc is deleted, memory device 108 is defragmented, and its physical address mapping is modified in conjunction with the dynamic repartitioning techniques described herein such that the order in which data associated with the physical memory addresses are stored in the set of sequential memory blocks is A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2, B3, B4, B5, B6, B7, Aecc, Becc.In this manner, the physical memory addresses Aecc and Becc from which data has been deleted (due to ECC being disabled for a given memory 108) are grouped into adjacent physical memory locations (memory blocks) at the "edges" of the set of sequential memory blocks to reduce the occurrence of "gaps" (i.e., empty memory blocks) in the set of sequential memory blocks when disabling ECC. Data stored at physical memory addresses that are shifted to different physical memory locations in this manner is temporarily relocated during ECC reconfiguration, as described above.

[0037] As another example, when changing the ECC scheme implemented in a given memory device 108, the amount of memory space allocated for storing ECC data will typically change, which may result in changes to the physical address mapping of the given memory device 108. For example, when performing an ECC reconfiguration of the given memory device 108 to change the ECC scheme used by the memory device 108 from 8 / 9 ECC encoding, in which every 8th page of data is ECC encoded using the 9th page of ECC data, to a 128 / 130 ECC encoding scheme, in which every 128th page of data is ECC encoded using the 129th and 130th pages of ECC data, some or all of the data stored in the given memory device 108 will be rearranged to accommodate the new ECC encoding scheme, resulting in modifications to the physical memory address mapping for corresponding memory addresses and physical memory locations of the given memory device 108, and such data will be rearranged during the ECC reconfiguration as described above.

[0038] After identifying memory locations where data will be relocated for dynamic repartitioning, processor 102 repartitions physical memory map 112 according to the new ECC configuration. Traditionally, repartitioning physical memory map 112 as part of any type of system reconfiguration would require processing system 100 to be rebooted. However, in this example, by dynamically repartitioning physical memory map 112, the ECC reconfiguration is performed without requiring a reboot of processing system 100.

[0039] In another example, the processing system 100 includes interleaving configuration data 116 (e.g., stored as part of a basic input / output system (BIOS)-like structure or table and then loaded into on-chip configuration registers during active operation of the processing system 100) that defines an interleaving pattern (e.g., a coarse-grained interleaving pattern, a fine-grained interleaving pattern, or a combination thereof) according to which physical memory addresses should be distributed across the memory devices 108. Examples of such interleaving patterns are described in more detail below in conjunction with FIGS. 3, 4, and 8. In some embodiments, the interleaving configuration of the processing system 100 is repartitioned such that existing interleaving patterns are replaced with new interleaving patterns. Such changes in the interleaving pattern may be referred to herein as “interleaving reconfiguration.”

[0040] For example, the processor 102 will perform an interleaving reconfiguration of the processing system 100 in response to one or more manual or automatic requests that cause the interleaving configuration data 116 to be modified and a corresponding dynamic repartitioning indicator 118 to be generated. As an example, a manual or automatic request to change the interleaving configuration such that a subset of the memory devices 108 is switched from a fine-grained interleaving configuration to a coarse-grained interleaving configuration causes the processor 102 to generate a corresponding dynamic repartitioning indicator 118 that defines the subset of the memory devices 108 as selected for dynamic repartitioning. The processor 102 then temporarily relocates data stored on the subset of the memory devices 108 to one or more other memory devices 108 (i.e., one or more of the memory devices 108 that are not in the subset of memory devices selected for dynamic repartitioning), the mass storage device 110, or a combination thereof. The processor 102 then repartitions the physical memory map 112 such that the physical addresses associated with the subset of memory devices 108 identified in the physical memory map 112 and selected for dynamic repartitioning are remapped from a fine-grained interleaving configuration to a coarse-grained interleaving configuration in the repartitioned physical memory map 112. In this example, repartitioning the physical memory map 112 advantageously does not require the processing system 100 to be rebooted because, at the time the physical memory map 112 is repartitioned, any data that would typically be affected by modifying or otherwise repartitioning the physical memory map 112 has already been relocated out of the affected memory blocks. The processor 102 then reloads the relocated data onto the memory devices 108 according to the coarse-grained interleaving configuration (now represented by the new physical address mapping of the repartitioned physical memory map 112). The processor 102 also modifies the interleaving configuration data 116 to indicate that the subset of the memory devices 108 is in a coarse grain interleaving configuration rather than a fine grain interleaving configuration.

[0041] Furthermore, in some embodiments, the interleaving reconfiguration involving dynamic repartitioning of the physical memory map 112 is performed by some of the memory devices 108 to which a particular interleaving pattern is applied. In one example, the processor 102 causes the memory devices 108 to be reconfigured from a global fine-grained interleaving pattern, where a single fine-grained interleaving pattern is applied across all of the memory devices 108, to a set of domain-level fine-grained interleaving patterns, where the memory devices 108 are logically organized into different domains, such as domains 120, 122, 124, 126, and respective fine-grained interleaving patterns are applied to the memory devices 108 within each domain. When performing such an interleaving reconfiguration, the processor 102 temporarily rearranges data stored in the memory device 108 to one or more of other memory devices, mass storage devices 110, or a combination thereof, then repartitions the physical memory map 112 according to the new domain level fine-grained interleaving pattern, then reads the rearranged data onto the memory device 108 according to the new domain level fine-grained interleaving pattern, and updates the interleaving configuration data 116 to indicate that the new domain level fine-grained interleaving pattern is applied to the memory device 108.

[0042] In some embodiments, the interleaving reconfiguration to transition from a global fine-grained interleaving configuration to a set of domain-level fine-grained interleaving configurations is performed by the processor 102 in response to the processor 102 identifying a non-uniform memory access (NUMA)-aware workload processed by one or more of the cores 104 of the processor 102. For example, some workloads, in some embodiments, exploit or are otherwise aware of the NUMA configuration employed by the processing system 100. In this example, such workloads are referred to as "NUMA-aware" workloads. Such NUMA-aware workloads are typically optimized to place data in specific physical memory locations based on the expected frequency with which the data will be used and the proximity of the physical memory locations to the processor cores executing the corresponding workload. For example, data that is expected to be used more frequently when executing a NUMA-aware workload is stored in memory devices 108 that are physically closer to the processor cores 104 executing the NUMA-aware workload (i.e., memory devices 108 that are in the same domain as those processor cores 104), while data that is expected to be used less frequently when executing the NUMA-aware workload is stored in memory devices 108 that are physically farther from the processor cores 104 executing the NUMA-aware workload (i.e., memory devices 108 that are in a different domain than the domain of the processor cores 104).

[0043] In some embodiments, one or more memory locations (i.e., memory blocks) of a given memory device are reserved for data that is critical to the operation of processing system 100 (e.g., OS data, page table data, etc.). Such memory locations may be referred to herein as “critical memory locations” or “critical memory blocks.” In some embodiments, dynamic repartitioning is disabled for such critical memory locations because temporarily relocating the data stored therein risks destabilizing the operation of processing system 100. For example, if data in a critical memory location storing OS data is suddenly relocated during dynamic repartitioning, this would likely result in an unexpected shutdown of the processing system or an error that could otherwise impair the functionality of the processing system, since OS data is typically required for the processing system to properly execute the corresponding OS software.

[0044] As another example, consider memory device 108-1 including one or more critical memory locations that store critical data, and dynamic repartitioning of physical memory address mapping is disabled for such critical memory locations. When performing dynamic repartitioning of physical memory map 112 associated with memory device 108, only memory locations of a first subset of memory locations of memory device 108-1 that are not critical memory locations (e.g., storing user data or job data) are identified as eligible for dynamic repartitioning and for corresponding temporary relocation of data stored therein (i.e., dynamic repartitioning is enabled for memory locations of the first subset). In contrast, memory locations of a second subset of memory locations of memory device 108-1 that include critical memory locations are identified as not eligible for dynamic repartitioning and for corresponding temporary relocation of data stored therein (i.e., dynamic repartitioning is disabled for memory locations of the second subset).

[0045] As provided in the previous example, by disabling dynamic repartitioning of physical memory address mappings for critical memory locations, the associated risk of failure of operation of the processing system 100 is mitigated or avoided entirely.

[0046] 2 illustrates a method 200 for dynamically repartitioning physical memory address mappings for a processing system. For ease of illustration, the method 200 is described with respect to an exemplary implementation in the processing system 100 of FIG. 1 and its constituent components and modules.

[0047] At block 202, processor 102 receives a dynamic repartitioning indication, such as an embodiment of dynamic repartitioning indication 118. In some embodiments, the dynamic repartitioning indication is generated as part of a broader system reconfiguration performed by processor 102, such as an ECC reconfiguration or an interleaving reconfiguration. In some embodiments, the dynamic repartitioning indication identifies a subset of memory devices, shown here as 201-1, and one or more memory blocks within each identified memory device that will be involved in the dynamic repartitioning of physical memory map 112. The subset of memory devices 201-1, in some embodiments, corresponds to an example embodiment of a first subset of memory devices 108 of FIG. 1. Data stored in the identified memory blocks will be temporarily relocated during the dynamic repartitioning.

[0048] At block 204, data stored in memory blocks of memory device 201-1 identified by the dynamic repartitioning index is temporarily relocated to another memory device or mass storage device. In some embodiments, relocating this data involves erasing the identified memory blocks of memory device 201-1 (e.g., by writing binary zeros to each of the identified memory blocks). In other embodiments, relocating the data is performed by copying the data to another memory device or mass storage device without erasing the data from memory device 201-1.

[0049] At block 206, the relocated data from the identified memory blocks of memory device 201-1 is stored in one or more of mass storage devices 110, or in a subset of memory devices, shown here as 201-2. The subset of memory devices 201-2, in some embodiments, corresponds to an example embodiment of a second subset of memory devices 108 of FIG. 1 that is different from the first subset of memory devices 108 to which the subset of memory devices 201-1 corresponds. That is, in some embodiments, memory device 201-2 corresponds to one or more of memory devices 108 that were not identified in the dynamic repartitioning index.

[0050] In block 208, the processor 102 reconfigures the processing system 100. According to various examples, the system reconfiguration includes one or more of an ECC reconfiguration, an interleaving reconfiguration, or another reconfiguration of the system that requires the physical memory address mapping of the processing system 100 (i.e., the mapping defined in the physical memory map 112) to be subdivided.

[0051] At block 210, one or more physical address mappings defined in physical memory map 112 are repartitioned in accordance with the system reconfiguration. For example, if the system reconfiguration is an interleaving reconfiguration, an existing interleaving pattern (such as the exemplary fine-grained and coarse-grained interleaving patterns described with reference to FIGS. 3 and 4 below) used to map physical addresses to physical memory blocks is changed to a new interleaving pattern (such as the exemplary fine-grained and coarse-grained interleaving patterns described with reference to FIGS. 3 and 4 below), and one or more of the physical address mappings defined in physical memory map 112 are modified to correspond to the new interleaving pattern. For example, if the system reconfiguration is an ECC reconfiguration, one or more of the physical address mappings defined in physical memory map 112 are modified to correspond to ECC being enabled or disabled or the ECC scheme being changed for one or more of memory devices 201-1. The physical address mappings repartitioned at block 210 correspond to memory blocks identified in the dynamic repartitioning index from which data is relocated at block 204.

[0052] In block 212, after the physical address mapping defined in the physical memory map 112 is repartitioned, the relocated data stored in one or more of the mass storage device 110 or the memory device 201-2 is reloaded onto the memory device 201-1 according to the repartitioned physical address mapping. In some embodiments, instead of moving the relocated data back to the memory device 201-1 in block 212, the relocated data instead remains stored in the memory device 201-2, and the memory device 201-1 remains empty except for the new memory allocation. In some embodiments, the relocated data is moved back onto the memory device 201-1 from the memory device 201-2 opportunistically, not during the reconfiguration process. In this example, repartitioning the physical memory map 112 advantageously does not require the processing system 100 to be rebooted. In block 214, the memory device 201-1 stores the previously relocated data according to the new physical address mapping.

[0053] FIG. 3 is a diagram 300 illustrating a fine-grained interleaving pattern for accessing four memory devices in a processing system, such as processing system 100 of FIG. 1. In this example, the fine-grained interleaving pattern is applied to memory devices 108-1, 108-2, 108-3, and 108-4. Path 302 represents the order in which data is written to memory blocks, such as memory block 304, of memory devices 108-1 through 108-4 according to the fine-grained interleaving pattern. The illustrated fine-grained interleaving pattern is one example of an interleaving configuration defined, for example, in an embodiment of interleaving configuration data 116. In some embodiments, dynamic repartitioning of the physical memory address mapping of processing system 100 is performed in conjunction with changing the interleaving configuration of processing system 100 to or from the example fine-grained interleaving pattern or another similar fine-grained interleaving pattern.

[0054] For example, when data is transmitted for storage in memory devices 108-1-108-4, the data is divided into blocks and adjacent blocks are stored contiguously in memory devices 108-1-108-4. Here, "adjacent" blocks of data refer to adjacent divisions of data within an ordered array of data of a data set (e.g., a file) that are to be stored in adjacent physical memory addresses. As an example, a data file stored by processing system 100 and arranged as an ordered array of data is logically divided into blocks of data and the blocks of data are designated for storage across a range of adjacent physical memory addresses such that a first block of data is stored at a first physical memory address and a second block of data adjacent to the first block of data is stored at a second memory address adjacent to the first physical memory address. When the processing system 100 is configured to implement a fine-grained interleaving pattern for the first and second physical memory addresses, the first block of data and the second block of data are stored in different memory devices of the memory device 108 according to the fine-grained interleaving pattern, despite being adjacent data blocks and stored in adjacent physical memory addresses.

[0055] For example, if five adjacent blocks of data that would fill five blocks of memory are to be stored in memory devices 108-1 through 108-4, the five blocks of data are stored contiguously in a first memory block of memory device 108-1, a first memory block of memory device 108-2, a first memory block of memory device 108-3, a first memory block of memory device 108-4, and a second memory block of memory device 108-1, respectively. In general, fine-grained interleaving provides rapid access to the memory devices by a processor that can access all of memory devices 108-1 through 108-4 with similar access speeds.

[0056] FIG. 4 is a diagram 400 illustrating a coarse-grained interleaving pattern for accessing four memory devices in a processing system, here corresponding to an embodiment of the processing system 100 of FIG. 1. In this example, the coarse-grained interleaving pattern is applied to memory devices 108-1, 108-2, 108-3, and 108-4. Path 402 represents the order in which data is written to memory blocks, such as memory block 404, of memory devices 108-1 through 108-4 according to the coarse-grained interleaving pattern. The illustrated coarse-grained interleaving pattern is one example of an interleaving configuration defined, for example, in an embodiment of interleaving configuration data 116. In some embodiments, dynamic repartitioning of the physical memory address mapping of the processing system 100 is performed in conjunction with changing the interleaving configuration of the processing system 100 to or from the example coarse-grained interleaving pattern or another similar coarse-grained interleaving pattern.

[0057] For example, when data is transmitted for storage in memory devices 108-1 through 108-4, the data is divided into blocks and adjacent blocks are stored to consecutively fill each of memory devices 108-1 through 108-4. That is, processor 102 may completely fill a given memory device 108-1 with data before storing the data in the next memory device 108-2, for example. Typically, coarse-grained interleaving is advantageous for processors that cannot access multiple memory devices in parallel with similar access speeds.

[0058] 5 illustrates a method 500 for dynamically repartitioning physical memory address mappings for a processing system in conjunction with modifying an interleaving configuration of the processing system. For ease of illustration, the method 500 is described with respect to an exemplary implementation in the processing system 100 of FIG. 1 and its constituent components and modules.

[0059] At block 502, processor 102 receives a dynamic repartitioning indicator, such as an embodiment of dynamic repartitioning indicator 118. In this example, the dynamic repartitioning indicator is generated as part of an interleaving reconfiguration to be performed by processor 102, where the dynamic repartitioning indicator identifies a first subset of memory devices of memory devices 108 and one or more memory blocks within each identified memory device that will be involved in the dynamic repartitioning of physical memory map 112. Data stored in the identified memory blocks will be temporarily relocated during the dynamic repartitioning.

[0060] At block 504, data stored in memory blocks of the first subset of memory devices identified in the dynamic re-partitioning index is temporarily relocated to one or more mass storage devices of mass storage devices 110, one or more memory devices of a second subset of memory devices of memory devices 108 that were not identified in the dynamic re-partitioning index, or a combination thereof. In some embodiments, relocating this data involves erasing the identified memory blocks of the first subset of memory devices 108 (e.g., by writing binary zeros to each of the identified memory blocks).

[0061] At block 506, the processor 102 reconfigures the interleaving configuration of the processing system 100. For example, the processor 102 updates the interleaving configuration data 116, which defines one or more interleaving patterns according to which physical memory addresses are to be distributed across one or more memory blocks of the memory devices 108 (i.e., in this example, across the identified memory blocks of the first subset of memory devices identified in the dynamic repartitioning indicator).

[0062] At block 508, one or more physical address mappings defined in the physical memory map 112 are repartitioned according to the updated interleaving configuration. In some embodiments, an existing interleaving pattern used to map physical addresses to physical memory blocks is changed to the new interleaving pattern, and one or more of the physical address mappings defined in the physical memory map 112 are modified to correspond to the new interleaving pattern. The physical address mappings repartitioned at block 508 correspond to the memory blocks identified in the dynamic repartitioning index, from which data was relocated at block 504. In this example, repartitioning the physical memory map 112 advantageously does not require the processing system 100 to be rebooted.

[0063] At block 510, after the physical address mapping defined in physical memory map 112 has been re-partitioned, the re-located data is re-loaded onto the first subset of memory devices of memory devices 108 in a pattern corresponding to the re-partitioned physical address mapping (i.e., corresponding to the new interleaving pattern). In some embodiments, at block 510, instead of moving the re-located data onto the first subset of memory devices again, the re-located data instead remains stored in the second subset of memory devices, and the first subset of memory devices remains empty except for the new memory allocation. In some embodiments, the re-located data is moved again from the second subset of memory devices to the first subset of memory devices opportunistically, rather than during a reconfiguration process.

[0064] 6 is a block diagram illustrating an ECC-enabled configuration for four memory devices in a processing system, here corresponding to an embodiment of the processing system 100 of FIG. 1. In this example, the ECC configuration of the processing system 100 (which may be specified in the ECC configuration data 114) causes the memory devices 108-1, 108-2, 108-3, 108-4 to be ECC-enabled. That is, memory blocks 602 of the memory devices 108-1 through 108-4 are available for storing data, such as user data, job data, operating system data, etc., while memory blocks 604 of the memory devices 108-1 through 108-4 are reserved for exclusively storing ECC data used to detect and correct errors in the data stored in the memory blocks 602. In some embodiments, an ECC reconfiguration of the processing system 100 is performed (e.g., by the processor 102), which changes the number of memory blocks of the memory devices 108-1 through 108-4 that are reserved for storing ECC data. In some embodiments, such an ECC reconfiguration disables ECC for memory devices 108-1 through 108-4, such that memory blocks 604 are no longer reserved for storing ECC data, but are instead made available for storing other types of data. As discussed above, changing the ECC configuration of one or more of memory devices 108 typically requires that physical memory map 112 be repartitioned.

[0065] 7 illustrates a method 700 for dynamically repartitioning physical memory address mapping for a processing system in conjunction with modifying the ECC configuration of the processing system. The method 700 is described with respect to an exemplary implementation in the processing system 100 of FIG. 1 and its constituent components and modules.

[0066] At block 702, processor 102 receives a dynamic repartitioning indicator, such as an embodiment of dynamic repartitioning indicator 118. In this example, the dynamic repartitioning indicator is generated as part of an ECC reconfiguration to be performed by processor 102, where the dynamic repartitioning indicator identifies a first subset of memory devices of memory devices 108 and one or more memory blocks within each identified memory device that will be involved in the dynamic repartitioning of physical memory map 112. Data stored in the identified memory blocks will be temporarily relocated during the dynamic repartitioning.

[0067] At block 704, data stored in memory blocks of the first subset of memory devices identified in the dynamic re-partitioning index is temporarily relocated to one or more mass storage devices of mass storage devices 110, one or more memory devices of a second subset of memory devices of memory devices 108 that were not identified in the dynamic re-partitioning index, or a combination thereof. In some embodiments, relocating this data involves erasing the identified memory blocks of the first subset of memory devices 108 (e.g., by writing binary zeros to each of the identified memory blocks).

[0068] At block 706, the processor 102 reconfigures the ECC configuration of the processing system 100. For example, the processor 102 updates the ECC configuration data 114, which defines which memory blocks of the memory device 108 are reserved for storing ECC data. In some embodiments, the update to the ECC configuration data 114 involves reserving new memory blocks of the identified first set of the memory device for storing ECC data. In some embodiments, the update to the ECC configuration data involves canceling an existing reservation of one or more of the memory blocks of the identified first set of the memory device and making such memory blocks available for storing data other than ECC data.

[0069] At block 708, one or more physical address mappings defined in physical memory map 112 are repartitioned in accordance with the updated ECC configuration (e.g., as described in the example above). The physical address mappings repartitioned at block 708 correspond to the memory blocks identified in the dynamic repartitioning index, from which data was relocated at block 704. In this example, repartitioning physical memory map 112 advantageously does not require processing system 100 to be rebooted.

[0070] At block 710, after the physical address mapping defined in physical memory map 112 has been subdivided, the relocated data is read back onto the first subset of memory devices of memory devices 108 in a pattern corresponding to the subdivided physical address mapping (i.e., corresponding to the ECC configuration). In some embodiments, at block 710, instead of moving the relocated data back onto the first subset of memory devices, the relocated data instead remains stored in the second subset of memory devices, and the first subset of memory devices remains empty except for the new memory allocation. In some embodiments, the relocated data is moved back from the second subset of memory devices onto the first subset of memory devices opportunistically, rather than during a reconfiguration process.

[0071] In some embodiments, one or more memory blocks of a given memory device are reserved for critical data, such as OS data or page table data, and cannot be dynamically repartitioned. Figure 8 is a block diagram illustrating an example corresponding to an embodiment of the processing system 100 of Figure 1 in which the physical address mappings for all of the memory devices 108 are dynamically repartitioned, with a subset of the memory blocks in each of the memory devices 108 being omitted from the dynamic repartitioning because they are reserved for critical data storage.

[0072] As shown in this example, prior to dynamic repartitioning, memory devices 108 are in a first interleaving configuration 801, and such data will be stored in memory blocks, such as memory block 802, of memory devices 108-1 through 108-8 according to a fine-grained interleaving pattern represented by path 804. Here, a first set of memory blocks 823 is designated for storing non-critical data, such as job data or user data, while a second set of memory blocks 824 is designated for storing critical data, such as OS data or page table data. Thus, dynamic relocation of physical memory addresses is enabled for the first set of memory blocks 823 and their corresponding physical memory addresses, and disabled for the second set of memory blocks 824 and their corresponding physical memory addresses.

[0073] For example, when the processor 102 performs dynamic repartitioning of the memory device 108 to change the interleaving configuration of the memory device 108 from the first interleaving configuration 801 to the second interleaving configuration 806, only the data (e.g., non-critical data) stored in the first set of memory blocks 823 is rearranged, while the data (e.g., critical data) stored in the second set of memory blocks 824 is not rearranged. Because dynamic repartitioning of physical memory addresses is disabled for the second set of memory blocks 824, the interleaving pattern applied in the second set of memory blocks 824 does not change during such dynamic repartitioning.

[0074] The data stored on the first set of memory blocks 823 is relocated (e.g., by the processor 102) to one or more other memory devices, one or more of the mass storage devices 110, or a combination thereof. The processor 102 then repartitions the physical memory map 112 and modifies the interleaving configuration data 116 according to the new interleaving pattern to be applied in the first set of memory blocks 823 in the second interleaving configuration 806. In this example, repartitioning the physical memory map 112 advantageously does not require the processing system 100 to be rebooted. The temporarily relocated data is then stored in the first set of memory blocks 823 according to the second interleaving configuration 806.

[0075] In this example, the processor logically divides the first set of memory blocks 823 into domains 816, 818, 820, 822 (each corresponding to, for example, domains 120, 122, 124, 126, respectively). In the second interleaving configuration 806, a fine-grained interleaving pattern is applied in each of the domains 816, 818, 820, 822. That is, a first fine-grained interleaving pattern corresponding to the first path 808 is applied in the memory blocks of the memory devices 108-1 and 108-2 included in the first set of memory blocks 823. A second fine-grained interleaving pattern corresponding to the second path 810 is applied in the memory blocks of the memory devices 108-3 and 108-4 included in the first set of memory blocks 823. A third fine-grained interleaving pattern corresponding to a third path 812 is applied in the memory blocks of memory devices 108-5 and 108-6 included in the first set of memory blocks 823. A fourth fine-grained interleaving pattern corresponding to a fourth path 814 is applied in the memory blocks of memory devices 108-7 and 108-8 included in the first set of memory blocks 823. Since the second set of memory blocks 823 were not dynamically repartitioned, their corresponding interleaving patterns remain unchanged in the second interleaving configuration 806. By disabling dynamic repartitioning of physical memory address mappings for critical memory blocks in this manner, the associated risk of failure of operation of the processing system 100 is mitigated or avoided altogether.

[0076] 9 illustrates a method 900 for dynamically repartitioning physical memory address mappings in which only a portion of a memory block within a given memory device is reallocated. The method 900 is described with respect to an exemplary implementation in the processing system 100 of FIG. 1 and its constituent components and modules.

[0077] At block 902, the processor 102 receives a dynamic repartitioning indicator, such as an embodiment of the dynamic repartitioning indicator 118. In this example, the dynamic repartitioning indicator is generated as part of an interleaving reconfiguration to be performed by the processor 102. Here, the dynamic repartitioning indicator identifies a set of physical addresses corresponding to a first set of memory blocks of a memory device of the memory device 108 that will be involved in the dynamic repartitioning of the physical memory map 112. In this example, the memory device includes a second set of memory blocks that are not identified in the dynamic repartitioning indicator. In some embodiments, one or more memory blocks of the second set of memory blocks are reserved for storing critical data, and dynamic repartitioning of physical memory addresses associated with such memory blocks is disabled. Data stored in the first set of memory blocks associated with the identified set of physical addresses is to be temporarily relocated during the dynamic repartitioning.

[0078] At block 904, the data stored in the first set of memory blocks is temporarily relocated to one or more mass storage devices in mass storage device 110, one or more other memory devices in memory device 108, or a combination thereof. In some embodiments, relocating this data involves erasing the memory blocks in the first set of memory blocks (e.g., by writing binary zeros to each of the memory blocks in the first set of memory blocks). The data stored in the second set of memory blocks is not relocated at block 904 because no dynamic reconfiguration of physical memory address mapping is performed for the second set of memory blocks.

[0079] In block 906, the processor 102 reconfigures the processing system 100. According to various examples, the system reconfiguration includes one or more of an ECC reconfiguration, an interleaving reconfiguration, or another reconfiguration of the system that requires the physical memory address mapping of the processing system 100 (i.e., the mapping defined in the physical memory map 112) to be subdivided.

[0080] At block 908, one or more physical address mappings defined in the physical memory map 112 are repartitioned according to the system reconfiguration. For example, if the system reconfiguration is an interleaving reconfiguration, an existing interleaving pattern used to map physical addresses to the first set of memory blocks is changed to a new interleaving pattern, and one or more of the physical address mappings defined in the physical memory map 112 are modified to correspond to the new interleaving pattern. For example, if the system reconfiguration is an ECC reconfiguration, one or more of the physical address mappings defined in the physical memory map 112 are modified to correspond to ECC being enabled or disabled or an ECC scheme being changed for one or more of the first set of memory blocks. The physical address mappings repartitioned at block 908 correspond to the physical addresses identified in the dynamic repartitioning index. In this example, repartitioning the physical memory map 112 advantageously does not require the processing system 100 to be rebooted. In block 910, after the physical address mapping defined in the physical memory map 112 is subdivided, the relocated data is reloaded onto the first set of memory blocks of the memory device according to the subdivided physical address mapping.

[0081] In some embodiments, the above apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing system 100 described above with reference to FIG. 1. Electronic design automation (EDA) and computer aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system for operating the computer system to operate on code representing circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC devices is stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

[0082] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0083] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0084] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0085] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. A method comprising: Storing first data in a first set of memory blocks of a first memory device; without rebooting the first memory device; storing the first data in a second set of memory blocks of a plurality of memory devices; and repartitioning at least one physical memory map associated with the first memory device to generate at least one subdivided physical memory map that maps memory addresses associated with the first data to the second set of memory blocks. method.

2. including inhibiting subdivision of the third set of memory blocks in response to an indication that the third set of memory blocks stores critical data.

10. The method of claim 1.

3. The critical data includes operating system (OS) data, page table data, or both. The method of claim 2.

4. The repartitioning of the at least one physical memory map is performed in connection with a change in a system configuration of a processing system.

10. The method of claim 1.

5. redividing the at least one physical memory map includes changing a mapping for a first physical address defined by the at least one physical memory map; the at least one physical memory map mapping the first physical address to a first memory block of the first set of memory blocks; the at least one subdivided physical memory map mapping the first physical address to a second memory block of the second set of memory blocks; 10. The method of claim 1.

6. 1. A processing system comprising: a first memory device for storing first data in a first set of memory blocks; at least one processor configured to execute instructions without rebooting the first memory device; The instruction: storing the first data in a second set of memory blocks of a plurality of memory devices; repartitioning at least one physical memory map associated with at least some of the plurality of memory devices to generate at least one subdivided physical memory map that maps memory addresses associated with the first data to the second set of memory blocks; causing the at least one processor to perform Processing system.

7. the instructions cause the at least one processor to disable subdivision of the third set of memory blocks in response to an indication that the third set of memory blocks stores critical data. The processing system of claim 6.

8. the instructions cause the at least one processor to repartition the at least one physical memory map based at least in part on a change in a system configuration of the processing system. The processing system of claim 6.

9. the system configuration change corresponds to a change to an error correction code (ECC) configuration of the processing system, the ECC configuration identifying ECC memory blocks of the plurality of memory devices that are reserved for storing ECC data; The processing system of claim 8.

10. the change in the system configuration corresponds to a change in an interleaving configuration of the processing system, the interleaving configuration defining at least one interleaving pattern in which data is stored in the second set of memory blocks. The processing system of claim 8.

11. the alteration of the interleaving configuration corresponds to replacing a first interleaving pattern with a second interleaving pattern, and the at least one subdivided physical memory map reflects the second interleaving pattern. The processing system of claim 10.

12. the instructions cause the at least one processor to modify a mapping for a first physical address defined by the at least one physical memory map to subdivide the at least one physical memory map; the at least one physical memory map mapping the first physical address to a first memory block of the first set of memory blocks; the at least one subdivided physical memory map mapping the first physical address to a second memory block of the second set of memory blocks; The processing system of claim 6.

13. A first memory device having a first memory block in which first data is stored; at least one processor configured to execute instructions without rebooting the first memory device; The instruction: storing the first data in a second memory block of a plurality of memory devices; repartitioning at least one physical memory map associated with at least some of the plurality of memory devices to generate at least one subdivided physical memory map that maps memory addresses associated with the first data to the second memory blocks; causing the at least one processor to perform system.

14. storing the first data in the second memory block includes transmitting the first data to at least some of the plurality of memory devices and transmitting the first data from at least some of the plurality of memory devices to the second memory block; The system of claim 13.

15. The instructions cause the at least one processor to repartition the physical memory map in connection with a change in system configuration of the system. The system of claim 13.

16. The system configuration change corresponds to a change in an error correcting code (ECC) configuration of the system, the ECC configuration identifying ECC memory blocks of the first memory device that are reserved for storing ECC data.

16. The system of claim 15.

17. The instructions cause the at least one processor to modify a mapping for a first physical address defined by the at least one physical memory map to subdivide the physical memory map; the physical memory map associating the first physical address with the first memory block; the subdivided physical memory map associating the first physical addresses with the second memory blocks; The system of claim 13.

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