COMPOSITE STRUCTURE COMPRISING A FUNCTIONAL LAYER OF SINGLE CRYSTALLINE SIC ON A CARRIER SUBSTRATE OF POLYCRYSTALLINE SIC AND PROCESS FOR MANUFACTURING SUCH STRUCTURE - Patent application

Abstract

The invention relates to a process for manufacturing a composite structure comprising a functional layer of monocrystalline silicon carbide deposited on a carrier substrate of polycrystalline silicon carbide, comprising the steps of: a) providing an initial substrate of polycrystalline silicon carbide containing grains of average size greater than 0.5 μm in the plane of its front side; b) forming a surface layer of polycrystalline silicon carbide on the initial substrate to form a carrier substrate, the surface layer being made of grains of average size smaller than 500 nm and having a thickness of 50 nm to 50 μm; c) conditioning the free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; and d) transferring the functional layer to the carrier substrate on the basis of molecular bonding. The invention further relates to a composite structure comprising a carrier substrate of polycrystalline silicon carbide and a functional layer of monocrystalline silicon carbide.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductors for microelectronic components. In particular, it relates to a composite structure with a functional layer made of monocrystalline silicon carbide applied to a carrier substrate made of polycrystalline silicon carbide and a process for manufacturing said structure. The invention also relates to a carrier substrate made of polycrystalline silicon carbide. [Background technology]

[0002] SiC is being increasingly used to manufacture innovative power devices to meet the needs of a growing field of electronic applications, especially electric vehicles.

[0003] Power devices and integrated power systems based on single crystal silicon carbide are capable of managing much higher power densities than conventional silicon equivalents, and can do so with smaller sized active areas. To further limit the dimensions of power devices on SiC, it would be advantageous to fabricate vertical rather than lateral components. To do this, the SiC structure must allow vertical electrical conduction between electrodes placed on the front side and the back side of the structure.

[0004] Nevertheless, single crystal SiC substrates intended for the microelectronics industry remain expensive and difficult to supply in large sizes. It is therefore advantageous to employ thin layer transfer solutions to fabricate composite structures that typically comprise a thin layer (lamina) of single crystal SiC (c-SiC) on an inexpensive single crystal (c-SiC) or polycrystalline (p-SiC) carrier substrate. One well-known thin layer transfer solution is the Smart Cut® process, which is based on implanting light ions and bonding by direct bonding at the bonded interface. The bonded interface is designed to have the lowest possible resistivity, preferably below 1 mohm.cm. 2 Lower than or even 0.1mohm.cm 2It must have a resistivity lower than

[0005] Many prior art solutions propose using conductor-conductor bonding based on a metal layer deposited on the surfaces to be bonded. For example, the publication by Letertre ("Silicon carbide and related materials", Material Science Forum - volumes 389-393, April 2002) or the document US Pat. No. 7,208,392 describe the deposition of a layer of tungsten and a layer of silicon to form a conductive intermediate layer based on tungsten silicide (WSi2). One drawback of this approach may result from the formation of voids in this intermediate layer due to the shrinkage of the silicide relative to the initially deposited material, which may affect, among other things, the quality of the surface semiconductor layer and possibly the entire semiconductor structure. In addition, with this type of intermediate layer, it is difficult to reduce the resistivity of the bonding interface to the level required by some applications that require very good vertical electrical conductivity.

[0006] Direct bonding of the SiC surfaces of the functional layer and the carrier substrate can also be envisaged, but this remains difficult, especially when polycrystalline carrier substrates are involved, and the question is then how to transfer a monocrystalline functional layer by direct bonding with the required bonding interface quality (low defect density, high bonding energy, very low resistivity). G. Chichignoud et al. ("Processing of poly-SiC substrate with large grains for wafer bonding" - Materials Science Forum, vol. 527-529, pp. 71-74 (2006)) propose to transfer a monocrystalline SiC layer to a polycrystalline SiC carrier substrate, which has thermal and electrical properties favorable for power microelectronic applications, as well as physical properties (surface roughness, curvature) comparable to direct bonding. The grains of the SiC polycrystals are selected to be large in size (typically larger than 1 cm in size), and chemical-mechanical polishing, performed to condition the surface before bonding, allows an average roughness of less than 5 nm to be obtained.

[0007] The document EP 3441506 provides a p-SiC carrier substrate onto which a c-SiC semiconductor layer can be transferred via direct bonding. The carrier substrate has grains of an average size of the order of 10 μm and exhibits a degree of variation in grain size between the front and rear sides of the carrier substrate of less than 0.43% divided by the thickness of the carrier substrate, the latter feature making it possible to limit the residual stresses in the carrier substrate and therefore the curvature of the carrier substrate. An average roughness of less than 1 nm is realized on the surface of the carrier substrate which is to be bonded to the layer made of c-SiC.

[0008] Using carrier substrates made of p-SiC such as those proposed in the two documents mentioned above, the Applicant has nevertheless observed residual relief (recesses or bumps) due to anomalous removal of the intergrain regions or pull-out of all or part of the surface grains, which has a detrimental effect on the quality of the bonding interface (bonding defects) and therefore on the overall performance of the resulting composite structure. Summary of the Invention

[0009] The present invention aims to overcome all or part of the aforementioned drawbacks and provides an alternative to the prior art solutions.The present invention relates to a process for manufacturing a composite structure comprising a functional layer made of monocrystalline SiC transferred to a carrier substrate made of polycrystalline SiC, the invention also relates to said carrier substrate and to the composite structure obtained.

[0010] The invention relates to a process for manufacturing a composite structure comprising a functional layer made of monocrystalline silicon carbide applied to a carrier substrate made of polycrystalline silicon carbide, the process comprising: a) providing an initial substrate made of polycrystalline silicon carbide having a front side and including grains of an average size greater than 0.5 μm in the plane of said front side; b) forming a surface layer of polycrystalline silicon carbide on the initial substrate to form the carrier substrate, the surface layer being made of grains with an average size smaller than 500 nm and having a thickness comprised between 50 nm and 50 μm; c) conditioning the free surface of the surface layer of the carrier substrate to obtain a roughness smaller than 1 nm RMS; d) transferring the functional layer onto the carrier substrate based on molecular bonding, the surface layer being located between the functional layer and the initial substrate; The present invention relates to a process including the steps of:

[0011] According to other advantageous, non-limiting features of the invention, which can be applied individually or in any technically feasible combination, Step a) is carried out using a chemical vapor deposition technique at a temperature comprised between 1100° C. and 1500° C., Step a) is carried out using a sintering technique or using a physical vapor deposition technique, step b) comprises depositing a layer of polycrystalline silicon carbide, carried out using a chemical vapor deposition technique at a temperature below 1100° C., or even below 1000° C., Step b) is carried out subsequent to step a) with the same items of equipment as step a) and without returning said initial substrate to an air atmosphere, step b) comprises depositing a layer of amorphous silicon carbide on the initial substrate and performing a recrystallization anneal to form said surface layer of polycrystalline silicon carbide; The surface layer formed in step b) has a surface roughness of 1E18 / cm 3 and 1E21 / cm 3 and having a dopant concentration inclusive of step c) comprises chemical-mechanical polishing of the surface layer with removal of an amount comprised between 1 and 10 times the average size of the grains making up the surface layer; Step d) is the next step, d1) providing a donor substrate; d2) introducing light element species into the donor substrate in order to form a buried plane of weakness that defines the functional layer to be transferred on the front side of the donor substrate; d3) bonding the front side of the donor substrate to the carrier substrate by molecular bonding; d4) peeling along the embedded plane of weakness resulting in transfer of the functional layer to the carrier substrate. Including, the manufacturing process comprises, before or after step d2), forming a second surface layer of the same nature as the surface layer on the front side of the donor substrate, Step d) may comprise, prior to bonding step d3), depositing an additional film of metal or silicon on the surface layer of the carrier substrate and / or on the front side of the donor substrate.

[0012] The present invention provides a carrier substrate made of polycrystalline silicon carbide, comprising: an initial substrate comprising silicon carbide grains, said grains having an average size greater than 0.5 μm; a surface layer provided at least on the front side of the initial substrate, the surface layer comprising silicon carbide grains having an average size smaller than 500 nm and having a thickness comprised between 50 nm and 50 μm; The present invention also relates to a carrier substrate comprising:

[0013] According to other advantageous, non-limiting features of the invention, which can be applied individually or in any technically feasible combination, The free surface of said surface layer has a roughness of less than 1 nm RMS and less than 1 defect / cm2 as measured by reflective dark field microscopy with a threshold of 0.5 μm. 2 has less than the thickness of said surface layer is comprised between 200 nm and 5 μm, The surface layer has a thickness of 1E18 / cm 3 and 1E21 / cm 3 and a dopant concentration inclusive.

[0014] Finally, the present invention provides a composite structure comprising: a carrier substrate as described above; A functional layer made of single crystal silicon carbide installed on the surface layer. The present invention relates to a composite structure comprising:

[0015] The composite structure may further comprise at least one power device on or in said functional layer. [Brief description of the drawings]

[0016] Other features and advantages of the invention will become apparent from the following detailed description of the invention, which proceeds with reference to the accompanying drawings. [Figure 1] FIG. 1 illustrates a composite structure produced using a manufacturing process according to the invention. [Figure 2a] 1A-1D illustrate steps of a manufacturing process according to the invention. [Figure 2b] 1A-1D illustrate steps of a manufacturing process according to the invention. [Figure 2c] 1A-1D illustrate steps of a manufacturing process according to the invention. [Figure 2d] 1A-1D illustrate steps of a manufacturing process according to the invention. [Figure 3a] FIG. 1 shows the steps of one preferred embodiment of the manufacturing process according to the invention. [Figure 3b] FIG. 1 shows the steps of one preferred embodiment of the manufacturing process according to the invention. [Figure 3c] FIG. 1 shows the steps of one preferred embodiment of the manufacturing process according to the invention. [Figure 3d] FIG. 1 shows the steps of one preferred embodiment of the manufacturing process according to the invention.

[0017] The same reference signs in several figures may be used for the same type of elements. The figures are schematic representations that are not drawn to scale for ease of reading. In particular, the thickness of the layers along the z-axis is not to scale with respect to the lateral dimensions along the x- and y-axes; the relative thicknesses of the layers with respect to one another need not necessarily be respected in the figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The invention relates to a process for manufacturing a composite structure 100 (FIG. 1) comprising a functional layer 10 made of monocrystalline silicon carbide ("c-SiC" will be used below to designate monocrystalline silicon carbide) mounted on a carrier substrate 20. The carrier substrate 20 is made of polycrystalline silicon carbide ("p-SiC" will be used to designate polycrystalline SiC). It will be noted that for the fabrication of microelectronic components on and / or in the functional layer 10 of the composite structure 100, it is usually desirable to have a silicon face for the free side of the functional layer 10 made of c-SiC.

[0019] The process first comprises a step a) of providing an initial substrate 21 made of polycrystalline silicon carbide, said substrate giving its mechanical properties to the carrier substrate 20 (FIG. 2a). In other words, the initial substrate 21 represents the majority of the thickness of the carrier substrate 20. It preferably takes the form of a wafer of 100 mm or 150 mm diameter, or even 200 mm, having a front side 21a and a back side 21b, and of a thickness typically comprised between 200 μm and 800 μm.

[0020] The polycrystalline initial substrate 21 comprises grains of 4H, 6H and / or 3C silicon carbide. The grains have an average size in the plane of the front side 21a greater than 0.5 μm, typically comprised between 1 μm and 10 μm. The size of the grains, defined by the grain boundaries, corresponds to the largest dimension of said grains in the plane of the front side 21a. The average size of the grains is defined by the average of the sizes of the various grains in the plane of the front side 21a. Grains of very small size, typically smaller than 50 nm, are preferably excluded from the measurement in order to limit the measurement uncertainty. It can be based on measurements of the grain dimensions or the distance between the grain boundaries on images obtained by conventional scanning electron microscopy (SEM) or including electron backscatter diffraction (EBSD). It is also conceivable to use X-ray crystallography methods.

[0021] Large dimensions of p-SiC grains favor good thermal conductivity and are therefore preferred for the initial substrate 21. For the targeted application (vertical electronic components), a thermal conductivity higher than 200 W / m / K and preferably higher than 250 W / m / K, and a resistivity lower than 10 mohm.cm and preferably lower than 5 mohm.cm are expected from the carrier substrate 20; such electrical and thermal properties are therefore selected for the initial substrate 21. The initial substrate 21 has a thermal conductivity of 1E18 / cm 3 and 1E21 / cm 3 Including between 1E19 / cm 3 and 1E20 / cm 3 Although p-type and n-type dopants are envisioned, it is common to employ n-type dopants, such as nitrogen dopants, for electronic devices that will be fabricated in the composite structure 100.

[0022] Step a) may be carried out using known prior art techniques such as sintering, physical vapor deposition (PVD) or even chemical vapor deposition (CVD). Sintered substrates are advantageous due to their relatively limited cost. The CVD technique is advantageous in that it allows to obtain high quality p-SiC substrates of large diameter; the deposition is preferably carried out at temperatures comprised between 1100°C and 1500°C.

[0023] The applicant has carried out many attempts of treatments to condition the surface of the initial substrate 21, such as those mentioned above, with the aim of transferring a functional layer to the front side 21a of the initial substrate. The typical initial RMS roughness of the front side of the initial substrate 21 can vary from a few nanometers to a few microns (as measured by Atomic Force Microscopy (AFM) on a 20 μm×20 μm scan) depending on the fabrication technique and the smoothing treatment applied by the supplier. Chemical-mechanical polishing is required to reduce this roughness (which needs to be less than 1 nm RMS, or even less than 0.5 nm RMS) to ensure a good quality direct molecular bond and therefore a good quality transferred functional layer.

[0024] It is known that SiC is a difficult material to polish due to its hardness. The applicant has further observed that polishing a surface made of p-SiC locally pulls out grains or segments of grains, leaving voids and other defects in the polished surface. Even if very locally the required roughness value may be reached after polishing, on the scale of the substrate the density of voids and other surface defects remains high.

[0025] To address this problem involving defect density, the manufacturing process according to the invention comprises a step b) of forming on the initial substrate 21 a surface layer 22 of polycrystalline silicon carbide of a specific morphology in order to make it possible to tailor a surface suitable for high-quality molecular bonding without significantly degrading the thermal and electrical properties expected from the carrier substrate 20 (FIG. 2b). The formed carrier substrate 20 comprises the initial substrate 21 and the surface layer 22 and has a front side 22a (the free side of the surface layer 22) and a back side 21b (the back side of the initial substrate 21).

[0026] It will be noted that a layer of the same nature as the surface layer 22 may optionally also be deposited on the back side 21b of the initial substrate 21 (not shown), in particular to avoid affecting the curvature of the initial substrate 21.

[0027] The surface layer 22 is formed on the front side 21a of the initial substrate 21 without a preceding polishing step; the roughness of the initial substrate 21 at the time of deposition of step b) is therefore typically comprised between 10 nm and 3000 nm RMS.

[0028] The thickness of the surface layer 22, comprised between 50 nm and 50 μm, and typically comprised between 100 nm and 5 μm, is adjusted depending on the roughness of the initial substrate 21. For a roughness of said substrate 21 of about 15 nm RMS, the thickness of the surface layer 22 is preferably chosen between 200 nm and 500 nm.

[0029] The surface layer 22 is composed of grains of 4H, 6H and / or 3C silicon carbide. These grains have an average size smaller than 500 nm, or even smaller than 100 nm, and typically comprised between 10 nm and 100 nm. The size of the grains, defined by the grain boundaries, corresponds to the maximum dimension of said grains in the plane of the free surface of the surface layer 22. The average size of the grains is defined by the average of the sizes of the various grains in said plane.

[0030] The p-SiC surface layer 22 has a thickness of 1E18 / cm 3 and 1E21 / cm 3 Including between 1E19 / cm 3 and 1E20 / cm 3 The doping type and level of the surface layer 22 is generally selected to be the same as or higher than that of the initial substrate 21, respectively.

[0031] According to a first embodiment, step b) comprises depositing silicon carbide in polycrystalline form to form the surface layer 22 .

[0032] Advantageously, said deposition is carried out using chemical vapor deposition techniques, in particular at low pressure (LPCVD) and at temperatures below 1100° C., or even below 1000° C. By lowering the deposition temperature, surface diffusion is reduced and the number of nucleation sites is increased, which promotes the formation of very small p-SiC grains. Since the thickness of the surface layer 22 generally remains small (typically smaller than 5 μm), the average size of the grains can easily be kept smaller than 500 nm, or even smaller than 100 nm.

[0033] The precursors may be selected from methylsilane, dimethyldichlorosilane, preferably with a C / Si ratio greater than 1, or even dichlorosilane and i-butane.

[0034] Of course, other temperatures may be performed for p-SiC deposition, provided that the aforementioned grain sizes are respected, for example temperatures lower than 1400° C.

[0035] Although step b) has been described as being performed on the initial substrate 21 at the end of step a), it is envisaged that it may be performed using the same deposition technique and with the same items of equipment as step a), without returning the initial substrate 21 to the air atmosphere following step a).

[0036] According to a second embodiment, step b) comprises depositing silicon carbide in amorphous form to form the surface layer 22, then carrying out an annealing to recrystallize it into polycrystalline form.

[0037] The amorphous SiC may be deposited using chemical vapor deposition (e.g. plasma enhanced chemical vapor deposition (PECVD) or direct liquid injection chemical vapor deposition (DLI-CVD)) techniques, using physical vapor deposition techniques, or using any other known technique. A recrystallization anneal is then carried out at a temperature typically higher than 900°C, and preferably higher than 1100°C, higher than 1200°C or even higher than 1400°C. This anneal is carried out in order to obtain a surface layer 22 composed of grains of 4H, 6H and / or 3C silicon carbide having an average size smaller than 500 nm, or even smaller than 100 nm, typically comprised between 10 nm and 100 nm.

[0038] Returning to the general description of the process, the second half then comprises a step c) of conditioning the free surface 22a of the surface layer 22 to obtain a roughness less than or equal to 1 nm RMS, advantageously less than or equal to 0.5 nm RMS (FIG. 2c).

[0039] Step c) can be carried out in various ways: Chemical smoothing (dry or wet etching) By heat treatment in a temperature range and atmosphere that are easy to smooth the surface of the surface layer 22, Chemical mechanical polishing using conventional silicon carbide polishing processes Or even by mechanical polishing (fine grinding) It may be executed.

[0040] With reference to the latter option, it is preferred that the nanoscale size of the p-SiC grains in the surface layer 22 is much smaller than the typical planarization length of chemical mechanical polishing techniques, which is of the order of 1 μm.

[0041] When step c) is based on chemical mechanical polishing of the surface layer 22, it typically involves removing an amount comprised between 1 and 10 times the average size of the grains of the surface layer 22, depending on the roughness of the initial substrate 21 and the deposited thickness of the surface layer 22.

[0042] Step c) allows roughnesses of 1 nm RMS or less, preferably 0.5 nm RMS or less, for example about 0.1 nm to 0.5 nm RMS, to be obtained in a spatial wavelength range ranging from tens of nanometers to tens of microns. After smoothing, a conventional cleaning (chemical cleaning, possibly with brush scrubbing) is applied to the carrier substrate 20. The defect density level obtained is 10 defects / cm, as measured by reflected dark field microscopy, with a threshold of 0.5 μm. 2 Fewer than 1 defect / cm 2 Less than, very low.

[0043] The process finally comprises step d) of transferring the functional layer 10 made of monocrystalline silicon carbide to a carrier substrate 20 based on molecular bonding, the surface layer 22 then being located between the functional layer 10 and the initial substrate 21 (Figure 2d).

[0044] It will be noted that a second surface layer may be formed on the side of the functional layer 10 that is to be bonded to the carrier substrate 20 prior to molecular bonding. This has the advantage that several layers of the same nature (surface layer 22 and second surface layer), i.e. several layers of p-SiC nanograins, are bonded; such a configuration allows the quality of the direct bonding to be improved.

[0045] Various methods of layer transfer are known in the art and will not be described exhaustively here.

[0046] According to one preferred embodiment, step d) of the process comprises implanting light element species according to the principles of the Smart-Cut® process.

[0047] In a first step d1), a donor substrate 1 made of monocrystalline silicon carbide is prepared (FIG. 3a) on which the functional layer 10 will be obtained. The donor substrate 1 preferentially takes the form of a wafer with a diameter of 100 mm or 150 mm or even 200 mm (identical to the diameter of the carrier substrate 20) and a thickness typically comprised between 300 μm and 800 μm. The donor substrate has a front side 1a and a back side 1b. The surface roughness of the front side 1a is advantageously selected to be smaller than 1 nm RMS, or even smaller than 0.5 nm RMS, as measured by atomic force microscopy (AFM) on a 20 μm×20 μm scan. The front side 1a of the donor substrate 1 will be selected to have a carbon surface, so as to obtain a free silicon surface for the functional layer 10 of the composite structure 100. The donor substrate 1 may be of 4H or 6H polytype and may have n-type or p-type doping depending on the requirements of the components to be fabricated on and / or in the functional layer 10 of the composite structure 100.

[0048] The second step d2) corresponds to the introduction of light element species into the donor substrate 1 in order to form a buried weak plane 11 defining the functional layer 10 to be transferred on the front side of the donor substrate 1 (Figure 3b).

[0049] Light element species, preferentially hydrogen, helium or a co-implantation of these two ion species, are implanted into the donor substrate 1 to a given depth that corresponds to the targeted thickness of the functional layer 10. These light element species will form microcavities in the vicinity of the given depth, distributed as a thin layer parallel to the free surface 1a of the donor substrate 1, i.e. parallel to the plane (x,y) in the figure. This thin layer is called, for simplicity, the buried plane of weakness 11.

[0050] The energy of the implantation of the light element species is selected to reach a given depth. For example, hydrogen ions are implanted at 500 nm with energies comprised between 10 keV and 250 keV to define a functional layer 10 having a thickness of about 100 nm to 1500 nm. E 16 / cm 2 and 1 E 17 / cm 2 and . It will be noted that a protective layer will likely be deposited on the front side 1a of the donor substrate 1 prior to the ion implantation step. This protective layer may for example be made of a material such as silicon oxide or silicon nitride. The protective layer is removed prior to the next step.

[0051] Optionally, as mentioned above, a second surface layer (of the same nature as the surface layer 22) may be formed on the front side 1a of the donor substrate 1 before or after the second step d2) of introducing light element species. This second surface layer may possibly be formed and conditioned under the aforementioned conditions of steps b) and c).

[0052] In the case where the second surface layer is formed before step d2), the implantation energy (and possibly the dose) of the light element species will be adjusted so that the light element species penetrates this additional layer. In the case where the second surface layer is formed after step d2), care will be taken to form this second surface layer with a thermal budget smaller than the blistering thermal budget, which corresponds to the growth of microcavities in the embedded plane of weakness 11 and the appearance of bubbles at the surface of the donor substrate 1 as a result of overpressurization.

[0053] The transferring step d) then comprises a third step d3) of bonding the front side 1a of the donor substrate 1 to the front side 22a of the carrier substrate 20 by molecular bonding along the bonding interface 3 (FIG. 3c).

[0054] As is known per se, direct molecular bonding does not require adhesives since the bond forms on an atomic scale between the surfaces to be bonded. There are several types of molecular bonding, which differ notably in their conditions in terms of temperature, pressure or atmosphere, or in terms of the treatment carried out before the surfaces are brought into contact. Mention may be made to lamination at room temperature with or without previous plasma activation of the surfaces to be bonded, atomic diffusion bonding (ADB), surface activated bonding (SAB), etc.

[0055] The bonding step d3) may include a conventional sequence of chemical cleaning (e.g. RCA cleaning) and surface activation (e.g. with oxygen or nitrogen plasma) or other surface preparation (such as brush scrubbing) that possibly enhances the quality of the bonding interface 3 (low defect density, high adhesion energy) before the sides 1a, 22a to be bonded are brought into contact.

[0056] The low defect density and roughness level of the front side 22a of the carrier substrate 20 (due to the surface conditioning of the surface layer 22) is particularly advantageous with regard to obtaining a high quality bonding interface 3. In the case where the donor substrate 1 further comprises a second surface layer of the same nature as the surface layer 22 of the carrier substrate 20, the quality of the direct bonding may be further improved since two surfaces of the same polycrystalline nature or even the same polytype, preferably 3C, are joined.

[0057] Optionally, step d) comprises, before the bonding step d3), depositing an additional film of metal or amorphous or polycrystalline silicon on the prepared front side 22a of the surface layer 22 and / or on the front side of the donor substrate 1. The metal may possibly be chosen from tungsten, nickel, titanium, etc. As the surface roughness of the free side 22a of the surface layer 22 is very small, the thickness of this additional film is advantageously limited, typically between a few nanometers and a few tens of nanometers. Its purpose is to essentially increase the bonding energy (especially at intermediate temperatures below 1100° C.), this increase being due to the formation of covalent bonds at lower temperatures than is the case for two directly bonded SiC surfaces, another advantage of this additional film may be to improve the vertical electrical conduction of the bonding interface 3.

[0058] Finally, a fourth step d4) comprises a peel along the embedded plane of weakness 11, which results in the transfer of the functional layer 10 to the carrier substrate 20 (FIG. 3d).

[0059] The delamination along the embedded plane of weakness 11 is usually carried out by applying a heat treatment at a temperature comprised between 800 ° C. and 1200 ° C. Such a heat treatment causes cavities and microcracks to develop in the embedded plane of weakness 11, which are pressurized by light element species present in gaseous form until the cracks propagate along said plane of weakness 11. Alternatively or in conjunction, a mechanical stress may be applied to the bonded assembly, in particular to the embedded plane of weakness 11, in order to propagate or to promote the mechanical propagation of the cracks that lead to the delamination. At the end of this delamination, a semiconductor structure 100 is obtained, which comprises, on the one hand, the carrier substrate 20 and the transferred functional layer 10 made of monocrystalline SiC, and, on the other hand, the remainder 1' of the donor substrate. The level and type of doping of the functional layer 10 is determined by the choice of the characteristics of the donor substrate 1 or may be adjusted later by known techniques for the doping of semiconductor layers.

[0060] The free surface 10a of the functional layer 20 is usually rough after the peeling. For example, it has a roughness comprised between 5 nm and 100 nm RMS (AFM, 20 μm×20 μm scan). Cleaning and / or smoothing steps may be applied to regain a good surface finish (typically less than 2-3 Angstroms RMS roughness in a 20 μm×20 μm AFM scan). In particular, these steps may comprise chemical-mechanical treatments to smooth the free surface of the functional layer 10. A removal amount comprised between 50 nm and 300 nm allows to effectively regain the surface finish of said layer 10. Said steps may further comprise at least one heat treatment at a temperature comprised between 1300° C. and 1800° C. Such a heat treatment is applied to remove residual light element species from the functional layer 10 and to promote the rearrangement of the crystal lattice of the functional layer 10. The heat treatment further allows to strengthen the bonding interface 3. Heat treatment in this temperature range can also cause an increase in the grain size of the surface layer 22 (and of the second surface layer, if present), which is an advantageous method of improving the thermal conduction properties of the composite structure 100.

[0061] Finally, it will be noted that the transferring step d) may also comprise a step of reconditioning the remainder 1' of the donor substrate with a view to reusing it as a donor substrate 1 for the new composite structure 100. A mechanical and / or chemical treatment similar to the treatment applied to the composite structure 100 may be applied to the front side 1'a of the remaining substrate 1'. The reconditioning step may also comprise one or more treatments of the edge and / or its back side 1'b of the remaining substrate 1' by chemical-mechanical polishing, grinding and / or dry or wet chemical etching.

[0062] The invention also relates to a carrier substrate 20 produced according to steps a) and b) of the manufacturing process (FIG. 2b) described in detail above, said carrier substrate comprising: an initial substrate 21 comprising silicon carbide grains, said grains having an average size greater than 0.5 μm; a surface layer 22 applied at least to the front side of the initial substrate 21, the surface layer 22 comprising silicon carbide grains having an average size smaller than 500 nm, preferably smaller than 100 nm, and having a thickness comprised between 50 nm and 50 μm, preferably between 100 nm and 5 μm, or even between 200 nm and 500 nm; Includes.

[0063] As mentioned with reference to the manufacturing process, a layer of the same nature as the surface layer 22 may further be present on the back side and edges of the initial substrate 21, allowing said substrate 21 to be encapsulated, and a low-quality initial substrate (e.g. a sintered substrate) may thus be selected in order to limit the cost of the carrier substrate 20.

[0064] After step c) of the manufacturing process (FIG. 2c), the free surface 22a of the surface layer of the carrier substrate 20 has a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, and less than 10 defects / cm, as measured by reflective dark field microscopy at a threshold of 0.5 μm. 2 Fewer than or even 1 defect / cm 2These properties make the carrier substrate 20 particularly suitable for carrying out a step of molecular bonding between the functional layer 10 made of monocrystalline silicon carbide (or p-SiC when a second surface layer is present) and the nanograined p-SiC front side 22 a.

[0065] Finally, the present invention relates to a composite structure 100 produced by the manufacturing process described above, said composite structure comprising: A carrier substrate 20 as described above; A functional layer 10 made of single crystal silicon carbide disposed on the surface layer 22; Equipped with.

[0066] Such a composite structure 100 is extremely robust to the very high temperature heat treatments that are likely to be applied to improve the quality of the functional layer 10 or to manufacture components on and / or in said layer 10 .

[0067] The composite structure 100 according to the invention is particularly suitable for the production of one (or more) high voltage microelectronic component(s), such as, for example, Schottky diodes, MOSFETs, etc. More generally, the composite structure 100 allows for excellent vertical electrical conduction and resulting good thermal conductivity, and provides high quality c-SiC functional layers, thus satisfying the requirements of power microelectronic applications.

[0068] Naturally, the invention is not limited to the examples and embodiments described, and variations of the embodiments may be adopted without departing from the scope of the invention as defined by the claims.

Claims

1. A process for manufacturing a composite structure (100) comprising a functional layer (10) made of single-crystalline silicon carbide disposed on a carrier substrate (20) made of polycrystalline silicon carbide, a) providing an initial substrate (21) made of polycrystalline silicon carbide having a front side and containing grains with an average size greater than 0.5 μm in the plane of the front side; b) forming a surface layer (22) made of polycrystalline silicon carbide on the initial substrate (21) to form the carrier substrate (20), the surface layer (22) being made of grains with an average size smaller than 500 nm and having a thickness between 50 nm and 50 μm; c) conditioning the free surface of the surface layer (22) of the carrier substrate (20) to obtain a roughness smaller than 1 nm RMS; d) transferring the functional layer (10) to the carrier substrate (20) based on molecular bonding, the surface layer (22) being located between the functional layer (10) and the initial substrate (21); A process for manufacturing, comprising the steps above.

2. The process for manufacturing according to claim 1, wherein step a) is carried out at a temperature between 1100 °C and 1500 °C using chemical vapor deposition technology.

3. The process for manufacturing according to claim 1, wherein step a) is carried out using sintering technology or physical vapor deposition technology.

4. The process for manufacturing according to claim 1, wherein step b) comprises depositing a layer made of polycrystalline silicon carbide and is carried out at a temperature of 1100 °C or lower, or rather 1000 °C or lower, using chemical vapor deposition technology.

5. The process for manufacturing according to claim 1, wherein step b) is carried out in the same equipment item as step a) and follows step a) without returning the initial substrate to the ambient atmosphere.

6. The process for manufacturing according to claim 1, wherein step b) comprises depositing a layer made of amorphous silicon carbide on the initial substrate (21) and performing a recrystallization anneal to form the surface layer (22) made of polycrystalline silicon carbide.

7. The surface layer (22) formed in step b) has a dopant concentration that includes between 1E18 / cm ３ and 1E21 / cm ３ The process for manufacturing according to claim 1, wherein the process has a dopant concentration.

8. The process for manufacturing according to claim 1, wherein step c) comprises chemical mechanical polishing of the surface layer (22) involving removal of an amount included between 1 time and 10 times the average size of the grains constituting the surface layer (22).

9. Step d) is the next step, namely, d1) a step of preparing a donor substrate (1); d2) a step of introducing a light element species into the donor substrate (1) to form an embedded fragile plane (11) defining the functional layer (10) to be transferred on the front side of the donor substrate (1); d3) a step of bonding the front side of the donor substrate (1) to the carrier substrate (20) by molecular bonding; d4) a step of peeling along the embedded fragile plane (11) to effect transfer of the functional layer (10) to the carrier substrate (20). The process for manufacturing according to any one of claims 1 to 8, comprising the steps above.

10. The process for manufacturing according to claim 9, comprising a step of forming a second surface layer having the same properties as the surface layer (22) on the front side of the donor substrate (1) before or after step d2).

11. The process for manufacturing according to claim 9, wherein step d) includes depositing an additional film made of metal or silicon on the surface layer (22) of the carrier substrate (20) and / or on the front side of the donor substrate (1) before the bonding step d3).

12. A carrier substrate (20) made of polycrystalline silicon carbide, an initial substrate (21) including silicon carbide grains, the grains having an average size larger than 0.5 μm, and a surface layer (22) including silicon carbide grains having an average size smaller than 500 nm and having a thickness included between 50 nm and 50 μm, provided at least on the front side of the initial substrate (21). The carrier substrate (20) comprising the above components.

13. The free surface of the surface layer (22) has a roughness smaller than 1 nm RMS and less than 1 defect / cm when measured by a reflection dark-field microscope with a threshold of 0.5 μm. ２ The carrier substrate (20) according to claim 12, having the above properties.

14. The carrier substrate (20) according to claim 12, wherein the thickness of the surface layer (22) is included between 200 nm and 5 μm.

15. The surface layer (22) has a dopant concentration included between 1E18 / cm ３ and 1E21 / cm ３ The carrier substrate (20) according to claim 12.

16. A composite structure (100) comprising the carrier substrate (20) according to any one of claims 12 to 15 and a functional layer (10) made of single crystal silicon carbide provided on the surface layer (22). The composite structure (100) comprising the above components.

17. The composite structure (100) according to claim 16, further comprising at least one power device on or in the functional layer (10).

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