Reducing latency in pseudo-channel based memory systems - Patents.com

Abstract

Various embodiments include methods and devices for reducing latency in a pseudo channel based memory system. The embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input / output (IO) and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, and the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and the second IO simultaneously. The embodiments may include a pseudo channel based memory system configured to receive a memory access command targeted to the first pseudo channel and to use the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command.

Description

[Technical field]

[0001] Related Applications This application claims the benefit of priority from U.S. Nonprovisional Patent Application No. 17 / 452,606, filed October 28, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] Next-generation double data rate random access memories (herein referred to as "DDR") are expected to be widely used in mobile devices because they can provide a good balance of high performance, low power, competitive memory costs, a variety of package types, and multi-sourcing availability that is attractive for mobile and non-mobile applications. However, proposed or existing DDR systems are based on high performance, low latency, and low power schemes that use data communication protocols that exhibit greater latency, thereby limiting the use and efficiency of these systems to levels below acceptable use and efficiency for many applications, such as vehicle safety-related systems. For example, proposed low power DDR ("LPDDR") systems may utilize techniques that result in degraded latency for some operating points when compared to previous generations. Summary of the Invention [Means for solving the problem]

[0003] Various aspects disclosed include devices and methods for reducing latency in a pseudo channel based memory system. Various aspects may include a pseudo channel based memory system including a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input / output (IO) and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to simultaneously communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and the second IO in a first mode of operation.

[0004] In some aspects, the first IO may include a first pseudo channel data bus and the second IO may include a second pseudo channel data bus, and the pseudo channel based memory system may further include a first internal data bus having a larger bit-width than the first pseudo channel data bus and communicatively connected to the first pseudo channel, a second internal data bus having the same bit-width as the first pseudo channel data bus and communicatively connected between a first portion of the first internal data bus and the first pseudo channel selection device, and a third internal data bus having the same bit-width as the second pseudo channel data bus and communicatively connected between a second portion of the first internal data bus and the second pseudo channel selection device.

[0005] In some aspects, the first internal data bus may have a bit width equal to an integer multiple of the first pseudo channel data bus.

[0006] Some embodiments may further include a fourth internal data bus having a larger bit width than the first pseudo channel data bus and communicatively connected to a second pseudo channel of the plurality of pseudo channels, a fifth internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the fourth internal data bus and the first pseudo channel selection device, and a sixth internal data bus having the same bit width as the second pseudo channel data bus and communicatively connected between a second portion of the fourth internal data bus and the second pseudo channel selection device.

[0007] In some aspects, the first pseudo channel selection device and the second pseudo channel selection device may be operable to simultaneously communicatively connect the first pseudo channel to the first IO and the second IO in response to the pseudo channel-based memory system receiving a low latency type memory access command targeting the first pseudo channel.

[0008] Some aspects may further include a memory control device configured to receive a low latency type memory access command targeting the first pseudo channel, and in response to receiving the low latency type memory access command, send at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0009] In some aspects, the first pseudo channel selection device and the second pseudo channel selection device may be operable to simultaneously communicatively connect the first pseudo channel to the first IO and the second IO in response to the pseudo channel based memory system receiving a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands, and in response to the pseudo channel based memory system receiving consecutive memory access commands targeted to the first pseudo channel.

[0010] Some aspects may further include a memory control device configured to receive a mode register write command and, in response to receiving the mode register write command, set a register value configured to cause the memory control device to treat consecutive memory access commands as low latency type memory access commands; receive consecutive memory access commands targeting the first pseudo channel; and, in response to receiving the consecutive memory access commands, send at least one pseudo channel select signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0011] In some aspects, the first pseudo channel selection device and the second pseudo channel selection device may each include at least one multiplexer.

[0012] In some aspects, in the second mode of operation, the first pseudo channel selection device is operable to communicatively connect a first pseudo channel to a first IO, and the second pseudo channel selection device is operable to communicatively connect a second pseudo channel of the plurality of pseudo channels to a second IO.

[0013] Various aspects may include a pseudo channel-based memory system including a plurality of pseudo channels including a first pseudo channel, the pseudo channel-based memory system configured to receive a memory access command targeted to the first pseudo channel and to use the first pseudo channel data bus and a second pseudo channel data bus to execute the memory access command.

[0014] In some aspects, the memory access command may be a read memory access command, and the pseudo channel based memory system may be configured such that using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes outputting data from the first pseudo channel in response to the read memory access command over the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0015] In some aspects, the memory access command may be a write memory access command, and the pseudo channel based memory system may be configured such that using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes receiving data of the write memory access command for the first pseudo channel over the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0016] In some aspects, the memory access command may be configured to indicate to the pseudo channel based memory system that the memory access command is a low latency type memory access command.

[0017] In some aspects, the pseudo channel based memory system may be further configured to receive a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands, and the memory access commands targeted to the first pseudo channel may be consecutive memory access commands to the mode register write command.

[0018] Further aspects include methods for performing the operations of the systems summarized above.

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the various embodiments and, together with the general description above and the detailed description below, serve to explain the features of the claims. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments. [Diagram 2] FIG. 1 is a component block diagram illustrating an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Figure 3A] FIG. 1 is a component block diagram illustrating an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Figure 3B] FIG. 1 is a component block diagram illustrating an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Figure 4A] FIG. 1 is a component block and functional diagram of an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Figure 4B] FIG. 1 is a component block and functional diagram of an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Figure 4C]FIG. 1 is a component block and functional diagram of an exemplary pseudo-channel based memory system suitable for implementing various embodiments. [Diagram 5] FIG. 1 is a process flow diagram illustrating a method for reducing latency in a pseudo channel based memory system, according to one embodiment. [Figure 6] FIG. 1 is a process flow diagram illustrating a method for reducing latency in a pseudo channel based memory system, according to one embodiment. [Figure 7] FIG. 1 is a process flow diagram illustrating a method for reducing latency in a pseudo channel based memory system for a read memory command, according to one embodiment. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for reducing latency in a pseudo channel based memory system for write memory commands, according to one embodiment. [Figure 9] FIG. 1 is a process flow diagram illustrating a method for reducing latency in a pseudo channel based memory system, according to one embodiment. [Figure 10A] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 10B] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 11A] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 11B] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 12]FIG. 2 is a timing diagram illustrating an example of using low latency type memory access commands to reduce latency in a pseudo channel based memory system according to an embodiment. [Figure 13A] FIG. 1 is a timing diagram illustrating an example of reducing latency in a pseudo-channel based memory system using mode register writes to enable low latency type memory access commands, according to one embodiment. [Figure 13B] FIG. 1 is a timing diagram illustrating an example of reducing latency in a pseudo-channel based memory system using mode register writes to enable low latency type memory access commands, according to one embodiment. [Figure 14A] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 14B] FIG. 1 is a timing diagram illustrating example memory access commands with and without reduced latency in a pseudo channel based memory system, according to one embodiment. [Figure 15] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 16] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 17] FIG. 1 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Various embodiments are described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts. References made to specific examples and implementations are for illustrative purposes only and do not limit the scope of the claims.

[0022] Various embodiments include methods of reducing latency in a pseudo channel based memory system, and computing devices implementing such methods. A pseudo channel selection device may be used in a pseudo channel based memory system. Multiple pseudo channels may be communicatively connected to the pseudo channel selection device via an internal data bus that is wider than a dedicated input / output (IO) data bus of the pseudo channel. The pseudo channel selection device may be configured to enable the pseudo channel based memory system to read data from and / or write data to the pseudo channel using multiple IOs of the multiple pseudo channels in parallel.

[0023] The term "computing device" may refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers (such as vehicles and other larger systems), computerized vehicles (e.g., passenger cars, commercial vehicles, recreational vehicles, military vehicles, partially or fully autonomous land, air, and / or underwater vehicles such as drones), servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any one or all of cellular phones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptops / tablets (2-in-1 computers), smartbooks, ultrabooks, netblocks, palmtop computers, wireless email receivers, multimedia Internet-enabled cellular phones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and a programmable processor.

[0024] For ease and clarity of description, various embodiments are described in terms of code, e.g., processor-executable instructions, but may be equally applicable to any data, e.g., code, program data, or other information stored in memory. The terms "code," "data," and "information" are used interchangeably herein and are not intended to limit the scope of the claims and descriptions to the types of code, data, and information used as examples in describing various embodiments.

[0025] Next generation double data rate random access memory (herein referred to as "DDR") may provide a balance of high performance, low power, competitive memory costs, a variety of package types, and / or multi-sourcing availability that is attractive for mobile and non-mobile applications. Existing DDR systems support a pseudo channel mode in which multiple pseudo channels are implemented per channel of the DDR system. However, proposed or existing DDR systems are based on high performance, low latency, and / or low power schemes that use data communication protocols that may exhibit high latency. Such latency limits the use and efficiency of these systems to levels below that acceptable for many applications.

[0026] The proposed or existing DDR system supports a pseudo channel mode in which multiple pseudo channels are implemented per channel of the DDR system. Each pseudo channel has a dedicated bank and a dedicated data bus, and may share or have a dedicated command and address bus with at least one other pseudo channel. The IO of the pseudo channel may be managed by a combination of IO schemes, specifically, PAM (e.g., PAM4) that sends multiple bytes of data (e.g., 2 bytes) per write / read via Pulse Amplitude Modulation (PAM) coding, and Non-Return to Zero (NRZ) coding that sends one byte of data per write / read cycle. PAM coding may be used for clock frequencies greater than 1600 MHz, while NRZ coding may be used for clock frequencies equal to or less than 1600 MHz. IO signaling based on PAM coding reduces IO power efficiency as its operating frequency decreases, since the PAM transmitter consumes DC current when driving the PAM multi-level signal. However, NRZ transmitters do not consume as much DC current, and NRZ signal interfaces are more suitable for low frequencies in systems that depend on power efficiency, such as cell phones. As a result, the two different IO schemes require dynamic burst lengths during write / read operations to achieve the same data transmission. These differences in write / read burst lengths result in latency differences between the different IO schemes. The net result is that when NRZ coding is used, below a certain clock frequency (e.g., 1600 MHz), it takes longer to transfer data to or from the memory bank, increasing latency. This may not be acceptable for some applications.

[0027] The embodiments described herein address the aforementioned problems of a DDR system by reducing the latency for read and / or write operations in the DDR system by using one or more pseudo channel selection devices configured to selectively communicatively connect at least one selected pseudo channel of a plurality of pseudo channels of the DDR system to an IO data bus shared by at least two of the plurality of pseudo channels. The embodiments described herein may be applied to any DDR system, such as DDR, LPDDR, GDDR, WideIO, etc. For example, the implementation of one or more pseudo channel selection devices may reduce the latency when operating the DDR at a low frequency (e.g., ≦1600 MHz) when a NRZ coding IO scheme is implemented by simultaneously using two (or more) data buses (e.g., 16-bit data buses) to transfer data (e.g., 32-bit, 64-bit, etc.). As another example, implementations of one or more pseudo channel selection devices may reduce latency when DDR operates at high frequencies (e.g., >1600 MHz) and a PAM coding IO scheme is implemented by transferring data (e.g., 32-bit, 64-bit, etc.) using two (or larger) data buses (e.g., 16-bit data buses) simultaneously.

[0028] Various embodiments include an adaptive IO scheme for pseudo channels in a DDR system that reduces the latency of memory access transactions compared to proposed or existing DDR systems. The DDR system may include one or more pseudo channel selection devices, such as multiplexers configured with multiplexing and demultiplexing capabilities, integrated on a DDR chip. Each pseudo channel selection device may allow two (or more) pseudo channels to share a dedicated data bus of the DDR system. In some examples, a larger pseudo channel selection device may include multiple smaller pseudo channel selection devices.

[0029] In one embodiment, described in detail below with reference to FIG. 3A and FIG. 4A-4C, each of the two or more pseudo channel selection devices may be connected to a respective dedicated data bus (e.g., a 16-bit bus) of the DDR system, allowing the two (or more) pseudo channels to share the dedicated data bus. By providing two (or more) pseudo channel selection devices and connecting the pseudo channel selection devices to the two (or more) pseudo channels, the two (or more) pseudo channels may access a combined data bus (e.g., a 32-bit bus). The combined data bus may include a dedicated data bus connected to two or more pseudo channel selection devices, and may therefore have a width greater (e.g., twice as large) than each of the individual dedicated data buses. In other words, the width of the combined data bus may be a multiple, in bits, greater than "one" of the width of the dedicated data bus connected to each memory bank. Each pseudo channel may be communicatively connected to the two (or more) pseudo channel selection devices by an internal data bus. The bit width of the internal data bus in the pseudo channel may be the same width as the combined data bus, and the bit width of the internal data bus in each pseudo channel selection device may be a fraction of the bit width of the internal data bus, such as half or less of the bit width of the internal data bus. For example, each internal data bus may be a 32-bit internal data bus in the pseudo channel, and a 16-bit or less internal data bus in each of the two or (more) pseudo channel selection devices. The two (or more) pseudo channel selection devices may selectively connect selected pseudo channels to the combined data bus via their respective internal data buses. The two (or more) pseudo channel selection devices may be mn:m multiplexers, where "m" and "n" are integers greater than "1", such as integer "m" equal to the width of the dedicated data bus, and integer "n" equal to the number of pseudo channels communicatively connected to each pseudo channel selection device. For example, the pseudo channel selection device may be a 16n:16 multiplexer.As another example, for two pseudo channels, the pseudo channel selection device may be a 32:16 multiplexer.

[0030] In another implementation, described in detail below with reference to FIG. 3B and FIG. 4A-4C, the pseudo channel selection device may be connected to two (or more) dedicated data buses (e.g., 16-bit buses) of a DDR system, allowing the two (or more) pseudo channels to share the dedicated data bus. By providing a pseudo channel selection device and connecting the pseudo channel selection device to the two (or more) pseudo channels, the two (or more) pseudo channels may have access to a combined data bus (e.g., a 32-bit bus). The combined data bus may include the dedicated data buses connected to the pseudo channel selection device and may therefore have a larger width (e.g., twice as large) than the individual dedicated data buses. In other words, the width of the combined data bus may be a multiple of the width of the dedicated data buses connected to each memory bank, in bits. Each pseudo channel may be communicatively connected to the pseudo channel selection device by an internal data bus. The bit width of the internal data bus may be the same width as the combined data bus. For example, each internal data bus may be a 32-bit internal data bus. The pseudo channel selection device may selectively connect selected pseudo channels to the combined data bus via the respective internal data bus. The pseudo channel selection device may be a pn:p multiplexer, where "p" and "n" are integers greater than "1", such as integer "p" equal to the width of the combined data bus and integer "n" equal to the number of pseudo channels communicatively connected to the pseudo channel selection device. For example, the pseudo channel selection device may be a 32n:32 multiplexer. As another example, for two pseudo channels, the pseudo channel selection device may be a 64:32 multiplexer. The pseudo channel selection device may further include multiple smaller pseudo channel selection devices configured similarly to the two (or more) pseudo channel selection devices described above.

[0031] The DDR system may be configured with any number of pseudo channels per DDR chip, such as at least two pseudo channels. For example, a DDR chip may include two pseudo channels, three pseudo channels, four pseudo channels, six pseudo channels, eight pseudo channels, etc. One or more pseudo channel selection devices may be configured to select at least one of the pseudo channels of the DDR chip. The DDR chip may include multiple pseudo channel selection devices communicatively connected in parallel to the combined data bus. The multiple pseudo channel selection devices may be configured to function together as a larger pseudo channel selection device, as described above, such that selection of the pseudo channels to selectively communicatively connect to the combined data bus may be controlled via the multiple pseudo channel selection devices.

[0032] A DDR system using one or more pseudo channel selection devices that select at least one of the pseudo channels for a memory access transaction reduces latency by allowing the width of the combined data bus to be used for each connected pseudo channel, particularly compared to the NRZ coding IO scheme of existing DDR systems. The burst length for transmitting data over the wider combined data bus is reduced compared to the narrower dedicated data bus by doubling (or increasing) the number of bits transmitted using NRZ in one write or read operation. As a result of the wider combined data bus and the reduced burst length, the latency of data transmission is reduced compared to conventional DDR systems.

[0033] 1 illustrates a system including a computing device 100 suitable for use with various embodiments. Computing device 100 may include a system on a chip (SoC) 102 having a central processing unit 104, a memory 106, a communication interface 108, a memory interface 110, a peripheral device interface 120, and a processing device 124. Computing device 100 may further include a communication component 112, such as a wired or wireless modem, memory 114, an antenna 116 for establishing a wireless communication link, and / or peripheral devices 122. Processor 124 may include any of a variety of processing devices, e.g., several processor cores.

[0034] The term "system on chip" or "SoC" is used herein to generally refer to a set of interconnected electronic circuits including, but not limited to, a processing device, memory, and a communication interface. The processing device may include various different types of processors and / or processor cores, such as a central processing unit (CPU) 104 and / or processor 124 including a general purpose processor, a central processing unit (CPU) 104, a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a secure processing unit (SPU), an intellectual property unit (IPU), a subsystem processor for a particular component of a computing device such as an image processor for a camera subsystem or a display processor for a display, an auxiliary processor, a peripheral device processor, a single-core processor, a multi-core processor, a controller, and / or a microcontroller. The processing device may further incorporate other hardware and combinations of hardware, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. An integrated circuit may be constructed such that components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0035] The SoC 102 may include one or more CPUs 104 and processors 124. The computing device 100 may include more than one SoC 102, thereby increasing the number of CPUs 104, processors 124, and processor cores. The computing device 100 may also include CPUs 104 and processors 124 that are not associated with the SoC 102. Individual CPUs 104 and processors 124 may be multi-core processors. The CPUs 104 and processors 124 may each be configured for a specific purpose, which may be the same or different from other CPUs 104 and processors 124 of the computing device 100. One or more of the CPUs 104, processors 124, and processor cores of the same or different configurations may be grouped together. A group of CPUs 104, processors 124, or processor cores may be referred to as a multi-processor cluster.

[0036] The memory 106 of the SoC 102 may be a volatile or non-volatile memory configured to store data and processor-executable code for access by the CPU 104, processor 124, or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106 configured for various purposes. The one or more memories 106 may include volatile memories, such as random access memories (RAM), including DDR, implemented as main memory or cache memory. These memories 106 may be configured to temporarily hold data received from data sensors or subsystems, data and / or processor-executable code instructions requested from the non-volatile memory and loaded from the non-volatile memory into the memory 106 in anticipation of future access based on various factors, and / or a limited amount of intermediate processing data and / or processor-executable code instructions generated by the CPU 104 and / or processor 124 that are not stored in the non-volatile memory but are temporarily stored for quick future access. Memory 106 may be configured to at least temporarily store data and processor-executable code that is loaded into memory 106 from another memory device, such as another memory 106 or memory 114, for access by one or more of CPU 104, processor 124, or other components of SoC 102. In some embodiments, any number and combination of memories 106 may include one-time programmable or read-only memory.

[0037] The memory interface 110 and the memory 114 may operate together to enable the computing device 100 to store and retrieve data and processor-executable code to and from volatile and / or non-volatile storage media. The memory 114 may be configured much like an embodiment of the memory 106, such as a main memory, where the memory 114 may store data or processor-executable code for access by one or more of the CPU 104, the processor 124, or other components of the SoC 102. In some embodiments, the memory 114, being non-volatile, may retain information after the computing device 100 is powered off. When power is applied again and the computing device 100 reboots, the information stored on the memory 114 may be available to the computing device 100. In some embodiments, the memory 114, being volatile, may not retain information after the computing device 100 is powered off. The memory interface 110 may control access to the memory 114 and allow the CPU 104 , the processor 124 , or other components of the SoC 102 to read data from and write data to the memory 114 .

[0038] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined differently while still performing the functionality of the various embodiments. Computing device 100 may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of computing device 100.

[0039] FIG. 2 illustrates an exemplary pseudo-channel-based memory system (e.g., memory 106, memory 114 of FIG. 1) suitable for implementing various embodiments. With reference to FIGS. 1 and 2, the exemplary pseudo-channel-based memory system may include any number of DDR chips 200. Each DDR chip 200 may include any number of banks 224a, 224b. For example, the DDR chip 200 may include 32 banks. The banks 224a, 224b may be arranged in any number and combinations to form any number of bank groups 222a, 222b. For example, the DDR chip 200 may include 16 bank groups 222a, 222b, and each bank group 222a, 222b may include two banks 224a, 224b. The bank group 222a includes two banks 224a, and the bank group 222b includes two banks 224b. The banks 224a, 224b and bank groups 222a, 222b may be arranged in any number and combination to form at least two pseudo channels 220a, 220b. In other words, each pseudo channel 220a, 220b may include one or more bank groups 222a, 222b, and each bank group 222a, 222b may include one or more banks 224a, 224b. Different bank groups 222a, 222b of the pseudo channels 220a, 220b may include the same number of banks 224a, 224b or may include different numbers of banks 224a, 224b. Different pseudo channels 220a, 220b may include the same number of bank groups 222a, 222b or may include different numbers of bank groups 222a, 222b. For example, the DDR chip 200 may include two pseudo channels 220a, 220b, each pseudo channel 220a, 220b may include eight bank groups 222a, 222b, and each bank group 222a, 222b may include two banks 224a, 224b.More specifically, the pseudo channel 220a may include eight bank groups 222a, each of which may include two banks 224a, and the pseudo channel 220b may include eight bank groups 222b, each of which may include two banks 224b.

[0040] The pseudo channels 220a, 220b including banks 224a, 224b may be communicatively connected to the pseudo channel IOs 202a, 202b and the shared IOs 210 via an internal bus 230. For example, each pseudo channel 220a, 220b may be communicatively connected to a dedicated one of the pseudo channel IOs 202a, 202b, and at least two pseudo channels 220a, 220b may be communicatively connected to the shared IOs 210. Thus, the DDR chip 200 may include the same number of pseudo channels 220a, 220b and pseudo channel IOs 202a, 202b.

[0041] Each pseudo channel IO 202a, 202b may include a data bus 204a, 204b, respectively. Each pseudo channel IO 202a, 202b may be configured to enable the DDR chip 200 to receive data from a host (e.g., CPU 104, processor 124 of FIG. 1) and transmit data to the pseudo channel 220a, 220b via the communicatively connected data bus 204a, 204b. Further, each pseudo channel IO 202a, 202b may be configured to enable the DDR chip 200 to receive data from the pseudo channel 220a, 220b and transmit data to the host via the communicatively connected data bus 204a, 204b. The data bus 204a, 204b may be part of a larger data bus than the data bus 204a, 204b dedicated to the communicatively connected pseudo channel IO 202a, 202b. Each pseudo channel IO 202a, 202b may further include a write clock 206a, 206b and a read strobe 208a, 208b configured to provide signals for operation of the pseudo channel 220a, 220b communicatively connected to the pseudo channel IO 202a, 202b.

[0042] Each shared IO 210 may include a command address (CA) bus 214. The CA bus 214 may be configured to enable the DDR chip 200 to execute memory access commands, such as reads and / or writes, at specified addresses within the pseudo channels 220a, 220b communicatively connected to the shared IO 210. Each shared IO 210 may further include a clock 212, a chip select 216, and a reset 218 configured to provide signals for operation of the pseudo channels 220a, 220b communicatively connected to the shared IO 210.

[0043] Conventionally, each pseudo channel 220a, 220b may be communicatively connected only to a respective dedicated channel of the pseudo channel IO 202a, 202b, and may not be communicatively connected to the other pseudo channel IO 202a, 202b. For example, the pseudo channel 220a may be communicatively connected only to the pseudo channel IO 202a, and the pseudo channel 220b may be communicatively connected only to the pseudo channel IO 202b. In particular, the pseudo channel 220a may be communicatively connected only to the data bus 204a of the pseudo channel IO 202a, and the pseudo channel 220b may be communicatively connected only to the data bus 204b of the pseudo channel IO 202b. In the embodiments provided herein, each pseudo channel 220a, 220b may be communicatively connected to multiple pseudo channel IOs 202a, 202b. For example, pseudo channel 220a may be communicatively connected to pseudo channel IO 202a, 202b, and pseudo channel 220b may be communicatively connected to pseudo channel IO 202a, 202b. In particular, pseudo channel 220a may be communicatively connected to data bus 204a of pseudo channel IO 202a and data bus 204b of pseudo channel IO 202b, and pseudo channel 220b may be connected to data bus 204a of pseudo channel IO 202a and data bus 204b of pseudo channel IO 202b. Communicatively connecting pseudo channels 220a, 220b to multiple data buses 204a, 204b in this manner may provide pseudo channels 220a, 220b with access to a larger portion of a larger data bus than would be possible if pseudo channels 220a, 220b were conventionally connected to only a dedicated one of data buses 204a, 204b. For example, connecting the pseudo channels 220a, 220b to multiple data buses 204a, 204b may provide the pseudo channels 220a, 220b with access to a portion of the data bus that is larger than the size of the combined data buses 204a, 204b. Connecting the pseudo channels 220a, 220b to only a dedicated one of the data buses 204a, 204b as in the past provides the pseudo channels 220a, 220b with access to a portion of the data bus that is larger than the size of the individual data buses 204a, 204b.

[0044] 3A and 3B illustrate an exemplary pseudo channel-based memory system (e.g., memory 106, memory 114 of FIG. 1) suitable for implementing various embodiments. With reference to FIGS. 1-3B, the exemplary pseudo channel-based memory system may include any number of DDR chips 300a, 300b (e.g., DDR chip 200 of FIG. 2). The DDR chips 300a, 300b may include any number and combination of banks 224a, 224b, bank groups 222a, 222b, and pseudo channels 220a, 220b. For ease of explanation and clarity, the examples presented herein are based on two pseudo channels. However, such examples are not meant to limit the scope of the claims or description, and the examples presented herein may include any number of pseudo channels, three pseudo channels, four pseudo channels, six pseudo channels, eight pseudo channels, two pseudo channels, or any combination of pseudo channels, where "x" is an integer greater than "0". x The same may be applied to a DDR chip including a plurality of pseudo channels, etc.

[0045] The DDR chip 300a, 300b may further include a prefetch memory 302a, 302b associated with each pseudo channel 220a, 220b. The prefetch memory 302a, 302b may be configured to hold data retrieved from the bank 224a, 224b of the associated pseudo channel 220a, 220b. The prefetch memory 302a, 302b may generally have a smaller capacity than the bank 224a, 224b. In some examples, the prefetch memory 302a, 302b may have a capacity equal to the bit width of the internal data bus 306a, 306b described further herein. For example, the prefetch memory 302a, 302b may be an array of registers with a combined capacity of 256 bits.

[0046] In the example shown in FIG. 3A, the DDR chip 300a may further include pseudo channel selection devices 304a, 304b. For example, the pseudo channel selection devices 304a, 304b may be any number and combination of multiplexers. Each pseudo channel selection device 304a, 304b may be communicatively connected to a pseudo channel data bus 312a, 312b (e.g., data bus 204a, 204b of FIG. 2). Each pseudo channel selection device 304a, 304b may be communicatively connected to at least two pseudo channels 220a, 220b. The pseudo channel selection devices 304a, 304b may be communicatively connected to the pseudo channels 220a, 220b via internal data buses 306a, 306b, 308a, 308b, 308c, 308d. For example, internal data buses 306a and 308a may communicatively couple the pseudo channel selection device 304a to the pseudo channel 220a, and internal data buses 306a and 308b may communicatively couple the pseudo channel selection device 304b to the pseudo channel 220a. Further, internal data buses 306b and 308c may communicatively couple the pseudo channel selection device 304a to the pseudo channel 220b, and internal data buses 306b and 308d may communicatively couple the pseudo channel selection device 304b to the pseudo channel 220b. The pseudo channel selection devices 304a, 304b may be configured to communicatively connect the pseudo channels 220a, 220b to multiple pseudo channel data buses 312a, 312b via internal data buses 306a, 306b, 308a, 308b, 308c, 308d, as further described herein. The internal data buses 306a, 306b may be sized to have the same bit width as at least two pseudo channel data buses 312a, 312b to which the internal data buses 306a, 306b may be communicatively connected. For example, the internal data buses 306a, 306b may each have a 32-bit width, and the pseudo channel data buses 312a, 312b may each have a 16-bit width.The internal data buses 308a, 308b, 308c, 308d may be sized to have the same bit width as the pseudo channel data buses 312a, 312b to which the internal data buses 308a, 308b, 308c, 308d may be communicatively connected. For example, the internal data buses 308a, 308b, 308c, 308d may each have a 16-bit width, and the pseudo channel data buses 312a, 312b may each have a 16-bit width.

[0047] As another example, a dedicated internal data bus (not shown) may communicatively connect the pseudo channels 220a, 220b to the respective pseudo channel selection devices 304a, 304b. The dedicated internal data bus may be sized to have the same bit width as the pseudo channel data buses 312a, 312b to which the dedicated internal data buses may be communicatively connected. For example, the dedicated internal data buses may each have a 16-bit width, and the pseudo channel data buses 312a, 312b may each have a 16-bit width. The prefetch memories 302a, 302b may have a capacity equal to the combined bit width of the respective dedicated internal data buses, or a separate prefetch memory may be provided for each dedicated internal data bus.

[0048] The DDR chip 300a may include a pseudo channel controller 316 that may be communicatively coupled to the CA bus 314 (e.g., CA bus 214 of FIG. 2) and the pseudo channel selection devices 304a, 304b via pseudo channel selection signal lines 318a, 318b. The pseudo channel controller 316 may be configured to receive a memory access command via the CA bus 314. The pseudo channel controller 316 may be configured to interpret the memory access command and determine whether to provide a pseudo channel selection signal to the pseudo channel selection devices 304a, 304b via the pseudo channel selection signal lines 318a, 318b (including by asserting or deasserting the pseudo channel selection signal). The pseudo channel controller 316 may receive a memory access command configured to indicate that the memory access is a low latency type memory access. For example, the memory access command may include an indication, such as a value in a field, of a low latency type memory access. As another example, a memory access command may be preceded by a mode register write, which may be configured to set a register value to instruct the pseudo channel controller 316 that any subsequent memory access command should be implemented as a low latency type memory access. The pseudo channel controller 316 may also determine the pseudo channel 220a, 220b that is the target of the low latency type memory access and issue a pseudo channel select signal to the pseudo channel selection device 304a, 304b. The pseudo channel select signal may prompt the pseudo channel selection device 304a, 304b to configure the pseudo channel 220a, 220b that is the target of the memory access to communicatively connect to the pseudo channel data bus 312a, 312b via the internal data bus 306a, 306b, 308a, 308b, 308c, 308d. In some examples, the pseudo channel selection signal to the pseudo channel selection devices 304a, 304b may be the same pseudo channel selection signal.In some examples, the pseudo channel select signals to the pseudo channel selection devices 304a, 304b may each be a different pseudo channel select signal. In any of the foregoing examples, the DDR chip 300a and / or components of the DDR chip 300a, including the pseudo channel selection devices 304a, 304b and the pseudo channel controller 316, may operate in a first operating mode that implements low latency type memory accesses, regardless of whether the memory access command is configured to indicate that the memory access is a low latency type memory access or whether the memory access command follows a mode register write.

[0049] Similarly, the pseudo channel controller 316 may receive a memory access command configured to indicate that the memory access is a standard type memory access or a non-low latency type memory access. For example, the memory access command may include an indication, such as a value in a field, of a standard type memory access or a non-low latency type memory access. As another example, the memory access command may not be followed by a mode register write configured to set a register value to instruct the pseudo channel controller 316 that any subsequent memory access command should be implemented as a low latency type memory access. Furthermore, the memory access command may be followed by a mode register write configured to set a register value to instruct the pseudo channel controller 316 that any subsequent memory access command should be implemented as a standard type memory access or a non-low latency type memory access.

[0050] The pseudo channel controller 316 may also determine the pseudo channel 220a, 220b to which the standard type memory access or the non-low latency type memory access is targeted and issue a pseudo channel selection signal to the pseudo channel selection device 304a, 304b. The pseudo channel selection signal may prompt the pseudo channel selection device 304a, 304b to configure the pseudo channel 220a, 220b targeted by the memory access to be communicatively connected to the respective pseudo channel data bus 312a, 312b via the internal data bus 306a, 306b, 308a, 308b, 308c, 308d. In some embodiments, the pseudo channel selection signals to the pseudo channel selection devices 304a, 304b may be the same pseudo channel selection signal. In some embodiments, the pseudo channel selection signals to the pseudo channel selection devices 304a, 304b may be different pseudo channel selection signals. In any of these embodiments, the DDR chip 300a and / or components of the DDR chip 300a including the pseudo channel selection devices 304a, 304b and the pseudo channel controller 316 may operate in a second operational mode that performs standard type memory accesses or non-low latency type memory accesses if the memory access command is not followed by a mode register write that causes any subsequent memory access to be performed as a low latency type memory access, or if the memory access command is followed by a mode register write that causes any subsequent memory access to be performed as a standard type memory access or a non-low latency type memory access, regardless of whether the memory access command is configured to indicate that the memory access is a standard type memory access or a non-low latency type memory access.

[0051] In the example shown in Figure 3B, the DDR chip 300b may further include a pseudo channel selection device 320, which may include several pseudo channel selection devices 304a, 304b and combinations thereof as described herein with reference to Figure 3A. The pseudo channel selection device 320 may be communicatively connected to the pseudo channel data buses 312a, 312b (e.g., the data buses 204a, 204b of Figure 2). The pseudo channel selection device 320 may also be communicatively connected to at least two pseudo channels 220a, 220b. The pseudo channel selection device 320 may be communicatively connected to the pseudo channels 220a, 220b via the internal data buses 306a, 306b. The pseudo channel selection device 320 may communicatively connect the internal data buses 306a, 306b, 308a, 308b, 308c, 308d, and the pseudo channel selection devices 304a, 304b may be communicatively connected to the pseudo channels 220a, 220b via the internal data buses 306a, 306b, 308a, 308b, 308c, 308d, as described herein with reference to Figure 3A. As another example, the pseudo channel selection device 320 may be communicatively connected to the pseudo channels 220a, 220b and the pseudo channel selection devices 304a, 304b via a dedicated internal data bus (not shown), as described herein with reference to Figure 3A.

[0052] The DDR chip 300b may include a pseudo channel controller 316 that may be communicatively connected to a CA bus 314 (e.g., CA bus 214 of FIG. 2) as described herein with reference to FIG. 3A and to a pseudo channel selection device 320 via a pseudo channel selection signal line(s) 318c. The pseudo channel controller 316 may be communicatively connected to the pseudo channel selection devices 304a, 304b via the pseudo channel selection device 320. The pseudo channel controller 316 may be configured to receive a memory access command via the CA bus 314. The pseudo channel controller 316 may be configured to interpret the memory access command and determine whether to provide a pseudo channel selection signal to the pseudo channel selection devices 320, 304a, 304b via the pseudo channel selection signal line 318c (including by asserting or deasserting the pseudo channel selection signal). The pseudo channel controller 316 may receive a memory access command configured to indicate that the memory access is a low latency type memory access and may determine the pseudo channel 220a, 220b to which the low latency type memory access is targeted, as described herein with reference to FIG. 3A. The pseudo channel controller 316 may issue a pseudo channel selection signal to the pseudo channel selection device 320, which may send the pseudo channel selection signal to the pseudo channel selection devices 304a, 304b. In some embodiments, the pseudo channel selection device 320 may forward the pseudo channel selection signal to one or more of the pseudo channel selection devices 304a, 304b. The pseudo channel selection signal may prompt the pseudo channel selection devices 304a, 304b to configure the pseudo channel 220a, 220b that is the target of the memory access to communicatively connect to the pseudo channel data buses 312a, 312b via the internal data buses 306a, 306b, 308a, 308b, 308c, 308d, as described herein with reference to FIG. 3A.In any of the aforementioned examples, regardless of whether the memory access command is configured to indicate that the memory access is a low latency type memory access or whether the memory access command follows a mode register write, the DDR chip 300b and / or components of the DDR chip 300b, including the pseudo channel selection devices 304a, 304b, 320 and the pseudo channel controller 316, may operate in a first operating mode that implements a low latency type memory access.

[0053] Similarly, the pseudo channel controller 316 may receive a memory access command configured to indicate that the memory access is a standard type memory access or a non-low latency type memory access, as described herein with reference to FIG. 3A, and determine the pseudo channel 220a, 220b to which the standard type memory access or the non-low latency type memory access is targeted. The pseudo channel controller 316 may issue a pseudo channel selection signal to the pseudo channel selection device 320, which may transmit the pseudo channel selection signal to the pseudo channel selection devices 304a, 304b. In some embodiments, the pseudo channel selection device 320 may forward the pseudo channel selection signal to one or more of the pseudo channel selection devices 304a, 304b. The pseudo channel selection signal may prompt the pseudo channel selection devices 304a, 304b to configure the pseudo channel 220a, 220b that is the target of the memory access to be communicatively connected to the respective pseudo channel data buses 312a, 312b via the internal data buses 306a, 306b, 308a, 308b, 308c, 308d, as described herein with reference to FIG. 3A. The DDR chip 300b, and / or components of the DDR chip 300b including the pseudo channel selection devices 304a, 304b, 320 and the pseudo channel controller 316, may operate in a second operational mode that performs standard type memory accesses or non-low latency type memory accesses if the memory access command is not followed by a mode register write that causes any subsequent memory access to be performed as a low latency type memory access, or if the memory access command is followed by a mode register write that causes any subsequent memory access to be performed as a standard type memory access or a non-low latency type memory access, regardless of whether the memory access command is configured to indicate that the memory access is a standard type memory access or a non-low latency type memory access.

[0054] In the examples provided herein, specific values ​​such as the number, size, and / or capacity of components are not meant to limit the scope of the claims and description. The examples presented herein may equally apply to numbers, sizes, and / or capacities of components that are greater than and / or less than the exemplary numbers, sizes, and / or capacities provided herein. For example, the prefetch memories 302a, 302b may be 256-bit or larger or smaller than 256-bit. X As another example, the internal data buses 306a, 306b may have a capacity of 2 or more than 32 bits. X As another example, the pseudo channel data buses 312a, 312b may have a width of 2 or 3, which may be greater than or less than 16 bits. X As another example, the internal data buses 308a, 308b, 308c, 308d may have a width of 2 or 32 bits, which may be greater than or less than 16 bits. XIn the above example, "X" is an integer greater than "0". As noted herein, the DDR chips 300a, 300b may include more than two pseudo channels 220a, 220b. Thus, the DDR chips 300a, 300b may include an appropriate number of pseudo channel selection devices 304a, 304b, 320, internal data buses 306a, 306b, 308a, 308b, 308c, 308d, and pseudo channel selection signal lines 318a, 318b, 318c to implement the embodiments provided herein. For example, the DDR chips 300a, 300b may include one or more copies of the pseudo channels 220a, 220b, pseudo channel selection devices 304a, 304b, 320, internal data buses 306a, 306b, 308a, 308b, 308c, 308d, and pseudo channel selection signal lines 318a, 318b, 318c, as in the example shown in Figure 3. As another example, the DDR chips 300a, 300b may include additional pseudo channels, pseudo channel selection devices, internal data buses, and pseudo channel selection signal lines that extend the example shown in Figures 3A and 3B. For example, one or more additional pseudo channels may be communicatively connected to one or more of the pseudo channel selection devices 304a, 304b, 320 and at least one additional pseudo channel selection device via an additional internal data bus, and additional pseudo channel selection signal lines may be communicatively connected to any additional pseudo channel selection devices.

[0055] 4A-4C illustrate an exemplary function of a pseudo channel-based memory system (e.g., memory 106, memory 114 of FIG. 1) suitable for implementing various embodiments. With reference to FIG. 1-4C, the exemplary pseudo channel-based memory system may include a DDR chip 300a (e.g., DDR chip 200 of FIG. 2), which includes pseudo channels 220a, 220b, banks 224a, 224b, bank groups 222a, 222b, prefetch memories 302a, 302b, pseudo channel selection devices 304a, 304b, internal data buses 306a, 306b, 308a, 308b, 308c, 308d, a pseudo channel controller 316, and pseudo channel selection signal lines 318a, 318b. The DDR chip 300a may also include pseudo channel data buses 312a, 312b and a CA bus 314.

[0056] The examples shown in Figures 4A and 4B may be examples of a DDR chip 300a and / or components of the DDR chip 300a including the pseudo channel selection devices 304a, 304b and the pseudo channel controller 316 operating in a first mode of operation implementing low latency type memory accesses. With reference to Figure 4A, the pseudo channel controller 316 may determine a low latency type memory access targeting the pseudo channel 220a. The pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304a configured to cause the pseudo channel selection device 304a to communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a. In response, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a via the internal data buses 306a, 308a. For the same low latency type memory access targeting the pseudo channel 220a, the pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304b configured to cause the pseudo channel selection device 304b to communicatively connect the pseudo channel 220a to the pseudo channel data bus 312b. In response, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312b via the internal data buses 306a, 308b. Communicatively connecting the pseudo channel 220a to the pseudo channel data buses 312a, 312b may include communicatively disconnecting the pseudo channel 220b from the pseudo channel data buses 312a, 312b by the pseudo channel selection devices 304a, 304b (illustrated using dashed internal data buses 306b, 308c, 308d).

[0057] For a low latency type read memory access, data may be read from the prefetch memory 302a associated with the pseudo channel 220a and provided to the pseudo channel data buses 312a, 312b via the internal data buses 306a, 308a, 308b and the pseudo channel selection devices 304a, 304b. For a low latency type write memory access, data may be written to the bank 224a associated with the pseudo channel 220a and provided from the pseudo channel data buses 312a, 312b via the internal data buses 306a, 308a, 308b and the pseudo channel selection devices 304a, 304b.

[0058] As mentioned above, in alternative implementations, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a via a dedicated internal data bus (not shown). Similarly, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312b via a dedicated internal data bus (not shown).

[0059] 4B, the pseudo channel controller 316 may determine a low latency type memory access targeted to the pseudo channel 220b. The pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304a configured to cause the pseudo channel selection device 304a to communicatively connect the pseudo channel 220b to the pseudo channel data bus 312a. In response, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312a via the internal data buses 306b, 308c. For the same low latency type memory access targeted to the pseudo channel 220b, the pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304b configured to cause the pseudo channel selection device 304b to communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b. In response, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b via the internal data buses 306b, 308d. Communicatively connecting the pseudo channel 220b to the pseudo channel data buses 312a, 312b may include communicatively disconnecting the pseudo channel 220a from the pseudo channel data buses 312a, 312b by the pseudo channel selection devices 304a, 304b (illustrated with dashed internal data buses 306a, 308a, 308b).

[0060] For a low latency type read memory access, data may be read from the prefetch memory 302b associated with the pseudo channel 220b and provided to the pseudo channel data buses 312a, 312b via the internal data buses 306b, 308c, 308d and the pseudo channel selection devices 304a, 304b. For a low latency type write memory access, data may be written to the bank 224b associated with the pseudo channel 220b and provided from the pseudo channel data buses 312a, 312b via the internal data buses 306b, 308c, 308d and the pseudo channel selection devices 304a, 304b.

[0061] As mentioned above, in alternative implementations, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312a via a dedicated internal data bus (not shown). Similarly, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b via a dedicated internal data bus (not shown).

[0062] The example shown in FIG. 4C is an example of a DDR chip 300a and / or components of the DDR chip 300a including pseudo channel selection devices 304a, 304b and a pseudo channel controller 316, where the DDR chip 300a and / or components thereof operate in a second operating mode performing standard type memory accesses or non-low latency type memory accesses. With reference to FIG. 4C, the pseudo channel controller 316 may determine the standard type memory accesses or the non-low latency type memory accesses targeting either of the pseudo channels 220a, 220b. The pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304a configured to cause the pseudo channel selection device 304a to communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a. In response, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a via the internal data buses 306a, 308a. Communicatively connecting the pseudo channel 220a to the pseudo channel data bus 312a may include communicatively disconnecting the pseudo channel 220b from the pseudo channel data bus 312a by the pseudo channel selection device 304a (illustrated with the dashed internal data bus 308c). For the same standard type or non-low latency type memory accesses targeting either of the pseudo channels 220a, 220b, the pseudo channel controller 316 may send a pseudo channel selection signal to the pseudo channel selection device 304b configured to cause the pseudo channel selection device 304b to communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b. In response, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b via the internal data buses 306b, 308d. Communicatively connecting the pseudo channel 220b to the pseudo channel data bus 312b may include communicatively disconnecting the pseudo channel 220a from the pseudo channel data bus 312b by the pseudo channel selection device 304b (illustrated with the dashed internal data bus 308b).

[0063] In the case of a standard type memory access or a non-low latency type read memory access, data may be read from the prefetch memory 302a, 302b associated with the targeted pseudo channel 220a, 220b and provided via appropriate internal data buses 306a, 306b, 308a, 308d and appropriate pseudo channel selection devices 304a, 304b to pseudo channel data buses 312a, 312b communicatively connected to the targeted pseudo channel 220a, 220b. For standard type write memory accesses or non-low latency type write memory accesses, data may be written to the bank 224a, 224b associated with the targeted pseudo channel 220a, 220b and may be provided from a pseudo channel data bus 312a, 312b communicatively connected to the targeted pseudo channel 220a, 220b via an appropriate internal data bus 306a, 306b, 308a, 308d and an appropriate pseudo channel selection device 304a, 304b.

[0064] In an alternative implementation, the pseudo channel selection device 304a may communicatively connect the pseudo channel 220a to the pseudo channel data bus 312a via a dedicated internal data bus (not shown). Similarly, the pseudo channel selection device 304b may communicatively connect the pseudo channel 220b to the pseudo channel data bus 312b via a dedicated internal data bus (not shown).

[0065] The above examples described with reference to Figures 4A-4C may be similarly applicable to the exemplary pseudo-channel-based memory system shown in Figure 3B, which includes a DDR chip 300b (e.g., the DDR chip 200 of Figure 2) (not shown), which includes pseudo channels 220a, 220b, banks 224a, 224b, bank groups 222a, 222b, prefetch memories 302a, 302b, pseudo channel selection devices 304a, 304b, 320, internal data buses 306a, 306b, 308a, 308b, 308c, 308d, a pseudo channel controller 316, and a pseudo channel selection signal line(s) 318c. The DDR chip 300b may also include pseudo channel data buses 312a, 312b, and a CA bus 314. However, instead of the pseudo channel controller 316 sending the pseudo channel selection signal to the pseudo channel selection devices 304a, 304b over the pseudo channel selection signal lines 318a, 318b, the pseudo channel controller 316 may send the pseudo channel selection signal(s) to the pseudo channel selection devices 304a, 304b, 320 over the pseudo channel selection signal line(s) 318c. In some embodiments, the pseudo channel controller 316 may send one or more pseudo channel selection signals to the pseudo channel selection device 320, which may send one or more pseudo channel selection signals to the pseudo channel selection devices 304a, 304b.

[0066] FIG. 5 illustrates a method 500 for reducing latency in a pseudo channel based memory system (e.g., memory 106, memory 114, DDR 200, FIG. 2, DDR 300a, DDR 300b, FIG. 3A-4C) according to some embodiments. With reference to FIG. 1-5, the method 500 may be implemented in a computing device (e.g., computing device 100, FIG. 1), in hardware, in software running on a processor, or in combination with a software configured processor and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114, FIG. 1, DDR 200, FIG. 2, DDR 300a, 300b, FIG. 3A-4C, banks 224a, 224b, FIG. 2-4C) and various memory / cache controllers (e.g., pseudo channel controller 316, FIG. 3A-4C). To encompass alternative configurations usable in the various embodiments, the hardware that performs the method 500 is referred to herein as a "memory control device."

[0067] At block 502, the memory control device may receive a memory access command. The memory access command may include a standard type memory access command or a non-low latency type memory access command, or a low latency type memory access command. The standard type memory access command or the non-low latency type memory access command and the low latency type memory access command may be memory access type commands where the low latency type memory access command may be configured to provide memory access with lower latency than the standard type memory access command or the non-low latency type memory access command. In some examples, the memory access command may include an aspect configured to indicate whether the memory access command is a low latency type memory access command. For example, the memory access command may include a field configured to have a value indicating whether the memory access command is a low latency type memory access command. The memory access command may also be associated with a target address for the memory access command, and the target address may be present in a pseudo channel (e.g., pseudo channels 220a, 220b of FIGS. 2-4C).

[0068] A memory access command may be received by the memory control device via a CA bus (e.g., CA bus 214 in FIG. 2, CA bus 314 in FIG. 3A-4C). In some examples, the memory access command may be a write memory access, and data associated with the write memory access may be received in a memory associated with the memory control device or included in the memory control device (e.g., memory 106, memory 114 in FIG. 1, DDR 200 in FIG. 2, DDR 300a, 300b in FIG. 3A-4C) via one or more pseudo channel data buses (e.g., data buses 204a, 204b in FIG. 2, pseudo channel data buses 312a, 312b in FIG. 3A-4C). For example, in the case of a standard type write memory access or a non-low latency type write memory access, the data may be received on a pseudo channel data bus dedicated to the target pseudo channel. In another example, for a low latency type write memory access, the data may be received on multiple pseudo channel data buses, one of which may be a pseudo channel data bus dedicated to the target pseudo channel. In some examples, the memory control device that receives the memory access command in block 502 may include a pseudo channel controller (e.g., pseudo channel controller 316 of FIGS. 3A-4C).

[0069] In block 504, the memory control device may determine a pseudo channel for the memory access command. The memory control device may use the received address in the memory access command to determine the pseudo channel in which the address resides. In some examples, the memory control device may access a data structure, such as a table, array, etc., that associates pseudo channel identifiers (IDs) of the pseudo channels with address ranges for the pseudo channels. The memory control device may compare the address of the memory access command to the address ranges of the pseudo channels and determine the pseudo channel ID associated with the address range in which the address of the memory access command resides. In some examples, the memory control device that determines the pseudo channel for the memory access command in block 504 may include a pseudo channel controller.

[0070] In a determination block 506, the memory control device may determine whether the received memory access command is a low latency type memory access command. The memory control device may interpret an aspect of the memory access command configured to indicate whether the memory access command is a low latency type memory access command to determine whether the received memory access command is a low latency type memory access command. For example, a value in a field of the memory access command may be configured to indicate whether the memory access command is a low latency type memory access command. In some examples, the value may be a bit value, where a bit value of "1" may indicate a low latency type memory access command and a bit value of "0" may indicate a standard type memory access command or a non-low latency type memory access command, or vice versa. In some examples, the memory control device that determines whether the received memory access command is a low latency type memory access command in the determination block 506 may include a pseudo channel controller.

[0071] In response to determining that the received memory access command is a low latency type memory access command (i.e., decision block 506="Yes"), the memory control device may transmit a pseudo channel selection signal to two or more pseudo channel selection devices (e.g., pseudo channel selection devices 304a, 304b, 320 of FIGS. 3A-4C) in block 508. The pseudo channel selection signal may be configured to cause the pseudo channel selection device to configure a communication connection between one or more pseudo channel data buses and a plurality of internal data buses (e.g., internal data buses 306a, 306b, 308a, 308b, 308c, 308d of FIGS. 3A-4C). In effect, the pseudo channel selection signal may be configured to cause the pseudo channel selection device to configure a communication connection between one or more pseudo channel data buses and a pseudo channel that includes a bank of pseudo channels (e.g., banks 224a, 224b of FIGS. 2-4C). The pseudo channel selection signal may instruct the pseudo channel selection device to communicatively connect the pseudo channel targeted by the low latency type memory access command to the multiple pseudo channel data buses. In some examples, the memory control device may send the same pseudo channel selection signal to the pseudo channel selection device. In some examples, the memory control device may send different pseudo channel selection signals to the pseudo channel selection device. In some examples, sending the pseudo channel selection signal to the pseudo channel selection device may include not sending the pseudo channel selection signal. For example, in response to not receiving the pseudo channel selection signal, the pseudo channel selection device may select a particular (pre-configured) pseudo channel by default. The memory control device may operate in a first operating mode that achieves low latency type memory access. In some examples, the memory control device that sends the pseudo channel selection signal to the pseudo channel selection device at block 508 may include a pseudo channel controller.

[0072] In block 510, the memory control device may simultaneously read data from and / or write data to the target pseudo channel via the pseudo channel IO (e.g., pseudo channel IO 202a, 202b, data bus 204a, 204b of FIG. 2, pseudo channel selection device 304a, 304b, 320, pseudo channel data bus 312a, 312b of FIG. 3A-4C). The pseudo channel targeted by the low latency type memory access command may be read from and / or written to the memory using multiple pseudo channel data buses via the communication connection configured by the pseudo channel selection device. Conventionally, the pseudo channel targeted by any memory access command may be read and / or written using only a single pseudo channel data bus dedicated to the pseudo channel. Thus, the bit width of the IO of the pseudo channel is limited by the bit width of the single pseudo channel data bus. By allowing multiple pseudo channel data buses to be used simultaneously to read from and / or write to a targeted pseudo channel of low latency type memory access commands, the bit width of the pseudo channel IO may be increased compared to using a single pseudo channel data bus by using the maximum total bit width of the multiple pseudo channel data buses. Furthermore, increasing the bit width of the pseudo channel IO may allow for a shorter burst length for reading from and / or writing to the pseudo channel since more data can be read and / or written simultaneously using multiple pseudo channel data buses. In some embodiments, the memory control device that reads data from and / or writes data to the pseudo channel via the pseudo channel IOs simultaneously at block 510 may include a pseudo channel controller, a pseudo channel selection device, and / or a pseudo channel IO (e.g., pseudo channel IOs 202a, 202b of FIG. 2).

[0073] In response to determining that the received memory access command is not a low-latency type memory access command (i.e., decision block 506="No"), the memory control device may send a pseudo channel selection signal to one or more pseudo channel selection devices in block 512. The pseudo channel selection signal may be similar to the pseudo channel selection signal described in block 508. However, the pseudo channel selection signal may cause the pseudo channel selection device to communicatively connect the pseudo channels targeted by the standard type memory access command or the non-low latency type memory access command to a single pseudo channel data bus dedicated to the pseudo channels. The memory control device may operate in a second operating mode to perform the standard type memory access or the non-low latency type memory access. In some examples, the memory control device that sends the pseudo channel selection signal to the pseudo channel selection device in block 512 may include a pseudo channel controller.

[0074] In block 514, the memory control device may read data from and / or write data to the target pseudo channel via a single dedicated pseudo channel IO. The target pseudo channel of a standard type memory access command or a non-low latency type memory access command may be read and / or written using a single dedicated pseudo channel data bus via a communication connection configured by a respective pseudo channel selection device. In some embodiments, the memory control device that reads data from and / or writes data to a pseudo channel via a single dedicated pseudo channel IO in block 514 may include a pseudo channel controller, a pseudo channel selection device, and / or a pseudo channel IO (e.g., pseudo channel IO 202a, 202b of FIG. 2).

[0075] FIG. 6 illustrates a method 600 for reducing latency in a pseudo channel based memory system (e.g., memory 106, memory 114, DDR 200, FIG. 2, DDR 300a, 300b, FIG. 3A-4C) according to some embodiments. With reference to FIG. 1-6, the method 600 may be implemented in a computing device (e.g., computing device 100, FIG. 1), in hardware, in software running on a processor, or in combination with a software configured processor and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114, FIG. 1, DDR 200, FIG. 2, DDR 300a, 300b, FIG. 3A-4C, banks 224a, 224b, FIG. 2-4C) and various memory / cache controllers (e.g., pseudo channel controller 316, FIG. 3A-4C). To encompass alternative configurations usable in various embodiments, the hardware performing method 600 is referred to herein as a “memory control device.” Blocks 502, 504, 508, 510 may be implemented similarly to similarly numbered blocks of method 500 described herein with reference to FIG.

[0076] At block 602, the memory control device may receive a mode register write command for a low latency type memory access. The mode register write command may be configured to prompt the memory control device to set a register value to indicate to the memory control device that any subsequent memory access commands should be implemented as low latency type memory accesses.

[0077] In block 604, the memory control device may set register values ​​for low latency type memory access. The memory control device may then operate in a first operation mode implementing low latency type memory access. The memory control device that receives the mode register write command for low latency type memory access in block 602 and sets register values ​​for low latency type memory access in block 604 may include a pseudo channel controller (e.g., pseudo channel controller 316 of FIGS. 3A-4C).

[0078] A memory control device may receive a memory access command in block 502. In some examples, the memory control device that receives the memory access command in block 502 may include a pseudo channel controller (e.g., pseudo channel controller 316 of FIGS. 3A-4C).

[0079] In block 504, the memory control device may determine a pseudo channel for the memory access command (e.g., pseudo channels 220a, 220b of FIGS. 2-4C). In some examples, the memory control device that determines the pseudo channel for the memory access command in block 504 may include a pseudo channel controller.

[0080] In block 508, the memory control device may send the pseudo channel selection signal to a pseudo channel selection device (e.g., the pseudo channel selection devices 304a, 304b, 320 of FIGS. 3A-4C). In some examples, the memory control device that sends the pseudo channel selection signal to the pseudo channel selection device in block 508 may include a pseudo channel controller.

[0081] At block 510, the memory control device may read data from and / or write data to the pseudo channel simultaneously via the pseudo channel IO (e.g., data buses 204a, 204b of FIG. 2, pseudo channel selection devices 304a, 304b, 320 of FIGS. 3A-4C, pseudo channel data buses 312a, 312b). In some embodiments, the memory control device that reads data from and / or writes data to the pseudo channel simultaneously via the pseudo channel IO at block 510 may include a pseudo channel controller, a pseudo channel selection device, and / or a pseudo channel IO (e.g., pseudo channel IO 202a, 202b of FIG. 2).

[0082] FIG. 7 illustrates a method 700 for reducing latency in a pseudo channel based memory system (eg, memory 106, memory 114 of FIG. 1, DDR 200 of FIG. 2, DDR 300a, 300b of FIGS. 3A-4C) for a read memory command, according to one embodiment. 1-7, the method 700 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software running on a processor, or in a combination of dedicated hardware including a software configured processor and other individual components such as various memories / caches (e.g., memory 106 of FIG. 1, memory 114, DDR 200 of FIG. 2, DDR 300a, 300b of FIG. 3A-4C, banks 224a, 224b of FIG. 2-4C, pseudo channel selection devices 304a, 304b, 320 of FIG. 3A-4C) and various memory / cache controllers (e.g., pseudo channel controller 316 of FIG. 3A-4C). To encompass alternative configurations usable in various embodiments, the hardware implementing the method 700 is referred to herein as a "memory control device." Blocks 702, 704, 706, 708 contain further details regarding the operations in block 510 of methods 500, 600 as described.

[0083] At block 702, the memory control device may receive pseudo channel read data. The pseudo channel read data may be read from a prefetch memory (e.g., prefetch memory 302a, 302b of FIGS. 3A-4C) associated with a target pseudo channel (e.g., pseudo channel 220a, 220b of FIGS. 3A-4C) of a low latency type read memory access or a prefetch memory included in the target pseudo channel. The pseudo channel read data may be transmitted to multiple pseudo channel selection devices (e.g., pseudo channel selection devices 304a, 304b, 320 of FIGS. 3A-4C) via an internal data bus (e.g., internal data bus 306a, 306b, 308a, 308b, 308c, 308d of FIGS. 3A-4C). In some examples, the memory control device receiving the pseudo channel read data at block 702 may include multiple pseudo channel selection devices.

[0084] At block 704, the memory control device may receive a pseudo channel selection signal. The pseudo channel selection signal may be the pseudo channel selection signal transmitted at block 508 of the methods 500, 600 as described. The pseudo channel selection signal may be received at multiple pseudo channel selection devices. In some examples, the memory control device receiving the pseudo channel selection signal at block 704 may include multiple pseudo channel selection devices.

[0085] In block 706, the memory control device may configure the pseudo channel selection device to output pseudo channel read data from the target pseudo channel to a number of pseudo channel IOs (e.g., pseudo channel IOs 202a, 202b, data buses 204a, 204b, and pseudo channel data buses 312a, 312b, of FIG. 2, and FIG. 3A-4C, respectively). The pseudo channel selection device may be configured to communicatively connect a respective pseudo channel data bus (e.g., data buses 204a, 204b, and FIG. 3A-4C, respectively) to a number of internal data buses. In effect, the pseudo channel selection device may be configured to communicatively connect a number of pseudo channel data buses to a target pseudo channel that includes a bank of target pseudo channels (e.g., banks 224a, 224b, of FIG. 2, respectively). The pseudo channel selection device may be configured to communicatively connect a pseudo channel that is a target of a low latency type read memory access to multiple pseudo channel data buses in response to a pseudo channel selection signal. In some examples, a memory control device that configures the pseudo channel selection device to output pseudo channel read data from the target pseudo channel to multiple pseudo channel IOs in block 706 may include multiple pseudo channel selection devices.

[0086] The memory control device may output the pseudo channel read data at the pseudo channel selection device to the pseudo channel IO at block 708. The memory control device may simultaneously output the pseudo channel read data received at block 702 to multiple pseudo channel IOs communicatively connected to the target pseudo channel of the low latency type read memory access at block 706. In some examples, the memory control device that outputs the pseudo channel read data at the pseudo channel selection device to the pseudo channel IO at block 708 may include multiple pseudo channel selection devices and / or pseudo channel IOs.

[0087] FIG. 8 illustrates a method 800 for reducing latency in a pseudo channel based memory system (eg, memory 106, memory 114 of FIG. 1, DDR 200 of FIG. 2, DDR 300a, 300b of FIGS. 3A-4C) for a write memory command, according to one embodiment. 1-8, the method 800 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software running on a processor, or in a combination of dedicated hardware including a software configured processor and other individual components such as various memories / caches (e.g., memory 106 of FIG. 1, memory 114, DDR 200 of FIG. 2, DDR 300a, 300b of FIG. 3A-4C, banks 224a, 224b of FIG. 2-4C, pseudo channel selection devices 304a, 304b, 320 of FIG. 3A-4C) and various memory / cache controllers (e.g., pseudo channel controller 316 of FIG. 3A-4C). To encompass alternative configurations usable in various embodiments, the hardware implementing the method 800 is referred to herein as a "memory control device." Blocks 802, 804, 806 include more detailed operations that may be performed in block 510 of methods 500, 600 described herein with reference to FIGS.

[0088] In block 802, the memory control device may receive pseudo channel write data at a pseudo channel selection device (e.g., pseudo channel selection devices 304a, 304b, 320 of FIG. 3A-4C) via multiple pseudo channel IOs (e.g., pseudo channel IOs 202a, 202b, data buses 204a, 204b of FIG. 2, pseudo channel data buses 312a, 312b of FIG. 3A-4C). The pseudo channel write data may be received simultaneously from a host (e.g., CPU 104, processor 124 of FIG. 1) via multiple pseudo channel data buses (e.g., data buses 204a, 204b of FIG. 2, pseudo channel data buses 312a, 312b of FIG. 3A-4C) for low latency type write memory access. Each pseudo channel data bus may be communicatively coupled to a different pseudo channel selection device. Data transmitted by each pseudo channel data bus may be simultaneously received at a respective communicatively connected pseudo channel selection device. In some examples, the memory control device that receives pseudo channel write data at the pseudo channel selection device via multiple pseudo channel IOs at block 802 may include multiple pseudo channel selection devices.

[0089] At block 704, the memory control device may receive a pseudo channel selection signal. The pseudo channel selection signal may be the pseudo channel selection signal transmitted at block 508 of the methods 500, 600 described herein with reference to Figures 5 and 6. The pseudo channel selection signal may be received at multiple pseudo channel selection devices. In some examples, the memory control device receiving the pseudo channel selection signal at block 804 may include multiple pseudo channel selection devices.

[0090] In block 804, the memory control device may configure the pseudo channel selection device to output pseudo channel write data from the plurality of pseudo channel IOs to a target pseudo channel (e.g., pseudo channels 220a, 220b of FIGS. 3A-4C) of a low latency type write memory access. The pseudo channel selection device may be configured to communicatively connect a respective pseudo channel data bus (e.g., data buses 204a, 204b of FIG. 2, pseudo channel data buses 312a, 312b of FIGS. 3A-4C) to a plurality of internal data buses (e.g., internal data buses 306a, 306b, 308a, 308b, 308c, 308d of FIGS. 3A-4C). In effect, the pseudo channel selection device may be configured to communicatively connect a plurality of pseudo channel data buses to a target pseudo channel that includes a bank of target pseudo channels (e.g., banks 224a, 224b of FIGS. 2-4C). The pseudo channel selection device may be configured to communicatively connect a pseudo channel that is a target of a low latency type write memory access to a plurality of pseudo channel data buses in response to a pseudo channel selection signal. In some examples, the memory control device that configures the pseudo channel selection device to output pseudo channel write data from a plurality of pseudo channel IOs to a target pseudo channel of a low latency type write memory access in block 806 may include a plurality of pseudo channel selection devices.

[0091] The memory control device may output the pseudo channel write data at the pseudo channel selection device to a target pseudo channel of the low latency type write memory access at block 806. The memory control device may output the pseudo channel write data received at block 802 to a target pseudo channel of the low latency type write memory access communicatively connected to the multiple pseudo channel IOs at block 806. In some examples, the memory control device that outputs the pseudo channel write data at the pseudo channel selection device to the target pseudo channel of the low latency type write memory access at block 808 may include multiple pseudo channel selection devices.

[0092] FIG. 9 illustrates a method 900 for reducing latency in a pseudo channel based memory system (e.g., memory 106, memory 114, DDR 200, FIG. 2, DDR 300a, 300b, FIG. 3A-4C) according to one embodiment. With reference to FIGS. 1-9, the method 900 may be implemented in a computing device (e.g., computing device 100, FIG. 1), in hardware, in software running on a processor, or in combination with a software configured processor and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114, FIG. 1, DDR 200, FIG. 2, DDR 300a, 300b, FIG. 3A-4C, banks 224a, 224b, FIG. 2-4C) and various memory / cache controllers (e.g., pseudo channel controller 316, FIG. 3A-4C). To encompass alternative configurations possible in various embodiments, the hardware performing method 900 is referred to herein as a “memory control device.” In some examples, method 900 may be performed prior to and / or concurrently with methods 500, 600 described herein with reference to FIGS.

[0093] In decision block 902, the memory control device may determine whether to execute a low latency memory access command. In some examples, a condition for determining whether to execute a low latency memory access command may be met. For example, implementing the low latency memory access command may depend on a clock frequency of the pseudo channel based memory system. For example, the low latency memory access command may be implemented for a clock frequency of the pseudo channel based memory system below a threshold, such as 1600 MHz. As another example, implementing the low latency memory access command may depend on an IO scheme implemented for the pseudo channel based memory system. For example, the low latency memory access command may be implemented for an NRZ coding IO scheme implemented for the pseudo channel based memory system. As another example, implementing the low latency memory access command may depend on a combination of a clock frequency of the pseudo channel based memory system and an IO scheme implemented for the pseudo channel based memory system. For example, the low latency memory access command may be implemented for a clock frequency of the pseudo channel based memory system below a threshold, such as 1600 MHz, and implemented for an NRZ coding IO scheme implemented for the pseudo channel based memory system. In some examples, the memory control device that determines whether to execute the low latency memory access command in block 902 may include a pseudo channel controller (eg, pseudo channel controller 316 of FIGS. 3A-4C).

[0094] In response to determining to execute a low latency memory access command (i.e., decision block 902="yes"), the memory control device may perform method 500 beginning with operations at any of blocks 502, 504, 506 described herein with reference to Figure 5, or method 600 beginning with operations at any of blocks 602, 604 described herein with reference to Figure 6, for example. In response to determining not to execute a low latency memory access command (i.e., decision block 902="no"), the memory control device may perform operations at block 512 of method 500 described herein with reference to Figure 5.

[0095] 10A, 10B, 11A, and 11B show examples of timing diagrams of memory access commands with and without reduced latency in a pseudo-channel-based memory system (e.g., memory 106, memory 114 in FIG. 1, DDR 200 in FIG. 2, DDR 300a, 300b in FIG. 3A-FIG. 4C) according to some embodiments. With reference to FIG. 1-FIG. 11B, a DDR operating in a second operation mode (e.g., DDR 200 in FIG. 2, DDR 300a, 300b in FIG. 3A-FIG. 4C) may conventionally implement standard type memory access commands or non-low latency type memory access commands as shown in FIG. 10A and FIG. 11A, and a DDR operating in a first operation mode may implement low latency type memory access commands as shown in FIG. 10B and FIG. 11B. The DDR may include multiple pseudo channel data buses (e.g., data buses 204a, 204b in FIG. 2, pseudo channel data buses 312a, 312b in FIGS. 3A-4C) ("data bus A", "data bus B"). The pseudo channel data buses may have a particular bit width. For example, the bit width of the pseudo channel data bus may be 16 bits.

[0096] In a conventional implementation of a standard type memory access command or a non-low latency type memory access command, the DDR may transmit or receive data on a single dedicated pseudo channel data bus that requires a specific burst length, e.g., data bus A. In the example shown in FIG. 10A, the burst length is 32 bytes. In the example shown in FIG. 11A, the burst length is 64 bytes. When implementing a low latency type memory access command, the DDR may transmit or receive data on multiple pseudo channel data buses simultaneously, e.g., data bus A and data bus B. For example, the DDR may alternately transmit or receive odd and even bytes of data on the multiple pseudo channel data buses. In the example shown in FIG. 10B and FIG. 11B, the DDR may transmit or receive odd bytes of data on data bus A and even bytes of data on data bus B. As another example (not shown), the DDR may transmit or receive even bytes of data on data bus A and odd bytes of data on data bus B. A pair of odd and even bytes transmitted or received on data buses A and B may be a word of data having an upper byte and a lower byte. The upper byte may be transmitted or received on one of data buses A or B, and the lower byte may be transmitted or received on the other of data buses A or B. For example, the upper byte may be transmitted or received on data bus A or B dedicated to the target pseudo channel of the low latency type memory access command (e.g., pseudo channels 220a, 220b of FIGS. 3A-4C), and the lower byte may be transmitted or received on the other data bus A or B. Transmitting or receiving data on multiple pseudo channel data buses allows for a shorter burst length compared to conventional implementations of standard type memory access commands or non-low latency type memory access commands. For example, the burst length of conventional implementations of standard type memory access commands or non-low latency type memory access commands may be divided by the number of pseudo channel data buses used to transmit or receive the data. In the example shown in FIG. 10B, the burst length is 16 bytes, whereas in the example shown in FIG. 10A, it is 32 bytes.In the example shown in Figure 11B, the burst length is 32 bytes, compared to 64 bytes in the example shown in Figure 11A. Reducing the burst length may also reduce the number of clock cycles to complete a low latency memory access command compared to a standard memory access command or a low latency memory access command.

[0097] FIG. 12 illustrates an example timing diagram for using low-latency type memory access commands to reduce latency in a pseudo-channel based memory system (e.g., memory 106, memory 114, DDR 200, DDR 300a, 300b, FIG. 3A-4C) according to some embodiments. With reference to FIGS. 1-12, a DDR operating in a first mode of operation (e.g., DDR 200, DDR 300a, 300b, FIG. 3A-4C) may perform a low-latency type read memory access. The DDR may receive signals for performing a low-latency type read memory access, e.g., a column address strobe ("CAS"), and a signal for performing a low-latency type read memory access for a pseudo channel (e.g., pseudo channel 220a, 220b, FIG. 3A-4C) ("RD_LL_PC0"). The DDR may output data from the target pseudo channel on multiple pseudo channel data buses (e.g., data buses 204a, 204b in FIG. 2 and pseudo channel data buses 312a, 312b in FIGS. 3A-4C), data bus A and data bus B, in response to signals to perform low latency type read memory accesses.

[0098] 13A and 13B are timing diagrams illustrating an example of reducing latency in a pseudo-channel-based memory system (e.g., memory 106, memory 114, DDR 200, DDR 300a, 300b, DDR 300a, 300b, DDR 300a, 300b, DDR 400a, 300b, DDR 500a, 300b, DDR 600a, 300b, DDR 700a, 300b, DDR 800a, 300b, DDR 900a, 300b, DDR 1000a, 300b, DDR 1100a, 300b, DDR 1200a, 300b, DDR 1300a, 300b, DDR 1400a, 300b, DDR 1500a, 300b, DDR 1600a, 300b, DDR 1700a, 300b, DDR 1800a, 300b, DDR 1900a, 300b, DDR 200a, 300b, DDR 200a, 300b, DDR 200a, 300b, DDR 3 ... For a mode register write, the signal(s) may include a register address in the DDR and data to write to the register. For example, referring to FIG. 13B, MRW1 and MRW2 together may form a single mode register write. MRW1 may include a register address in the DDR and MRW2 may include data to write to the register. The DDR may receive signals to perform read memory accesses, such as a column address strobe ("CAS"), and a signal ("RD_PC0") to perform standard or non-low latency read memory accesses for a pseudo channel (e.g., pseudo channels 220a, 220b of FIGS. 3A-4C). The DDR may perform the read memory access as a low latency type read memory access in response to signals for the mode register write and signals for performing the read memory access, and output data from the target pseudo channel onto multiple pseudo channel data buses (e.g., data buses 204a, 204b in FIG. 2 and pseudo channel data buses 312a, 312b in FIGS. 3A-4C), data bus A and data bus B.

[0099] 14A and 14B are timing diagrams illustrating examples of memory access commands with and without reduced latency in a pseudo-channel-based memory system (e.g., memory 106, memory 114 in FIG. 1, DDR 200 in FIG. 2, DDR 300a, 300b in FIG. 3A-FIG. 4C) according to one embodiment. With reference to FIGS. 1-14B, a DDR operating in a second operation mode (e.g., DDR 200 in FIG. 2, DDR 300a, 300b in FIG. 3A-FIG. 4C) may conventionally implement standard type memory access commands or non-low latency type memory access commands as shown in FIG. 14A, and a DDR operating in a first operation mode may implement low latency type memory access commands as shown in FIG. 14B. The DDR may include multiple pseudo channels (e.g., pseudo channels 220a, 220b of Figures 2-4C) ("PC0", "PC1") and pseudo channel data buses (e.g., data buses 204a, 204b of Figure 2, pseudo channel data buses 312a, 312b of Figures 3A-4C) ("DQ0", "DQ1").

[0100] 14A and 14B, each chip select (CS) signal may correspond to a respective command and address (CA) validity signal (A, B, C, D in FIG. 14A and Q, R, S, T in FIG. 14B) and a respective memory access command (command) signal (E, F, G, H in FIG. 14A and U, V, W, X in FIG. 14B). Transmission of data signals (I, J in FIG. 14A and Y1, Y2, Z1, Z2 in FIG. 14B) may correspond to a respective command signal. A pseudo channel based memory system may implement memory access commands according to different clock cycles of different clocks, such as a system clock (CK_c, CK_t) and clocks for each pseudo channel (PC0, PC1), a write clock for PC0 (WCK0_c, WCK0_t) and a read clock for PC0 (RDQS0_t, RDQS0_c), and a write clock for PC1 (WCK1_c, WCK1_t) and a read clock for PC1 (RDQS1_t, RDQS1_c).

[0101] For the memory access command in the example shown in FIG. 14A, the CA validity signal A may correspond to a first CAS signal E, and the CA validity signal B may correspond to a first standard type memory access command or a non-low latency type memory access command F. The CA validity signal C may correspond to a second CAS signal G, and the CA validity signal D may correspond to a second standard type memory access command or a non-low latency type memory access command H. In a conventional implementation of standard type memory access commands or non-low latency type memory access commands for a pseudo channel, the DDR may transmit or receive data for each standard type memory access command or non-low latency type memory access command on a single dedicated pseudo channel data bus, for example, DQ0 for a read memory access of PC0(F) and DQ1 for a read memory access of PC1(H), and a specific burst length is required for each read memory access. In the example shown in FIG. 14A, the burst length is 32 bytes. Consecutive standard type memory access commands or non-low latency type memory access commands for different pseudo channels may be performed simultaneously, but may not be aligned to start and complete at the same time, requiring more clock cycles than would be required to complete a single standard type memory access command or non-low latency type memory access command. For example, a data signal (I) transmitted on DQ0 in response to a read memory access of PC0(F) may not be aligned with a data signal (J) transmitted on DQ1 in response to a read memory access of PC1(H).

[0102] For the memory access commands in the example shown in FIG. 14B, the CA validity signal Q may correspond to a first CAS signal U. The CA validity signal R may correspond to a first low latency type memory access command V. The CA validity signal S may correspond to a second CAS signal W, and the CA validity signal T may correspond to a second low latency type memory access command X. To implement a low latency type memory access command (V,X) for a pseudo channel, the DDR may transmit or receive data simultaneously on multiple pseudo channel data buses, such as DQ0 and DQ1 for a low latency type read memory access of PC0 (V) or PC1 (X). For example, the DDR may alternately transmit or receive odd and even bytes of data on multiple pseudo channel data buses. In the example shown in FIG. 14B, the DDR may transmit or receive odd bytes of data on DQ0 and simultaneously transmit or receive even bytes of data on DQ1. Transmitting or receiving data on multiple pseudo channel data buses allows for a shorter burst length compared to conventional implementations of standard type memory access commands or non-low latency type memory access commands. For example, the burst length of conventional implementations of standard type memory access commands or non-low latency type memory access commands may be divided by the number of pseudo channel data buses used to transmit or receive data. In the example shown in FIG. 14B, the burst length is 16 bytes, whereas in the example shown in FIG. 14A, it is 32 bytes. As shown in the command address (CA) lines, consecutive low latency type memory access commands for different pseudo channels, such as PC0 and PC1, may be performed consecutively, and shortening the burst length may allow for using fewer clock cycles than are required to complete the same number of standard type memory access commands or non-low latency type memory access commands.For example, a data signal (Y1) may be transmitted on DQ0 simultaneously with a data signal (Y2) transmitted on DQ1 in response to a read memory access of PC0(V), and a data signal (Z1) may be transmitted on DQ0 simultaneously with a data signal (Z2) transmitted on DQ1 in response to a successive read memory access of PC1(X).

[0103] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-14B) may be implemented in a wide variety of computing systems, including mobile computing devices, one example of a mobile computing device suitable for use with various embodiments is shown in FIG. 15. The mobile computing device 1500 may include a processor 1502 coupled to a touch screen controller 1504 and an internal memory 1506. The processor 1502 may be one or more multi-core integrated circuits designated for general purpose or specific processing tasks. The internal memory 1506 may be volatile or non-volatile memory, and may be secure and / or encrypted, or non-secure and / or non-encrypted, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 1504 and the processor 1502 may also be coupled to a touchscreen panel 1512, such as a resistive-sensing touchscreen, a capacitive-sensing touchscreen, an infrared-sensing touchscreen, etc. Additionally, the display of the mobile computing device 1500 need not have touchscreen capabilities.

[0104] The mobile computing device 1500 may have one or more wireless signal transceivers 1508 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio, etc.) and antennas 1510 coupled to each other and / or to the processor 1502 for transmitting and receiving communications. The transceivers 1508 and antennas 1510 may be used with the circuitry described above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1500 may include a cellular network wireless modem chip 1516 that enables communication over a cellular network and is coupled to the processor.

[0105] The mobile computing device 1500 may include a peripheral device connection interface 1518 coupled to the processor 1502. The peripheral device connection interface 1518 may be solely configured to accept one type of connection or may be configured to accept various types of common or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1518 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0106] The mobile computing device 1500 may also include a speaker 1514 to provide audio output. The mobile computing device 1500 may also include a housing 1520 constructed from plastic, metal, or a combination of materials that encases all or a portion of the components described herein. The mobile computing device 1500 may include a power source 1522 coupled to the processor 1502, such as a disposable battery or a rechargeable battery. The rechargeable battery may also be coupled to a peripheral device connection port to receive charging current from a source external to the mobile computing device 1500. The mobile computing device 1500 may also include a physical button 1524 to receive user input. The mobile computing device 1500 may also include a power button 1526 to turn the mobile computing device 1500 on and off.

[0107] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-14B) may be implemented in a wide variety of computing systems, including a laptop computer 1600, an example of which is shown in FIG. 16. Many laptop computers include a touchpad touch surface 1617 that serves as the computer's pointing device and may therefore receive drag, scroll, and flick gestures similar to those implemented on the computing devices described above equipped with touch screen displays. The laptop computer 1600 typically includes a processor 1602 coupled to a volatile memory 1612 and a large capacity non-volatile memory, such as a flash memory disk drive 1613. In addition, the computer 1600 may have one or more antennas 1608 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular telephone transceiver 1616 coupled to the processor 1602. The computer 1600 may also include a floppy disk drive 1614 and a compact disk (CD) drive 1615 coupled to the processor 1602. In a notebook configuration, the computer housing includes a touchpad 1617, a keyboard 1618, and a display 1619, all coupled to the processor 1602. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (e.g., via a USB input), as is well known, which may also be used with the various embodiments.

[0108] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-14B) may be implemented in a fixed computing system, such as any of a variety of commercially available servers. An exemplary server 1700 is shown in FIG. 17. Such a server 1700 typically includes one or more multi-core processor assemblies 1701 coupled to volatile memory 1702 and large capacity non-volatile memory, such as disk drive 1704. As shown in FIG. 17, multi-core processor assemblies 1701 may be added to the server 1700 by inserting them into a rack of assemblies. The server 1700 may also include a floppy disk drive, compact disk (CD) or digital versatile disk (DVD) disk drive 1706 coupled to the processor 1701. The server 1700 may also include a network access port 1703 coupled to the multi-core processor assembly 1701 for establishing a network interface connection with a network 1705, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0109] Example implementations are described in the following paragraphs. Although some of the example implementations below are described with respect to example systems, devices, or methods, further example implementations may include the example systems or devices discussed in the following paragraphs implemented as a method for performing operations of the example systems or devices, implemented by a computing device comprising a processing device configured with processing device executable instructions for performing operations of the example systems, devices, or methods, the example systems, devices, or methods discussed in the following paragraphs implemented by a computing device including means for performing the functions of the example systems, devices, or methods, and the example systems, devices, or methods discussed in the following paragraphs implemented as a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of the example systems, devices, or methods.

[0110] Example 1. A pseudo channel-based memory system including a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input / output (IO) and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to simultaneously communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and the second IO in a first operating mode.

[0111] Example 2. The pseudo channel based memory system of Example 1, wherein the first IO includes a first pseudo channel data bus and the second IO includes a second pseudo channel data bus, and the pseudo channel based memory system further includes: a first internal data bus having a bit width greater than the first pseudo channel data bus and communicatively connected to the first pseudo channel; a second internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the first internal data bus and the first pseudo channel selection device; and a third internal data bus having the same bit width as the second pseudo channel data bus and communicatively connected between a second portion of the first internal data bus and the second pseudo channel selection device.

[0112] Example 3. The pseudo channel based memory system of example 2, wherein the first internal data bus has a bit width equal to an integer multiple of the first pseudo channel data bus.

[0113] Example 4. A pseudo channel-based memory system as described in Example 2 or 3, further including: a fourth internal data bus having a bit width greater than the first pseudo channel data bus and communicatively connected to a second pseudo channel of the plurality of pseudo channels; a fifth internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the fourth internal data bus and the first pseudo channel selection device; and a sixth internal data bus having the same bit width as the second pseudo channel data bus and communicatively connected between a second portion of the fourth internal data bus and the second pseudo channel selection device.

[0114] Example 5. A pseudo channel based memory system as described in any of Examples 1 to 4, wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to simultaneously communicatively connect the first pseudo channel to the first IO and the second IO in response to the pseudo channel based memory system receiving a low latency type memory access command targeting the first pseudo channel.

[0115] Example 6. The pseudo channel based memory system of Example 5, further including a memory control device configured to receive a low latency type memory access command targeting the first pseudo channel, and in response to receiving the low latency type memory access command, send at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0116] Example 7. A pseudo channel based memory system as described in any of Examples 1 to 4, wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to simultaneously communicatively connect the first pseudo channel to the first IO and the second IO in response to the pseudo channel based memory system receiving a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands, and in response to the pseudo channel based memory system receiving consecutive memory access commands targeting the first pseudo channel.

[0117] Example 8. The pseudo channel based memory system of Example 7, further including a memory control device configured to receive a mode register write command, and in response to receiving the mode register write command, set a register value configured to cause the memory control device to treat consecutive memory access commands as low latency type memory access commands, receive consecutive memory access commands targeting the first pseudo channel, and in response to receiving the consecutive memory access commands, send at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0118] Example 9. The pseudo channel based memory system of any of Examples 1 to 8, wherein the first pseudo channel selection device and the second pseudo channel selection device each include at least one multiplexer.

[0119] Example 10. A pseudo channel-based memory system as described in any of Examples 1 to 9, wherein in a second operating mode, the first pseudo channel selection device is operable to communicatively connect a first pseudo channel to a first IO, and the second pseudo channel selection device is operable to communicatively connect a second pseudo channel of the plurality of pseudo channels to a second IO.

[0120] Example 11. A method for reducing latency in a pseudo channel-based memory system, comprising: communicatively connecting a first pseudo channel of a plurality of pseudo channels to a first IO of a plurality of input / outputs (IOs) by a first pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a first IO of the plurality of IOs; and in a first operating mode, communicatively connecting the first pseudo channel to a second IO of the plurality of IOs by a second pseudo channel selection device simultaneously with communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device, wherein the second pseudo channel selection device is configured to selectively communicatively connect one of the plurality of pseudo channels to the second IO.

[0121] Example 12. The method of example 11, wherein the first IO includes a first pseudo channel data bus and the second IO includes a second pseudo channel data bus, the method further including: transmitting data between the first pseudo channel data bus and the first pseudo channel via a first internal data bus having a bit-width greater than the first pseudo channel data bus and communicatively connected to the first pseudo channel, and a second internal data bus having the same bit-width as the first pseudo channel data bus and communicatively connected between a first portion of the first internal data bus and the first pseudo channel selection device; and transmitting data between the second pseudo channel data bus and the first pseudo channel via the first internal data bus and a third internal data bus having the same bit-width as the second pseudo channel data bus and communicatively connected between a second portion of the first internal data bus and the second pseudo channel selection device.

[0122] Example 13. The method of example 12, wherein the first internal data bus has a bit width equal to an integer multiple of the first pseudo channel data bus.

[0123] Example 14. The method of example 12 or 13, further comprising: transmitting data between the first pseudo channel data bus and a second pseudo channel of the plurality of pseudo channels via a fourth internal data bus having a bit width greater than the first pseudo channel data bus and communicatively connected to the second pseudo channel, and a fifth internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the fourth internal data bus and the first pseudo channel selection device; and transmitting data between the second pseudo channel data bus and the second pseudo channel via the fourth internal data bus and a sixth internal data bus having the same bit width as the second pseudo channel data bus and communicatively connected between a second portion of the fourth internal data bus and the second pseudo channel selection device.

[0124] Example 15. A method according to any of Examples 11 to 14, further comprising receiving a low latency type memory access command targeting a first pseudo channel, wherein the first pseudo channel is communicatively connected to the first IO by the first pseudo channel selection device and simultaneously the first pseudo channel is communicatively connected to the second IO by the second pseudo channel selection device in response to receiving the low latency type memory access command.

[0125] Example 16. The method of Example 15, further comprising, in response to receiving a low latency type memory access command, sending at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0126] Example 17. A method according to any of Examples 11 to 14, further comprising: receiving a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands; and receiving consecutive memory access commands targeted to a first pseudo channel, wherein communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device and simultaneously communicatively connecting the first pseudo channel to the second IO by the second pseudo channel selection device are performed in response to receiving the mode register write command and in response to receiving the consecutive memory access commands.

[0127] Example 18. The method of Example 17, further comprising: in response to receiving a mode register write command, setting a register value configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands; and in response to receiving the consecutive memory access commands, sending at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

[0128] Example 19. The method of any of Examples 11 to 18, wherein the first pseudo channel selection device and the second pseudo channel selection device each include at least one multiplexer.

[0129] Example 20. The method of any of Examples 11 to 19, further comprising, in the second operating mode, communicatively connecting, by a second pseudo channel selection device, a second pseudo channel of the plurality of pseudo channels to a second IO of the plurality of IOs.

[0130] Example 21. A pseudo channel-based memory system including a plurality of pseudo channels including a first pseudo channel, the pseudo channel-based memory system being configured to receive a memory access command targeted to the first pseudo channel and to use the first pseudo channel data bus and a second pseudo channel data bus to execute the memory access command.

[0131] Example 22. The pseudo channel based memory system of Example 21, wherein the memory access command is a read memory access command, and the pseudo channel based memory system is configured such that using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes outputting data from the first pseudo channel in response to the read memory access command via the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0132] Example 23. A pseudo channel based memory system as described in Example 21 or 22, wherein the memory access command is a write memory access command, and the pseudo channel based memory system is configured such that using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes receiving data of the write memory access command for the first pseudo channel via the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0133] Example 24. A pseudo channel based memory system as described in any of Examples 21 to 23, wherein the memory access command is configured to instruct the pseudo channel based memory system that the memory access command is a low latency type memory access command.

[0134] Example 25. A pseudo channel based memory system according to any of Examples 21 to 23, wherein the pseudo channel based memory system is further configured to receive a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands, and the memory access commands targeted to the first pseudo channel are consecutive memory access commands for the mode register write command.

[0135] Example 26. A method for reducing latency in a pseudo channel-based memory system having multiple pseudo channels including a first pseudo channel, comprising: receiving a memory access command targeted to the first pseudo channel; and using the first pseudo channel data bus and a second pseudo channel data bus to execute the memory access command.

[0136] Example 27. The method of example 26, wherein the memory access command is a read memory access command, and using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes outputting data from the first pseudo channel in response to the read memory access command via the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0137] Example 28. The method of example 26 or 27, wherein the memory access command is a write memory access command, and using the first pseudo channel data bus and the second pseudo channel data bus to execute the memory access command includes receiving data of the write memory access command for the first pseudo channel via the first pseudo channel data bus and the second pseudo channel data bus simultaneously.

[0138] Example 29. The method of any of Examples 26 to 28, wherein the memory access command is configured to indicate to the pseudo channel based memory system that the memory access command is a low latency type memory access command.

[0139] Example 30. A method as described in any of Examples 26 to 28, further comprising receiving a mode register write command configured to cause the pseudo channel based memory system to treat consecutive memory access commands as low latency type memory access commands, wherein the memory access commands targeted to the first pseudo channel are consecutive memory access commands for the mode register write command.

[0140] Computer program code or "program code" for execution on a programmable processor to perform operations of various embodiments may be written in a high level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or a variety of other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine code (such as object code) whose format is understandable by a processor.

[0141] The above method descriptions and process flow diagrams are provided merely as illustrative examples and do not require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of operations in the above-described embodiments may be performed in any order. Words such as "thereafter," "then," and "next" do not limit the order of operations. These words are merely used to guide the reader through the method description. Furthermore, any reference to a claim element in the singular, for example using the articles "a," "an," or "the," should not be construed as limiting the element to the singular.

[0142] The various exemplary logic blocks, modules, circuits, and algorithmic operations described with respect to the various embodiments may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0143] The hardware used to implement the various example logic, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0144] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable storage medium or a processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that may be accessed by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, operations of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable medium and / or a non-transitory computer-readable medium that may be embodied in a computer program product.

[0145] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. 1. A pseudo-channel based memory system, comprising: a first pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a first input / output (IO); a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO; a first pseudo channel selection device and a second pseudo channel selection device operable to simultaneously communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and the second IO in a first operating mode in response to the pseudo channel-based memory system receiving a mode register write command configured to cause the pseudo channel-based memory system to treat consecutive memory access commands as low latency type memory access commands, and in response to the pseudo channel-based memory system receiving consecutive memory access commands targeted to a first pseudo channel.

2. the first IO includes a first pseudo channel data bus, the second IO includes a second pseudo channel data bus, and the pseudo channel-based memory system comprises: a first internal data bus having a bit width greater than that of the first pseudo channel data bus and communicatively connected to the first pseudo channel; a second internal data bus having the same bit width as the first pseudo channel data bus, the second internal data bus being communicatively connected between the first portion of the first internal data bus and the first pseudo channel selection device; 2. The pseudo-channel-based memory system of claim 1, further comprising: a third internal data bus having a same bit width as the second pseudo-channel data bus, the third internal data bus being communicatively connected between a second portion of the first internal data bus and the second pseudo-channel selection device.

3. 3. The pseudo-channel-based memory system of claim 2, wherein the first internal data bus has a bit width equal to an integer multiple of the first pseudo-channel data bus.

4. a fourth internal data bus having a bit width greater than that of the first pseudo channel data bus and communicatively connected to a second pseudo channel of the plurality of pseudo channels; a fifth internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between the first portion of the fourth internal data bus and the first pseudo channel selection device; 3. The pseudo-channel-based memory system of claim 2, further comprising: a sixth internal data bus having the same bit width as the second pseudo-channel data bus, the sixth internal data bus being communicatively connected between a second portion of the fourth internal data bus and the second pseudo-channel selection device.

5. 2. The pseudo channel-based memory system of claim 1, wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to simultaneously communicatively connect the first pseudo channel to the first IO and the second IO in response to the pseudo channel-based memory system receiving a low latency type memory access command targeting the first pseudo channel.

6. The memory control device further includes: receiving the low latency type memory access command targeted to the first pseudo channel; 6. The pseudo channel-based memory system of claim 5, configured to, in response to receiving the low latency type memory access command, send at least one pseudo channel select signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

7. The memory control device further includes: receiving the mode register write command; In response to receiving the mode register write command, setting a register value configured to cause the memory control device to treat the consecutive memory access commands as low latency type memory access commands; receiving the continuous memory access command targeted to the first pseudo channel; 2. The pseudo channel-based memory system of claim 1, configured to, in response to receiving the consecutive memory access commands, send at least one pseudo channel select signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

8. 2. The pseudo-channel-based memory system of claim 1, wherein the first pseudo-channel selection device and the second pseudo-channel selection device each include at least one multiplexer.

9. 2. The pseudo channel-based memory system of claim 1, wherein in a second mode of operation, the first pseudo channel selection device is operable to communicatively connect the first pseudo channel to the first IO and the second pseudo channel selection device is operable to communicatively connect a second pseudo channel of the plurality of pseudo channels to the second IO.

10. 1. A method for reducing latency in a pseudo-channel based memory system, comprising: receiving a mode register write command configured to cause the pseudo-channel based memory system to treat consecutive memory access commands as low latency type memory access commands; receiving successive memory access commands targeted to a first pseudo channel; communicatively connecting a first pseudo channel of a plurality of pseudo channels to a first input / output (IO) by a first pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to the first IO of a plurality of IOs; in a first mode of operation, communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device and simultaneously communicatively connecting the first pseudo channel to a second IO of the plurality of IOs by a second pseudo channel selection device, the second pseudo channel selection device being configured to selectively communicatively connect one of the plurality of pseudo channels to the second IO; wherein communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device and simultaneously communicatively connecting the first pseudo channel to the second IO by the second pseudo channel selection device are performed in response to receiving the mode register write command and in response to receiving the consecutive memory access command.

11. the first IO includes a first pseudo channel data bus, the second IO includes a second pseudo channel data bus, and the method further comprises: transmitting data between the first pseudo channel data bus and the first pseudo channel via a first internal data bus having a bit width greater than that of the first pseudo channel data bus and communicatively connected to the first pseudo channel, and a second internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the first internal data bus and the first pseudo channel selection device; 11. The method of claim 10, further comprising transmitting data between the second pseudo channel data bus and the first pseudo channel via the first internal data bus and a third internal data bus having the same bit width as the second pseudo channel data bus, the third internal data bus being communicatively connected between a second portion of the first internal data bus and the second pseudo channel selection device.

12. the first internal data bus has a bit width equal to an integer multiple of the first pseudo channel data bus; or transmitting data between the first pseudo channel data bus and a second pseudo channel of the plurality of pseudo channels via a fourth internal data bus having a bit width greater than that of the first pseudo channel data bus and communicatively connected to a second pseudo channel, and a fifth internal data bus having the same bit width as the first pseudo channel data bus and communicatively connected between a first portion of the fourth internal data bus and the first pseudo channel selection device; 12. The method of claim 11, further comprising transmitting data between the second pseudo channel data bus and the second pseudo channel via the fourth internal data bus and a sixth internal data bus having the same bit width as the second pseudo channel data bus, the sixth internal data bus being communicatively connected between a second portion of the fourth internal data bus and the second pseudo channel selection device.

13. receiving a low latency type memory access command targeted to the first pseudo channel; 11. The method of claim 10, wherein communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device and simultaneously communicatively connecting the first pseudo channel to the second IO by the second pseudo channel selection device are performed in response to receiving the low latency type memory access command.

14. 14. The method of claim 13, further comprising, in response to receiving the low latency type memory access command, sending at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously.

15. In response to receiving the mode register write command, setting a register value configured to cause the pseudo-channel based memory system to treat the consecutive memory access commands as low latency type memory access commands; In response to receiving the consecutive memory access commands, transmitting at least one pseudo channel selection signal to the first pseudo channel selection device and the second pseudo channel selection device to cause the first pseudo channel selection device and the second pseudo channel selection device to communicatively connect the first pseudo channel to the first IO and the second IO simultaneously; or the first pseudo channel selection device and the second pseudo channel selection device each include at least one multiplexer; or 11. The method of claim 10, further comprising, in a second mode of operation, communicatively connecting, by the second pseudo channel selection device, a second pseudo channel of the plurality of pseudo channels to the second IO of the plurality of IOs.

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