Structures with conductive features for direct bonding and methods of forming same - Patents.com

Abstract

A structure and method for direct bonding are disclosed. The bonded structure can include a first element and a second element. The first element can include a first non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature having a first conductive material disposed in the cavity and a second conductive material thereon. The second conductive material can have a maximum grain size in a linear lateral dimension that is less than 20% of the linear lateral dimension of the conductive feature. The second conductive material can have less than 20 parts per million (ppm) of impurities present in the grain boundaries.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 291,285, entitled "STRUCTURE WITH CONDUCTIVE FEATURE FOR DIRECT BONDING AND METHOD OF FORMING SAME," filed on December 17, 2021, the contents of which are incorporated by reference in their entirety into this specification.

[0002] This field relates to structures and methods for direct bonding, and in particular to hybrid direct bonding of both conductive and non-conductive features. [Background technology]

[0003] Semiconductor elements, such as integrated device dies or chips, can be mounted or stacked on other elements. For example, a semiconductor element can be mounted on a carrier, such as an interposer, a reconstituted wafer, or an element. As another example, a semiconductor element can be stacked on another semiconductor element, such as a first integrated device die on a second integrated device die. Each semiconductor element can have conductive pads for mechanically and electrically coupling the semiconductor elements to one another. Summary of the Invention [Problem to be solved by the invention]

[0004] There are many advantages to directly bonding components together without the use of an intervening adhesive such as solder. However, direct hybrid bonding of both conductive and non-conductive areas is difficult. Thus, there is a continuing need for improved methods for forming conductive features such as conductive pads used in direct bonding. [Means for solving the problem]

[0005] Specific implementations are now described, by way of example and not limitation, with reference to the following drawings in which: [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of two elements prior to direct hybrid bonding. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after direct hybrid bonding. [Figure 2A] 1 is a cross-sectional scanning electron microscope (SEM) image of a conductive feature of two relatively small grains bonded together. [Figure 2B] 13A-13C are cross-sectional SEM images of a set of conductive features that are bonded to one another and a set of conductive features that are not bonded to one another. [Figure 2C] Cross-sectional SEM image of two fine copper pads containing large amounts of impurities that are only connected by a small area. [Figure 3A] 1A-1D illustrate steps in a manufacturing process for a bonded structure according to an embodiment. [Figure 3B] 1A-1D illustrate steps in a manufacturing process for a bonded structure according to an embodiment. [Figure 3C] 1A-1D illustrate steps in a manufacturing process for a bonded structure according to an embodiment. [Figure 3D] 1A-1D illustrate steps in a manufacturing process for a bonded structure according to an embodiment. [Figure 3E] 1A-1D illustrate steps in a manufacturing process for a bonded structure according to an embodiment. [Figure 4A] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Figure 4B] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Figure 4C] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Figure 4D] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Figure 4E] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Figure 4F] 5A-5C illustrate steps in a manufacturing process for a bonded structure according to another embodiment. [Diagram 5] 1 is an image generated to generally illustrate a conductive feature 42 including a first conductive material 36 and a second conductive material 38, according to one embodiment. [Figure 6] 2 is an image produced to generally illustrate a conductive feature 62 including a first conductive material 36 and a second conductive material 38 according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] This disclosure describes methods for forming conductive features having small grains at or near the bonding surface and large grains below the small grains. Such conductive features having different sized grains can be advantageous for direct metallurgical bonding, such as direct hybrid bonding. For example, two or more semiconductor elements (such as integrated device dies, wafers, etc.) can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure. The methods and bond pad structures described herein can be useful in other contexts as well.

[0008] Various embodiments disclosed herein relate to direct bonded structures that can bond two or more elements directly to each other without the use of an intervening adhesive. FIGS. 1A and 1B are schematic diagrams illustrating a process for forming a direct hybrid bonded structure without the use of an intervening adhesive, according to some embodiments. In FIGS. 1A and 1B, a bonded structure 100 includes two elements 102 and 104 that can be directly bonded to each other at a bonding interface 118 without the use of an intervening adhesive. To form the bonded structure 100, two or more microelectronic elements 102 and 104 (e.g., semiconductor elements including integrated device dies, wafers, passive devices, individual active devices such as power switches, etc.) can be stacked or bonded to each other. A conductive feature 106a (e.g., a contact pad, an exposed end of a via (e.g., TSV), or a through-substrate electrode) of the first element 102 can be electrically connected to a corresponding conductive feature 106b of the second element 104. Any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, etc. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the laterally stacked additional elements can be twice as small as the second element.

[0009] In some embodiments, the elements 102 and 104 are directly bonded to each other without the use of adhesive. In various embodiments, a non-conductive field region comprising a non-conductive or dielectric material can serve as the first bonding layer 108a of the first element 102, which can be directly bonded without the use of adhesive to a corresponding non-conductive field region comprising a non-conductive or dielectric material that serves as the second bonding layer 108b of the second element 104. The non-conductive bonding layers 108a and 108b can be disposed on the front sides 114a and 114b of the device portions 110a and 110b, such as the semiconductor (e.g., silicon) portions of the elements 102, 103, respectively. Active devices and / or circuits can be patterned and / or otherwise disposed in or on the device portions 110a and 110b. Active devices and / or circuits may be located on or near the front side 114a, 114b of the device portion 110a, 110b and / or on or near the opposite back side 116a, 116b of the device portion 110a, 110b. The bonding layer may be applied to the front side and / or back side of the element. The non-conductive material may be referred to as the non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 may be directly bonded to the corresponding non-conductive bonding layer 108b of the second element 104 using a dielectric-dielectric bonding technique. For example, the direct bonding techniques disclosed in at least U.S. Pat. Nos. 9,564,414, 9,391,143 and 10,434,749 may be used to form the non-conductive or dielectric-dielectric bond without the use of adhesives. It should be appreciated that in various embodiments, bonding layers 108a and / or 108b can include a non-conductive material, such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.Suitable dielectric bonding surfaces or materials for direct bonding may include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or materials that contain carbon, such as silicon carbide, silicon oxynitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. In some embodiments, the dielectric material does not include polymeric materials such as epoxies, resins, or molding compounds.

[0010] In some embodiments, the device portions 110a and 110b can have significantly different coefficients of thermal expansion (CTE) that define dissimilar structures. The CTE difference between the device portions 110a and 110b, especially between the bulk semiconductors that are typically the single crystal portions of the device portions 110a, 110b, can be greater than 5 ppm or 10 ppm. For example, the CTE difference between the device portions 110a and 110b can be in the range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 110a and 110b can comprise optoelectronic single crystal materials, including perovskite materials useful for opto-piezoelectric or pyroelectric applications, and the other of the device portions 110a, 110b can comprise a more conventional substrate material. For example, one of the device portions 110a, 110b may be made of lithium tantalate (LiTaO 3 ) or lithium niobate (LiNbO 3), and the other of device portions 110a, 110b includes silicon (Si), quartz, fused silica, sapphire, or glass. In other embodiments, one of device portions 110a, 110b can include a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of device portions 110a, 110b can include a non-III-V semiconductor material, such as silicon (Si), or another material having a similar CTE, such as quartz, fused silica, sapphire, or glass.

[0011] In various embodiments, a direct hybrid bond can be formed without the use of an intervening adhesive. For example, the non-conductive bonding surfaces 112a and 112b can be polished to a high degree of smoothness. The bonding surfaces 112a and 112b can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces 112a and 112b. In some embodiments, the surfaces 112a and 112b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces 112a and 112b, and the termination process can provide additional chemical species at the bonding surfaces 112a and 112b that increase the bond energy during direct bonding. In some embodiments, activation and termination are performed in the same step, such as activating and terminating the surfaces 112a and 112b with a plasma. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the terminating species can include nitrogen. For example, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surface 112a, 112b can be exposed to fluorine. For example, one or more fluorine peaks can be present at or near the bonding interface 118 between the first and second elements 102, 104. Thus, in the direct bonding structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a and 108b) can include a very smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface 118. Further examples of activation and / or termination processes are described in U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0012] In various embodiments, the conductive features 106a of the first element 102 can also be directly bonded to the corresponding conductive features 106b of the second element 104. For example, direct hybrid bonding techniques can be used to provide conductor-conductor direct bonding along a bonding interface 118 that includes covalently directly bonded non-conductor-non-conductor (e.g., dielectric-dielectric) surfaces prepared as described above. In various embodiments, conductor-conductor (e.g., conductive feature 106a-conductive feature 106b) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, the contents of each of which are incorporated herein by reference in their entirety for all purposes. In the direct hybrid bonding embodiments described herein, the conductive features are provided in a non-conductive bonding layer, and both the conductive and non-conductive features are prepared for direct bonding, such as by planarization, activation, and / or termination processes described above. Thus, the bonding surface prepared for direct bonding includes both conductive and non-conductive features.

[0013] For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (e.g., inorganic dielectric surfaces) can be prepared as described above and bonded directly to one another without the use of an intervening adhesive. Conductive contact features (e.g., conductive features 106a, 106b that can be at least partially surrounded by a non-conductive dielectric field region in bonding layers 108a, 108b) can also be bonded directly to one another without the use of an intervening adhesive. In various embodiments, the conductive features 106a, 106b can include discrete pads or traces at least partially embedded in a non-conductive field region. In some embodiments, the conductive contact features can include exposed contact surfaces of through-substrate vias (e.g., through-silicon vias (TSVs)). In some embodiments, the respective conductive features 106a and 106b can be recessed downward from the dielectric field region or outer (e.g., upper) surface of the non-conductive bonding layers 108a and 108b (non-conductive bonding surfaces 112a and 112b) by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements can be sized such that the total gap between the opposing contact pads is less than 15 nm or less than 10 nm. In some embodiments, the non-conductive bonding layers 108a and 108b can be directly bonded to each other at room temperature without the use of adhesive, and the bonded structure 100 can then be annealed. Upon annealing, the conductive features 106a and 106b can expand and contact each other to form a metal-metal direct bond. The use of Direct Bond Interconnect or DBI (registered trademark) technology, available from Adeia, Inc. of San Jose, California, can advantageously enable high density connection of conductive features 106a and 106b (e.g., small or fine pitch for regular arrays) across the direct bond interface 118.In some embodiments, the pitch of the conductive features 106a and 106b, such as conductive traces embedded in the bonding surface of one of the bonded elements, can be less than 100 microns, or less than 10 microns, or less than 2 microns. In some applications, it is desirable for the ratio of the pitch of the conductive features 106a and 106b to one of the dimensions of the bond pad (e.g., diameter) to be less than 20, or less than 10, or less than 5, or less than 3, and in some cases less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonded elements can range from 0.3 to 20 microns, such as, for example, 0.3 to 3 microns. In various embodiments, the conductive features 106a and 106b and / or traces can include copper or a copper alloy, although other metals may be suitable. For example, the conductive features disclosed herein, such as the conductive features 106a and 106b, can include a fine-grain metal (e.g., fine-grain copper).

[0014] Thus, in a direct bonding process, the first element 102 may be directly bonded to the second element 104 without the use of an intervening adhesive. In some configurations, the first element 102 may include a singulated element, such as a singulated integrated device die. In other configurations, the first element 102 may include a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) element regions that upon singulation form multiple integrated device dies. Similarly, the second element 104 may also include a singulated element, such as a singulated integrated device die. In other configurations, the second element 104 may include a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially coplanar and may include markings indicative of the common singulation process of the bonded structures (e.g., saw markings if a saw singulation process is used).

[0015] As described herein, the first and second elements 102, 104 can be directly bonded to each other without the use of adhesives, which is different from a deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element 102 in the bonded structure is similar to the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonded structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements 102 and 104 can include non-deposited elements. Furthermore, the direct bonded structure 100, unlike a deposited layer, can include defect regions along the bonded interface 118 where nanometer-scale voids (nanovoids) exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces 112a and 112b. As described above, the bonded interface 118 can include a concentration of material from the activation and / or the last chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, nitrogen peaks may form at the bonding interface 118. The nitrogen peaks may be detected using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) converts OH groups on hydrolyzed (OH-terminated) surfaces to NH 2 The bonding layer 108a and 108b may be substituted into the molecule to provide a nitrogen-terminated surface. In embodiments utilizing an oxygen plasma for activation, an oxygen peak may form at the bonding interface 118. In some embodiments, the bonding interface 118 may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond may include a covalent bond that is stronger than van der Waals bonds. The bonding layers 108a and 108b may also include a highly smoothly planarized polished surface.

[0016] In various embodiments, the metal-metal bond between the conductive features 106a and 106b can be bonded such that the metal grains grow into one another across the bond interface 118. In some embodiments, the metal is or includes copper and can have grains oriented mostly along 111 crystal planes to enhance diffusion of copper across the bond interface 118. In some embodiments, the conductive features 106a and 106b can include a nanotwinned copper grain structure that can aid in fusion of the conductive features during annealing. The bond interface 118 can extend substantially completely through at least a portion of the bonded conductive features 106a and 106b such that substantially no gaps exist between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer (which can include, for example, copper) can be applied below and / or laterally surrounding the conductive features 106a and 106b. However, in other embodiments, there may be no barrier layer beneath the conductive features 106a and 106b, as described, for example, in U.S. Pat. No. 11,195,748, which is incorporated herein by reference in its entirety for all purposes.

[0017] Use of the hybrid bonding techniques described herein has the advantage that they can enable very fine pitches between adjacent conductive features 106a and 106b and / or small pad sizes. For example, in various embodiments, the pitch p (i.e., end-to-end or center-to-center distance as shown in FIG. 1A) between adjacent conductive features 106a (or 106b) can be in the range of 0.5 microns to 50 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Additionally, the major lateral dimensions (e.g., pad diameter) can also be small, such as in the range of 0.25 microns to 30 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns.

[0018] As described above, the non-conductive bonding layers 108a, 108b can be bonded directly to one another without the use of adhesives, and the bonded structure 100 can then be annealed. Upon annealing, the conductive features 106a, 106b can expand and contact one another to form direct metal-metal bonds. In some embodiments, the materials of the conductive features 106a, 106b can interdiffuse during the annealing process.

[0019] The grain size of a conductive feature can affect the bond strength between the conductive feature and another conductive feature (e.g., conductive features 106a, 106b). In some embodiments, the conductive feature can include a metal feature, such as a copper contact pad or line. A conductive feature with a relatively small grain can be energetically unstable, and the grains can move toward equilibrium over time. Thus, conductive features with a relatively small grain size can be bonded to each other with a relatively high bond strength with minimal heat application, and lower annealing temperatures can be achieved for direct bonding with a relatively small grain size. For a given annealing temperature, the bond strength between such conductive features with a relatively small grain size is greater than the bond strength between single grain or large grain conductive features. In fact, a single grain across the surface of a metal feature may prevent bonding altogether, as shown in the right feature of FIG. 2B. In some embodiments, the conductive features being bonded can both include conductive features with relatively small grains. In some other embodiments, one of the conductive features may include a relatively small grain conductive feature, and the other of the conductive features may have a large grain conductive feature with multiple grain boundaries at the bonding surface. Bonding between small grain conductive features by interdiffusion may provide a sufficiently reliable metal-metal bond, whereas bonding between single grain or large grain conductive features by interdiffusion at a given annealing temperature may not provide a reliable conductor-conductor (e.g., metal-metal) bond. Impurities at the grain boundaries may inhibit or inhibit grain migration and bonding. Thus, minimal impurities near the bonding interface may be preferred. For example, in various embodiments disclosed herein, the grain boundaries of the conductive material at or near the bonding interface may have less than 20 parts per million (ppm) of impurities, such as 1 ppm or 3 ppm of impurities.In some embodiments, the grain boundaries of the conductive material at or near the bonding interface can have impurities between 1 ppm and 20 ppm, 5 ppm and 20 ppm, 1 ppm and 15 ppm, or 5 ppm and 15 ppm. The impurities can be measured, for example, using secondary ion mass spectrometry (SIMS) scanning techniques. For example, time-of-flight SIMS (TOF-SIMS) can be used to map the concentrations of various elements relative to the grain structure, including the boundaries. The crystal orientation of the conductive material can be determined, for example, using electron backscatter diffraction (EBSD) techniques. The grain boundary structure of the conductive material can be determined, for example, using electron microscopy (EM) techniques, such as high-resolution transmission electron microscopy (HRTEM) techniques. Based on the determined structure of the conductive material, the number of sites containing a particular impurity can be estimated.

[0020] In general, the grain size near the bonding interface can be observed on the surface of the conductive feature (before bonding) or on a cross-sectional view of the conductive feature. The grain size can be measured with respect to the lateral size of the conductive feature to be bonded, since one objective is to allow the grain boundaries of the conductive features on opposing elements to cross each other to facilitate mobility and therefore direct bonding. In conventionally processed substrates, as the pitch and lateral dimensions of the conductive features (e.g., bond pads, vias, traces, or TSVs) become smaller in successive integrated circuits (ICs), the grain size as a percentage of the feature becomes larger (e.g., bamboo grain structures), reducing the likelihood of the grain boundaries crossing each other during hybrid direct bonding. Small grains can be advantageous for mobility to facilitate direct bonding of the conductive features, compared to conventional processing and / or lateral dimensions of the conductive features composed of multiple grains or subgrains at the direct bonding interface. Presenting multiple grains at the bond interface increases the likelihood or probability that grain boundaries from opposing elements will intersect, even with the relatively small conductive feature sizes employed in today's ICs, and future conductive feature sizes expected to be even smaller. Thus, having small grains at the bond interface increases the likelihood or probability of forming a bond compared to having a larger grain at the bond interface, which has a greater number of grains present at the bond interface and brings fewer grain boundaries to the bond interface (e.g., a single grain). Conductive features such as bond pads, vias (e.g., TSVs), traces, or through-substrate electrodes of the embodiments described herein can have a maximum lateral dimension in the range of about 0.01 μm to 15 μm, about 0.1 μm to 10 μm, about 0.5 μm to 8 μm, about 2 μm to 5 μm, about 1 μm to 3 μm, or about 0.01 μm to 1 μm. An example of a relatively small high pitch bond pad is, for example, about 7 μm. 2 In one embodiment, the conductive feature has an exposed area greater than 100 mm.

[0021] The grain size at the top surface of the conductive feature that forms part of the hybrid direct bond interface prior to bonding is described. Thus, the grain size at the top surface of the conductive feature that forms part of the hybrid direct bond interface can be less than 20%, less than 10%, less than 5%, or less than 2% of the contact surface of the conductive feature that is configured to contact a corresponding contact surface of another element prior to bonding. These percentages can be calculated by dividing the average or maximum grain size by the conductive feature size, both of which are measured linearly in a lateral (e.g., x or y) dimension (linear lateral dimension), such as in a vertical cross section. In terms of area, the interfacial grain size (measured laterally at the bond interface) prior to bonding is less than 2000 nm 2 Less than 1000nm 2 Less than 500 nm 2 Less than 300 nm 2 Less than or equal to 180 nm 2 The conductive features provided by such relatively small grains can have 3-20, 3-15, or 4-8 grains exposed at the bonding surface, maximizing the likelihood of grain boundaries meeting at the bonding interface between two directly bonded conductive features. The maximum pre-bonding lateral dimension of the grains at the bonding interface can be less than 200 nm, less than 100 nm, less than 50 nm, less than 25 nm, less than 20 nm, or less than 15 nm.

[0022] We now describe the grain size at the top surface of the conductive features that form part of the hybrid direct bond interface after bonding. The interfacial grain size can be less than 30%, less than 20%, or less than 15% of the contact surface of the conductive features after bonding, which can include annealing to expand the conductive features into contact, tending to increase the grain size compared to the grain size before bonding, but remaining small compared to the post-anneal grain size resulting from conventional mass manufacturing, as described below. As with the pre-bonding comparison, these percentages can be calculated by dividing the average or maximum grain size by the conductive feature size, both grain size and feature size being measured linearly in a lateral (e.g., x or y) dimension, such as in a vertical cross section. The interfacial grain size (measured transversely in a vertical cross section) can be, for example, less than 30%, less than 20%, or less than 15% of the contact surface of the conductive features after bonding, which can include annealing to expand the conductive features into contact, tending to increase the grain size compared to the grain size before bonding, but remaining small compared to the post-anneal grain size resulting from conventional mass manufacturing, as described below. As with the pre-bonding comparison, these percentages can be calculated by dividing the average or maximum grain size by the conductive feature size, both grain size and feature size being measured linearly in a lateral (e.g., x or y) dimension, such as in a vertical cross section. 2 Less than 50000nm 2 Less than 20000nm 2 Less than 10000nm 2 Less than or equal to 8000 nm 2 It can mean less than.

[0023] Conductive features fabricated using conventional bulk manufacturing processes (e.g., bottom-up plating) may have relatively large grain sizes. Having a majority of conductive features with such large grain sizes may be advantageous because such grain sizes are more stable than smaller grain sizes, may exhibit better electrical conductivity and signal speed, and may have less electron migration. However, as discussed above, such large grains may be disadvantageous at direct bond interfaces. One way to achieve small grain sizes is to employ impurities that inhibit grain growth during the plating process. However, such processes may introduce high concentrations of impurities, especially at the grain boundaries, which may create another barrier to the mobility of the conductive material at the bond interface. It is difficult to form conductive features with relatively small grain sizes without impurities using such conventional processes. Also, forming relatively large conductive features with only small grains is time-consuming, economically inefficient, and may also adversely affect stability and electrical conductivity. Furthermore, forming relatively large conductive features with only small grains may also result in the formation of undesirable voids within the conductive features.

[0024] In general, impurities in the plated conductive material (e.g., copper) can include, for example, carbon, oxygen, nitrogen, and sulfur. The impurities can include, for example, non-alloying impurities that do not form an alloy with the conductive material (e.g., copper) of the contact pad. In another example, the impurities can include silicon oxide particles or silicon carbide particles.

[0025] FIG. 2A is a cross-sectional image of two conductive features (first conductive feature 10 and second conductive feature 12) bonded together. The first and second conductive features 10, 12 in the image of FIG. 2A comprise fine-grained copper (Cu) with multiple overlapping grain boundaries at the bond interface. Fine-grained metals can be defined as metals with an average grain width of less than 15 nm, less than 20 nm, less than 50 nm, less than 100 nm, less than 200 nm, less than 300 nm, or less than 500 nm. For example, the maximum grain width in fine-grained metals can be in the range of 10 nm to 500 nm, 10 nm to 300 nm, 15 nm to 500 nm, 15 nm to 300 nm, 15 nm to 100 nm, 15 nm to 50 nm, 50 nm to 500 nm, 50 nm to 300 nm, or 100 nm to 300 nm. In some embodiments, most of the grains in the fine-grained metal can have a width in the range of 10 nm to 500 nm, 10 nm to 300 nm, 15 nm to 500 nm, 15 nm to 300 nm, 15 nm to 100 nm, 15 nm to 50 nm, 50 nm to 500 nm, 50 nm to 300 nm, or 100 nm to 300 nm. In one example process, fine-grained copper is plated at a plating speed of about 0.28 μm per minute. FIG. 2A shows that many grains of the first and second conductive features 10, 12 intersect with the bonding interface between the first and second conductive features 10, 12, which can contribute to providing a reliable direct bond between the first and second conductive features 10, 12.

[0026] FIG. 2B is a cross-sectional image of conductive features 14a, 16a bonded together and conductive features 14b, 16b not bonded together. The grains of the conductive features 14a, 14b, 16a, 16b are relatively large compared to the overall feature size (e.g., there are a limited number of grain boundaries at the surface of the features). FIG. 2B shows that the conductive features 14b, 16b were prepared to bond together. However, the conductive features 14b, 16b did not bond together. The structure shown in FIG. 2B can show that the grains of the conductive feature 14b extending or spreading across almost the entire bonding interface of the conductive feature 14b prevent the formation of a metal-metal bond. Thus, there is not enough grain boundary overlap between the conductive features 14b, 16b to bond. This indicates that features with a large grain size compared to the feature size or bonding interface of the conductive features may have a high probability of not bonding the metal features. Thus, an array with a relatively large number of bonded features will have some of them not bonded, thus reducing the yield.

[0027] Figure 2C is a cross-sectional image of fine copper pads 18, 20 that contain a large amount of impurities bonded to each other only at small point regions. As described herein, one way to achieve relatively small grains (e.g., fine grains) is to introduce impurities that inhibit grain growth during the plating process. Figure 2C shows a less reliable bond between the fine copper pads 18, 20 than the first and second conductive features 10, 12 of Figure 2A.

[0028] Various embodiments disclosed herein relate to methods of forming conductive features that include relatively small grains at or near the bonding surface without excessive impurities or voids. According to various embodiments, the conductive features can be formed using two or more different processes. In one example, a plating process and a deposition process can be used to form the conductive features. In another example, a first plating process at a first rate and a second plating process at a second rate (e.g., using a higher current density) can be used to form the conductive features. In yet another example, a first conductor forming process provides the bulk of the conductive features, an annealing process provides larger and more stable grains, and a second conductor forming process provides the surface of the conductive features, with no annealing between the forming and bonding processes. The methods taught herein can form small grains near the bonding interface and larger grains further away from the interface, but without excessive additives at the grain boundaries near the interface.

[0029] Since the relatively small grains may grow over time, it may be advantageous to bond a conductive feature (a first conductive feature) to another conductive feature (a second conductive feature) relatively quickly. For example, bonding the first and second conductive features within 1-2 weeks of forming the first and second conductive features may maximize the chances of successful metal-metal direct bonding. When a chip or wafer is stored after fabrication for an extended period (e.g., 6 months or 1 year), the large grains tend to grow and inhibit the metal-metal bond, possibly due to a slower creep rate of the large grains or a reduction in the intersecting grain boundaries in the conductive features.

[0030] 3A-3E illustrate various steps in a manufacturing process for producing a bonding structure 30 according to some embodiments. In FIG. 3A, a cavity 32 may be formed in a non-conductive structure 34. In some embodiments, the non-conductive structure 34 may be disposed on a device portion 35. In FIG. 3B, a first deposition process may be used to at least partially fill the cavity 32 with a first conductive material 36. The first conductive material 36 may include copper. In some embodiments, the first conductive material 36 may be deposited over a thickness of about 1 cm. 2 less than 30mA per cm 2 The first conductive material 36 may be plated into the cavity 32 by a bottom-up fill process using a relatively low current density (less than 15 mA per second) and a relatively low deposition rate. The sidewalls 32 of the cavity 32 may be completely covered by the first conductive material 36. In some embodiments, the first conductive material 36 may be annealed prior to deposition of the second conductive material 38 to grow and stabilize the grains of the first conductive material 36. As shown, the first deposition process may be stopped before completely filling the cavity 32, leaving an opening 40 in the cavity 32.

[0031] In FIG. 3C, a second deposition process can be used to provide a second conductive material 38 at the opening 40 above the first conductive material 36 in the cavity 32. The second conductive material 38 can include copper. In some embodiments, the second conductive material 38 can be provided by plating at a higher deposition rate (higher current density) than the first deposition process using a relatively low additive concentration. For example, about 2 amperes per square decimeter (ASD) or amps / dm 2Relatively high current densities, such as above 7ASD or above, may be employed to form relatively fine grains. However, very high current densities, such as above the mass transfer limit of the 7ASD or plating bath, should be avoided to minimize coarse or porous metal coatings. In some embodiments, the first deposition process includes plating and the second deposition process includes vapor deposition, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Regardless of whether formed by a different plating or vapor deposition process, the grain size of the second conductive material 38 is on average appreciably smaller than the grain size of the first conductive material 36 and / or the second conductive material 38 has appreciably fewer impurities, such as those present from plating additives for grain control, compared to the first conductive material 36. In some embodiments, the first conductive material 36 may include more impurities than the second conductive material 38.

[0032] The surface including at least a portion of the non-conductive structure 34 and at least a portion of the second conductive material 38 may be polished and the surface may be treated (e.g., activated and terminated) to define a bonding surface for the element (e.g., the first element 30a). In some embodiments, the surface of the second conductive material 38 may be flush or nearly flush with the surface of the non-conductive structure 34. In other embodiments, the surface of the second conductive material 38 may be recessed relative to the surface of the non-conductive structure 34, as described above. The thickness of the second conductive material 38 may be less than 70%, less than 30%, or less than 20% of the thickness of the conductive feature 42 (the combination of the first conductive material 36 and the second conductive material 38). In some embodiments, the thickness of the second conductive material 38 may be between 30 nm and 600 nm, and the thickness of the first conductive material 36 may be between 400 nm and 5000 nm.

[0033] In FIG. 3D, the element formed in FIG. 3C (first element 30a) can be contacted with another element (second element 30b). The second element 30b can have the same or substantially similar structure as the first element 30a. The first conductive material 36 can be annealed prior to the formation of the second conductive material 38, which can be annealed prior to bonding or can be annealed at a lower temperature and / or for a shorter period of time compared to the annealing of the first conductive material having large grains at the bonding surface as described above. When the first element 30a is contacted with the second element 30b at room temperature, the non-conductive structure 34 of the first element 30a and the non-conductive structure 44 of the second element 30b can be bonded to each other along the bonding interface 47. In some embodiments, the non-conductive structure 44 can be disposed on the device portion 45. In some embodiments, when the first element 30a is contacted with the second element 30b at room temperature, the second conductive material 38 of the first element 30a and the conductive features 52 (which may include the third conductive material 46 and the fourth conductive material 48) of the second element 30b may bond together along the bond interface 47. In FIG. 3E, after the initial room temperature bonding of the non-conductive features 42, 52, the contacted first and second elements 30a, 30b may be annealed, and such post-bonding annealing may cause the conductive features to expand together to complete the hybrid bond and form the bonded structure 30. In some embodiments, the grain size of the second conductive material 38 in the bonded structure 30 may remain smaller than the grain size of the first conductive material 36.

[0034] 4A-4F illustrate various steps in a manufacturing process for producing a bonded structure 60, according to some embodiments. In FIG. 4A, a cavity 32 can be formed in a non-conductive structure 34. In FIG. 4B, a first deposition process can be used to fill the cavity 32 with a first conductive material 36. The first conductive material 36 can include copper. In some embodiments, the first conductive material 36 can be deposited at a current density (e.g., less than 2 amperes per square decimeter (ASD), more particularly less than 0.5 ASD or 30 mA / cm). 2less than, more specifically, 15 mA / cm 2 The first conductive material 36 may be plated into the cavity 32 by a bottom-up fill process using a relatively low current density (less than 1000 Å) and a relatively low deposition rate. In some embodiments, the cavity 32 may be completely filled with the first conductive material 36. Typically, the cavity 32 is overfilled and a CMP process is employed to remove the excess conductive material from above the non-conductive material 34, and then the excess conductive material is removed or planarized to form the structure shown in FIG. 4B. In some embodiments, the first conductive material 36 may be annealed to grow and stabilize the grains of the first conductive material 36 prior to deposition of the second conductive material 38.

[0035] In FIG. 4C, at least a portion of the first conductive material 36 may be removed to define an opening 64. In some embodiments, the first conductive material 36 may be selectively removed by etching (e.g., wet etching) to form a recess or opening 64 in the first conductive feature 36 shown in FIG. 2C. In some embodiments, a barrier layer (not shown) may be provided at least partially on the surface of the cavity 32. The first conductive material 36 may be provided after the barrier layer is formed to interpose the barrier layer between the surface of the cavity 32 and the first conductive material 36. In some embodiments, a portion of the first conductive material 36 may be selectively removed without removing the barrier layer. The recess or opening 64 may be formed by removing a portion of the first conductive material 36 disposed in the cavity 32 of the non-conductive material 34. The first conductive material 36 having the recess may be annealed to enlarge or stabilize the grains.

[0036] In FIG. 4D, a second deposition process can be used to provide a second conductive material 38 on the first conductive material 36 in the cavity 32. The second conductive material 38 can include copper. In some embodiments, the second conductive material 38 can be provided by plating at a higher deposition rate (higher current density) than the first deposition process using a lower additive concentration. For example, a relatively high current density, such as about 2 ASD or more, can be employed to form a relatively fine grain. However, very high current densities, such as above 7 ASD or 10 ASD, may not be preferred, as deposition at very high current densities can make the material rough or porous. In some embodiments, the first deposition process includes plating, and the second deposition process includes deposition, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Regardless of whether formed by a different plating or deposition process, the grain size of second conductive material 38 is, on average, appreciably smaller than the grain size of first conductive material 36, and second conductive material 38 has appreciably fewer impurities, such as those present from plating additives for grain control, compared to first conductive material 36.

[0037] A surface including at least a portion of the non-conductive structure 34 and at least a portion of the second conductive material 38 may be polished and treated (e.g., activated and terminated) to define a bonding surface for an element (e.g., first element 60A). In some embodiments, the surface of the second conductive material 38 may be flush or nearly flush with the surface of the non-conductive structure 34. In other embodiments, the surface of the second conductive material 38 may be recessed relative to the surface of the non-conductive structure 34, as described above.

[0038] In some embodiments, the pre-bonding recesses can have a depth of less than 75 nm, less than 50 nm, and preferably less than 20 nm below the non-conductive bonding surface. The thickness of the second conductive material 38 can be less than 70%, less than 50%, less than 30%, or less than 20% of the thickness of the conductive feature 62 (the combination of the first conductive material 36 and the second conductive material 38). In some embodiments, the thickness of the second conductive material 38 can be between 30 nm and 600 nm, and the thickness of the first conductive material 36 can be between 400 nm and 5000 nm. In some embodiments, the thickness of the second conductive material 38 can be greater than 50 nm.

[0039] In FIG. 2E, the element formed in FIG. 2D (first element 60a) can be contacted with another element (second element 60b). The first conductive material 36 can be annealed before forming the second conductive material 38, but the second conductive material 38 can be annealed at a lower temperature and / or for a shorter time compared to the annealing of the first conductive material so that the grain of the second conductive material 38 remains small as described above. The second element 60b can have the same or substantially similar structure as the first element 60a. When the first element 60a is contacted with the second element 60b at room temperature, the non-conductive structure 34 of the first element 60a and the non-conductive structure 44 of the second element 60b can be bonded to each other along the bonding interface 47. In some embodiments, when the first element 60a is contacted with the second element 60b at room temperature, the second conductive material 38 of the first element 60a and the conductive features 72 (which may include the third conductive material 46 and the fourth conductive material 48) of the second element 60b can bond together along the bond interface 47. In FIG. 2F, after the initial room temperature bonding of the non-conductive features 34, 44, the contacted first and second elements 60a, 60b can be annealed, and such post-bonding annealing can cause the conductive features 62, 72 to expand together to complete the hybrid bond and form the bonded structure 60. In the bonded structure 60, the grain size of the second conductive material 38 can remain smaller on average than the grain size of the first conductive material 36.

[0040] The components of Figures 3A-3E and 4A-4F can be the same as or generally similar to similar components disclosed herein, such as, for example, the components of Figures 1A and 1B. For example, non-conductive features 42, 52 can be the same as or generally similar to non-conductive bonding layers 108a, 108b, and device portions 35, 45 can be the same as or generally similar to device portions 110a, 110b.

[0041] In both the embodiment shown in Figures 3A-3E and the embodiment shown in Figures 4A-4F, the second conductive material 38 can include small or fine grains. The maximum grain size (measured in a lateral dimension in a vertical cross section) of the second conductive material 38 prior to bonding can be less than 20%, less than 10%, less than 5%, or less than 2% of the maximum lateral dimension of the contact surface of the conductive feature 62. In terms of the area occupied at the bond interface, the grain size prior to bonding can be less than 2000 nm 2 Less than 1000nm 2 Less than 500 nm 2 Less than 300 nm 2 Less than or equal to 180 nm 2 The maximum grain size of the second conductive material 38 before bonding, measured linearly in a lateral dimension, can be less than 500 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 25 nm, less than 20 nm, or less than 15 nm. For example, the maximum grain width of the second conductive material 38 can be in the range of 10 nm to 500 nm, 10 nm to 300 nm, 15 nm to 500 nm, 15 nm to 300 nm, 15 nm to 100 nm, 15 nm to 50 nm, 50 nm to 500 nm, 50 nm to 300 nm, or 100 nm to 300 nm.

[0042] In contrast, the lower first conductive material 36 may have larger grains. For example, in terms of lateral area, the grains of the first conductive material before bonding may be 2000 nm 2 Ultra, 4000nm 2 Ultra, 7000nm 2 Over 10,000 nm2 The maximum particle size of the first conductive material prior to bonding, measured linearly in a lateral dimension, can be greater than 50 nm, greater than 100 nm, greater than 300 nm, or greater than 500 nm. The average size of the first conductive material prior to bonding is greater than the average size of the second conductive material. In some embodiments, the average size of the first conductive material can be 10% to 200% greater than the average size of the second conductive material both prior to bonding and after bonding.

[0043] As described above, an annealing process can be performed after the initial bonding to further grow the conductive features 42, 52, 62, 72 of the opposing elements 30a, 30b, 60a, 60b together to complete the hybrid bond. This annealing process also increases the grain size of the second conductive material 38, but the second conductive material average grain size of the second conductive material 38 remains smaller than the average conductive material grain size of the underlying first conductive material 36. Although the first and second conductive materials 36, 38 can both comprise largely the same metal or metal alloy (e.g., copper), they can be distinguished by observably different average and maximum grain sizes, and in some embodiments, by a significantly higher additive impurity in the first conductive material 36 compared to the second conductive material 38. The grain size of the second conductive material 38 can have a maximum lateral dimension before bonding that is less than 200 nm, less than 150 nm, less than 100 nm, less than 50 nm, or less than 20 nm. The maximum cross-sectional area of ​​the second conductive material 38 before bonding is 2000 nm 2 Less than 1000nm 2 Less than 500 nm 2 Less than 300 nm 2 Less than or equal to 180 nm 2 The grain size of the second conductive material 38 after bonding can be less than 2 μm, less than 1 μm, less than 500 nm, or less than 300 nm due to grain growth during annealing. The maximum lateral dimension of the grain size of the second conductive material 38 after bonding can be less than 4 μm 2 Less than 1μm 2 Less than 250,000 nm 2 It can be less than.

[0044] Although the grains grow during the annealing process, the grains of the second conductive material 38 remain small relative to the conductive features 42, 62. The maximum grain size of the second conductive material 38 measured linearly in the lateral dimension can be less than 30%, less than 20%, or less than 15% of the width of the conductive features 42, 62 after bonding, where both grain size and feature size are measured linearly in the lateral dimension. The small grains of the second conductive material 38 can represent the top 1-20 grain layers, or more specifically the top 2-5 grain layers, from the bonding interface 47, while the grains further away from the bonding interface 47 are larger and can include higher impurity concentrations. After bonding, the average size of the first conductive material 36 can remain larger than the average size of the second conductive material 38 depending at least in part on the temperature profile of the post-bonding high temperature annealing process, e.g., a temperature of 200° C. or less and a bonding time of 60 minutes. In some embodiments, the average size of the first conductive material 36 after bonding can be 2-4 times larger than the average size of the second conductive material 38 .

[0045] FIG. 5 is an image generated to show what a conductive feature 42 looks like, including a first conductive material 36 and a second conductive material 38. FIG. 6 is an image generated to show what a conductive feature 62 looks like, including a first conductive material 36 and a second conductive material 38. FIGs. 5 and 6 show that the grain sizes of the first and second conductive materials 36, 38 are visibly different. One skilled in the art will recognize that the conductive features 42, 62 each include portions that include larger grains (e.g., the first conductive material 36) and visibly noticeable portions that include smaller grains (e.g., the second conductive material 38).

[0046] In one embodiment, a method of forming an element is disclosed. The method can include providing a non-conductive structure and forming a cavity in the non-conductive structure. The cavity extends at least partially through a thickness of the non-conductive structure from a surface of the non-conductive structure. The method can include providing a conductive feature including a first conductive material in the cavity and a second conductive material on the first conductive material. The second conductive material is disposed on a bonding surface of the element. A maximum grain size in a linear lateral dimension of the second conductive material is less than 20% of a linear lateral dimension of the conductive feature. The method can include preparing the bonding surface of the element for direct bonding.

[0047] In one embodiment, the second conductive material has less than 20 parts per million (ppm) of impurities at its grain boundaries.

[0048] In one embodiment, the average grain size of the second conductive material is smaller than the average grain size of the first conductive material.

[0049] In one embodiment, providing the conductive feature includes separately providing a first conductive material and a second conductive material. Providing the first conductive material can include partially filling the cavity. Providing the first conductive material can include filling the cavity with the first conductive material and removing a portion of the first conductive material. The method can further include annealing the first conductive material before providing the second conductive material. Providing the conductive material can include providing the second conductive material on the first conductive material by plasma vapor deposition (PVD). The second conductive material can be provided by plating at a higher current density than the first deposition process that provides the first conductive material. Preparing the bonding surface can include polishing the surfaces of the non-conductive material and the second conductive material.

[0050] In one embodiment, the maximum grain size of the second conductive material is less than 10% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 5% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 2% of the linear lateral dimension of the conductive feature.

[0051] In one embodiment, the area of ​​the conductive features on the bonding surface is 7 μm 2 Less than.

[0052] In one embodiment, the maximum grain lateral area in a cross-section of the second conductive material at the bonding surface is 2000 nm 2 Less than.

[0053] In one embodiment, the maximum linear lateral grain size of the second conductive material at the bonding surface is less than 200 nm.

[0054] In one embodiment, the first conductive material and the second conductive material include copper.

[0055] In one embodiment, the method further includes providing an intervening layer between the first conductive material and the second conductive material.

[0056] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material can be less than 30% of the thickness of the conductive feature.

[0057] In one aspect, a method of forming a bonded structure is disclosed. The method can include preparing a first element including a first non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature having a first conductive material disposed in the cavity and a second conductive material on the first conductive material. The second conductive material is at least partially exposed at the bonding surface of the element. The average grain size of the second conductive material is smaller than the average grain size of the first conductive material. The method can include preparing a second element including a second non-conductive structure and a second conductive feature. The method can include contacting the bonding surface of the first element with the bonding surface of the second element without performing an annealing process on the second conductive material, and directly bonding the first element with the second element after the contact.

[0058] In one embodiment, the second conductive material has less than 20 parts per million (ppm) of impurities at its grain boundaries.

[0059] In one embodiment, directly bonding the first element and the second element includes directly bonding the first non-conductive structure and the second non-conductive structure without the use of an intervening adhesive, and directly bonding the first conductive feature and the second conductive feature without the use of an intervening adhesive.

[0060] In one embodiment, providing the first element includes providing a first non-conductive structure, forming a cavity in the first non-conductive structure, providing a first conductive material, and providing a second conductive material after providing the first conductive material. The method can further include annealing the first conductive material before providing the second conductive material.

[0061] In one embodiment, the method further comprises annealing the bonded first and second elements.

[0062] In one embodiment, the method further includes preparing a bonding surface of the element for direct bonding. Preparing the bonding surface can include polishing a surface of the non-conductive material and the second conductive material.

[0063] In one embodiment, the maximum grain size in a linear lateral dimension of the second conductive material prior to directly bonding the first and second elements is less than 20% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material prior to directly bonding the first and second elements can be less than 10% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material prior to directly bonding the first and second elements can be less than 5% of the linear lateral dimension of the conductive feature.

[0064] In one embodiment, the overall exposed area of ​​the conductive features is less than 7 μm 2 Less than.

[0065] In one embodiment, the maximum grain lateral area of ​​the second conductive material prior to direct bonding of the first element and the second element is 2000 nm 2 Less than.

[0066] In one embodiment, the second conductive material has a maximum linear lateral grain size of less than 200 nm prior to directly bonding the first and second elements.

[0067] In one embodiment, the maximum grain size in a linear lateral dimension of the second conductive material after directly bonding the first element and the second element is less than 30% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 20% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 15% of the linear lateral dimension of the conductive feature.

[0068] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface after the first element and the second element are directly bonded is 71000 nm2 Less than.

[0069] In one embodiment, the maximum linear lateral grain size of the second conductive material at the bonding surface after direct bonding of the first element and the second element is less than 2 μm.

[0070] In one embodiment, the first conductive material and the second conductive material include copper.

[0071] In one embodiment, the method further includes providing an intervening layer between the first conductive material and the second conductive material.

[0072] In one embodiment, an element is disclosed. The element can include a non-conductive structure and a cavity in the non-conductive structure. The cavity extends at least partially through a thickness of the non-conductive structure from a surface of the non-conductive structure. The element can include a conductive feature in the cavity including a first conductive material and a second conductive material on the first conductive material. The second conductive material is disposed on a bonding surface of the element. A maximum grain size in a linear lateral dimension of the second conductive material is less than 20% of a linear lateral dimension of the conductive feature.

[0073] In one embodiment, the second conductive material has less than 20 parts per million (ppm) of impurities at its grain boundaries.

[0074] In one embodiment, the second conductive material has an average grain size in a linear lateral dimension that is smaller than the average grain size in a linear lateral dimension of the first conductive material.

[0075] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material can be less than 30% of the thickness of the conductive feature.

[0076] In one embodiment, the bonding surface of the component is prepared for direct bonding. The bonding surface may have a root mean square (rms) surface roughness of less than 2 nm.

[0077] In one embodiment, the maximum grain size of the second conductive material is less than 10% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 5% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 2% of the linear lateral dimension of the conductive feature.

[0078] In one embodiment, the linear lateral dimension of the conductive features at the bonding surface is 7 μm. 2 Less than.

[0079] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface is 2000 nm 2 Less than.

[0080] In one embodiment, the maximum grain size of the second conductive material at the bonding surface is less than 200 nm.

[0081] In one embodiment, the first conductive material and the second conductive material include copper.

[0082] In one embodiment, the element further includes an intervening layer between the first conductive material and the second conductive material.

[0083] In one embodiment, a bonded structure is disclosed. The bonded structure can include a first element including a first non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature having a first conductive material disposed in the cavity and a second conductive material on the first conductive material. The average grain size of the second conductive material is smaller than the average grain size of the first conductive material. The second conductive material has less than 20 parts per million (ppm) of impurities at its grain boundaries. The bonded structure can include a second element including a second non-conductive structure and a second conductive feature. The first element and the second element are bonded together such that the first non-conductive structure and the second non-conductive structure are directly bonded together without the use of an intervening adhesive. The second conductive material and the second conductive feature are directly bonded together without the use of an intervening adhesive.

[0084] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material is less than 30% of the thickness of the conductive feature.

[0085] In one embodiment, the first conductive material and the second conductive material include copper.

[0086] In one embodiment, the bond structure further comprises an intervening layer between the first conductive material and the second conductive material.

[0087] In one embodiment, the maximum grain size in a linear lateral dimension of the second conductive material after directly bonding the first element and the second element is less than 30% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 20% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 15% of the linear lateral dimension of the conductive feature.

[0088] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface after the first element and the second element are directly bonded is 71000 nm 2 Less than.

[0089] In one embodiment, the maximum linear lateral grain size of the second conductive material after direct bonding of the first element and the second element is less than 2 μm.

[0090] In one aspect, a method of forming an element is disclosed. The method includes providing a non-conductive structure, forming a cavity in the non-conductive structure, and providing a conductive feature including a first conductive material and a second conductive material on the first conductive material in the cavity such that the second conductive material is at least partially exposed at a bonding surface of the element. The second conductive material has less than 20 parts per million (ppm) of impurities at grain boundaries, and the second conductive material has a maximum grain size in a linear lateral dimension that is less than 20% of the linear lateral dimension of the conductive feature.

[0091] In one embodiment, providing the conductive feature includes separately providing a first conductive material and a second conductive material. Providing the first conductive material can include partially filling the cavity. Providing the first conductive material can include filling the cavity with the first conductive material and removing a portion of the first conductive material. The method can further include annealing the first conductive material before providing the second conductive material. Providing the conductive material can include providing the second conductive material on the first conductive material by vapor deposition. The vapor deposition can be physical vapor deposition or chemical vapor deposition. The second conductive material can be provided by plating at a higher current density than the first deposition process that provides the first conductive material.

[0092] In one embodiment, the method further includes preparing a bonding surface of the element for direct bonding. Preparing the bonding surface can include polishing the surfaces of the non-conductive material and the second conductive material. The maximum grain size of the second conductive material can be less than 5% of a linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 2% of a linear lateral dimension of the conductive feature.

[0093] In one embodiment, the overall exposed area of ​​the conductive features is less than 7 μm 2 Less than.

[0094] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface is 2000 nm 2 Less than.

[0095] In one embodiment, the maximum particle size of the second conductive material is less than 200 nm.

[0096] In one embodiment, the first conductive material and the second conductive material include copper.

[0097] In one embodiment, the method further includes providing an intervening layer between the first conductive material and the second conductive material.

[0098] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material is less than 30% of the thickness of the conductive feature.

[0099] In one aspect, a method of forming a bonded structure is disclosed. The method can include providing a first element including a first non-conductive structure having a non-conductive bonding surface, a cavity in the non-conductive structure, and a first conductive feature having a first conductive material disposed in the cavity and a second conductive material on the first conductive material. The second conductive material is at least partially exposed at the bonding surface of the element. The second conductive material has less than 20 parts per million (ppm) of impurities at grain boundaries. The second conductive material has a maximum grain size in a linear lateral dimension that is less than 20% of the linear lateral dimension of the conductive feature. The method can include providing a second element including a second non-conductive structure and a second conductive feature. The method can include contacting the bonding surface of the first element with the bonding surface of the second element without performing an annealing process on the second conductive material, and directly bonding the first element with the second element after the contact.

[0100] In one embodiment, directly bonding the first element and the second element includes directly bonding the first non-conductive structure and the second non-conductive structure without the use of an intervening adhesive, and directly bonding the first conductive feature and the second conductive feature without the use of an intervening adhesive.

[0101] In one embodiment, providing the first element includes providing a first non-conductive structure, forming a cavity in the first non-conductive structure, providing a first conductive material, and providing a second conductive material after providing the first conductive material. The method can further include annealing the first conductive material before providing the second conductive material.

[0102] In one embodiment, the method further comprises annealing the bonded first and second elements.

[0103] In one embodiment, the method further includes preparing a bonding surface of the element for direct bonding. Preparing the bonding surface can include polishing a surface of the non-conductive material and the second conductive material.

[0104] In one embodiment, the maximum grain size of the second conductive material prior to directly bonding the first and second elements is less than 5% of a linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material prior to directly bonding the first and second elements can be less than 2% of a linear lateral dimension of the conductive feature.

[0105] In one embodiment, the overall exposed area of ​​the conductive features is less than 7 μm 2 Less than.

[0106] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface before the first element and the second element are directly bonded is 2000 nm 2 Less than.

[0107] In one embodiment, the maximum particle size of the second conductive material prior to direct bonding of the first element and the second element is less than 200 nm.

[0108] In one embodiment, the maximum grain size of the second conductive material after directly bonding the first element and the second element is less than 30% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 20% of the linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 15% of the linear lateral dimension of the conductive feature.

[0109] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface after the first element and the second element are directly bonded is 71000 nm 2 Less than.

[0110] In one embodiment, the maximum grain size of the second conductive material after directly bonding the first element and the second element is less than 2 μm.

[0111] In one embodiment, the first conductive material and the second conductive material include copper.

[0112] In one embodiment, the method further includes providing an intervening layer between the first conductive material and the second conductive material.

[0113] In one embodiment, an element is disclosed. The element can include a non-conductive structure and a cavity in the non-conductive structure. The cavity extends at least partially through a thickness of the non-conductive structure from a surface of the non-conductive structure. The element can include a conductive feature including a first conductive material in the cavity and a second conductive material on the first conductive material. The second conductive material is disposed on a bonding surface of the element. The second conductive material has a maximum grain size in a linear lateral dimension that is less than 20% of the linear lateral dimension of the conductive feature. The second conductive material has less than 20 parts per million (ppm) of impurities in its grain boundaries.

[0114] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material can be less than 30% of the thickness of the conductive feature.

[0115] In one embodiment, the bonding surface of the component is prepared for direct bonding. The bonding surface may have a root mean square (rms) surface roughness of less than 2 nm.

[0116] In one embodiment, the maximum grain size of the second conductive material is less than 5% of a linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material can be less than 2% of a linear lateral dimension of the conductive feature.

[0117] In one embodiment, the area of ​​the conductive features on the bonding surface is 7 μm 2 Less than.

[0118] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface is 2000 nm 2 Less than.

[0119] In one embodiment, the maximum particle size of the second conductive material is less than 200 nm.

[0120] In one embodiment, the first conductive material and the second conductive material include copper.

[0121] In one embodiment, the element further includes an intervening layer between the first conductive material and the second conductive material.

[0122] In one embodiment, a bonded structure is disclosed. The bonded structure can include a first element including a first non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature having a first conductive material disposed in the cavity and a second conductive material on the first conductive material. The bonded structure can include a second element including a second non-conductive structure and a second conductive feature. The first element and the second element are bonded together such that the first non-conductive structure and the second non-conductive structure are directly bonded together without the use of an intervening adhesive, and the second conductive material and the second conductive feature are directly bonded together without the use of an intervening adhesive. The second conductive material has a maximum grain size in a linear lateral dimension after directly bonding the first element and the second element is less than 30% of the linear lateral dimension of the conductive feature.

[0123] In one embodiment, the second conductive material has less than 20 parts per million (ppm) of impurities at its grain boundaries.

[0124] In one embodiment, the thickness of the second conductive material is less than 50% of the thickness of the conductive feature. The thickness of the second conductive material is less than 30% of the thickness of the conductive feature.

[0125] In one embodiment, the first conductive material and the second conductive material include copper.

[0126] In one embodiment, the bond structure further comprises an intervening layer between the first conductive material and the second conductive material.

[0127] In one embodiment, the maximum grain size of the second conductive material after directly bonding the first element and the second element is less than 20% of a linear lateral dimension of the conductive feature. The maximum grain size of the second conductive material after directly bonding the first element and the second element can be less than 15% of a linear lateral dimension of the conductive feature.

[0128] In one embodiment, the maximum grain lateral area of ​​the second conductive material at the bonding surface after the first element and the second element are directly bonded is 71000 nm 2 Less than.

[0129] In one embodiment, the maximum grain size of the second conductive material after directly bonding the first element and the second element is less than 2 μm.

[0130] In one embodiment, the overall exposed area of ​​the conductive features is less than 7 μm 2 Less than.

[0131] In one aspect, a method of forming conductive features in a substrate for direct hybrid bonding is disclosed. The method can include depositing a first conductive material by a first deposition process including plating under conditions to form a first average grain size. The method can include depositing a second conductive material by a second deposition process different from the first deposition process without increasing the impurity level relative to the first deposition process. The second deposition process forms a second average grain size smaller than the first deposition process. The method can include preparing a bonding surface for direct hybrid bonding including a second conductive material and a non-conductive surface.

[0132] In one embodiment, the first conductive material has an impurity level equal to or greater than the second conductive material.

[0133] In one embodiment, the second deposition process is a process that inhibits grain growth without introducing less than 20 parts per million (ppm) of impurities into the grain boundaries of the second conductive material.

[0134] In one embodiment, the first deposition process comprises a plating process and the second deposition process comprises an evaporation process. The plating process is performed at 2 amp / dm 2 Current densities in excess of 1000 .mu.m can be used.

[0135] In one embodiment, the first deposition process includes plating with a first current density and the second deposition process includes plating with a second current density that is higher than the first current density.

[0136] In one embodiment, the first deposition process comprises plating and the second deposition process comprises evaporation.

[0137] In one embodiment, the first conductive material and the second conductive material comprise primarily copper.

[0138] Unless the context clearly requires otherwise, words such as "comprise, comprising, include, including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to," rather than an exclusive or exhaustive sense. The word "coupled," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Similarly, the word "connected," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Additionally, when the application uses words such as "herein," "above," "below," and words of similar import, these words are intended to refer to the application as a whole and not to any particular portion of the application. Furthermore, when a first element is described herein as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact with each other, or indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. Words using the singular or plural in the above detailed description can also include the plural or singular, respectively, where the context allows. The word "or" when referring to a list of two or more items covers all interpretations of the word, such as any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0139] Additionally, as used herein, inter alia, conditional terms such as "can, could, might, may" and "eg, for example, such as" are generally intended to convey that some embodiments include certain features, elements and / or conditions and other embodiments do not include them, unless expressly stated otherwise or understood otherwise within the context of use. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required for one or more embodiments.

[0140] Although several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, method and system described herein may be embodied in various other forms, and various omissions, substitutions and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although blocks are shown in a given arrangement, another embodiment may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. 1. A method of forming a device, comprising: Providing a non-conductive structure; forming a cavity in the non-conductive structure extending from a surface of the non-conductive structure through at least a portion of a thickness of the non-conductive structure; providing a conductive feature including a first conductive material in the cavity and a second conductive material on the first conductive material, the second conductive material being disposed on a bonding surface of the element, the second conductive material having a maximum grain size in a linear lateral dimension that is less than 20% of a linear lateral dimension of the conductive feature; preparing the bonding surface of the component for direct bonding; A method comprising:

2. impurities present at grain boundaries of the second conductive material at less than 20 parts per million (ppm); The method of claim 1.

3. the average particle size of the second conductive material is smaller than the average particle size of the first conductive material; The method of claim 1.

4. providing the conductive feature includes separately providing the first conductive material and the second conductive material; further comprising annealing the first conductive material before providing the second conductive material. The method of claim 1.

5. providing the conductive material includes providing the second conductive material on the first conductive material by plasma vapor deposition (PVD) or by plating at a higher current density than a first deposition process providing the first conductive material; The method of claim 1.

6. the maximum grain size of the second conductive material is less than 10% of the linear lateral dimension of the conductive feature; The method of claim 1.

7. a maximum linear lateral grain size of the second conductive material at the bonding surface is less than 200 nm; The method of claim 1.

8. the thickness of the second conductive material is less than 50% of the thickness of the conductive feature; The method of claim 1.

9. 1. A method for forming a bonded structure, comprising: a first non-conductive structure having a non-conductive bonding surface; a cavity extending at least partially through the thickness of the non-conductive structure from the non-conductive bonding surface; a first conductive feature having a first conductive material disposed in the cavity and a second conductive material on the first conductive material; providing a first element comprising: the second conductive material being at least partially exposed at a bonding surface of the element, and the second conductive material having an average grain size smaller than the average grain size of the first conductive material; a second non-conductive structure; and a second conductive feature; and providing a second element comprising: contacting the bonding surface of the first element with the bonding surface of the second element without subjecting the second conductive material to an annealing process; directly bonding the first element and the second element after said contacting; A method comprising:

10. impurities present at grain boundaries of the second conductive material at less than 20 parts per million (ppm); 10. The method of claim 9.

11. directly bonding the first element and the second element includes directly bonding the first non-conductive structure and the second non-conductive structure without an intervening adhesive, and directly bonding the first conductive feature and the second conductive feature without an intervening adhesive.

10. The method of claim 9.

12. Providing the first element includes: providing the first non-conductive structure; forming a cavity in the first non-conductive structure; providing a first conductive material; providing a second conductive material after providing the first conductive material; annealing the first conductive material before providing the second conductive material; 10. The method of claim 9, comprising:

13. The total exposed area of ​​the conductive features is 7 μm 2 is smaller than 10. The method of claim 9.

14. a maximum grain size in a linear lateral dimension of the second conductive material after directly bonding the first element and the second element is less than 30% of a linear lateral dimension of the conductive feature; 10. The method of claim 9.

15. the maximum linear lateral grain size of the second conductive material at the bonding surface after direct bonding of the first element and the second element is less than 2 μm; 10. The method of claim 9.

16. 1. A method of forming conductive features in a substrate for direct hybrid bonding, comprising: depositing a first conductive material by a first deposition process including plating under conditions to form a first average grain size; depositing a second conductive material by a second deposition process different from the first deposition process, the second deposition process forming a second average grain size smaller than the first deposition process, without increasing impurity levels relative to the first deposition process; preparing a bonding surface comprising the second conductive material and a non-conductive surface for direct hybrid bonding; A method comprising:

17. the impurity level of the first conductive material is equal to or greater than that of the second conductive material; 17. The method of claim 16.

18. the second deposition process inhibits grain growth without introducing less than 20 parts per million (ppm) of impurities into the grain boundaries of the second conductive material.

17. The method of claim 16.

19. the first deposition process comprises a plating process and the second deposition process comprises an evaporation process; 17. The method of claim 16.

20. the first deposition process includes plating using a first current density, and the second deposition process includes plating using a second current density higher than the first current density; 17. The method of claim 16.

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