Multilayer Ceramic Capacitors

Abstract

The present invention is directed to a multilayer capacitor and a circuit board including the multilayer capacitor. The capacitor comprises a body including a set of alternating dielectric layers and internal electrode layers, the set including a first internal electrode layer and a second internal electrode layer, each internal electrode layer including a top edge, a bottom edge opposite the top edge, and two side edges extending between the top and bottom edges, which define the body of the internal electrode layer. Each internal electrode layer includes at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the capacitor and on a bottom surface of the capacitor opposite the top surface of the capacitor. The capacitor comprises one or more dielectric regions including one or more voids.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 295,079, having a filing date of December 30, 2021, which is incorporated by reference in its entirety herein. [Background technology]

[0002] Multilayer capacitors are generally constructed with multiple dielectric and internal electrode layers arranged in a stack. During manufacture, the stacked dielectric and internal electrode layers are compressed and sintered to obtain a substantially unitary capacitor body. In attempts to improve the performance of these capacitors, various configurations and designs have been used for the dielectric and internal electrode layers.

[0003] However, these configurations are commonly modified as rapid changes occur in the electronics industry that require new performance standards. Specifically, various application design considerations have created the need to redefine capacitor parameters and their performance in high speed environments, especially in light of faster and higher density integrated circuits. For example, higher currents, higher density circuit boards, and rising costs have all served to focus the need for better and more efficient capacitors. Additionally, the design of various electronic components has been driven by general industry trends toward miniaturization as well as increased functionality. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 7,177,137 [Patent Document 2] U.S. Patent No. 7,463,474 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, there is a need to provide a capacitor having improved operating characteristics. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The capacitor includes a body including a set of alternating dielectric layers and internal electrode layers, the set including a first internal electrode layer and a second internal electrode layer, each internal electrode layer including a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge, which define the body of the internal electrode layer. Each internal electrode layer includes at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the capacitor and a bottom surface of the capacitor opposite the top surface of the capacitor. The capacitor includes one or more dielectric regions including one or more air voids.

[0007] Other features and aspects of the invention are described in greater detail below.

[0008] A full and enabling disclosure of the present invention, including the best mode thereof, to one of ordinary skill in the art, is set forth more particularly in remaining portions of the specification, including reference to the accompanying figures. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1 is a general top and side external perspective view of one embodiment of a capacitor including two external terminals in accordance with the present invention. [Figure 1B] FIG. 1B is a top external perspective view of the internal electrode layers of the capacitor of FIG. 1A. [Figure 2A] FIG. 2 is a general top and side external perspective view of another embodiment of a capacitor including four external terminals in accordance with the present invention. [Figure 2B]FIG. 2B is a top external perspective view of the internal electrode layers of the capacitor of FIG. 2A. [Figure 3A] FIG. 1 is a perspective view of a 2 by 2 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 3B] FIG. 2 is a perspective view of a two-by-two capacitor including external terminals on the top and bottom surfaces according to the present invention. [Figure 3C] FIG. 2 is a perspective view of a two-by-two capacitor including external terminals on the top and bottom surfaces according to the present invention. [Figure 3D] FIG. 2 is a perspective view of a two-by-two capacitor including external terminals on the top and bottom surfaces according to the present invention. [Figure 4A] FIG. 1 is a perspective view of a 2 by 4 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 4B] FIG. 1 is a perspective view of a 2-by-4 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 4C] FIG. 1 is a perspective view of a 2-by-4 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 4D] FIG. 1 is a perspective view of a 2-by-4 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 5A] FIG. 1 is a perspective view of a 4 by 4 capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. [Figure 5B] FIG. 2 is a perspective view of a four-by-four capacitor including external terminals on the top and bottom surfaces in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Those skilled in the art should appreciate that this discussion is merely a description of exemplary embodiments and is not intended as a limitation of the broader aspects of the invention.

[0011] In general, the present invention is directed to a multilayer capacitor. The multilayer capacitor includes at least one capacitive element within a body. Specifically, the at least one capacitive element is within a single integral package. In this regard, the multilayer capacitor includes a set of alternating dielectric layers and internal electrode layers. Generally, the set of alternating dielectric layers and internal electrode layers defines a capacitive element. The capacitor also includes a dielectric region that includes an air gap.

[0012] The particular arrangement of the capacitive elements within a single integral package (i.e., a single body) and the inclusion of the air gap can provide several advantages. For example, by utilizing the air gaps disclosed herein, crosstalk and interference between external terminals can be specifically minimized and / or eliminated, especially when the capacitors are utilized in various electronic devices. Furthermore, due to the nature of the construction, the capacitors of the present invention can be mounted on a circuit board as surface mount capacitors and can provide a smaller footprint on the circuit board. This can also allow for a reduction in the size of the circuit board.

[0013] Furthermore, in certain applications, it is desirable to keep the inductance (i.e., parasitic inductance) as low as possible. The use of the capacitor of the present invention allows for a substantial reduction in inductance. Specifically, minimizing the distance or path for the ground connection can aid in reducing the inductance. In general, the use of the capacitor of the present invention can allow for at least an order of magnitude reduction in inductance compared to using multiple individual multilayer ceramic capacitors. For example, the use of the capacitor of the present invention can provide an inductance on the order of picohenries or even femtohenries compared to prior art capacitors exhibiting greater inductance. In general, the inductance can be less than 1 nanohenry. Specifically, the inductance can be 900 picohenries or less, e.g., 750 picohenries or less, 500 picohenries or less, 400 picohenries or less, 250 picohenries or less, 100 picohenries or less, 50 picohenries or less, 25 picohenries or less, 15 picohenries or less, 10 picohenries or less, etc. The inductance may be 1 femtohenries or more, e.g., 25 femtohenries or more, 50 femtohenries or more, 100 femtohenries or more, 250 femtohenries or more, 500 femtohenries or more, 750 femtohenries or more, etc. Minimizing such inductance may contribute to good performance, particularly under fast transient conditions, and in particular good decoupling performance.

[0014] Furthermore, the capacitor can provide a desired capacitance. Specifically, the capacitance can be 1,000 μF or less, such as 750 μF or less, 500 μF or less, 250 μF or less, 100 μF or less, 50 μF or less, 25 μF or less, 20 μF or less, 15 μF or less, 10 μF or less, 5 μF or less, 2.5 μF or less, 1 μF or less, 0.75 μF or less, 0.5 μF or less, etc. The capacitance can be 1 pF or more, such as 10 pF or more, 25 pF or more, 50 pF or more, 100 pF or more, 250 pF or more, 500 pF or more, 750 pF or more, 900 pF or more, 1 μF or more, 2 μF or more, 3 μF or more, 5 μF or more, 8 μF or more, 10 μF or more, etc. The capacitance can be measured using common techniques known in the art.

[0015] Furthermore, the capacitor can provide a desired resistance. Specifically, the resistance can be 100mOhms or less, such as 75mOhms or less, 50mOhms or less, 40mOhms or less, 30mOhms or less, 25mOhms or less, 20mOhms or less, 15mOhms or less, 10mOhms or less, 5mOhms or less, etc. The resistance can be 0.01mOhms or more, such as 0.1mOhms or more, 0.25mOhms or more, 0.5mOhms or more, 1mOhms or more, 1.5mOhms or more, 2mOhms or more, 5mOhms or more, 10mOhms or more, etc. The resistance can be measured using common techniques known in the art.

[0016] As mentioned above, the present invention includes a multi-layer capacitor that houses one or more capacitive elements in a single integral package. The capacitor includes a top surface and a bottom surface opposite the top surface. The capacitor also includes at least one side surface, specifically at least two side surfaces, extending between the top and bottom surfaces. The capacitor may include at least one end surface, specifically at least two end surfaces, extending between the top and bottom surfaces. In general, the side surfaces extend in a length (L) direction and generally have a longer dimension than the end surfaces, and the end surfaces extend in a width (W) direction and generally have a shorter dimension. In one embodiment, the capacitor includes a total of at least six surfaces (e.g., one top, one bottom, two sides, and two ends). For example, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0017] Additionally, the capacitor can have a desired height. For example, the height can be 10 microns or more, e.g., 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 400 microns or more, 450 microns or more, 500 microns or more, 1,000 microns or more, 2,000 microns or more, etc. The height can be 5,000 microns or less, e.g., 4,000 microns or less, 2,500 microns or less, 2,000 microns or less, 1,000 microns or less, 750 microns or less, 600 microns or less, 500 microns or less, 450 microns or less, etc. When surrounded by a ball grid array, the height of the capacitor can be within 10%, e.g., within 7%, 5%, 3%, 2%, 1%, etc., of the height (or diameter) of the balls of the ball grid array. For example, such height can be the initial height prior to any reflow.

[0018] The capacitor can have a desired length. For example, the length can be 10 microns or more, such as 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 400 microns or more, 450 microns or more, 500 microns or more, 1,000 microns or more, 1,500 microns or more, 2,000 microns or more, 2,500 microns or more, 3,000 microns or more, 3,500 microns or more, 4,000 microns or more, etc. The length can be 10,000 microns or less, such as 8,000 microns or less, 6,000 microns or less, 5,000 microns or less, 4,000 microns or less, 3,000 microns or less, 2,500 microns or less, 2,000 microns or less, 1,000 microns or less, 750 microns or less, 600 microns or less, 500 microns or less, 450 microns or less, etc.

[0019] The capacitor can also have a desired width. For example, the width can be 10 microns or more, such as 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 400 microns or more, 450 microns or more, 500 microns or more, 750 microns or more, 1,000 microns or more, 1,500 microns or more, 2,000 microns or more, 2,500 microns or more, 3,000 microns or more, etc. The width can be 5,000 microns or less, such as 4,000 microns or less, 3,000 microns or less, 2,500 microns or less, 2,000 microns or less, 1,500 microns or less, 1,000 microns or less, 750 microns or less, 600 microns or less, 500 microns or less, 450 microns or less, etc.

[0020] Generally, a multilayer capacitor includes a set of alternating dielectric layers and internal electrode layers. The capacitor also includes external terminals electrically connected to the internal electrode layers and formed on a top surface of the capacitor and a bottom surface of the capacitor opposite the top surface of the capacitor. In one embodiment, the external terminals may also be formed on the opposing end surfaces. For example, in such an embodiment, the external terminals may wrap and extend from the top surface to adjacent end and bottom surfaces. Specifically, both ends of the capacitor may include external terminals having such a configuration, and such respective external terminals are not connected.

[0021] Generally, a capacitor includes at least one set of alternating dielectric layers and internal electrode layers. The capacitor may also include a second set of alternating dielectric layers and internal electrode layers. In this regard, the capacitor may include at least two sets of alternating dielectric layers and internal electrode layers, such as at least three sets, at least four sets, etc. However, it should be understood that the present invention may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited thereto. Furthermore, each set of alternating dielectric layers and internal electrode layers may be separated from an adjacent set by a certain distance. For example, the distance may be greater than the thickness of an individual dielectric layer in the set. Specifically, the distance may be at least twice, such as at least three times, at least five times, at least ten times, etc., the thickness of the dielectric layers in the set.

[0022] Furthermore, in one embodiment, before the first internal electrode layer in each set closest to the side surface, one or more dielectric layers may be provided such that such one or more dielectric layers are between such internal electrode layer and the adjacent side surface. Similarly, after the last internal electrode layer in each set closest to the side surface, one or more dielectric layers may be provided such that such one or more dielectric layers are between such internal electrode layer and the adjacent side surface. In this regard, such dielectric layers may include at least two, e.g., at least three, at least five, at least ten, etc., dielectric layers. Thus, such regions may have a thickness greater than the thickness of the individual dielectric layers in the respective set. Specifically, the distance may be at least twice, e.g., at least three, at least five, at least ten, etc., the thickness of the dielectric layers in the set.

[0023] The set of alternating dielectric layers and internal electrode layers, and any additional dielectric layers forming the dielectric regions, may form at least a portion of the body of the capacitor. By arranging the dielectric layers and internal electrode layers in a stacked or laminated configuration, the capacitor may be considered a multilayer capacitor, and may particularly be considered a multilayer ceramic capacitor, for example if the dielectric layers comprise ceramic.

[0024] The set of alternating dielectric layers and internal electrode layers comprises dielectric layers interleaved with the internal electrode layers, specifically, the internal electrode layers include first and second internal electrode layers interleaved in opposing relationship and separated by a dielectric layer disposed between each of the internal electrode layers.

[0025] In general, the thickness of the dielectric layers and the internal electrode layers is not limited and may be any thickness desired depending on the performance characteristics. For example, the thickness of the internal electrode layers may be, but is not limited to, about 500 nm or more, such as about 1 μm or more, about 2 μm or more, to about 10 μm or less, such as about 5 μm or less, about 4 μm or less, about 3 μm or less, about 2 μm or less, etc. For example, the internal electrode layers may have a thickness of about 1 μm to about 2 μm.

[0026] Furthermore, the present invention is not necessarily limited by the number of internal electrode layers per set of alternating dielectric layers and internal electrode layers, or the number of internal electrode layers in the entire capacitor. For example, each set may include 10 or more internal electrode layers, such as 25 or more, 50 or more, 100 or more, 200 or more, 300 or more, 500 or more, 600 or more, 750 or more, 1,000 or more, etc. Each set may have 5,000 or less internal electrode layers, such as 4,000 or less, 3,000 or less, 2,000 or less, 1,500 or less, 1,000 or less, 750 or less, 500 or less, 400 or less, 300 or less, 250 or less, 200 or less, 175 or less, 150 or less, etc. The entire capacitor may also include the above-mentioned number of electrode layers.

[0027] The internal electrode layer has a top edge and a bottom edge opposite the top edge. The internal electrode layer also has two side edges extending between the top and bottom edges. In one embodiment, the side edges, the top edge, and the bottom edge define a body of the internal electrode layer. In general, the body may have a rectangular structure or shape.

[0028] In general, the top and bottom edges may have the same dimension (e.g., length-L direction). The side edges may have the same dimension (e.g., height-T direction). In general, the side edges may have a dimension (e.g., height-T direction) that is shorter than the dimension (e.g., length-L direction) of the top and / or bottom edges. In this regard, the height of the side edges of the internal electrode layers when extending between the top and bottom surfaces of the capacitor may be less than the length of the top and / or bottom edges of the internal electrode layers when extending between the end surfaces of the capacitor. In other words, the internal electrode layers may have top and / or bottom edges of larger dimensions than the side edges of smaller dimensions. In this regard, the "short" sides of the layers may be aligned in the height direction of the capacitor.

[0029] The internal electrode layers have lead tabs extending from the body of the layer. The lead tabs extend from the top and bottom edges. In other words, the internal electrode layers may have lead tabs extending from the "long" sides or edges of the layer. The lead tabs may extend to the edge of the dielectric layer and / or surface of the capacitor. For example, when in a stacked configuration, the leading edge of the lead tab may extend to the edge of the dielectric layer. Such leading edge may be used to form an external terminal. Additionally, the edge may have at least one lead tab extending therefrom, e.g., at least two lead tabs, at least three lead tabs, at least four lead tabs, etc.

[0030] Each top and bottom edge of the internal electrode layer may have the same number of lead tabs extending therefrom. For example, each edge may have at least one lead tab extending therefrom. In another embodiment, each edge may have at least two lead tabs extending therefrom. However, it should be understood that the present invention may include, and is not necessarily limited to, any number of lead tabs extending from an internal electrode layer.

[0031] In one embodiment, at least one lead tab extends from the top and bottom edges of the body of the internal electrode layer, and the edges of the lead tab are aligned with the side edges of the body of the internal electrode layer. For example, at least one side edge (i.e., an edge aligned in the height direction) of the lead tab may be substantially aligned with a side edge of the body of the internal electrode layer. In this regard, the at least one lead tab may not be offset from the side edge of the internal electrode layer.

[0032] Furthermore, where there may be more than one lead tab along an edge, the lead tab may extend from an inner portion of the top and bottom edges of the body of the internal electrode layer. In this regard, the lead tab may not extend directly from a side edge of the internal electrode layer. In other words, the lead tab may be offset from the side edge of the internal electrode layer. The offset may be such that the lead tab is offset and positioned between the side edges of the internal electrode layer, specifically at a position at least 50% of the length of the internal electrode layer (e.g., beyond the center of the internal electrode layer).

[0033] The lead tabs extending from the top edge of each internal electrode layer and the bottom edge of the same internal electrode layer may be offset from the side edges by the same distance. In this regard, at least one side edge (i.e., an edge that is aligned in the height direction) of the lead tabs may be substantially aligned. In one embodiment, both side edges of each lead tab may be substantially aligned.

[0034] In another embodiment, all of the lead tabs may extend from the inner portions of the top and bottom edges of the body of the internal electrode layer. In this regard, none of the lead tabs may extend directly from the side edges of the internal electrode layer. In other words, the lead tabs may be offset from the side edges of the internal electrode layer. The offset may be such that the lead tabs are offset and positioned between the side edges of the internal electrode layer, specifically between the side edges of the internal electrode layer and the center of the internal electrode layer.

[0035] Furthermore, the lead tabs extending from the top edge of each internal electrode layer and the bottom edge of the same internal electrode layer may be offset the same distance from the side edges. In this regard, at least one side edge (i.e., an edge that is aligned in the height direction) of the lead tabs may be substantially aligned.

[0036] When each edge includes at least two lead tabs, the first lead tab on the top edge may be offset from the side edge the same distance as the first lead tab on the bottom edge. Additionally, the second lead tab on the top edge may be offset from the side edge the same distance as the second lead tab on the bottom edge. In this regard, the side edges of the respective lead tabs may be substantially aligned.

[0037] However, it should be understood that the offset from a side edge of a first lead tab on a top and / or bottom edge may be different from the offset from the opposing side edge of a second lead tab on the same edge.

[0038] The length of a lead tab extending from a top edge (ie, extending longitudinally from one end surface to another end surface) may be the same as the length of a corresponding lead tab extending from a bottom edge.

[0039] The length of the lead tab can be 0.3 mm or more, such as 0.4 mm or more, 0.5 mm or more, 0.6 mm or more, 0.7 mm or more, etc. The length of the lead tab can be 1.1 or less, such as 0.9 or less, 0.8 or less, 0.7 or less, 0.6 or less, 0.5 or less, etc. When there is more than one lead tab along an edge, each lead tab can have the same length.

[0040] In another embodiment, each lead tab may have a different length. For example, the lead tab substantially aligned with the side edge of the internal electrode layer may have a length greater than the lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer may be 0.3 or more, e.g., 0.5 or more, 0.7 or more, 0.9 or more, 1 or more, 1.1 or more, 1.2 or more, 1.3 or more, 1.4 or more, 1.5 or more, etc. The ratio may be 5 or less, e.g., 4 or less, 3 or less, 2 or less, 1.8 or less, 1.7 or less, 1.6 or less, 1.5 or less, 1.4 or less, etc.

[0041] By substantially aligned it is meant that the offset of one side edge of the first and / or second lead tab on the top edge from the side edge is within + / - 10%, e.g., within + / - 5%, within + / - 4%, within + / - 3%, within + / - 2%, within + / - 1%, within + / - 0.5%, etc., of the offset of the corresponding side edge of the first and / or second lead tab on the bottom edge from the side edge.

[0042] The distance between adjacent exposed lead tabs of the internal electrode layers in a given row may be specifically designed to ensure guided formation of the terminations. Such distance between exposed lead tabs of the internal electrode layers in a given row may be about 10 microns or less, e.g., about 8 microns or less, about 5 microns or less, about 4 microns or less, about 2 microns or less, about 1.5 microns or less, about 1 micron or less, etc. The distance may be about 0.25 microns or more, e.g., about 0.5 microns or more, about 1 micron or more, about 1.5 microns or more, about 2 microns or more, about 3 microns or more, etc. However, it should be understood that such distances are not necessarily limited.

[0043] Additionally, the distance between adjacent columnar stacks of electrode tabs may be, but is not limited to, at least twice as large as the distance between adjacent lead tabs in a given column to ensure that separate terminations do not extend together. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances may be highly dependent on the desired capacitance performance and circuit board configuration.

[0044] The distance may be 0.1 mm or more, e.g., 0.2 mm or more, 0.3 mm or more, 0.4 mm or more, 0.5 mm or more, 0.6 mm or more, etc. The distance may be 1.5 mm or less, e.g., 1.3 mm or less, 1 mm or less, 0.9 mm or less, 0.7 mm or less, 0.6 mm or less, 0.5 mm or less, 0.4 mm or less, etc. Such distances may be determined based on a center point of each lead tab in one embodiment. In another embodiment, such distances may be based on a distance between adjacent side edges of the lead tabs. Additionally, such distances may correspond to separation distances of balls on a ball grid array.

[0045] The lead tabs of the first and second internal electrode layers in a set of alternating dielectric and internal electrode layers are offset from one another in the longitudinal direction. That is, the lead tabs of each internal electrode layer may be symmetrically offset a certain distance from a centerline (e.g., with respect to a longitudinal centerline or a vertical line) of the internal electrode layer and / or dielectric layer. That is, the lead tabs of each internal electrode layer may be symmetrically offset with respect to a vertical line of the internal electrode layer and / or dielectric layer. Nevertheless, a gap region is formed between the lead tabs of each internal electrode layer.

[0046] Additionally, an internal electrode layer may be symmetrical in a given direction regardless of the number of lead tabs extending therefrom, for example, the lead tabs may be symmetrical about a horizontal line passing through the center of the body of the internal electrode layer (i.e., a line extending from the center of one side edge of the internal electrode layer to the center of the other side edge of the internal electrode layer).

[0047] Further, as shown herein, each internal electrode layer includes at least two side edges. When stacked to form the body of the capacitor, such side edges of alternating internal electrode layers may not be substantially aligned with one another. For example, the side edges may be offset from one another.

[0048] As shown herein, the capacitor includes a set of alternating dielectric layers and internal electrode layers. When the capacitor includes a second set of alternating dielectric layers and internal electrode layers, in one embodiment, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set may exceed the distance between adjacent internal electrode layers in a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set may exceed the distance between the first internal electrode layer of the first set and the second internal electrode layer.

[0049] As shown herein, the capacitor comprises a dielectric region that includes one or more voids. In this regard, the dielectric region may be a region that includes dielectric material but does not include internal electrode material. In this regard, the dielectric region may constitute a region that does not include alternating dielectric layers and internal electrode layers. Thus, the dielectric region may include dielectric material between each set of alternating dielectric layers and internal electrode layers in the "W" direction. Furthermore, the dielectric region may include dielectric material between the lateral edges of the electrodes in a given set of alternating dielectric layers and internal electrode layers and adjacent end surfaces in the longitudinal direction, for example to the extent that such internal electrode layers do not extend to the end surfaces and, as a result, they are offset from the end surfaces. It should be understood that such dielectric regions may be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, but such regions do not include any internal electrode material or corresponding layers. As a result, voids may be provided within such regions. Furthermore, the dielectric region may include dielectric material present between the first internal electrode layer of each set and adjacent side surfaces of the capacitor. The dielectric region may also include the dielectric material present between the last internal electrode layer of each set and adjacent side surfaces of the capacitor. The dielectric region may also include the dielectric material between the side edges of adjacent lead tabs that extend from the body of the internal electrode layers. In one particular embodiment, the dielectric region may include a region in the capacitor that is present between two external terminals. Additionally, it should be understood that the dielectric region may include any combination of the above-mentioned regions.

[0050] As mentioned above, the dielectric region includes a region that includes dielectric material but does not include internal electrode material. Thus, excluding voids, the dielectric region may include 90 vol.% or more of dielectric material, such as 93 vol.% or more, 95 vol.% or more, 97 vol.% or more, 98 vol.% or more, 99 vol.% or more, 100 vol.% etc.

[0051] In general, such voids may not include any material, and in particular may not include any dielectric material or internal electrode material. In one embodiment, the voids may be closed, for example partially or completely, by an enclosure material. In one embodiment, the voids may be partially closed by an enclosure material. By partially closed, the enclosure material is present only partially around the interior of the void such that the void is partially separated from the dielectric material. In this regard, at least a certain perimeter of the void may be in direct contact with the dielectric material of the dielectric region. In another embodiment, the voids may be completely or entirely closed by an enclosure material. By entirely closed, the enclosure material is present around the interior of the void such that the void is entirely separated from the dielectric material. Nevertheless, the enclosure material may be utilized to function as a barrier between the interior of the void and the dielectric material of the dielectric region. In one embodiment, the enclosure material may be a non-conductive material. However, it should be understood that in one embodiment, the voids may not even be partially closed by the enclosure material.

[0052] In this regard, in one embodiment, the void may be provided without any barrier between the void and the dielectric material of the dielectric region. The void may have any shape, and is not necessarily limited. For example, the shape may be a sphere, a cylinder, etc. In one embodiment, the shape may be a sphere. The void may have a maximum dimension (e.g., length, width, diameter, etc.). The maximum dimension may be 5 microns or more, e.g., 10 microns or more, 20 microns or more, 30 microns or more, 40 microns or more, 50 microns or more, 80 microns or more, 100 microns or more, 200 microns or more, 300 microns or more, 400 microns or more, 500 microns or more, 600 microns or more, 800 microns or more, 1,000 microns or more, etc. The maximum dimension can be 5,000 microns or less, e.g., 4,000 microns or less, 3,000 microns or less, 2,000 microns or less, 1,800 microns or less, 1,600 microns or less, 1,400 microns or less, 1,200 microns or less, 1,000 microns or less, 800 microns or less, 600 microns or less, 500 microns or less, 400 microns or less, 300 microns or less, 250 microns or less, 200 microns or less, 180 microns or less, 160 microns or less, 140 microns or less, 120 microns or less, 100 microns or less, 80 microns or less, 60 microns or less, 50 microns or less, 40 microns or less, etc.

[0053] These voids may be provided using any means that can provide such voids in the capacitor. For example, these voids may be formed by printing specific patterns on ceramic green sheets, followed by lamination and firing the stacked laminates. Alternatively, these voids may be formed using various drilling techniques to provide any desired shape in the dielectric material of the dielectric region.

[0054] As another example, the air gap may be provided using one or more vias (e.g., through-hole vias). The vias may not be filled with any material, such as any conductive or non-conductive material, such that air is present inside. Additionally, in one embodiment, the vias may be provided such that they are only within the dielectric region. In this regard, the vias may be provided such that they do not contact any of the internal electrode layers.

[0055] In one embodiment, the vias may extend from the top surface of the capacitor to the bottom surface of the capacitor. In this regard, the vias may be cylindrical extending through the thickness of the capacitor. Thus, the vias may be through-hole conductive vias. In another embodiment, the vias may extend only partially through the thickness of the capacitor. For example, the vias may extend 10% or more of the thickness of the capacitor, such as 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, etc. The vias may extend 100% or less of the thickness of the capacitor, such as 90% or less, 80% or less, 70% or less, 60% or less, 50% or less, 40% or less, 30% or less, 20% or less, 10% or less, etc. In one embodiment, such an extension through the above-mentioned thickness may refer to the average extension of the vias through the thickness of the capacitor.

[0056] In embodiments including two or more vias, all of the vias may have the same length. For example, two or more of the vias may have the same length. However, it should be understood that two or more of the vias may have different lengths.

[0057] The cross-sectional area of ​​the via hole is 0.00005 mm 2 More than, for example, 0.0001 mm 2 More than 0.0005mm 2 Above 0.001mm 2 More than 0.005mm 2 Above 0.01mm 2 The cross-sectional area of ​​the via hole can be 1 mm 2 For example, 0.5 mm or less 2 Below, 0.1mm2 Below, 0.09mm 2 Below, 0.07mm 2 Below, 0.05mm 2 Below, 0.01mm 2 Below, 0.005mm 2 Below, 0.001mm 2 It could be the following etc.

[0058] The distance between the vias is not necessarily limited by the present invention. As described herein, the external terminals may have a certain pitch. In this regard, the vias may also have the same or similar pitch. Furthermore, the average pitch between a first via and an adjacent second via may be less than the average pitch between the first via and another adjacent third via.

[0059] Furthermore, the average length of the first and second vias may be a certain length compared to the average pitch between the first via and the adjacent second via. In one embodiment, the average length may be equal to or greater than the average pitch between the first via and the adjacent second via. In a further embodiment, the average length may be equal to or less than the average pitch between the first via and the adjacent second via. For example, the average length may be 10 times or less, such as 8 times or less, 6 times or less, 5 times or less, 4 times or less, 3 times or less, 2 times or less, 1 time or less, etc., of the average pitch between the first via and the adjacent second via. The average length may be 0.001 times or more, such as 0.01 times or more, 0.1 times or more, 0.2 times or more, 0.3 times or more, 0.5 times or more, 0.7 times or more, 0.9 times or more, 1 time or more, etc.

[0060] In one embodiment, the vias may be provided between adjacent external terminals in the "L" direction of the capacitor. In one embodiment, the vias may be provided between adjacent external terminals in the "W" direction of the capacitor. In yet a further embodiment, the vias are provided between adjacent external terminals in both the "L" and "W" directions of the capacitor.

[0061] The method may also include forming vias. In one embodiment, the vias may be formed by forming holes or notches in the ceramic green sheets before the ceramic green sheets are laminated together. Alternatively, the vias may be formed by forming holes in the stacked body after lamination. For example, this may be done after laminating the layers and the ceramic green sheets. Furthermore, in one embodiment, this may be done before firing the stacked body. In another embodiment, this may be done after firing the stacked body. Nevertheless, the vias may be capped, such as to cover any holes on the top and / or bottom surfaces of the capacitor. For example, the vias may be capped using a non-conductive material, such as a ceramic or a polymer. In particular, the ceramic may be a ceramic utilized to form a dielectric layer of the capacitor.

[0062] In another embodiment, the dielectric region may include hollow filler materials. For example, these hollow filler materials may allow for the presence of air within the interior of the material. These hollow filler materials may be entirely closed or at least partially open. By entirely closed, there is a barrier around the interior of the hollow filler material such that the hollow filler material is entirely separated from the dielectric material. On the other hand, in the case of an open hollow filler material, at least some of the perimeter is open and exposed such that there is no barrier between the interior of the hollow filler material and the dielectric material.

[0063] The hollow filler material may be any filler material that can contain a hollow interior. For example, they may include, but are not limited to, spheres, fibers, tubes, rods, and the like. In one embodiment, the filler material may include spheres, such as microspheres or nanospheres. For example, in one embodiment, the filler material may include microspheres. In another embodiment, the filler material may include nanospheres. In another embodiment, the filler material may include tubes.

[0064] In one embodiment, the hollow filler material may be non-conductive. For example, the hollow filler material may not be made of metal. Furthermore, in one embodiment, the hollow filler material may not be made of a material that includes metal additives. In this regard, in one embodiment, the hollow filler material may be made of a polymer or a ceramic. For example, the ceramic may include glass, silicate, and the like. In one embodiment, the ceramic may include glass. In another embodiment, the ceramic may include silicate, such as aluminosilicate. Meanwhile, the polymer may be a thermoplastic polymer or a thermosetting polymer. In one embodiment, the polymer may be a thermoplastic polymer. In another embodiment, the polymer may be a thermosetting polymer.

[0065] The hollow filler material may have a certain density. For example, the density may be 0.2 g / cc or more, such as 0.25 g / cc or more, 0.3 g / cc or more, 0.35 g / cc or more, 0.4 g / cc or more, 0.5 g / cc or more, 0.6 g / cc or more, 0.7 g / cc or more, etc. The density may be 1.5 g / cc or less, such as 1.3 g / cc or less, 1.1 g / cc or less, 1 g / cc or less, 0.9 g / cc or less, 0.8 g / cc or less, 0.7 g / cc or less, 0.6 g / cc or less, 0.5 g / cc or less, 0.4 g / cc or less, etc. In one embodiment, the density mentioned above may refer to bulk density.

[0066] The hollow filler material can have a maximum dimension (e.g., length, width, diameter, etc.) that can be 5 microns or more, e.g., 10 microns or more, 20 microns or more, 30 microns or more, 40 microns or more, 50 microns or more, 80 microns or more, 100 microns or more, 200 microns or more, 300 microns or more, 400 microns or more, 500 microns or more, 600 microns or more, 800 microns or more, 1,000 microns or more, etc. The maximum dimension can be 5,000 microns or less, e.g., 4,000 microns or less, 3,000 microns or less, 2,000 microns or less, 1,800 microns or less, 1,600 microns or less, 1,400 microns or less, 1,200 microns or less, 1,000 microns or less, 800 microns or less, 600 microns or less, 500 microns or less, 400 microns or less, 300 microns or less, 250 microns or less, 200 microns or less, 180 microns or less, 160 microns or less, 140 microns or less, 120 microns or less, 100 microns or less, 80 microns or less, 60 microns or less, 50 microns or less, 40 microns or less, etc.

[0067] The hollow filler material may be present in the dielectric region at a particular weight percentage, for example, the hollow filler material may be present in an amount of 0.1 wt.% or more, such as 0.5 wt.% or more, 1 wt.% or more, 2 wt.% or more, 3 wt.% or more, 5 wt.% or more, 8 wt.% or more, 10 wt.% or more, 15 wt.% or more, 20 wt.% or more, 25 wt.% or more, 30 wt.% or more, etc., of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 wt.% or less, e.g., 40 wt.% or less, 35 wt.% or less, 30 wt.% or less, 25 wt.% or less, 20 wt.% or less, 18 wt.% or less, 16 wt.% or less, 14 wt.% or less, 12 wt.% or less, 10 wt.% or less, 9 wt.% or less, 8 wt.% or less, 7 wt.% or less, 6 wt.% or less, 5 wt.% or less, etc.

[0068] The hollow filler material may be present in the dielectric region at a particular volume percentage. For example, the hollow filler material may be present in an amount of 0.1 vol.% or more, such as 0.5 vol.% or more, 1 vol.% or more, 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 8 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more, 25 vol.% or more, 30 vol.% or more, etc., of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 vol.% or less, such as 40 vol.% or less, 35 vol.% or less, 30 vol.% or less, 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 16 vol.% or less, 14 vol.% or less, 12 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc.

[0069] The above provides various options for providing voids in the dielectric region, but it should be understood that these options can be used individually or in combination. For example, voids formed in the body (e.g., without a barrier / enclosure material) can be combined with voids formed as vias. Similarly, the voids can include voids formed by vias and hollow filler materials. Alternatively, the voids can include a combination of voids formed in the body without a barrier / enclosure material and hollow filler materials. In this regard, it should be understood that the present invention is not necessarily limited in this respect.

[0070] The voids may constitute a certain volume of the capacitor. For example, the voids may constitute 1 vol.% or more, such as 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more of the capacitor, specifically the stacked laminate of the dielectric layers and the internal electrode layers. The voids may constitute 30 vol.% or less, such as 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 15 vol.% or less, 13 vol.% or less, 11 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc., of the capacitor, specifically the stacked laminate of the dielectric layers and the internal electrode layers.

[0071] The voids may constitute a certain volume of the dielectric region of the capacitor. For example, the voids may constitute 1 vol.% or more of the dielectric region of the capacitor, such as 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more, 25 vol.% or more, 30 vol.% or more, etc. The voids may constitute 40 vol.% or less of the dielectric region of the capacitor, such as 30 vol.% or less, 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 15 vol.% or less, 13 vol.% or less, 11 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc.

[0072] Although not intended to be limiting, by providing the above-mentioned voids, the dielectric region can have a relatively low relative dielectric constant. For example, the relative dielectric constant can be 3 or more, for example, 3.5 or more, 4 or more, 4.5 or more, 5 or more, 7 or more, 10 or more, 15 or more, 20 or more, 25 or more, 30 or more, 40 or more, 50 or more, 60 or more, 70 or more, 80 or more, 90 or more, 100 or more, 200 or more, 300 or more, 400 or more, 500 or more, 1,000 or more, etc. The relative dielectric constant can be 10,000 or less, for example, 5,000 or less, 2,000 or less, 1,000 or less, 800 or less, 600 or less, 400 or less, 200 or less, 150 or less, 100 or less, 90 or less, 80 or less, 70 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, 15 or less, 10 or less, etc. In one embodiment, such aforementioned relative dielectric constant is measured at 1 MHz.

[0073] The capacitor of the present invention also includes external terminals on the top and bottom surfaces. In one embodiment, the capacitor may also include external terminals on the opposing end surfaces. For example, the external terminals may extend from the top surface to the end surface closest to the bottom surface. If present on an end surface, the external terminals may only be partially present on the end surface such that the external terminals do not cover the entire end surface. In another embodiment, the capacitor may not include any external terminals on the opposing end surfaces. In one particular embodiment, the external terminals may not be present on the side surfaces of the capacitor.

[0074] The external terminals include at least one terminal of a first polarity and at least one terminal of a second opposite polarity. The capacitor may include at least one, e.g., at least two, at least four, at least six, at least eight, etc., terminal of the first polarity and / or the second opposite polarity on a top surface of the capacitor. Additionally, the capacitor may include the above-mentioned amount of terminals on a bottom surface of the capacitor.

[0075] The capacitor may include an equal number of terminals of a first polarity and / or terminals of a second polarity on the top surface of the capacitor and on the bottom surface of the capacitor. The number of terminals of a first polarity may be equal to the number of terminals of a second opposite polarity on the top surface of the capacitor. The number of terminals of a first polarity may be equal to the number of terminals of a second opposite polarity on the bottom surface of the capacitor. The total number of terminals present on the top surface of the capacitor may be equal to the total number of terminals present on the bottom surface of the capacitor. The total number of terminals of a first polarity present on the top and bottom surfaces of the capacitor may be equal to the total number of terminals of a second opposite polarity present on the top and bottom surfaces of the capacitor.

[0076] In general, the same polarity terminal on the bottom surface of the capacitor corresponding to a particular set of alternating dielectric layers and internal electrode layers is electrically connected to the same polarity terminal on the top surface of the capacitor. The same polarity terminals located on the top and bottom surfaces of the capacitor do not have to be interdigitated. In this regard, the corresponding same polarity terminals on the top and bottom surfaces do not have to be offset by terminal location, but instead may be positioned directly above or below another same polarity terminal on the opposite top or bottom surface. In other words, the corresponding same polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers, specifically the corresponding lead tabs of such a set, may be substantially aligned. By substantially aligned it is meant that the offset of one side edge of the polarity terminal on the top surface from the side edge is within + / - 10%, e.g., within + / - 5%, within + / - 4%, within + / - 3%, within + / - 2%, within + / - 1%, within + / - 0.5%, etc., of the offset from the side edge of the corresponding polarity terminal on the bottom surface.

[0077] In general, the pitch (i.e., the nominal distance between centers, also called center-to-center spacing) of the external terminals may be determined by the particular circuit board configuration. The pitch between external terminals in one direction (i.e., the x-direction or the y-direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any other two adjacent external terminals.

[0078] The pitch can be about 0.1 mm or more, such as about 0.2 mm or more, about 0.3 mm or more, about 0.4 mm or more, about 0.5 mm or more, about 0.6 mm or more, about 0.7 mm or more, about 0.8 mm or more, about 0.9 mm or more, about 1.0 mm or more, etc. The pitch can be about 2.0 mm or less, such as about 1.5 mm or less, about 1.4 mm or less, about 1.3 mm or less, about 1.2 mm or less, about 1.1 mm or less, about 1.0 mm or less, etc. For example, the pitch can be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. Specifically, the pitch can be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch can be about 0.6 mm, such as + / - 10%, + / - 5%, + / - 2%, + / - 1% of 0.6 mm, etc. In another embodiment, the pitch may be about 0.8 mm, e.g., + / - 10%, + / - 5%, + / - 2%, + / - 1% of 0.8 mm, etc. In a further embodiment, the pitch may be about 1 mm, e.g., + / - 10%, + / - 5%, + / - 2%, + / - 1% of 1 mm, etc.

[0079] As described above, the extension of the leading edge of the lead tab can assist in the formation of the external terminal. In this regard, the pitch between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be the same as that described above. That is, the pitch between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be substantially the same as the pitch between the corresponding external terminals that the lead tabs are utilized to form.

[0080] Additionally, the external terminals may be positioned similarly to the configuration of a ball grid array. For example, the external terminals may be provided to make contacts typically used by a ball grid array, particularly a peripheral ball grid array. In this regard, the pitch of the external terminals may be the same as the pitch of the peripheral ball grid array. That is, the pitch may be within 10%, e.g., within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc., of the pitch of the peripheral ball grid array.

[0081] Furthermore, like a ball grid array, the external terminals may be provided in rows and columns. That is, the external terminals may be provided such that they are in at least two rows and at least two columns. For example, the external terminals may be provided in at least two rows, e.g., at least three rows, at least four rows, etc. The number of rows may be determined by the number of different sets of alternating dielectric layers and internal electrode layers. Furthermore, the external terminals may be provided in at least two columns, e.g., at least three columns, at least four columns, etc. The number of columns may be determined by the number of different columnar tabs of the internal electrodes.

[0082] Furthermore, the length of an external terminal extending along the top surface (i.e., extending longitudinally from one end surface to another end surface) may be the same as the length of a corresponding external terminal extending along the bottom surface.

[0083] The length of the external terminals can be 0.3 mm or more, such as 0.4 mm or more, 0.5 mm or more, 0.6 mm or more, 0.7 mm or more, etc. The length of the external terminals can be 1.1 or less, such as 0.9 or less, 0.8 or less, 0.7 or less, 0.6 or less, 0.5 or less, etc. When there are more than one external terminal along the surface, each external terminal can have the same length. Additionally, the length of the external terminals can be less than the length of the capacitor, such as 50% or less, 40% or less, 30% or less, 25% or less, 20% or less, 15% or less, etc. of the length of the capacitor.

[0084] In another embodiment, each external terminal may have a different length. For example, an external terminal adjacent to an end surface may have a length greater than an external terminal offset from that end surface. In this regard, the ratio of the length of the external terminal adjacent to an end surface to the length of the external terminal offset from that end surface may be 0.3 or more, such as 0.5 or more, 0.7 or more, 0.9 or more, 1 or more, 1.1 or more, 1.2 or more, 1.3 or more, 1.4 or more, 1.5 or more, etc. The ratio may be 5 or less, such as 4 or less, 3 or less, 2 or less, 1.8 or less, 1.7 or less, 1.6 or less, 1.5 or less, 1.4 or less, etc.

[0085] Additionally, the width of the external terminal extending from one side surface to the opposite side surface may be the same on the top and bottom surfaces. For example, the width may be 0.3 mm or more, such as 0.4 mm or more, 0.5 mm or more, 0.6 mm or more, 0.7 mm or more, etc. The width of the external terminal may be 1.1 or less, such as 0.9 or less, 0.8 or less, 0.7 or less, 0.6 or less, 0.5 or less, etc. When there is more than one external terminal along a surface, each external terminal may have the same width. Additionally, the width of the external terminal may be less than the width of the capacitor.

[0086] Capacitors of the present invention may be further described in light of the embodiments illustrated in FIGS. 1A-1B, 2A-2B, 3A-3D, 4A-4D, and 5A-5B.

[0087] 1A illustrates a capacitor 10 in a 1 by 2 configuration, i.e., the capacitor includes two terminals along one dimension of the top and bottom surfaces. Additionally, the capacitor includes terminals along the end surfaces such that the terminals wrap from the top surface to the bottom surface along adjacent end surfaces. In this regard, the capacitor 10 includes a total of two external terminals 12, 14 on the top surface and two corresponding external terminals (not shown) on the bottom surface, where the external terminals on the top surface are electrically connected to the corresponding external terminals on the bottom surface.

[0088] Capacitor 10 of Figure 1A includes external terminals 12, 14 and, as shown in Figure 1B, a set of alternating dielectric and internal electrode layers 110. As shown in Figure 1B, set of alternating dielectric and internal electrode layers 110 includes internal electrode layers 105, 115 and a dielectric layer (not shown) in an alternating arrangement.

[0089] Generally, the internal electrode layer 105, 115 includes at least one lead tab 120, 130, 140, 150 that extends from the top and bottom edges of the body of the internal electrode layer. Generally, the lead tab 120, 130, 140, 150 of the internal electrode layer 105, 115 extends to the top and bottom surfaces of the capacitor to assist in forming an external terminal. In this regard, the lead tab 120, 130, 140, 150 may be exposed on the top and bottom surfaces of the capacitor to enable a connection between the body of the internal electrode layer and an external terminal. For example, the lead tab 120, 130, 140, 150 may include a leading edge 123, 133, 143, 153 that extends to the edge of the dielectric layer and enables the formation of an external terminal.

[0090] 1B, the first internal electrode layer 105 includes one lead tab 120, 130 extending from the body 135 along the top edge 105c and the bottom edge 105d. The second internal electrode layer 115 includes one lead tab 140, 150 extending from the body 145 along the top edge and the bottom edge.

[0091] The lead tabs 120, 130 on the top and bottom edges of the first internal electrode layer 105 may be aligned in the vertical direction, i.e., the side edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the side edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. Furthermore, such side edges 121, 131 may be aligned with the side edge 105a of the internal electrode layer 105.

[0092] However, it should be understood that both side edges 121, 122 of first lead tab 120 along top edge 105c can be aligned with side edges 131, 132 of first lead tab 130 along bottom edge 105d opposite top edge 105c. In other words, both side edges 122, 132 can be aligned along bottom edge 105d and top edge 105c and offset from side edges 105a-b by the same distance.

[0093] Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 may be aligned in the vertical direction. That is, the side edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the side edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. In one embodiment, both side edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the side edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. The relationship between the side edges of the first lead tab on the top edge and the side edges of the first lead tab on the bottom edge as described with respect to the internal electrode layer 105 may also be applied to the internal electrode layer 115.

[0094] With such an arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each respective gap may be substantially the same.

[0095] Lead tabs 120 and 140 may extend from the internal electrode layers 105 and 115 arranged parallel to lead tabs 130 and 150, respectively, such that the lead tabs extending from alternating electrode layers 105 and 115 may be aligned in respective rows. For example, lead tabs 120 and 130 of internal electrode layer 105 may be arranged in a respective stacked configuration, while lead tabs 140 and 150 of internal electrode layer 115 may be arranged in a respective stacked configuration.

[0096] It will be appreciated that lead tab 120 connects to external terminal 12, while lead tab 140 connects to external terminal 14. Thus, each lead tab 120 is interdigitated with a respective lead tab 140 in a manner similar to external terminals 12 and 14. The interdigitated lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0097] 1A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface. Although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity. Although also not shown, a first polarity terminal 12 extends from the end surface to the bottom surface.

[0098] 1A-1B, the capacitor includes two external terminals on each surface, and each internal electrode layer includes at least one lead tab extending from a top edge and a bottom edge, but as noted above, the invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top and / or bottom edges.

[0099] For example, FIG. 2A shows a capacitor 20 that includes four external terminals on each surface and two lead tabs extending from the top and bottom surfaces of each internal electrode layer.

[0100] As shown in FIG. 2A, the capacitor 20 has a 1 by 4 configuration; that is, the capacitor includes four terminals along one dimension of the top and bottom surfaces. In this regard, the capacitor includes a total of four external terminals 22a-b, 24a-b on the top surface and four corresponding external terminals (not shown) on the bottom surface, the external terminals on the top surface being electrically connected to the corresponding external terminals 22a-b, 24a-b on the bottom surface. Additionally, the external terminals 22a, 24a extend from the top surface to the bottom surface along adjacent edge surfaces.

[0101] Capacitor 20 of Figure 2A includes external terminals 22a-b, 24a-b, and, as shown in Figure 2B, a set 210 of alternating dielectric and internal electrode layers. As shown in Figure 2B, set 210 of alternating dielectric and internal electrode layers includes internal electrode layers 205, 215, and a dielectric layer (not shown) in an alternating arrangement.

[0102] Generally, the internal electrode layer 205, 215 includes at least one lead tab 220a-b, 230a-b, 240a-b, 250a-b extending from the top and bottom edges of the body of the internal electrode layer. Generally, the lead tab 220a-b, 230a-b, 240a-b, 250a-b of the internal electrode layer 205, 215 extends to the top and bottom surfaces of the capacitor to help form the external terminals. In this regard, the lead tab 220a-b, 230a-b, 240a-b, 250a-b may be exposed on the top and bottom surfaces of the capacitor to enable connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a-b, 230a-b, 240a-b, 250a-b may include leading edges 223a-b, 233a-b, 243a-b, 253a-b that extend to the edge of the dielectric layer and allow for the formation of external terminals.

[0103] As shown in Figure 2B, the internal electrode layers 205, 215 include at least two lead tabs 220a-b, 230a-b, 250a-b along the top and bottom edges. As shown in Figure 2B, the first internal electrode layer 205 includes two lead tabs 220a-b, 230a-b extending from the body 235 along each top edge 205c and bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240a-b, 250a-b extending from the body 245 along each top edge and bottom edge.

[0104] The lead tabs 220a-b, 230a-b on the top edge 205c and bottom edge 205d of the first internal electrode layer 205 may be aligned in the vertical direction. That is, the side edges 221a, 222a of the first lead tab 220a along the top edge 205c may be aligned with the side edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite the top edge 205c. Furthermore, such side edges 221a, 231a may be aligned with the side edge 205a of the internal electrode layer 205.

[0105] However, it should be understood that both side edges 221 a, 222 a of the first lead tab 220 a along the top edge 205 c can be aligned with the side edges 231 a, 232 a of the first lead tab 230 a along the bottom edge 205 d opposite the top edge 205 c. In other words, both side edges 222 a, 232 a can be offset the same distance from the side edges 205 a-b along the bottom edge 205 d and the top edge 205 c.

[0106] When the top and bottom edges 205c, 205d include at least two lead tabs 220a-b, 230a-b, at least one side edge of each lead tab on the top edge 205c can be aligned with a corresponding side edge of a lead tab on the bottom edge 205d, and both side edges of each lead tab on the top edge 205c can be aligned with corresponding side edges of a lead tab on the bottom edge 205d.

[0107] Similarly, the lead tabs 240a-b, 250a-b on the top and bottom edges of the second internal electrode layer 215 may be aligned in the vertical direction. That is, the side edges 241a, 242a of the first lead tab 240a along the top edge may be aligned with the side edges 251a, 252a of the first lead tab 250a along the bottom edge opposite the top edge. Both side edges 241a, 242a of the first lead tab 240a along the top edge may be aligned with the side edges 251a, 252a of the first lead tab 250a along the bottom edge opposite the top edge. The relationship between the side edges of the first lead tab on the top edge and the side edges of the first lead tab on the bottom edge as described with respect to the internal electrode layer 205 may also be applied to the internal electrode layer 215.

[0108] According to such an arrangement, gaps may be formed between any of the lead tabs along the top edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 220a-b, 240a-b extending from the top edge of the respective internal electrode layer. Additionally, gaps may be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 230a-b, 250a-b extending from the top edge of the respective internal electrode layer. Additionally, the size of the gap between two respective tabs extending from a top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, may be substantially the same as the size of the gap between two respective corresponding tabs extending from a bottom edge. For example, the gap between lead tabs 220a and 220b may be substantially the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a may be substantially the same as the gap between lead tabs 230 and 250a.

[0109] Any or all of the lead tabs 220a-b, 240a-b may extend from layers 205 and 215 arranged parallel to the lead tabs 230a-b, 250a-b such that the lead tabs extending from alternating electrode layers 205 and 215 may be aligned in respective rows. For example, the lead tabs 220a-b and 230a-b of the inner electrode layer 205 may be arranged in a respective stacked configuration, while the lead tabs 240a-b and 250a-b of the inner electrode layer 215 may be arranged in a respective stacked configuration.

[0110] It will be appreciated that lead tabs 220a-b connect to external terminals 22a-b, respectively, while lead tabs 240a-b connect to external terminals 24a-b, respectively. Thus, each lead tab 220a-b is interdigitated with a respective lead tab 240a-b, respectively, in a manner similar to external terminals 22a-b and 24a-b. The interdigitated lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0111] Additionally, the capacitor 20 of Figure 2A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface. Although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity. Specifically, Figure 2A includes two positive terminals 22a-b and two negative terminals 24a-b on the top surface.

[0112] 2A-2B, the capacitor includes four external terminals on each surface, and the capacitor includes two sets of alternating dielectric and internal electrode layers, but as noted above, the invention is not limited by the number of external terminals and / or the number of sets of alternating dielectric and internal electrode layers.

[0113] Additionally, although the illustrated embodiment uses only two internal electrode layers per set of alternating dielectric and internal electrode layers, it should be understood that the present invention may include any number of internal electrode layers per set as shown herein and is not necessarily limited thereto.

[0114] 3A illustrates the capacitor 10 in a two-by-two configuration, i.e., the capacitor includes two terminals along each dimension of the top and bottom surfaces. In this regard, the capacitor 10 includes a total of four external terminals 12, 14 on the top surface and four corresponding external terminals (not shown) on the bottom surface, where the external terminals on the top surface are electrically connected to the corresponding external terminals on the bottom surface.

[0115] The capacitor 10 of Figure 3A includes external terminals 12, 14 and two sets 110 of alternating dielectric and internal electrode layers, as shown in Figure 3D. As shown in Figures 3B and 3C, each set 110 of alternating dielectric and internal electrode layers includes internal electrode layers 105, 115 and a dielectric layer (not shown) in an alternating arrangement.

[0116] Generally, the internal electrode layer 105, 115 includes at least one lead tab 120, 130, 140, 150 that extends from the top and bottom edges of the body of the internal electrode layer. Generally, the lead tab 120, 130, 140, 150 of the internal electrode layer 105, 115 extends to the top and bottom surfaces of the capacitor to assist in forming an external terminal. In this regard, the lead tab 120, 130, 140, 150 may be exposed on the top and bottom surfaces of the capacitor to enable a connection between the body of the internal electrode layer and an external terminal. For example, the lead tab 120, 130, 140, 150 may include a leading edge 123, 133, 143, 153 that extends to the edge of the dielectric layer and enables the formation of an external terminal.

[0117] 3B and 3C, the first internal electrode layer 105 includes one lead tab 120, 130 extending from the body 135 along the top edge 105c and bottom edge 105d. The second internal electrode layer 115 includes one lead tab 140, 150 extending from the body 145 along the top edge and bottom edge.

[0118] The lead tabs 120, 130 on the top and bottom edges of the first internal electrode layer 105 may be aligned in the vertical direction. That is, the side edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the side edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. In other words, the side edges 121, 122 of the first lead tab 120 along the top edge 105c may be offset from the side edges 105a-b by the same distance (indicated by "O") as the side edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c.

[0119] However, it should be understood that both side edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with both side edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. In other words, both side edges 121, 122 of the first lead tab 120 along the top edge 105c may be offset from the side edges 105a-b the same distance as both side edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c.

[0120] Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 may be aligned in the vertical direction. That is, the side edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the side edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. In one embodiment, both side edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the side edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. The relationship between the side edges of the first lead tab on the top edge and the side edges of the first lead tab on the bottom edge as described with respect to the internal electrode layer 105 may also be applied to the internal electrode layer 115.

[0121] With such an arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each respective gap may be substantially the same.

[0122] Lead tabs 120 and 140 may extend from the internal electrode layers 105 and 115 arranged parallel to lead tabs 130 and 150, respectively, such that the lead tabs extending from alternating electrode layers 105 and 115 may be aligned in respective rows. For example, lead tabs 120 and 130 of internal electrode layer 105 may be arranged in a respective stacked configuration, while lead tabs 140 and 150 of internal electrode layer 115 may be arranged in a respective stacked configuration.

[0123] It will be appreciated that lead tab 120 connects to external terminal 12, while lead tab 140 connects to external terminal 14. Thus, each lead tab 120 is interdigitated with a respective lead tab 140 in a manner similar to external terminals 12 and 14. The interdigitated lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0124] Additionally, the capacitor 10 of Figure 3A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface. Although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity. Specifically, Figure 3A includes two positive terminals 12 and two negative terminals 14 on the top surface.

[0125] 3A-3D, the capacitor includes four external terminals on each surface, and each internal electrode layer includes at least one lead tab extending from a top edge and a bottom edge, but as noted above, the invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top and / or bottom edges.

[0126] For example, FIG. 4A shows a capacitor 20 that includes eight external terminals on each surface and two lead tabs extending from the top and bottom surfaces of each internal electrode layer.

[0127] 4A, the capacitor 20 has a two-by-four configuration, i.e., the capacitor includes two terminals along one dimension of the top and bottom surfaces and four terminals along the other dimension of the top and bottom surfaces. In this regard, the capacitor includes a total of eight external terminals 22a-b, 24a-b on the top surface and eight corresponding external terminals (not shown) on the bottom surface, which are electrically connected to the corresponding external terminals 22a-b, 24a-b on the bottom surface.

[0128] The capacitor 20 of Figure 4A includes external terminals 22a-b, 24a-b, and two sets 210 of alternating dielectric and internal electrode layers, as shown in Figure 4D. As shown in Figures 4B and 4C, each set 210 of alternating dielectric and internal electrode layers includes internal electrode layers 205, 215, and a dielectric layer (not shown) in an alternating arrangement.

[0129] Generally, the internal electrode layer 205, 215 includes at least one lead tab 220a-b, 230a-b, 240a-b, 250a-b extending from the top and bottom edges of the body of the internal electrode layer. Generally, the lead tab 220a-b, 230a-b, 240a-b, 250a-b of the internal electrode layer 205, 215 extends to the top and bottom surfaces of the capacitor to help form the external terminals. In this regard, the lead tab 220a-b, 230a-b, 240a-b, 250a-b may be exposed on the top and bottom surfaces of the capacitor to enable connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a-b, 230a-b, 240a-b, 250a-b may include leading edges 223a-b, 233a-b, 243a-b, 253a-b that extend to the edge of the dielectric layer and allow for the formation of external terminals.

[0130] As shown in Figures 4B and 4C, the internal electrode layers 205, 215 include at least two lead tabs 220a-b, 230a-b, 240a-b, 250a-b along the top and bottom edges. As shown in Figures 4B and 4C, the first internal electrode layer 205 includes two lead tabs 220a-b, 230a-b extending from the body 235 along each top edge 205c and bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240a-b, 250a-b extending from the body 245 along each top edge and bottom edge.

[0131] The lead tabs 220a-b, 230a-b on the top edge 205c and bottom edge 205d of the first internal electrode layer 205 may be aligned in the vertical direction. That is, the side edges 221a, 222a of the first lead tab 220 along the top edge 205c may be aligned with the side edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite the top edge 205c. In other words, the side edges 221a, 222a of the first lead tab 220 along the top edge 205c may be offset from the side edges 205a-b by the same distance (indicated by "O") as the side edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite the top edge 205c. Also, both side edges 221a, 222a of the first lead tab 220 along the top edge 205c may be aligned with the side edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite the top edge 205c, i.e., both side edges may be offset from the side edges 205a-b by the same distance.

[0132] When the top and bottom edges 205c, 205d include at least two lead tabs 220a-b, 230a-b, at least one side edge of each lead tab on the top edge 205c can be aligned with a corresponding side edge of a lead tab on the bottom edge 205d, and both side edges of each lead tab on the top edge 205c can be aligned with corresponding side edges of a lead tab on the bottom edge 205d.

[0133] Similarly, the lead tabs 240a-b, 250a-b on the top and bottom edges of the second internal electrode layer 215 may be aligned in the vertical direction. That is, the side edges 241a, 242a of the first lead tab 240 along the top edge may be aligned with the side edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. Both side edges 241a, 242a of the first lead tab 240 along the top edge may be aligned with the side edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The relationship between the side edges of the first lead tab on the top edge and the side edges of the first lead tab on the bottom edge as described with respect to the internal electrode layer 205 may also be applied to the internal electrode layer 215.

[0134] According to such an arrangement, gaps may be formed between any of the lead tabs along the top edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 220a-b, 240a-b extending from the top edge of the respective internal electrode layer. Additionally, gaps may be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 230a-b, 250a-b extending from the top edge of the respective internal electrode layer. Additionally, the size of the gap between two respective tabs extending from a top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, may be substantially the same as the size of the gap between two respective corresponding tabs extending from a bottom edge. For example, the gap between lead tabs 220a and 220b may be substantially the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a may be substantially the same as the gap between lead tabs 230a and 250a.

[0135] Any or all of the lead tabs 220a-b, 240a-b may extend from layers 205 and 215 arranged parallel to the lead tabs 230a-b, 250a-b, respectively, such that the lead tabs extending from alternating electrode layers 205 and 215 may be aligned in respective rows. For example, the lead tabs 220a-b and 230a-b of the inner electrode layer 205 may be arranged in a respective stacked configuration, while the lead tabs 240a-b and 250a-b of the inner electrode layer 215 may be arranged in a respective stacked configuration.

[0136] It will be appreciated that lead tabs 220a-b connect to external terminals 22a-b, respectively, while lead tabs 240a-b connect to external terminals 24a-b, respectively. Thus, each lead tab 220a-b is interdigitated with a respective lead tab 240a-b, respectively, in a manner similar to external terminals 22a-b and 24a-b. The interdigitated lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0137] Thus, the capacitor 20 of Figure 4A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface. Although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity. Specifically, Figure 4A includes four positive terminals 22a-b and four negative terminals 24a-b on the top surface.

[0138] 4A-4D, the capacitor includes eight external terminals on each surface, and the capacitor includes two sets of alternating dielectric and internal electrode layers, but as noted above, the invention is not limited by the number of external terminals and / or the number of sets of alternating dielectric and internal electrode layers.

[0139] For example, FIG. 5A shows a capacitor 30 that includes sixteen external terminals on each surface and four sets of alternating dielectric and internal electrode layers.

[0140] 5A, the capacitor 30 has a four-by-four configuration, i.e., the capacitor includes four terminals along one dimension of the top and bottom surfaces and four terminals along another dimension of the top and bottom surfaces. In this regard, the capacitor includes a total of 16 external terminals 32a-b, 34a-b on the top surface and 16 corresponding external terminals on the bottom surface, which may be electrically connected to the corresponding external terminals on the bottom surface.

[0141] The capacitor 30 of Figure 5A includes external terminals 32a-b, 34a-b, and four sets 210 of alternating dielectric and internal electrode layers, as shown in Figure 5B. As shown in Figures 4B and 4C, each set 210 of alternating dielectric and internal electrode layers includes internal electrode layers 205, 215, and a dielectric layer (not shown) in an alternating arrangement.

[0142] It will be appreciated that lead tabs 220a-b connect to external terminals 32a-b, respectively, while lead tabs 240a-b connect to external terminals 34a-b, respectively. Thus, each lead tab 220a-b is interdigitated with a respective lead tab 240a-b, respectively, in a manner similar to external terminals 32a-b and 34a-b. The interdigitated lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0143] Additionally, the capacitor 30 of Figure 5A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface. Although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity. Specifically, Figure 5A includes four positive terminals 32a-b and four negative terminals 34a-b on the top surface.

[0144] It should be understood that although the capacitors of Figures 4A, 4D and 5A, 5B use the set of alternating dielectric layers and internal electrode layers 210 of Figure 4B, other configurations may also be used. That is, the set of alternating dielectric layers and internal electrode layers 110 of Figures 3B, 3C may also be used in the capacitors 20 of Figures 4A, 4D and the capacitors 30 of Figures 5A, 5B. In this regard, rather than just using two sets of alternating dielectric layers and internal electrode layers 210 in the capacitors 20 of Figures 4A, 4D, the capacitor may use up to four sets of alternating dielectric layers and internal electrode layers 110. In this regard, the capacitors 20 of Figures 4A, 4D may use from two to four sets of alternating dielectric layers and internal electrode layers. Similarly, rather than just using four sets of alternating dielectric layers and internal electrode layers 210 in the capacitors 30 of Figures 5A, 5B, the capacitor may use up to eight sets of alternating dielectric layers and internal electrode layers 110. In this regard, capacitor 30 of FIGS. 5A and 5B can employ from two to eight sets of alternating dielectric and internal electrode layers.

[0145] Additionally, although the illustrated embodiment uses only four internal electrode layers per set of alternating dielectric and internal electrode layers, it should be understood that the present invention may include any number of internal electrode layers per set and is not necessarily limited thereto.

[0146] In general, the present invention provides a capacitor having a unique construction that provides various benefits and advantages. In this regard, it should be understood that the materials used to construct the capacitor are not limited and may be any commonly used in the art and may be formed using any method commonly used in the art.

[0147] In general, the dielectric layer is typically formed from a dielectric material. The dielectric material may have a relatively high relative dielectric constant in one embodiment. In another embodiment, the dielectric material may have a relatively low relative dielectric constant. For example, the relative dielectric constant may be 3 or more, such as 3.5 or more, 4 or more, 4.5 or more, 5 or more, 7 or more, 10 or more, 15 or more, 20 or more, 25 or more, 30 or more, 40 or more, 50 or more, 60 or more, 70 or more, 80 or more, 90 or more, 100 or more, 200 or more, 300 or more, 400 or more, 500 or more, 1,000 or more, 2,000 or more, 5,000 or more, 10,000 or more, etc. The dielectric constant can be 40,000 or less, for example, 30,000 or less, 20,000 or less, 10,000 or less, 5,000 or less, 2,000 or less, 1,000 or less, 800 or less, 600 or less, 400 or less, 200 or less, 150 or less, 100 or less, 90 or less, 80 or less, 70 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, 15 or less, 10 or less, etc.

[0148] In this regard, the dielectric material may be a ceramic, which may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or as a dielectric material that is co-fired within the device itself.

[0149] Specific examples of this type of high dielectric constant material include, for example, NPO (COG) materials (up to about 100), X7R materials (from about 3,000 to about 7,000), X7S materials, Z5U materials, and / or Y5V materials. It should be recognized that the above-mentioned materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Association (EIA) and thus should be recognized by those skilled in the art. For example, such materials may include ceramics. Such materials may include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuthate titanate, etc. For example, in one specific embodiment, a material having the chemical formula Ba x Sr 1-x TiO 3 Barium strontium titanate ("BSTO") may be used, where x is from 0 to 1, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO 3 where x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; and Pb x Zr 1-x TiO 3 ("PZT"), where x ranges from about 0.05 to about 0.4, as well as lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 , LiNbO 3 , LiTaO 3, PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ), and NaBa 2 (NbO 3 ) 5 KHb 2 PO 4 Still further complex perovskites may include A[B1 1 / 3 B2 2 / 3 ]O 3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), and B1 is Mg y Zinc 1-y (y can range from 0 to 1), and B2 is Ta z Nb 1-z where z can be a value from 0 to 1. In one specific embodiment, the dielectric layer can include a titanate.

[0150] The internal electrode layers may be formed from any of a variety of different materials, as known in the art. The internal electrode layers may be made from metals, such as conductive metals. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. In one particular embodiment, the internal electrode layers may include nickel or an alloy thereof.

[0151] The external terminals may be formed from any of a variety of different metals as known in the art. The external terminals may be made from a metal, such as a conductive metal. Materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., as well as various combinations thereof. In one particular embodiment, the external terminals may include copper or an alloy thereof.

[0152] The external terminals may be formed using any method commonly known in the art. The external terminals may be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, jet spray / airbrush, etc.

[0153] The external terminals may be formed such that they are thin film platings of metal. Such thin film platings may be formed by depositing a conductive material, such as a conductive metal, on exposed portions of the internal electrode layers. For example, leading edges of the internal electrode layers may be exposed to allow for the formation of plated terminations.

[0154] The external terminals may have an average thickness of about 50 μm or less, e.g., about 40 μm or less, about 30 μm or less, about 25 μm or less, about 20 μm or less, etc., to about 5 μm or more, e.g., about 10 μm or more, about 15 μm or more, etc. For example, the external terminals may have an average thickness of about 5 μm to about 50 μm, e.g., about 10 μm to about 40 μm, about 15 μm to about 30 μm, about 15 μm to about 25 μm, etc.

[0155] In general, the external terminals may include plated terminals. For example, the external terminals may include electroplated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals may be formed via electrolytic plating. The electroless plated terminals may be formed via electroless plating.

[0156] When multiple layers make up the external terminals, the external terminals may include electroplated terminals and electroless plated terminals. For example, electroless plating may be used first to deposit an initial layer of material. The plating technique may then be switched to electrochemical plating, which may allow for faster build-up of the material.

[0157] When forming a plating terminal using any plating method, the leading edge of the lead tab of the internal electrode layer exposed from the body of the capacitor is exposed to a plating solution. In one embodiment, exposing can mean immersing the capacitor in the plating solution.

[0158] The plating solution includes a conductive material, such as a conductive metal, that is used to form the plated terminations. Such conductive material may be any of the materials described above or any that are generally known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plating layer and external terminals include nickel. Alternatively, the plating solution may be a cuprate bath solution or other suitable copper solution, such that the plating layer and external terminals include copper.

[0159] Furthermore, it should be understood that the plating solution may contain other additives as is generally known in the art. For example, the additives may include other organic additives and media that can aid in the plating process. Additionally, additives may be used to provide a plating solution at a desired pH. In one embodiment, a resistance reducing additive may be used in the solution to aid in complete plating coverage and bonding of plating material to the exposed leading edges of the lead tabs of the capacitor and internal electrode layers.

[0160] The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined time. Such exposure time may be for a time sufficient to allow sufficient plating material to deposit to form a plating termination, but is not necessarily limited. In this regard, the time should be sufficient to allow for the formation of continuous connections between the desired exposed adjacent leading edges of the lead tabs of a given polarity of each internal electrode layer in a set of alternating dielectric and internal electrode layers.

[0161] In general, the difference between electrolytic and electroless plating is that electrolytic plating uses an electrical bias, such as by using an external power source. Electrolytic plating solutions typically use a high current density range, e.g., 10-15 amp / ft 2 (rated at 9.4 volts). A connection can be made with a negative connection to the capacitor requiring the formation of a plating terminal, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased with a polarity opposite that of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the exposed leading edge metal of the lead tab of the internal electrode layer.

[0162] Various pretreatment steps may be used prior to submerging or exposing the capacitor to the plating solution. Such steps may be performed for a variety of purposes, including catalyzing, accelerating, and / or improving adhesion of plating material to the leading edges of the lead tabs.

[0163] Additionally, an initial cleaning step may be used prior to plating or any other pretreatment step. Such a step may be used to remove any oxide buildup that forms on the exposed lead tabs of the internal electrode layers. This cleaning step may be particularly useful to help remove any buildup of nickel oxide when the internal electrodes or other conductive elements are formed of nickel. Component cleaning may be accomplished by complete immersion in a pre-cleaning solution layer, such as one that includes an acid cleaner. In one embodiment, the exposure may be for a predetermined period of time, such as on the order of about 10 minutes. Cleaning may alternatively be accomplished by a chemical polishing or harperizing step.

[0164] Additionally, a step may be taken to activate the exposed metallic leading edges of the lead tabs of the internal electrode layers to facilitate deposition of conductive material. Activation may be accomplished by palladium salt immersion, photopatterned (via mask or laser) palladium organometallic precursors, screen printed or inkjet deposited palladium compounds, or electrophoretic palladium deposition. It should be recognized that palladium-based activators are currently disclosed merely as examples of activation solutions that often work well with activation of exposed tab portions formed of nickel or its alloys. However, it should be understood that other activation solutions may be utilized and are therefore not necessarily limiting.

[0165] Also, instead of or in addition to the activation step described above, an activation dopant can be introduced into the conductive material when forming the internal electrode layers of the capacitor. For example, if the internal electrode layers include nickel and the activation dopant includes palladium, a palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layers. In this way, the palladium activation step can be eliminated. It should be further recognized that some of the above activation methods, such as organometallic precursors, also lend themselves to the co-deposition of glass formers to enhance adhesion to the generally ceramic body of the capacitor. When the activation step is performed as described above, it often leaves traces of the active body material on the exposed conductive parts before and after termination plating.

[0166] Additionally, post-plating steps may also be used as desired or necessary. Such steps may be performed for a variety of purposes, including strengthening and / or improving adhesion of the material. For example, a heating (or annealing) step may be used after performing the plating step. Such heating may be performed via baking, laser subjection, UV irradiation, microwave irradiation, arc welding, etc.

[0167] As shown herein, the external terminal comprises at least one plating layer. In one embodiment, the external terminal may comprise only one plating layer. However, it should be understood that the external terminal may comprise multiple plating layers. For example, the external terminal may comprise a first plating layer and a second plating layer. Furthermore, the external terminal may also comprise a third plating layer. Furthermore, the materials of these plating layers may be any of those described above and those generally known in the art.

[0168] For example, one plating layer, such as the first plating layer, may include copper or an alloy thereof. Another plating layer, such as the second plating layer, may include nickel or an alloy thereof. Alternatively, another plating layer, such as the second plating layer, may include copper or an alloy thereof. Another plating layer, such as the third plating layer, may include a combination, such as tin, lead, gold, or an alloy. Alternatively, an initial plating layer may include nickel followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper may be formed, followed by a layer of nickel.

[0169] In one embodiment, the initial or first plating layer can be a conductive metal (e.g., copper). This area can then be covered with a second layer comprising a resistive-polymeric material for sealing. This area can then be polished to selectively remove the resistive-polymeric material, and then plated again with a third layer comprising a conductive metallic material (e.g., copper).

[0170] The second layer above the initial plating layer may correspond to a solder barrier layer, for example a nickel solder barrier layer. In some embodiments, the layer may be formed by electroplating an additional layer of metal (e.g., nickel or copper) on top of an initial electroless or electrolytic plated layer (e.g., plated copper). Other exemplary materials for the solder barrier layer include nickel-phosphorus, gold, and silver. The third layer above the solder barrier layer may correspond to a conductive layer, such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder, in some embodiments.

[0171] Additionally, a layer of metal plating may be formed, followed by an electroplating step to provide a resistive or more resistive metal alloy coating, such as an electroless Ni-P alloy, over such metal plating, although it should be understood that any metal coating may be included, as would be understood by one of ordinary skill in the art from the full disclosure of this application.

[0172] It should be appreciated that any of the above steps may occur as a bulk process, such as a barrel plating termination process, a fluidized bed plating termination process, and / or a flow-through plating termination process, all of which are commonly known in the art. Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is particularly advantageous compared to traditional termination methods, such as printing thick film terminations, which require individual component processing.

[0173] As described herein, the formation of the external terminals is generally guided by the location of the exposed leading edges of the lead tabs of the internal electrode layers. Such a phenomenon may be referred to as "self-determining" since the formation of the external plated terminals is determined by the configuration of exposed conductive metal of the internal electrode layers at selected peripheral locations on the capacitor.

[0174] Further aspects of the above techniques for forming thin film plated terminations are described in U.S. Patent No. 7,177,137 to Ritter et al. and U.S. Patent No. 7,463,474 to Ritter et al., which are incorporated herein by reference for all purposes. It should be recognized that additional techniques for forming capacitor terminals may also fall within the scope of this technology. Exemplary alternatives include, but are not limited to, forming terminations by plating, magnetic, masking, electrophoretic / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming both thick film conductive layers or thin film conductive layers.

[0175] Additionally, the capacitor may then receive a solder mask. For example, this may allow the capacitor to be coated. Without intending to be limiting, such a mask may assist in preventing oxidation of a plating layer, such as a copper plating layer, especially when such a plating layer is the final plating layer of the external terminals. Such solder mask materials may not necessarily be limited by the present invention. For example, such materials may include any of the materials described above with respect to the solder barrier layer. Additionally or alternatively, such materials may include an epoxy, such as a liquid epoxy, which is subsequently cured.

[0176] When providing such materials on a capacitor, access to the plating layers and external terminals may be required to form electrical connections. In this regard, a laser may be utilized to form holes through the mask layer. Such holes may then be filled with a conductive material, such as copper, which may then be utilized to form electrical connections with the capacitor.

[0177] The capacitors disclosed herein may be mounted using a variety of means. For example, the capacitors may be mounted on a circuit board including a substrate (e.g., an insulating layer) having an upper surface and a lower surface. The circuit board has a plurality of current paths defined therein. The external terminals of the capacitors are in electrical communication with the respective predetermined current paths of the circuit board. Furthermore, the external terminals of the capacitors may be physically connected to the circuit board using any method commonly known in the art, such as general-purpose soldering techniques.

[0178] Additionally, an integrated circuit package may also be provided on the circuit board. The integrated circuit package may be connected to the circuit board using a ball grid array. The circuit board may further include a processor. The processor may also be connected to the integrated circuit package using a ball grid array.

[0179] In general, ball grid arrays may be configured such that the pitch is 1.5 mm or less, such as 1.25 mm or less, 1 mm or less, 0.8 mm or less, such as 0.6 mm or less, and 0.4 mm or more, such as 0.5 mm or more, 0.6 mm or more.

[0180] Furthermore, the integrated circuit package may also be connected to the circuit board using a capacitor as defined herein. In this regard, the internal electrode layers of the capacitor may be positioned so that they are perpendicular to the horizontal plane of the circuit board and the integrated circuit package. In other words, the internal electrode layers of the capacitor may be positioned so that they are substantially non-parallel to the circuit board. For example, the capacitor may be positioned between the integrated circuit package and the circuit board such that the capacitor is "sandwiched" between the two components. In this regard, the capacitor is directly connected to the integrated circuit package and the circuit board. For example, the capacitor may be connected (e.g., physically and / or electrically) to the circuit board and / or the circuit package using any method commonly known in the art, such as general-purpose soldering techniques.

[0181] By using a capacitor in the above arrangement, the capacitor may allow for the removal of a portion of the original ball grid array, however the capacitor may still be surrounded by the ball grid array.

[0182] In addition to the above, although not shown herein, in one embodiment, the integrated circuit package itself may include a multi-layer capacitor. In this regard, the capacitor may be embedded directly into the package. Such incorporation of the capacitor may allow for a reduction in size, which may be beneficial for various electronic applications.

[0183] While the above provides one example of a means for mounting the capacitors disclosed herein, it should be understood that other methods may be utilized. For example, the capacitors may be mounted via a land grid array configuration. The capacitors may also be embedded in another substrate or component.

[0184] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. Moreover, it should be understood that aspects of the various embodiments may be interchanged both in whole or in part. Moreover, the above description is by way of example only and is not intended to limit the invention, which is further described in the appended claims. [Explanation of symbols]

[0185] 10 Capacitor 12 External terminal, first polarity terminal, positive terminal 14 External terminal, negative terminal 20 Capacitor 22a External terminal 22b External terminal 24a External terminal 24b External terminal 30 Capacitor 32a External terminal 32b External terminal 34a External terminal 34b External terminal 105 First internal electrode layer 105a Side edge 105b Side edge 105c Top edge 105d bottom edge 110 A set of alternating dielectric layers and internal electrode layers 115 Second internal electrode layer 120 First lead tab 121 Lateral edge 122 Lateral edge 123 Leading Edge 130 First lead tab 131 Lateral edge 132 Lateral edge 133 Leading Edge 135 Main Unit 140 First lead tab 141 Lateral edge 142 Lateral edge 143 Leading Edge 145 Body 150 First Lead Tab 151 Lateral edge 152 Lateral edge 153 Leading Edge 205 First internal electrode layer 205a Side edge 205b Side edge 205c top edge 205d bottom edge 210 Set of alternating dielectric layers and internal electrode layers 215 Second internal electrode layer 220 First lead tab 220a first lead tab 220b lead tab 221a Lateral edge 222a Lateral edge 223a leading edge 223b leading edge 230 First lead tab 230a first lead tab 230b lead tab 231a Lateral edge 232a Lateral edge 233a Leading edge 233b Leading edge 235 Main Body 240a first lead tab 240b lead tab 241a Lateral edge 242a Lateral edge 243a Leading edge 243b Leading edge 245 Main Unit 250 First Lead Tab 250a First lead tab 250b lead tab 251a Lateral edge 252a Lateral edge 253a Leading edge 253b leading edge

Claims

1. a body including a first set of alternating dielectric layers and internal electrode layers, the set including a first internal electrode layer and a second internal electrode layer; each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top and bottom edges, which define a body of the internal electrode layer; a body, each internal electrode layer including at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer; an external terminal electrically connected to the internal electrode layer; wherein the external terminals are formed on a top surface of the capacitor and on a bottom surface of the capacitor opposite the top surface, the capacitor comprising one or more dielectric regions including one or more voids.

2. 2. The capacitor of claim 1 , wherein at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer include side edges aligned with side edges of the body of the internal electrode layer.

3. The capacitor of claim 1 , wherein the external terminals further extend along end surfaces between the top and bottom surfaces.

4. 2. The capacitor of claim 1, wherein the first and second internal electrode layers are interleaved in a facing relationship and a dielectric layer is positioned between the first and second internal electrode layers.

5. 2. The capacitor of claim 1 , wherein each internal electrode layer includes at least two lead tabs extending from the top edge, the bottom edge, or both the top and bottom edges, the two lead tabs including a first lead tab and a second lead tab.

6. The capacitor of claim 1 , wherein at least one side edge of the lead tab on the top edge is substantially aligned with at least one side edge of the lead tab on the bottom edge.

7. 2. The capacitor of claim 1, wherein both side edges of the lead tab on the top edge are substantially aligned with both side edges of the lead tab on the bottom edge.

8. 6. The capacitor of claim 5, wherein at least one side edge of the first lead tab and at least one side edge of the second lead tab on a top edge are substantially aligned with at least one side edge of the first lead tab and at least one side edge of the second lead tab on a top edge, respectively.

9. 6. The capacitor of claim 5, wherein both side edges of the first lead tab and both side edges of the second lead tab on a top edge are substantially aligned with both side edges of the first lead tab and both side edges of the second lead tab on the top edge.

10. The capacitor of claim 1 , wherein the body further comprises a second set of alternating dielectric and internal electrode layers.

11. The capacitor of claim 10 , wherein the one or more dielectric regions are between the first set and the second set.

12. The capacitor of claim 1 , wherein the one or more dielectric regions are between a first or last internal electrode layer in a set and an adjacent side surface.

13. The capacitor of claim 1 , wherein the one or more dielectric regions are between lateral edges of an internal electrode layer and an adjacent end surface.

14. The capacitor of claim 1 , wherein the one or more dielectric regions are between lateral edges of adjacent lead tabs.

15. The capacitor of claim 1 , wherein the one or more voids comprise a via.

16. The capacitor of claim 15 , wherein the via extends through a thickness of the capacitor.

17. The capacitor of claim 15 , wherein the via extends partially through a thickness of the capacitor.

18. The capacitor of claim 1 , wherein the dielectric region is the region that exists between two external terminals.

19. 10. The capacitor of claim 1, wherein the one or more voids comprise from 1 vol. % to 15 vol. % of the capacitor.

20. The capacitor of claim 4 , wherein the dielectric layer comprises a ceramic.

21. The capacitor of claim 1 , wherein the internal electrode layers comprise a conductive metal.

22. The capacitor of claim 1 , wherein the external terminals comprise an electroplated layer.

23. The capacitor of claim 1 , wherein the external terminals include an electroless plating layer.

24. The capacitor of claim 1 , wherein the external terminals include an electroless plating layer and an electroplating layer.

25. The capacitor of claim 1 , wherein the external terminals include a first electrolessly plated layer, a second electroplated layer, and a third electroplated layer.

26. 26. The capacitor of claim 25, wherein the first electroless plated layer comprises copper, the second electroplated layer comprises nickel, and the third electroplated layer comprises tin.

27. 10. The capacitor of claim 1 comprising at least three sets of alternating dielectric and internal electrode layers.

28. 10. A circuit board comprising the capacitor of claim 1 positioned on said circuit board.

29. 30. The circuit board of claim 28, further comprising an integrated circuit package, the capacitor being positioned vertically between the circuit board and the integrated circuit package such that the circuit board, the capacitor, and the integrated circuit package are in a stacked arrangement.

30. 30. The circuit board of claim 29, wherein the capacitor is directly connected to the circuit board and to the integrated circuit package.

31. 10. An integrated circuit package comprising the capacitor of claim 1.

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