Memory Devices

Abstract

1. A memory device (1) comprising a semiconductor pillar (40) and at least one memory cell (50) associated with the pillar (40), each of the at least one memory cell (50) comprising a charge trap (60) and a transistor (2), and for each of the at least one memory cell (50), the charge trap (60) of the memory cell (50) is configured to control a threshold voltage of the transistor (2) of the memory cell (50) by a stored charge, the transistor (2) of the memory cell (50) comprising a source pillar segment (10), a drain pillar segment (14), and a body pillar segment (12), and at least one p-doped pillar segment (10, 12, 14) of the transistor (2) comprises a plurality of semiconductor layers (20), the layers of the plurality of semiconductor layers (20) being fabricated from AlGaN or GaN, the plurality of semiconductor layers (20) being configured such that every other layer has a lower aluminum content than its neighboring mutually opposing layers.

Description

[Technical field]

[0001] The inventive concepts relate generally to memory devices, uses of memory devices, and methods for producing memory devices. [Background technology]

[0002] Memory devices, such as electronic non-volatile memory devices, are widely used in electronic devices. For example, flash memory can store information in the form of electric charge in memory cells. To increase memory capacity, 3D integrated circuit technology can be used to stack memory cells in multiple layers. However, there is still room for further improvement of memory devices. Summary of the Invention

[0003] It is an object of the present invention to provide a memory device having a high storage capacity. A further object is to provide a low cost memory device. A further object is to provide a memory device for high frequency and / or high power and / or high temperature operation. These and other objects of the inventive concept are at least partly met by the present invention as defined in the independent claims. Preferred embodiments are specified in the dependent claims.

[0004] In this document, abbreviations of natural elements are used according to the periodic table, e.g., Al means aluminum, Ga means gallium, As means arsenic, Mg means magnesium, O means oxygen, Si means silicon, and N means nitrogen.

[0005] According to a first aspect, there is provided a memory device including a pillar of semiconductor material and at least one memory cell associated with the pillar, each of the at least one memory cell including a charge trap and a transistor, and for each of the at least one memory cell: a charge trap of the memory cell configured to store a charge and to control a threshold voltage of a transistor of the memory cell by the stored charge; The transistor of the memory cell includes a source, a body, and a drain, the source, the body, and the drain being respective pillar segments along an axial direction of the pillar, the source pillar segment and the drain pillar segment being separated by a body pillar segment, and the transistor is an NPN transistor, in which the source pillar segments are n-doped, the body pillar segments are p-doped, and the drain pillar segments are n-doped, or - a PNP transistor, in which the source pillar segments are p-doped, the body pillar segments are n-doped, and the drain pillar segments are p-doped; At least one p-doped pillar segment of the transistor includes a plurality of semiconductor layers stacked axially of the pillar, the layers of the plurality of semiconductor layers being fabricated from AlGaN or GaN, and the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its neighboring mutually opposing layers.

[0006] It is recognized that the memory device may include a GaN-based material. As used herein, the term "GaN-based material" should be interpreted as any semiconductor material that includes gallium and nitrogen, such as GaN, AlGaN, InGaN, AlInGaN. According to the above, at least one p-doped pillar segment of the transistor of the memory cell includes a plurality of semiconductor layers, the layers of the plurality of semiconductor layers being made of AlGaN or GaN, and the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer. Other pillar segments of the transistor, such as the n-doped pillar segment, may include any GaN-based material, such as GaN.

[0007] GaN-based materials can facilitate high frequency and / or high power and / or high temperature operation. Thus, memory devices including GaN-based materials can operate at high frequency and / or high power and / or high temperature. Alternatively or additionally, memory devices including GaN-based materials can be embedded with electronic devices also made of GaN-based materials, for example, within the same chip or on the same substrate.

[0008] P doping can be difficult to achieve in GaN-based materials. Doping atoms, such as Mg, used for p doping are often passivated by hydrogen impurities or nitrogen defects. Thus, the free hole concentration can be low even with high doping concentrations. To remove the passivation (or activate the doping atoms), post-growth annealing, for example in an atmosphere with low hydrogen concentration, can be used.

[0009] It is a recognition that the multiple semiconductor layers may eliminate or reduce the need for post-growth annealing of p-doped GaN-based materials. This facilitates the production of NPN and / or PNP transistors, and thus memory devices based on NPN or PNP transistors. Thus, a p-doped body pillar segment of an NPN transistor of a memory cell of a memory device may include the multiple semiconductor layers. Alternatively or additionally, a p-doped source and / or drain pillar segment of a PNP transistor of a memory cell of a memory device may include the multiple semiconductor layers. Advantageously, both the p-doped source and drain pillar segments of a PNP transistor of a memory cell of a memory device may include the multiple semiconductor layers.

[0010] The semiconductor layers may enhance p-doping through variation of the valence band edge as described by Kozodoy et al. [Appl. Phys. Lett. 75, 2444 (1999)]. The variation of the valence band edge is caused herein by the variation of the Al content in the semiconductor layers. The acceptors may be ionized when the band edge is much lower than the Feremi energy, and the resulting holes may accumulate when the band edge is close to the Feremi level. The valence band edge may vary in a direction perpendicular to the layers of the semiconductor layers as described herein. As a result of the variation of the valence band edge, the hole concentration may also vary. However, the average hole concentration may be higher than in a bulk film where the valence band edge does not change. It should be understood that the variation of the valence band edge may be due to the changing band gap in the semiconductor layers as well as the polarization effect due to band bending.

[0011] Multiple semiconductor layers can also enhance hole mobility, as further explained in Kozodoy et al., Appl. Phys. Lett. 75, 2444-2446 (1999).

[0012] There are various means of implementing multiple semiconductor layers configured such that the aluminum content varies between each successive layer, such that every other layer has a lower aluminum content than its mutually opposing neighbors. Some examples are provided below.

[0013] In a first example, the plurality of semiconductor layers includes a sequence of layers where the even numbered layers have a low aluminum content and the odd numbered layers have a high aluminum content, or vice versa.

[0014] In a second example, the multiple semiconductor layers include a sequence of layers, each layer associated with a number n, where n represents a position in the sequence of layers, and the even n layers have a lower aluminum content than layer numbers n-1 and n+1.

[0015] In a third example, the multiple semiconductor layers include a sequence of layers, each layer associated with a number n, where n represents a position in the sequence of layers, and the odd-numbered layers have a lower aluminum content than layer number n-1 and layer number n+1.

[0016] As used herein, the term "memory cell" should be construed as a cell that stores at least one bit of binary information. Charges stored in the charge traps of a memory cell may represent the stored binary information.

[0017] For example, a memory cell may be configured to store a one bit. As used herein, the absence of charge in a charge trap, e.g., a charge trap storing a charge below a threshold value, may represent a one. The presence of charge in a charge trap, e.g., a charge trap storing a charge above a threshold value, may represent a zero.

[0018] Since the charge traps of the memory cell are configured to store charge and control the threshold voltage of the memory cell's transistor through the stored charge, the memory cell can be read by applying a voltage between the source pillar segment and the drain pillar segment. The threshold voltage at which the transistor turns on thus indicates which bit value is stored. The charge traps of the memory cell can be located near the body pillar segment of the memory cell's transistor. Thus, the charge stored in the charge traps can effectively control the threshold voltage of the transistor. The charge traps of the memory cell can be located, for example, to the side of the body pillar segment of the memory cell's transistor.

[0019] The memory device provides high storage capacity because the source, body, and drain of the transistor are respective pillar segments along the axial direction of the pillar, and therefore the source, body, and drain can be stacked on top of each other and thus have a small footprint on the substrate.

[0020] Further improvements in storage capacity can be achieved when multiple memory cells are associated with a pillar. Thus, the memory cells can be stacked in multiple layers such that a large memory capacity can be achieved within a small area on the substrate. It should be appreciated that facilitating a large memory capacity within a small area can ensure a low cost memory device since more memory cells can be produced from the same substrate.

[0021] Multiple memory cells associated with a pillar may be implemented by stacking transistors on top of each other along the height of the pillar. It should be understood that pillar segments may be shared by adjacent transistors. For example, a memory device including a pillar with two NPN transistors may be implemented with the following doping sequence: NPNPN. Herein, the middle n-doped pillar segment may function as both a drain pillar segment for the first transistor and a source pillar segment for the second transistor. There may be charge traps near each body pillar segment. In the above example of a memory device including a pillar with two NPN transistors, there may be charge traps near each of the two p-doped segments, for example, on the sides of each of the two p-doped segments.

[0022] As used herein, the term "pillar" should be construed as any elongated member in which the axial direction of the pillar is the main direction of extension. The pillar may stand on a substrate, with the axial direction of the pillar being perpendicular to the substrate. The pillar may be etched from a layer of semiconductor material or from multiple layers of semiconductor material. The semiconductor material herein may be a single crystal semiconductor material. The pillar may have a diameter smaller than 1 μm, for example, between 5 nm and 500 nm. The pillar may advantageously be a nanowire. The nanowire may have a diameter smaller than 100 nm, for example, between 5 and 100 nm or between 10 and 50 nm. The small diameter of the pillar may facilitate a small footprint. Furthermore, a small diameter, such as a diameter less than 100 nm, may result in high charge carrier mobility through quantum confinement effects. This may result in high read and write speeds of the memory device.

[0023] The bottom of the pillar may be connected to the substrate. The pillar may be embedded in a supporting and / or electrically insulating material. Alternatively, the pillar may stand free on the substrate without being embedded. One or more electrical gates may be disposed along the height of the pillar. For example, a control gate may be disposed near each body pillar segment, e.g., to the side of each body pillar segment.

[0024] The bottom and top pillar segments may each be electrically connected. The electrical connections in the bottom and top pillar segments may be configured to pass electrical current through the pillars from the bottom pillar segment to the top pillar segment or vice versa. The memory device may be configured such that, for at least one memory cell: The memory cell includes a control gate disposed laterally of the pillar, the control gate configured to control a current through the body pillar segment of the transistor by a voltage on the control gate relative to a threshold voltage of the transistor; and A charge trap of the memory cell is disposed between a control gate and a body pillar segment of a transistor of the memory cell, the charge trap includes a first oxide layer, a charge trapping layer, and a second oxide layer, the first oxide layer separating the charge trapping layer from the body pillar segment and the second oxide layer separating the charge trapping layer from the control gate, and the charge trapping layer includes a dielectric layer and / or a conductive layer.

[0025] As previously mentioned, the control gate of the memory cell may be disposed near the body pillar segment of the memory cell's transistor, for example, laterally of the body pillar segment. The control gate may be electrically isolated from the body pillar segment by first and second oxide layers. A voltage on the control gate may induce an electric field in the body pillar segment, thereby controlling a current through the body pillar segment. When the voltage on the control gate exceeds a threshold voltage of the memory cell's transistor, the transistor may be turned on, allowing a current to pass. When the voltage on the control gate falls below a threshold voltage of the memory cell's transistor, the transistor may be turned off, not allowing a current to pass. As previously mentioned, the charge trap of the memory cell is configured to store charge and to control a threshold voltage of the memory cell's transistor with the stored charge. When the charge trap of the memory cell is disposed between the control gate and the body pillar segment of the memory cell's transistor, the charge in the charge trap may screen an electric field from the control gate, thereby changing the threshold voltage.

[0026] According to the above, the first oxide layer may be considered as a tunnel oxide layer, and the second oxide layer may be considered as a gate oxide layer.

[0027] The following example illustrates how a value can be read from a memory cell. When no charge is stored in the charge traps, the threshold voltage of the transistor can be VT1. When charge is stored in the charge traps, the threshold voltage of the transistor can be V T2 V T2 >V T1Therefore, when charge is stored in the charge traps, a higher voltage on the control gate is required to turn on the transistor. So the control gate voltage can be set to an intermediate voltage, V T2 ~V T1 In this case, when the transistor is turned on at the above intermediate voltage, the threshold voltage is V T1 , indicating that no charge is stored in the charge trap. Thus, the absence of charge in the charge trap may be indicated by a current through the transistor, which may represent a binary value of 1. Similarly, if the transistor does not conduct at the intermediate voltage, then the threshold voltage is V T2 , indicating that a charge is stored in the charge trap. Thus, the presence of charge in the charge trap may be indicated by the absence of current through the transistor, which may represent a binary value of 0.

[0028] The following example describes how values ​​can be written to or erased from a memory cell. Writing and erasing can be performed by tunneling charge into or out of the charge trapping layer through the first oxide layer. The tunneling process can be Fowler-Nordheim tunneling. Writing can alternatively be performed by hot electron injection.

[0029] For each of the at least one memory cell, the first oxide layer and / or the second oxide layer of the charge trap of the memory cell may include Al2O3. An Al2O3 oxide layer may be advantageous because it may be provided by atomic layer deposition without parasitic trap states at the interface.

[0030] As described, the charge trapping layer may include a dielectric layer, for example, silicon nitride. The dielectric layer may be advantageous because the dielectric layer of one memory cell does not need to be electrically isolated from the dielectric layer of another memory cell. Even if the same dielectric layer is used for both memory cells, the charges may be stored in localized traps within the dielectric layer such that they cannot move from one memory cell to another. Thus, fabrication may be simplified. The dielectric layer may include a high-k dielectric material. For example, for each of the at least one memory cell, the charge trapping layer of the memory cell's charge trap may include a high-k dielectric material, such as Y2O3, TiO2, HfO2, ZrO2, or La2O3. The dielectric layer may be deposited, for example, by atomic layer deposition.

[0031] As described, the charge trapping layer may include a conductive layer. The conductive layer may include a conductive material such as a metal or a doped semiconductor material, for example, a degeneratively doped semiconductor material. The conductive layer may have the advantage that it is fairly insensitive to trap-related reliability issues. When using a conductive layer, it is less likely that a memory cell will be stuck in a permanent logic state (e.g., always at 1) due to poor trap reliability. When a conductive layer is used, the conductive layer of one memory cell may be electrically isolated from the conductive layer of another memory cell. The conductive layer may be deposited, for example, by atomic layer deposition.

[0032] It should be understood that the charge trapping layer may include both dielectric and conductive layers. Such a charge trapping layer may combine the advantages of the two materials.

[0033] For each of the at least one memory cell, a transistor of the memory cell may include a repeating pair of semiconductor layers, each pair of semiconductor layers comprising: a low Al content layer having an Al content below 10%, and The high Al content layer has an Al content of more than 15%.

[0034] Therefore, the low Al content layer is Al x Ga 1-xIt can be a layer of N, where x < 0.1. Similarly, the high-Al-content layer can be a layer of Al x Ga 1-x N, where x > 0.15. It is preferable that all the low-Al-content layers have the same composition. For example, all the low-Al-content layers can have zero Al content, that is, they contain GaN, that is, x = 0. It is preferable that all the high-Al-content layers have the same composition and that they have an Al content of 20% to 40%, that is, they contain a material ranging from Al 0.2 Ga 0.8 N to Al 0.4 Ga 0.6 N, that is, 0.2 < x < 0.4. An example of a plurality of semiconductor layers containing four layers can be Al 0.2 Ga 0.8 N / GaN / Al 0.2 Ga 0.8 N / GaN or Al 0.3 Ga 0.7 N / GaN / Al 0.3 Ga 0.7 N / GaN.

[0035] Alternatively, each pair of semiconductor layers can include low- and high-Al-content layers, but not all the low-Al-content layers necessarily have the same Al content. Similarly, not all the high-Al-content layers necessarily have the same Al content. Thus, the plurality of semiconductor layers can be, for example, Al 0.2 Ga 0.8 N / Al 0.05 Ga 0.95 N / Al 0.16 Ga 0.84 N / GaN, or Al 0.3 Ga 0.7 N / Al 0.09 Ga 0.91 N / Al 0.2 2Ga 0.78 N / Al 0.02 Ga 0.98 N / Al 0.2 Ga 0.8 N / Al 0.07 Ga 0.93 N.

[0036] A layer with a low Al content may, to a first approximation, have a smaller band gap than a layer with a high Al content. This may result in a variation in the valence band edge. However, polarization and / or strain effects between the low and high Al content layers may modify the variation in the valence band edge. For example, local energy minima and local energy maxima at the varying valence band edge may exist at the interface between the high and low Al content layers. To illustrate, assuming that the surface of the crystal is a Ga face proceeding upwards from the substrate through multiple semiconductor layers (which may be the case when MOCVD is used to initiate growth on sapphire), a local energy minimum may appear at the interface in the conduction band where the low Al content layer transitions to the high Al content layer (let us label this as region A), and a local energy maximum may appear at the interface where the high Al content layer transitions to the low Al content layer (let us label this as region B). The above explanation is similar to that on page 2445 of Appl. Phys. Lett. 75, 2444-2446 (1999), which is incorporated herein by reference.

[0037] It should be noted that when this document refers to the semiconductor layers being p-doped, it may be interpreted as the semiconductor layers being p-doped in the A regions but not in the B regions. Such doping may result in the highest hole mobility. However, it may also, of course, be interpreted as the semiconductor layers being p-doped throughout the layers of the semiconductor layers.

[0038] For each of the at least one memory cell, each layer of the plurality of semiconductor layers of the at least one p-doped pillar segment of the transistor may have a thickness between 3 nm and 10 nm. The layers may all have the same thickness, e.g., all layers have a thickness of 3 nm, all layers have a thickness of 6 nm, or all layers have a thickness of 10 nm. Alternatively, the plurality of semiconductor layers may include layers of different thicknesses. For example, all low Al content layers may have a thickness between 3 nm and 10 nm, and all high Al content layers may have a thickness between 3 nm and 10 nm, with the thickness of the low Al content layers being different from the thickness of the high Al content layers. For example, each pair of semiconductor layers may include, for example, a low Al content layer that is 6 nm thick and a high Al content layer that is 5 nm thick.

[0039] In the thickness range of 3 to 10 nm, the enhancement of p-doping may be most efficient, for example, the polarization effect and / or strain effect between the low Al content layer and the high Al content layer may be most effective in the thickness range.

[0040] It should be understood that the memory device may include multiple pillars. The memory device includes a first pillar and a second pillar, each of the first pillar and the second pillar having at least one memory cell associated with the pillar, the memory cell of the first pillar and the memory cell of the second pillar share a common control gate, the common control gate configured to simultaneously control current through a body pillar segment of a transistor of the memory cell of the first pillar and current through a body pillar segment of a transistor of the memory cell of the second pillar by a voltage of the common control gate.

[0041] Thus, the common control gate may be a word line of a memory device. The common control gate allows for simultaneous reading from several memory cells.

[0042] According to a second aspect there is provided a use of a memory device according to the first aspect for analog-to-digital conversion, wherein conversion rules for the analog-to-digital conversion may be stored in the memory device.

[0043] The conversion rule may be a look-up table stored in a memory device, which relates the amplitude of the incoming analog signal to the digital value to which said amplitude should be converted.

[0044] The conversion rule may be an algorithm stored in a memory device, which relates the amplitude of an incoming analog signal to a digital value to which said amplitude should be converted. The algorithm may be a self-calibrating algorithm.

[0045] The use of the memory device according to the first aspect may facilitate accurate analog-to-digital conversion. Furthermore, an analog-to-digital converter may include a memory device according to the first aspect, and conversion rules for the analog-to-digital conversion are stored in the memory device. Thus, an analog-to-digital converter including a GaN-based material may advantageously include a memory device according to the first aspect.

[0046] Other uses for the memory devices may include use in field programmable gate arrays (FPGAs), for example FPGAs for high power or high temperature use.

[0047] According to a second aspect, there is provided a method for producing a memory device, the method comprising: depositing semiconductor layers on a substrate, the semiconductor layers being stacked in a stacking direction such that a semiconductor structure is formed from the deposited semiconductor layers; Etching the semiconductor structure to form pillars, the pillars having an axial direction in a stacking direction; forming a transistor in the pillar, the transistor including a source, a body, and a drain, the source, body, and drain being respective pillar segments along an axial direction of the pillar, the source pillar segment and the drain pillar segment being separated by a body pillar segment, the transistor being: an NPN transistor, in which the source pillar segments are n-doped, the body pillar segments are p-doped, and the drain pillar segments are n-doped, or - a PNP transistor, in which the source pillar segments are p-doped, the body pillar segments are n-doped, and the drain pillar segments are p-doped; forming at least one p-doped pillar segment of the transistor comprising a plurality of semiconductor layers of deposited semiconductor layers stacked in an axial direction of the pillar, the layers of the plurality of semiconductor layers of the p-doped pillar segment being made of AlGaN or GaN, the plurality of semiconductor layers of the p-doped pillar segment being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its neighboring mutually opposing layers; forming a charge trap configured to store charge and, with the stored charge, to control a threshold voltage of the transistor; The transistor and the charge traps are part of a memory cell of a memory device.

[0048] The method facilitates simple production of memory devices, particularly compared to the production of conventional 3D flash architectures. Conventional 3D flash architecture devices can be produced by etching channel holes in a support material and then depositing channel material into the holes. It is recognized that the production of conventional 3D flash architectures has several drawbacks that current methods overcome.

[0049] In the production of conventional 3D flash architectures, the dry etching for the channel holes is a challenging step where classical dry etching chemistries are used to their limits.

[0050] Conventional 3D flash architectures may require depositing alternating layer stacks and then etching those stack layers with extreme precision. Step etch for contact landing, hard mask etch, gate trench etch, channel hole etch, and step contact etch are the main critical etches that may be required to fabricate conventional 3D flash devices. It is a recognition that the plasma etch processes involved in the fabrication of conventional 3D flash devices are becoming increasingly difficult. Step etch, which requires a vertical stack layer etch followed by a lateral resist mask etch with multiple repeated lateral / vertical etch cycles to form step-shaped contact landing pads, brings unique challenges in resist mask lateral vs. vertical etch rate control, resist mask shape control, stack layer etch selectivity control, step step width control, and step width uniformity control. The hard mask open, gate trench etch, channel hole etch, and step contact etch create significant challenges especially for etching high aspect ratio (HAR) features that range in aspect ratios from 30:1 to >80:1. Furthermore, etching through HAR alternating layer stacks places increased demands on the etch process, which must be capable of vertical profiles without etch distortion, bending, faceting, and feature plugging. Additionally, smooth sidewall transitions within the alternating stacks and very high selectivity to very small pads are required, especially for step contact etch applications that combine extreme simultaneous multi-level etching at aspect ratios ranging from 30:1 to >80:1 along with extremely high selectivity to negligible loss of the underlying contact material.

[0051] The current method may be considered a bottom-up production method, compared to the traditional top-down production of conventional 3D flash architectures.

[0052] It should be understood that more than one pillar may be etched according to the present method. A plurality of pillars, for example an array of pillars, may be etched.

[0053] The method may further include lithographically defining the lateral size and position of the pillars by imprint lithography. The imprint lithography may be nanoimprint lithography. The method may include lithographically defining the array of pillars by imprint lithography. Imprint lithography is a cheap and simple way of patterning large areas, e.g., an entire wafer.

[0054] The charge trap may be formed by depositing a first oxide layer, a charge trapping layer, a second oxide layer, and a control gate laterally of the pillar; a first oxide layer separating the charge trapping layer from the body pillar segments and a second oxide layer separating the charge trapping layer from the control gate; the charge trapping layer includes a dielectric layer and / or a conductive layer; The control gate is configured to control a current through the body pillar segment of the transistor depending on a voltage on the control gate relative to a threshold voltage of the transistor.

[0055] As previously explained, the first oxide layer may be considered a tunnel oxide layer, and the second oxide layer may be considered a gate oxide layer.

[0056] High quality charge traps can be formed by depositing layers laterally of the pillars. The layer thicknesses are precisely controlled by deposition. Thus, the tunnel oxide layer, the charge trapping layer, and the gate oxide layer have uniform thickness from pillar to pillar and from device to device.

[0057] The method may include etching a semiconductor structure to form a first pillar and a second pillar, each of the first pillar and the second pillar having at least one memory cell associated with the pillar, the method comprising: The method further includes forming a common control gate, the common control gate being shared by the memory cell of the first pillar and the memory cell of the second pillar, the common control gate being configured to simultaneously control a current through a body pillar segment of the transistor of the memory cell of the first pillar and a current through a body pillar segment of the transistor of the memory cell of the second pillar by a voltage of the common control gate, the common control gate being formed after etching the semiconductor structure to form the first pillar and the second pillar.

[0058] Thus, the common control gate may be a word line of a memory device. The common control gate allows for simultaneous reads from several memory cells. Forming the common control gate after etching the semiconductor structure to form the first and second pillars promotes a stable production process. In other words, forming the word lines around the pillars promotes a stable production process. In contrast, etching holes between the word lines to form channels within the holes may create a fragile structure, much like a "house of cards."

[0059] According to the method, the first oxide layer, the charge trapping layer, and the second oxide layer may be deposited by one or more conformal deposition techniques, such as atomic layer deposition, and / or chemical vapor deposition, and / or plasma enhanced chemical vapor deposition.

[0060] The conformal deposition technique may be a technique configured to deposit a layer largely independent of direction.

[0061] The control gate may be deposited by a directional deposition technique, such as evaporation or sputtering, that is configured to deposit a layer primarily in one direction, e.g., a direction defined by a straight line path between a heated boat of an evaporator and a target area of ​​the evaporator.

[0062] It should be noted that the memory device according to the first aspect, the use of the memory device according to the second aspect, and the method for producing the memory device according to the third aspect may all have the same or similar advantages.

[0063] The above, as well as additional objects, features, and advantages of the inventive concept will become better understood through the following illustrative and non-limiting detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals are used for like elements unless otherwise noted, in which: [Brief description of the drawings]

[0064] [Figure 1] 1 is a cross-sectional view of a memory device. [Diagram 2] 1 is a cross-sectional view of a memory device. [Diagram 3] FIG. 1 illustrates a memory device when viewed in cross-sectional side view. [Figure 4] FIG. 1 illustrates a memory device when viewed in cross-sectional view from above. [Diagram 5] FIG. 2 illustrates a memory device as viewed from above. [Figure 6] FIG. 1 illustrates a flow chart of a method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0065] In conjunction with the accompanying drawings, the technical contents and detailed description of the present invention will be described hereinafter according to preferred embodiments, and will not be used to limit the scope of the claims. The present invention may be embodied in many different forms, and should not be construed as being limited to the embodiments set forth herein, but rather, these embodiments are provided for thoroughness and completeness, to fully convey the scope of the present invention to those skilled in the art.

[0066] 1 and 2 each illustrate a cross-sectional view of a memory device 1. The illustrated memory devices 1 each include a pillar 40 of a semiconductor material. Each of the illustrated pillars 40 has an axial direction. In general, the pillars 40 of the memory device 1 are epitaxially grown on a substrate 90 (not shown in FIGS. 1-2). The pillars 40 then generally have an axial direction that is perpendicular to the substrate 90. In the following, the memory device 1 is described as having the pillars 40 on the substrate 90, and the axial direction of the pillars 40 is perpendicular to the substrate 90. In the coordinate system of the figures associated with this description, the axial direction of the pillars 40 is the Z direction. As a result, the transverse direction to the axial direction of the pillars 40 can be considered as a direction in a plane spanned by the X and Y directions in the coordinate system of the figures associated with this description.

[0067] The pillars 40 may have a diameter smaller than 1 μm, for example, between 5 nm and 500 nm, or between 5 nm and 100 nm, or between 10 nm and 50 nm. The pillars 40 are made of semiconductor materials, such as GaN and AlGaN.

[0068] The memory devices 1 of Figures 1 and 2 each include one single memory cell 50, which includes a charge trap 60 and a transistor 2. In Figure 1, the transistor 2 is an NPN transistor 2', and in Figure 2, the transistor 2 is a PNP transistor 2''.

[0069] As illustrated in Figures 1 and 2, each pillar 40 is doped to form a transistor 2 of a memory cell 50. The transistor 2 includes a source pillar segment 10 followed by a body pillar segment 12 followed by a drain pillar segment 14. Figure 1 illustrates an NPN transistor 2', where the source pillar segment 10 is n-doped, the body pillar segment 12 is p-doped, and the drain pillar segment 14 is n-doped. Figure 2 illustrates a PNP transistor 2'', where the source pillar segment 10 is p-doped, the body pillar segment 12 is n-doped, and the drain pillar segment 14 is p-doped.

[0070] The p-doped body pillar segment 12 of the NPN transistor 2' of FIG. 1 includes multiple semiconductor layers 20 stacked axially of the pillar 40, the layers of the multiple semiconductor layers 20 being made of AlGaN or GaN, and the multiple semiconductor layers 20 being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its mutually opposing neighboring layers.

[0071] Similarly, the p-doped source pillar segment 10 and drain pillar segment 14 of the PNP transistor 2'' of FIG. 2 include multiple semiconductor layers 20 stacked axially of the pillar 40, the layers of the multiple semiconductor layers 20 being made of AlGaN or GaN, and the multiple semiconductor layers 20 being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its mutually opposing neighboring layers.

[0072] A p-doped pillar segment including a plurality of semiconductor layers 20 may include repeating pairs of semiconductor layers, with each pair including a low Al content layer 22 and a high Al content layer 24. Thus, every other layer of the plurality of semiconductor layers 20 may be a low Al content layer 22, with a high Al content layer 24 disposed between the low Al content layers 22. The low Al content layers 22 may have an Al content below 10% and the high Al content layers 24 may have an Al content above 15%. By way of example, the plurality of semiconductor layers 20 may include a sequence of layers, with the even numbered layers being low Al content layers 22 and the odd numbered layers being high Al content layers 24, or vice versa. The low Al content layers 22 may be GaN layers, and the high Al content layers 24 may be AlGaN layers, e.g., Al 0.2 Ga 0.8 N layer or Al 0.4 Ga 0.6 There may be N layers.

[0073] Furthermore, each layer of the plurality of semiconductor layers 20 of the p-doped pillar segment of the transistor 2 may have a thickness between 3 nm and 10 nm.

[0074] 1 and 2 further includes a charge trap 60 configured to store charge and to control the threshold voltage of the transistor 2. The illustrated charge trap 60 is disposed near the body pillar segment 12 of the transistor 2. Thus, the charge in the charge trap 60 affects the threshold voltage of the transistor 2.

[0075] Each memory cell 50 in Figures 1 and 2 further includes a control gate 66 disposed laterally of the pillar 40, the control gate 66 being configured to control the current through the body pillar segment 12 of the transistor 2 depending on the voltage of the control gate 66 relative to the threshold voltage of the transistor 2.

[0076] 1 and 2, charge traps 60 are disposed between a control gate 66 and a body pillar segment 12 of transistor 2 of memory cell 50. Each illustrated charge trap 60 includes a first oxide layer 61, a charge trapping layer 64, and a second oxide layer 62, where first oxide layer 61 separates charge trapping layer 64 from body pillar segment 12 and second oxide layer 62 separates charge trapping layer 64 from control gate 66. Note that FIGS. 1 and 2 are cross-sectional views and that first oxide layer 61, charge trapping layer 64, second oxide layer 62, and control gate 66 may extend around the perimeter of pillar 40.

[0077] The charge trapping layer 64 may include a dielectric layer and / or a conductive layer.

[0078] For example, the charge trapping layer 64 may include a dielectric layer of Si3N4. The charge trapping layer 64 may include a dielectric layer of a high-k dielectric material, such as Y2O3, TiO2, HfO2, ZrO2, or La2O3.

[0079] Alternatively, or additionally, the charge trapping layer 64 may comprise a conductive layer such as a metal or a doped semiconductor material, for example degeneratively doped Si.

[0080] The first oxide layer 61 and / or the second oxide layer 62 may include Al2O3. Alternatively or additionally, other oxides may be used, for example, silicon dioxide.

[0081] A layer sequence that may be advantageously used to form the charge trap 60 and the control gate 66 will now be described. Herein, a 3 nm thick layer of Al2O3 is disposed laterally of the pillar 40, around the periphery of the pillar 40 and near the body pillar segment 12 of the transistor 2 of the memory cell 50, said layer forming the first oxide layer 61. A 10 nm thick layer of HfO2 is disposed on the first oxide layer 61, thereby forming the charge trap layer 64. A 15 nm thick layer of Al2O3 is disposed on the charge trap layer 64, thereby forming the second oxide layer 62. Finally, a 100 nm thick layer of AlCu is disposed on the second oxide layer 62, thereby forming the control gate 66.

[0082] 1 and 2, each pillar 40 has a bottom contact 70 and a top contact 72. Thus, current can be driven through the pillar from the top contact 72, through the source pillar segment 10, through the body pillar segment 12, through the drain pillar segment 14, to the bottom contact 70.

[0083] The memory device 1 may include two or more pillars 40. Furthermore, there may be two or more memory cells 50 associated with each pillar 40 of the memory device 1. FIGS. 3-5 illustrate a memory device 1 including a 4×4 array of pillars 40, with each pillar 40 associated with four memory cells 50 located at four different vertical heights of the pillar. It should be understood that the figures are schematic. There may be five or more memory cells 50 associated with each pillar 40. There may be, for example, 32, 64, or 128 memory cells 50 associated with each pillar 40. The memory cells 50 associated with each pillar 40 may be considered to form a string.

[0084] Figure 5 illustrates a top view of memory device 1. Figure 3 illustrates a cross-sectional side view, the cross section being taken along line A in Figure 5. Figure 4 illustrates a cross-sectional top view, the cross section being taken along line B in Figure 3.

[0085] In FIG. 3, four pillars 40 are seen in cross section, and the pillars may be referred to as a first pillar 41, a second pillar 42, a third pillar 43, and a fourth pillar 44. As illustrated, each pillar 40 is doped NPNPNPNPN from bottom to top, thus forming four NPN transistors 2'. Each NPN transistor 2' is associated with a charge trap 60, which together form part of a memory cell 50 similar to the memory cell 50 described in conjunction with FIG. 1. For memory devices 1 including multiple pillars 40, the pillars 40 may be doped to form PNP transistors 2'' instead of the illustrated NPN transistors 2'.

[0086] In the illustrated example, memory cells 50 at the same vertical height share a common control gate 68. Thus, reading, writing, and erasing can be performed simultaneously on all memory cells 50 that share the common control gate 68 by applying a voltage to said common control gate 68. The common control gate 68 may connect all memory cells 50 of an array of pillars at a particular vertical height, as illustrated in FIG. 4. Alternatively, the common control gate 68 may connect memory cells 50 in the same column of an array of pillars at a particular vertical height. The common control gate 68 may connect all memory cells 50 at the same position in a string.

[0087] 3, the first pillar 41, the second pillar 42, the third pillar 43, and the fourth pillar 44 have separate top contacts 72, but they share a common bottom contact 70. Alternatively, the first pillar 41, the second pillar 42, the third pillar 43, and the fourth pillar 44 may also have separate bottom contacts 70.

[0088] When memory device 1 includes two or more pillars 40, the following terminology may be used.

[0089] The top contacts 72 may be referred to as bitlines. Additionally, there may be several levels of bitlines. As illustrated in FIG. 3, the top contacts 72 may be considered first level bitlines 72. The first level bitlines 72 may be electrically connected to second level bitlines 76 via vertical connectors 96. The second level bitlines 76 are disposed above the first level bitlines 72.

[0090] The common control gate 68 may be referred to as a word line. Furthermore, there may be several levels of word lines. As illustrated in FIG. 3, the common control gate 68 may be electrically connected to a first level word line 73 via a vertical connector 96. The first level word line 73 may be electrically connected to a second level word line 74 via a vertical connector 96. The second level word line 74 is disposed above the first level word line 73.

[0091] The common bottom contact 70 may be referred to as a common source line.

[0092] According to the above, whenever this document refers to a top contact 72, it may be interpreted as a bit line, whenever this document refers to a common control gate 68, it may be interpreted as a word line, and whenever this document refers to a common bottom contact 70, it may be interpreted as a common source line.

[0093] The common control gate 68, also known as the word line, may include a metal, for example, an alloy of a Ni / Al / NiV stack, i.e., a Ni, Al, NiV layer structure. The bottom contact 70, also known as the common source line, may include a metal, for example, an alloy of a Ni / Al / NiV stack, i.e., a Ni, Al, NiV layer structure. The top contact 72, also known as the first level bit line 72 and the second level bit line 76, may include a metal, for example, AlCu. The first level word line 73 and the second level word line 74 may include a metal, for example, AlCu. The vertical connector 96 may include a metal, for example, TiN.

[0094] 3, pillars 40 may be disposed on a base layer 92, which is disposed on a substrate 90. Substrate 90 may be a silicon substrate. Base layer 92 may include an AlN layer on substrate 90, followed by an AlGaN or GaN layer. The AlN layer on substrate 90 may be sputtered AlN. The AlN layer may be patterned, e.g., corrugated. The AlN layer may thus mitigate dislocation formation in subsequent layers.

[0095] 3, the pillars 40 may be embedded in one or more buried layers 94. The buried layers 94 may be high frequency deposited plasma enhanced chemical vapor deposition oxide (HDPOX), or low frequency deposited plasma enhanced chemical vapor deposition oxide (LDPOX), or PSG, or any combination thereof.

[0096] In the following, a method 100 for producing the memory device 1 is described. Figure 6 illustrates a flow chart of the method 100. It should be understood that the steps of the method 100 do not necessarily have to be performed in the order illustrated.

[0097] According to the method 100, a semiconductor layer is deposited S102 on a substrate 90. For example, AlN may be sputtered on the silicon substrate 90. Subsequent layers may then be epitaxially grown, for example, by metalorganic vapor phase epitaxy. After the AlN layer, one or more AlGaN layers may be grown. The Al content may be gradually reduced to zero until pure GaN is achieved. The layers from the AlN layer to the pure GaN may be considered as a base layer 92. On top of the base layer 92, a sequence of layers with alternating doping may be grown, for example, NPNPNPNPN from bottom to top to produce the memory device 1 of FIG. 3. The n-doped layer may be, for example, GaN to produce the memory device 1 of FIG. 3. One or more of the p-doped layers include a plurality of semiconductor layers 20, the layers of which are made of AlGaN or GaN, and the plurality of semiconductor layers 20 are configured such that the aluminum content varies between each successive layer, such that every other layer has a lower aluminum content than its neighboring mutually opposite layers. For example, to produce the memory device 1 of FIG. 3, each p-doped layer may include multiple layers 20 as follows: Al 0.2 Ga 0.8 N / GaN / Al 0.2 Ga 0.8 N / GaN / Al 0.2 Ga 0.8 N / GaN / Al 0.2 Ga 0.8 N

[0098] According to the method 100 , the deposited S102 layers form a semiconductor structure that is then etched S104 to form one or more pillars 40 .

[0099] Prior to etching S104, the lateral size and position of pillars 40 may optionally be lithographically defined by imprint lithography. Thus, the top surface of the semiconductor structure may be coated with a polymer film and a stamp may selectively remove portions of the polymer film to expose the semiconductor structure, which may then be etched S104.

[0100] If the semiconductor layers of the semiconductor structure are doped during epitaxial growth, as explained above, the pillars 40 formed by etching S104 now form pillar segments of alternating doping. If the control gate 66 is placed near a p-doped pillar segment, an NPN transistor 2' may be formed S106. Similarly, if the control gate 66 is placed near an n-doped pillar segment, a PNP transistor 2'' may be formed S106. As an alternative to doping during epitaxial growth, the pillars 40 may be doped after epitaxial growth.

[0101] According to method 100, charge traps 60 are formed S108 that are configured to store charge and, through the stored charge, to control the threshold voltage of transistor 2. This may be done by depositing a first oxide layer 61, followed by a charge trapping layer 64, followed by a second oxide layer 62, on the sides of pillar 40. The layers may be deposited by one or more conformal deposition techniques, such as atomic layer deposition, and / or chemical vapor deposition, and / or plasma enhanced chemical vapor deposition.

[0102] The first oxide layer 61 and the second oxide layer 62 may be Al2O3. The charge trapping layer 64 may be, for example, Y2O3, TiO2, HfO2, ZrO2, La2O3, a metal or a doped semiconductor material.

[0103] After conformally coating the pillars 40 with the first oxide layer 61, the charge trapping layer 64, and the second oxide layer 62, a control gate 66, e.g., a common control gate 68, may be formed. A buried layer 94 may be deposited down to the bottom body pillar segment 12. The common control gate 68 may then be formed by depositing a metal by a directional deposition technique, such as evaporation or sputtering S110. The metal may be deposited in a direction along the axial direction of the pillars 40. The metal may form a layer normally along the axial direction of the pillars 40.

[0104] In the above, the inventive concept has been primarily described with reference to a limited number of examples. However, as will be readily appreciated by those skilled in the art, examples other than those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device (1) comprising a pillar (40) of semiconductor material and at least one memory cell (50) associated with said pillar (40), each of said at least one memory cell (50) comprising a charge trap (60) and a transistor (2), and for each of said at least one memory cell (50): the charge trap (60) of the memory cell (50) is configured to store a charge and to control a threshold voltage of the transistor (2) of the memory cell (50) by the stored charge; The transistor (2) of the memory cell (50) includes a source, a body, and a drain, the source, body, and drain being respective pillar segments along an axial direction of the pillar (40), a source pillar segment (10) and a drain pillar segment (14) being separated by a body pillar segment (12), and the transistor (2) is an NPN transistor (2'), in which the source pillar segment (10) is n-doped, the body pillar segment (12) is p-doped and the drain pillar segment (14) is n-doped, or - a PNP transistor (2''), in which the source pillar segment (10) is p-doped, the body pillar segment (12) is n-doped, and the drain pillar segment (14) is p-doped; 1. A memory device (1), wherein at least one p-doped pillar segment (10, 12, 14) of the transistor (2) comprises a plurality of semiconductor layers (20) stacked in the axial direction of the pillar (40), the layers of the plurality of semiconductor layers (20) being made of AlGaN or GaN, the plurality of semiconductor layers (20) being configured such that an aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its mutually opposing neighboring layers.

2. For each of the at least one memory cell (50), The memory cell (50) includes a control gate (66) disposed laterally of the pillar (40), the control gate (66) configured to control a current through the body pillar segment (12) of the transistor (2) depending on a voltage of the control gate (66) relative to the threshold voltage of the transistor (2); 2. The memory device of claim 1, wherein the charge trap (60) of the memory cell (50) is disposed between the control gate (66) and the body pillar segment (12) of the transistor (2) of the memory cell (50), the charge trap (60) comprising a first oxide layer (61), a charge trapping layer (64), and a second oxide layer (62), the first oxide layer (61) separating the charge trapping layer (64) from the body pillar segment (12), the second oxide layer (62) separating the charge trapping layer (64) from the control gate (66), and the charge trapping layer (64) comprising a dielectric layer and / or a conductive layer.

3. For each of the at least one memory cell, the charge trapping layer of the charge trap of the memory cell is ２ O ３ , TiO ２ , HfO ２ , ZrO ２ , or La ２ O ３ The memory device (1) of claim 2, comprising a high-k dielectric material such as

4. For each of the at least one memory cell (50), the first oxide layer (61) and / or the second oxide layer (62) of the charge trap (60) of the memory cell (50) is made of Al ２ O ３ A memory device (1) according to claim 2 or 3, comprising:

5. For each of the at least one memory cell (50), the transistor (2) of the memory cell (50) includes a repeating pair of semiconductor layers, each pair of semiconductor layers having: a low Al content layer (22) having an Al content below 10%, and A memory device (1) according to any one of the preceding claims, comprising a high Al content layer (24) having an Al content above 15%.

6. The memory device (1) of any one of claims 1 to 5, wherein for each of the at least one memory cell (50), each layer of the plurality of semiconductor layers (20) of the at least one p-doped pillar segment (10, 12, 14) of the transistor (2) has a thickness of 3 nm to 10 nm.

7. 7. The memory device (1) of claim 1, comprising a first pillar (41) and a second pillar (42), each of the first pillar (41) and the second pillar (42) having at least one memory cell (50) associated with the pillar (41, 42), the memory cell (50) of the first pillar (41) and the memory cell (50) of the second pillar (42) sharing a common control gate (68), the common control gate (68) being configured to simultaneously control a current through the body pillar segment (12) of the transistor (2) of the memory cell (50) of the first pillar (41) and a current through the body pillar segment (12) of the transistor (2) of the memory cell (50) of the second pillar (42) by a voltage of the common control gate (68).

8. Use of a memory device (1) according to any one of claims 1 to 7 for analog-to-digital conversion, wherein conversion rules for said analog-to-digital conversion are stored in said memory device (1).

9. A method (100) for producing a memory device (1), comprising: Depositing (S102) semiconductor layers on a substrate (90), the semiconductor layers being stacked in a stacking direction such that a semiconductor structure is formed from the deposited semiconductor layers; Etching (S104) the semiconductor structure to form pillars (40), the pillars (40) having an axial direction in the stacking direction; forming (S106) a transistor (2) in the pillar (40), the transistor (2) including a source, a body, and a drain, the source, body, and drain being respective pillar segments (10, 12, 14) along the axial direction of the pillar (40), the source pillar segment (10) and the drain pillar segment (14) being separated by a body pillar segment (12); the transistor (2) being: an NPN transistor (2'), in which the source pillar segment (10) is n-doped, the body pillar segment (12) is p-doped and the drain pillar segment (14) is n-doped, or - a PNP transistor (2''), in which the source pillar segment (10) is p-doped, the body pillar segment (12) is n-doped, and the drain pillar segment (14) is p-doped; forming (S106), at least one p-doped pillar segment (10, 12, 14) of the transistor (2) comprising a plurality of semiconductor layers (20) of the deposited semiconductor layers stacked in the axial direction of the pillar (40), the layers of the plurality of semiconductor layers (20) of the p-doped pillar segment (10, 12, 14) being made of AlGaN or GaN, the plurality of semiconductor layers (20) of the p-doped pillar segment (10, 12, 14) being configured such that an aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its mutually opposing neighboring layers; forming (S108) a charge trap (60) configured to store charge and to control a threshold voltage of the transistor (2) by the stored charge; The method (100), wherein the transistor (2) and the charge trap (60) are part of a memory cell (50) of the memory device (1).

10. The method (100) of claim 9, further comprising lithographically defining (S103) the lateral size and position of the pillars (40) by imprint lithography.

11. The charge trap (60) is formed (S108) by depositing a first oxide layer (61), a charge trapping layer (64), a second oxide layer (62), and a control gate (66) laterally of the pillar (40); the first oxide layer (61) separates the charge trapping layer (64) from the body pillar segment (12), and the second oxide layer (62) separates the charge trapping layer (64) from the control gate (66); The charge trapping layer (64) includes a dielectric layer and / or a conductive layer; 11. The method (100) of claim 9 or 10, wherein the control gate (66) is configured to control a current through the body pillar segment (12) of the transistor (2) depending on a voltage of the control gate (66) relative to the threshold voltage of the transistor (2).

12. The method (100) includes etching (S104) the semiconductor structure to form a first pillar (41) and a second pillar (42), each of the first pillar (41) and the second pillar (42) having at least one memory cell (50) associated with the pillar (41, 42), and the method (100) further comprises:

12. The method of claim 11, further comprising forming (S110) a common control gate (68), the common control gate (68) being shared by a memory cell (50) of the first pillar (41) and a memory cell (50) of the second pillar (42), the common control gate (68) being configured to simultaneously control a current through the body pillar segment (12) of the transistor (2) of the memory cell (50) of the first pillar (41) and a current through the body pillar segment (12) of the transistor (2) of the memory cell (50) of the second pillar (42) by a voltage of the common control gate (68), the common control gate (68) being formed after etching (S104) the semiconductor structure to form the first pillar (41) and the second pillar (42).

13. 13. The method (100) according to claim 11 or 12, wherein the first oxide layer (61), the charge trapping layer (64) and the second oxide layer (62) are deposited by one or more conformal deposition techniques, such as atomic layer deposition, and / or chemical vapor deposition, and / or plasma enhanced chemical vapor deposition.

14. The method (100) of any one of claims 11 to 13, wherein the control gate (66) is deposited by a directional deposition technique, such as evaporation or sputtering.

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