Allocation of Peripheral Component Interface Express (PCIe) Streams in a Configurable Multiport PCIe Controller

Abstract

A method for allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller includes the PCIe controller detecting a link with a first PCIe device and allocating a first one or more PCIe streams from a pool of PCIe streams for the link between the PCIe controller and the first PCIe device.

Description

[Background technology]

[0001] Peripheral Component Interface Express (PCIe) devices with Integrity and Data Encryption (IDE) capabilities use an IDE stream for encrypted communication with the controller. An IDE stream is a logical encrypted connection between two PCIe ports. PCIe controllers are typically limited in the number of streams that can be supported across all connected devices. For example, a PCIe controller implements a predefined pool of streams that are allocated (assigned) to connected devices. [Brief description of the drawings]

[0002] [Figure 1A] FIG. 1 is a block diagram of an example Peripheral Component Interface Express (PCIe) controller for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller in accordance with some embodiments. [Figure 1B] FIG. 1 is a block diagram of an example Peripheral Component Interface Express (PCIe) controller for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller in accordance with some embodiments. [Figure 1C] FIG. 1 is a block diagram of an example Peripheral Component Interface Express (PCIe) controller for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller in accordance with some embodiments. [Diagram 2]1 is an exemplary computer for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, according to some embodiments. [Diagram 3] 1 is a flowchart of an example method for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, according to some embodiments. [Figure 4] 4 is a flowchart of another example method for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, according to some embodiments. [Diagram 5] 4 is a flowchart of another example method for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] Peripheral Component Interface Express (PCIe) devices with integrity and data encryption (IDE) capabilities use an IDE stream for encrypted communication with a controller. An IDE stream is a logical encrypted connection between two PCIe ports, such as a controller and a peripheral device. PCIe controllers are typically limited in the number of streams that can be supported across all connected devices. For example, a PCIe controller implements a predefined pool of streams that are allocated to connected devices.

[0004] To that end, this specification specifies various embodiments for allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller. In some embodiments, a method for allocating (assigning) PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller includes detecting, by the PCIe controller, a link by a first PCIe device. The method also includes allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device.

[0005] In some embodiments, allocating the one or more PCIe streams includes receiving data from the first PCIe device indicating a number of requested streams for the first PCIe device and a number of PCIe lanes used by the first PCIe device, where the one or more PCIe streams are allocated based on the number of requested streams and the number of PCI lanes. In some embodiments, the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device. In some embodiments, the method further includes detecting, by the PCIe controller, another link by a second PCIe device and allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device. In some embodiments, allocating the second one or more PCIe streams includes reallocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. In some embodiments, the method further includes detecting removal of the first PCIe device and releasing the first one or more PCIe streams. In some embodiments, the method further includes reallocating one or more of the first one or more PCIe streams to one or more other PCIe devices.

[0006] This specification also describes various embodiments of a multi-port PCI controller that performs steps including detecting a link by a first PCIe device, the steps also including allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device.

[0007] In some embodiments, allocating the one or more PCIe streams includes receiving data from the first PCIe device indicating a number of requested streams for the first PCIe device and a number of PCIe lanes used by the first PCIe device, where the one or more PCIe streams are allocated based on the number of requested streams and the number of PCI lanes. In some embodiments, the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device. In some embodiments, this step further includes detecting, by the PCIe controller, another link by a second PCIe device and allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device. In some embodiments, allocating the second one or more PCIe streams includes reallocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. In some embodiments, the steps further include detecting removal of the first PCIe device and releasing the first one or more PCIe streams. In some embodiments, the steps further include reallocating one or more of the first one or more PCIe streams to one or more other PCIe devices.

[0008] Also described herein are various embodiments of an apparatus for allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, the apparatus including a processor and a PCIe controller operably coupled to the processor, the PCIe controller configured to perform steps including detecting a link by a first PCIe device, the steps also including allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device.

[0009] In some embodiments, allocating the one or more PCIe streams includes receiving data from the first PCIe device indicating a number of requested streams for the first PCIe device and a number of PCIe lanes used by the first PCIe device, where the one or more PCIe streams are allocated based on the number of requested streams and the number of PCI lanes. In some embodiments, the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device. In some embodiments, this step further includes detecting, by the PCIe controller, another link by a second PCIe device and allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device. In some embodiments, allocating the second one or more PCIe streams includes reallocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. In some embodiments, this step further includes detecting removal of the first PCIe device and releasing the first one or more PCIe streams.

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "back," "front," "top," "bottom," and the like are used herein to facilitate descriptions that describe the relationship of one element or feature to another element or feature, as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "back" are used herein to more easily identify various components and to identify those components as being on opposite sides of another component, for example. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures.

[0011] FIG. 1A is a block diagram of a non-limiting exemplary Peripheral Component Interface Express (PCIe) controller 100. The exemplary PCIe controller 100 can be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. In addition to the description set forth with respect to FIGS. 1A-1C, the functionality of the PCIe Express controller 100 is described in further detail in the manner described in FIGS. 3-5. The PCIe controller 100 allows PCIe compatible devices and components to be coupled and integrated into a device or system. As an example, the PCIe controller 100 allows peripheral components that use PCIe to be added to a computer or other device.

[0012] The PCIe controller 100 includes all of the hardware logic necessary to implement the transaction layer and data link layer of the PCIe specification for a single PCIe port. A PCIe port is used to send and receive data at one end of a PCIe link. In this example, the PCIe controller 100 is a multi-port PCIe controller 100. The multi-port PCIe controller 100 is an embodiment of a controller that supports multiple PCIe ports. In some embodiments, a multi-port controller is more efficient than multiple single-port controllers by sharing some logic between ports. Additionally, in some embodiments, it is more efficient to support various link subdivision modes where a fixed number of PHY lanes (described in more detail below) are mapped to different possible port configurations (e.g., 16 lanes are used as either a single x 16 port or 2 x 8 ports). In some embodiments, the multi-port controller can split a shared receive buffer to handle the bandwidth of a single 16 lane port or two 8 lane ports, whereas this is not possible with two single-port controllers.

[0013] The PCIe controller 100 includes one or more sockets 102. The one or more sockets 102 are physical interfaces for coupling or linking one or more PCIe devices to the PCIe controller 100. As shown in Figure 1A, a single device 104 (e.g., a PCIe compatible device) is coupled to the PCIe controller 100 via the socket 102. The device 104 may include any PCIe compatible device, such as a peripheral component of a computer, a parallel accelerator such as a graphics processing unit (GPU), or other device as may be appreciated.

[0014] The device 104 is coupled to the socket 102 using one or more lanes 106. A lane 106 is a physical, conductive connection between two endpoints, in this case the socket 102 and the device 104. When used in PCIe, a lane 106 includes two pairs of conductive wires or traces, one used to transmit data and one used to receive data. A PCIe compatible device 104 is described or characterized using the number of lanes 106 used to connect the device 104. For example, a x4 device 104 (e.g., a "by-four" device 104) connects to the PCIe controller 100 using four lanes 106. Thus, such a device 104 requires at least four available lanes 106 in the socket 102 to connect.

[0015] In some embodiments, a socket 102 has a number of available lanes 106 (e.g., connection points of lanes 106). Thus, the socket 102 can support connection by a number of devices 104 where the combined number of lanes 106 used is equal to or less than the number of lanes 106 provided by the socket 102. As an example, a 16-lane 106 socket 102 can support a single device 104 with up to 16 lanes 106, or multiple devices (e.g., an 8-unit device 104 and two 4-unit devices 104) with a total of 16 lanes 106.

[0016] To perform encrypted communications between the PCIe controller 100 and the devices 104, the PCIe controller 100 establishes one or more “streams” between the PCIe controller 100 and the devices 104. As described herein, a “stream” is a logically defined, encrypted communication path or session between the PCIe controller 100 and the devices 104. In some embodiments, a “stream” includes a PCIe Integrity and Data Encryption (IDE) stream that uses the IDE functionality of PCIe to maintain a logically encrypted path. To establish a stream, the PCIe controller 100 maintains stream configuration data 110 in the memory 108. Each portion of the stream configuration data 110 includes necessary data to be provided to the devices 104 to establish a single stream with the devices 104. As an example, the stream configuration data 110 includes one or more keys (e.g., encryption keys, decryption keys, etc.) used to encrypt or decrypt communications between the devices 104 and the PCIe controller 100. For example, a portion of the stream configuration data 110 includes a string that defines multiple keys, where each key corresponds to a substring of the string. As another example, the stream configuration data 110 includes an initialization vector for initiating an encrypted communication session between the device 104 and the PCIe controller 100.

[0017] The PCIe controller 100 maintains a certain amount of stream configuration data 110. In other words, since each portion of the stream configuration data 110 corresponds to a particular stream, the PCIe controller 100 maintains a collection or "pool" of streams that are allocated to the devices 104 that interface with the PCIe controller 100. If the device 104 can support a stream to the PCI controller 100 (e.g., if the device 104 can perform encrypted communication to the PCIe controller 100), the PCIe controller 100 allocates one or more streams to the device 104. Those skilled in the art will appreciate that in some embodiments, the device 104 can simultaneously maintain multiple streams to the PCIe controller 100. To allocate streams to the device 104, the PCIe controller 100 provides, for each stream allocated to the device 104, a portion of the stream configuration data 110 that corresponds to the allocated stream. The device 104 then performs the necessary configuration operations to use the stream configuration data 110 for each allocated stream.

[0018] In some embodiments, allocating the streams to the device 104 includes receiving data from the device 104 indicative of the number of streams requested by the device 104. For example, in some embodiments, the device 104 stores data in the configuration space 112 indicative of various operational parameters of the device 104. Such parameters may include, for example, a unique identifier for the device 104, an identified protocol or version (e.g., PCIe version) supported by the device 104, the number of lanes 106 used by the device 104, the maximum number of streams supported by the device 104, the number of streams requested by the device 104 when connected, and other parameters as may be appreciated.

[0019] Thus, upon connection of the device 104 to the socket 102, the device 104 provides data indicating the number of streams requested by the device 104. In some embodiments, the number of streams requested by the device 104 is equal to the maximum number of streams supported by the device 104. In this case, the PCIe controller 100 allocates a number of streams from the pool of available streams that is less than or equal to the indicated number of requested streams and provides the device with the corresponding portion of the stream configuration data 110. Because the number of available streams on the PCIe controller 100 is fixed and finite, the PCIe controller 100 is prevented from having an excessive number of streams unnecessarily allocated to the device 104 that the device 104 cannot use.

[0020] In some embodiments, the number of streams allocated to the device 104 is proportional to or based on the number of lanes 106 used by the device 104. In some embodiments, the number of streams allocated to the device 104 is proportional to the number of lanes 106 used by the device 104 relative to the number of lanes 106 provided by the PCIe controller 100. As an example, assume that the PCIe controller 100 has 16 lanes 106 available via the socket 102. Assuming that the PCIe controller 100 has 64 streams in its pool of streams, this means that the PCIe controller 100 can support up to 64 simultaneous streams. Furthermore, assuming that no streams are currently being allocated, this means that all 64 streams are available for allocation. When a 16-unit device 104 (e.g., a 16-lane 106 device 104) is linked with the PCIe controller 100, in some embodiments the device 104 is allocated all 64 streams when the device 104 uses all possible lanes 106. As another example, if an 8-unit device 104 is attached, then when the device 104 uses half of the supported lanes 106, 32 streams are allocated (eg, half the pool of streams).

[0021] Those skilled in the art will appreciate that if the device 104 supports a certain maximum number of streams known to the PCIe controller 100, then in some embodiments the number of streams allocated will be limited by the maximum number of supported streams. Continuing with the above example, assume a 16-unit device 104 with a maximum number of supported streams of 32 is coupled to the PCIe controller 100. Instead of allocating to the device 104 all 64 streams proportional to the number of lanes 106 used, the device 104 is instead allocated the maximum 32 supported streams. As a further example, if an 8-unit device 104 with a maximum of 16 streams is coupled to the PCI controller 100, then instead of the proportional 32 streams, the maximum 16 streams will be allocated.

[0022] In some embodiments, the number of streams allocated to a device 104 is proportional to or based on the number of lanes 106 used by the device 104 relative to other devices 104 coupled to the PCI controller 100. For example, assume an 8-unit device 104 is coupled to a PCIe controller 100 that supports 16 lanes 106 and has a pool of 64 streams. Since all 8 lanes 106 of the PCIe controller 100 being used are being used by the device 104, the 8-unit device 104 is allocated all 64 streams. If the 8-unit device 104 is coupled to the PCIe controller 100 along with two 4-unit devices 104, the 8-unit device 104 (using half the lanes 106) is allocated 32 streams (half the streams), while each of the 4-unit devices 104 (each using a quarter of the lanes 106) is allocated 16 streams (a quarter of the streams each).

[0023] In some embodiments, when the pool of streams is stored in an ordered or structured manner, the streams allocated to the devices 104 are allocated, at least in part, as contiguous portions of the pool of streams. For example, in some embodiments, the streams are preferentially allocated as contiguous portions of the pool of streams.

[0024] The PCIe controller 100 can dynamically allocate and reallocate streams as additional devices are coupled to or removed from the PCIe controller 100. Moving to the example of Figure 1B, after coupling device 104 and allocating a portion of the pool of streams to devices 104, 114, and 124, each with their respective configuration spaces 122 and 132, are coupled to the PCIe controller 100. In this example, assume that the PCIe controller 100 supports 16 lanes 106 and has a pool of 64 streams, with device 104 using 8 lanes 106 (e.g., an 8-unit device 104) and devices 114, 124 using 4 lanes 106 each.

[0025] In response to detecting the connection of devices 114, 124, the PCIe controller 100 allocates a portion of the pool of streams to each device 114, 124. For example, device 104 may be allocated 32 of the 64 streams as a proportionate share relative to the number (e.g., half) of lanes 106 used by device 104. In some embodiments, devices 114 and 124 are each allocated 16 of the remaining 32 streams in proportion to their respective use of four lanes 106.

[0026] As another example, suppose device 104 has been allocated all 64 available streams (e.g., by being the only device coupled to PCIe controller 100 at the time of allocation). In such an example, some of the streams allocated to device 104 must be reallocated to devices 114, 124. In other words, some of the streams allocated to device 104 are released to be available for reallocation to devices 114, 124.

[0027] In some embodiments, the reallocation of the streams allocated to the device 104 includes logically severing the connection to the device 104. For example, all existing communication sessions between the device 104 and the PCIe controller 100 are terminated. In some embodiments, the device 104 is reset or restarted to reinitialize the stream allocation process. In other embodiments, the device 104 is provided with a command or signal to terminate use of one or more streams, or potentially all streams, until a new allocation of streams is provided. The PCIe controller 100 then allocates the streams to each device 114, 124. For example, in some embodiments, the PCIe controller 100 provides the devices 114, 124 with stream configuration data 110 corresponding to the allocated streams. In embodiments where the connection to the device 104 is resumed, requiring a new allocation of streams to the device 104, the PCIe controller 100 provides the stream configuration data 110 corresponding to the new allocation of streams. In other words, in some embodiments, a portion of the stream allocated to device 104 remains allocated while another portion of the stream is reallocated to devices 114, 124, while in other embodiments, all of the stream allocated to device 104 is effectively released (e.g., due to a resumed link or a restart of device 104) and a new allocation of streams to devices 104, 114, 124 is performed.

[0028] When devices are removed from the PCIe controller 100, their respective allocated streams are released. Such released streams are then either reallocated to other devices or remain unallocated for use if another device is attached. Continuing with the example of FIG. 1B, moving to FIG. 1C, assume that device 124 is disconnected from the PCIe controller 100. Assume further that prior to the removal of device 124, device 104 was allocated 32 streams and devices 114, 124 were each allocated 16 streams. In some embodiments, after the removal of device 124, the 16 streams allocated to device 124 are effectively returned to the pool of available streams such that any of these streams may be available for future allocation to another device. In some embodiments, one or more of these streams previously allocated to device 124 are reallocated to device 104 or device 124.

[0029] Those skilled in the art will appreciate that the techniques described herein allow for dynamic allocation of streams to PCIe devices to a PCIe controller. Such dynamic allocation allows for devices to be added and removed during operation and for streams to be allocated accordingly. Thus, when a device is added, streams are allocated from the pool of available streams, reallocated from streams already allocated to attached devices, or a combination thereof. When a device is removed, those allocated streams are freed. The freed streams are added back to the pool of streams for later use, reallocated to devices still connected, or both.

[0030] In some embodiments, the PCIe controller 100 of FIG. 1 is implemented in a computer 200. The computer 200 includes at least one processor 202. In addition to the at least one processor 202, the computer 200 of FIG. 2 includes random access memory (RAM) 204 that is connected to the processor 202 and to other components of the computer 200 via a high speed memory bus 206 and a bus adapter 208. The RAM 204 stores an operating system 210. Although the operating system 210 in the example of FIG. 2 is shown in RAM 204, many components of such software are typically also stored in non-volatile memory, such as on data storage 212, e.g., a disk drive.

[0031] 2 includes a disk drive adapter 216 coupled to processor 202 and other components of computer 200 via expansion bus 218 and bus adapter 208. Disk drive adapter 216 connects non-volatile data storage to computer 200 in the form of data storage 212. Such disk drive adapters include Integrated Drive Electronics ("IDE") adapters, Small Computer System Interface ("SCSI") adapters, and other adapters as would occur to one of ordinary skill in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, an electrically erasable programmable read-only memory (also known as "EEPROM" or "flash" memory), a RAM drive, or the like, as would occur to one of ordinary skill in the art.

[0032] The example computer 200 of Figure 2 includes one or more input / output ("I / O") adapters 220. I / O adapters provide user-oriented input / output through software drivers and computer hardware for controlling output to a display device, such as a computer display screen, and user input from user input devices 222, such as a keyboard and mouse. The example computer 200 of Figure 2 includes a video adapter 224, which is an example of an I / O adapter specifically designed for graphics output to a display device 226, such as a display screen or computer monitor. The video adapter 224 is connected to the processor 202 via a high-speed video bus 228, the bus adapter 208, and a frontside bus 230, which is also a high-speed bus.

[0033] The example computer 200 of Figure 2 includes a communications adapter 232 for data communications with other computers and with a data communications network. Such data communications may occur serially, through an RS-232 connection, through an external bus such as a Universal Serial Bus ("USB"), through a data communications network such as an IP data communications network, and / or in any other manner as would occur to one skilled in the art. The communications adapter 232 provides the hardware level of data communications at which one computer sends data communications directly to another computer or over a data communications network. Such communications adapters 232 include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0034] The techniques described for allocating Peripheral Component Interface Express (PCIe) streams in a configurable multi-port PCIe controller with respect to FIGS. 1A-1C are also described as methods in the flowcharts of FIGS. 3-5. Accordingly, for further explanation, FIG. 3 sets forth a flowchart illustrating an exemplary method for allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller. The method of FIG. 3 is implemented, for example, in a PCIe controller 100. The method of FIG. 3 includes detecting 302 a link by a first PCIe device 104. In some embodiments, detecting 302 a link includes receiving an indication of a link from a backplane component to which the PCIe controller 100 is operably coupled. In some embodiments, the PCIe controller 100 receives the indication of a link from a Basic Input / Output System (BIOS). As an example, the PCIe controller 100 receives the indication from the BIOS during system startup where the device 104 is coupled to the PCIe controller 100 at startup. In other embodiments, the PCIe controller 100 detects a link by the first PCIe device 104 in response to the first PCIe device 104 being coupled to the PCIe controller 100 (e.g., via the socket 102) while the device including the PCIe controller 100 is active.

[0035] The method of FIG. 3 also includes allocating 304 a first one or more PCIe streams (e.g., to the first PCIe device 104) from the pool of PCIe streams. As specified above, a “stream” is a logically defined, encrypted communication path or session between the PCIe controller 100 and the device 104. The PCIe controller 100 maintains stream configuration data 110 in memory 108 (e.g., read-only memory (ROM) or some other type of memory) that embodies the “pool” of streams available for use by the PCIe controller 100. Each portion of the stream configuration data 110 includes necessary data to be provided to the device 104 to establish a single stream with the device 104. As an example, the stream configuration data 110 includes one or more keys (e.g., encryption key, decryption key, etc.) used to encrypt or decrypt communications between the device 104 and the PCIe controller 100. For example, a portion of the stream configuration data 110 includes a string that defines multiple keys, where each key corresponds to a substring of the string. As another example, the stream configuration data 110 includes an initialization vector for initiating an encrypted communication session between the device 104 and the PCIe controller 100.

[0036] The PCIe controller 100 maintains a certain amount of stream configuration data 110. In other words, because each portion of the stream configuration data 110 corresponds to a particular stream, the PCIe controller 100 maintains a collection or "pool" of streams available for allocation to devices 104 that interface with the PCIe controller 100. If the device 104 can support a stream to the PCI controller 100 (e.g., if the device 104 can perform encrypted communications to the PCIe controller 100), the PCIe controller 100 allocates one or more streams to the device 104. A stream allocated to a particular device 104 is then effectively "removed" from the pool of streams in that it cannot be allocated to another device 104 while it is allocated to the particular device 104. Those skilled in the art will appreciate that in some embodiments, the device 104 can simultaneously maintain multiple streams to the PCIe controller 100. To allocate streams to the devices 104, the PCIe controller 100 provides, for each stream allocated to the device 104, a portion of the stream configuration data 110 that corresponds to the allocated stream. The device 104 then performs the necessary configuration operations to use the stream configuration data 110 for each allocated stream.

[0037] In some embodiments, the number of streams allocated to the device 104 is proportional to or based on the number of lanes 106 used by the device 104. In some embodiments, the number of streams allocated to the device 104 is proportional to the number of lanes 106 used by the device 104 relative to the number of lanes 106 provided by the PCIe controller 100. As an example, assume that the PCIe controller 100 has 16 lanes 106 available via the socket 102. If the PCIe controller 100 has 128 streams in its pool of streams, this means that the PCIe controller 100 can support up to 128 simultaneous streams. Furthermore, if no streams are currently being allocated, this means that all 128 streams are available for allocation. When a 16-unit device 104 (e.g., a 16-lane 106 device 104) is linked with the PCIe controller 100, in some embodiments the device 104 is allocated all 128 streams when the device 104 uses all possible lanes 106. As another example, if an 8-unit device 104 is attached, then when the device 104 uses half of the supported lanes 106, 64 streams are allocated (eg, half the pool of streams).

[0038] Those skilled in the art will appreciate that if the device 104 supports a certain maximum number of streams known to the PCIe controller 100, then in some embodiments the number of streams allocated will be limited by the maximum number of streams supported. Continuing with the above example, assume a 16-unit device 104 with a maximum number of supported streams of 32 is coupled to the PCIe controller 100. Instead of allocating to the device 104 all 128 streams proportional to the number of lanes 106 used, the device 104 is instead allocated the maximum 32 streams supported. As a further example, if an 8-unit device 104 with a maximum of 16 streams is coupled to the PCI controller 100, then the maximum 16 streams will be allocated instead of the proportional 64 streams.

[0039] In some embodiments, the number of streams allocated to a device 104 is proportional to or based on the number of lanes 106 used by the device 104 relative to other devices 104 coupled to the PCI controller 100. For example, assume an 8-unit device 104 is coupled to a PCIe controller 100 that supports 16 lanes 106 and has a pool of 128 streams. Since all 8 lanes 106 of the PCIe controller 100 are being used by the device 104, the 8-unit device 104 is allocated all 128 streams. If the 8-unit device 104 is coupled to the PCIe controller 100 along with two 4-unit devices 104, the 8-unit device 104 (using half the lanes 106) is allocated 64 streams (half the streams), while each of the 4-unit devices 104 (each using a quarter of the lanes 106) is allocated 32 streams (each a quarter of the streams).

[0040] As another example, assume that an 8-unit device 104 is initially the only device coupled to the PCIe controller 100, thereby allocating all 128 streams. Furthermore, assume that two 4-unit devices 104 are subsequently connected. In some embodiments, in response to connecting the two 4-unit devices 104, the 64 streams allocated to the 8-unit device 104 are released and then reallocated to the two 4-unit devices 104. Thus, the proportional distribution of streams is maintained through the reallocation of previously allocated streams.

[0041] In some embodiments, allocating 304 the first one or more PCIe streams includes receiving 306 data from the first PCIe device 104 indicating a requested number of streams for the first PCIe device 104 and a number of PCIe lanes 106 used by the first PCIe device 104. For example, in some embodiments, the device 104 stores data in the configuration space 112 indicating various operational parameters including, for example, a unique identifier of the device 104, an identified protocol or version (e.g., PCIe version) supported by the device 104, the number of lanes 106 used by the device 104, a maximum number of streams supported by the device 104, the number of streams requested at the connection, and other parameters as may be appreciated.

[0042] Thus, in response to a device 104 being connected to a socket 102, the device 104 provides data to the PCIe controller 100 indicating the requested number of streams supported by the device 104 and the number of lanes 106 used by the device 104. The PCIe controller 100 then allocates a number of streams from the pool of available streams that are less than or equal to the requested number of supported streams and provides the device with the corresponding portion of the stream configuration data 110. Because the number of available streams on the PCIe controller 100 is fixed and finite, the PCIe controller 100 is prevented from having an excessive number of streams unnecessarily allocated to the device 104 that the device 104 cannot use.

[0043] For further explanation, Figure 4 sets forth a flowchart illustrating another exemplary method for allocating PCIe streams in a configurable multi-port peripheral component interface express (PCIe) controller in accordance with an embodiment of the present disclosure. The method of Figure 4 is similar to the method of Figure 3 in that it includes detecting 302 a link with a first PCIe device 104 and allocating 304 a first one or more PCIe streams from a pool of PCIe streams by receiving 306 data from the first PCIe device indicating a number of requested streams for the first PCIe device 104 and a number of PCIe lanes 106 used by the first PCIe device 104.

[0044] The method of Figure 4 differs from Figure 3 in that it includes detecting 402 another link by the second PCIe device 114. In some embodiments, detecting the other link 402 includes detecting a physical connection to the socket 102 by the PCIe controller 100. In some embodiments, detecting the other link 402 includes receiving a signal or other indication from a backplane component by the PCIe controller 100.

[0045] 4 also includes allocating 404 a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device 114. In some embodiments, the second one or more PCIe streams allocated to the device 114 include one or more streams that have not been previously allocated to another device (e.g., the first PCIe device 104).

[0046] In some embodiments, allocating 404 the second one or more PCIe streams includes reallocating 406 at least one of the first one or more PCIe streams from the first PCIe device 104 to the second PCIe device 114. For example, in some embodiments, the second PCIe device 114 is connected when there are no unallocated streams remaining in the pool of streams. As another example, in some embodiments, the PCIe controller 100 determines that the second PCIe device 114 should be allocated a number of streams that is greater than the number of available streams in the pool of streams. Thus, in some embodiments, one or more of the streams allocated to the first PCIe device 104 are reallocated from the first PCIe device 104 to the second PCIe device 104.

[0047] For example, in some embodiments, the PCIe controller 100 provides a command or signal to the first PCIe device 104 that one or more of the streams should be reallocated. In response, the first PCIe device 104 stops using the reallocated streams and continues to use the other allocated streams. The PCIe controller 100 then provides the stream configuration data 110 for the reallocated streams to the second PCIe device 114 to establish the streams between the PCIe controller 100 and the second PCIe device 114. In other embodiments, the PCIe controller 100 restarts the first PCIe device 104 or otherwise terminates and restarts the link between the PCIe controller 100 and the first PCIe device 104, effectively releasing all streams previously allocated to the first PCIe device 104. The first PCIe device 104 is then allocated a new subset of the pool of streams by the PCIe controller 100.

[0048] For further explanation, Figure 5 sets forth a flowchart illustrating another exemplary method for allocating PCIe streams in a configurable multi-port peripheral component interface express (PCIe) controller in accordance with an embodiment of the present disclosure. The method of Figure 5 is similar to the method of Figure 3 in that it includes detecting 302 a link with a first PCIe device 104 and allocating 304 a first one or more PCIe streams from a pool of PCIe streams by receiving 306 data from the first PCIe device indicating a number of requested streams for the first PCIe device 104 and a number of PCIe lanes 106 used by the first PCIe device 104.

[0049] The method of Figure 5 differs from Figure 3 in that it includes detecting 502 the removal of the first PCIe device 104. In some embodiments, detecting the removal 502 includes detecting that a physical connection to the socket 102 is no longer present. In some embodiments, detecting the removal 502 includes receiving, by the PCIe controller 100, a signal or other indication from a backplane component.

[0050] 5 also includes releasing 504 the first one or more PCIe streams. Releasing 504 the first one or more PCIe streams includes storing an indication in PCIe controller 100 that the first one or more PCIe streams are no longer allocated and thus available for allocation to other devices (e.g., currently connected devices or subsequently connected devices). For example, a table or other data structure associated with stream configuration data 110 for the released streams is updated to indicate that the released streams are available for allocation.

[0051] In some embodiments, if one or more other devices (e.g., devices 114, 124) are coupled to the PCIe controller 100, releasing 504 the first one or more PCIe streams includes reallocating 506 one or more of the first one or more PCIe streams to one or more other PCIe devices. For example, in some embodiments, the PCIe controller 100 provides stream configuration data 110 for the reallocated streams to the other device 114, 124, thereby enabling the device 114, 124 to establish another encrypted stream to the PCIe controller 100. In other embodiments, links or connections to the other devices are resumed, forcing a new allocation of streams to all devices connected to the PCIe controller 100. Thus, the previously allocated streams are reallocated with a new complete reallocation of streams among the connected devices.

[0052] In light of the above discussion, the reader will recognize that benefits of allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller include improved performance of a computing system through dynamic allocation and re-allocation of PCIe streams to PCIe devices.

[0053] Exemplary embodiments of the present disclosure are described primarily in the context of a fully functional computer system for allocating PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller. However, those skilled in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others as would occur to one skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means will be capable of executing the steps of the methods of the present disclosure embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0054] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions for causing a processor to perform aspects of the present disclosure.

[0055] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being an electromagnetic wave, such as an electric wave or other freely propagating electromagnetic wave, propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0056] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device.

[0057] The computer readable program instructions for carrying out the operations of the present disclosure can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions can be executed completely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to implement aspects of the present disclosure.

[0058] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer readable program instructions.

[0059] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / acts specified in the flowchart and / or block diagram blocks. These computer readable program instructions may also be stored in a computer readable storage medium capable of directing a computer, programmable data processing apparatus, and / or other device to function in a particular manner such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture including instructions for performing aspects of the functions / acts specified in the flowchart and / or block diagram blocks.

[0060] Furthermore, the computer readable program instructions may be loaded into a computer, other programmable data processing apparatus or other device and cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to generate a computer-implemented process such that the instructions executing on the computer, other programmable apparatus or other device perform the functions / acts specified in the flowchart and / or block diagram blocks.

[0061] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flow diagrams, as well as combinations of blocks in the block diagrams and / or flow diagrams, may be executed by a dedicated hardware-based system that performs the specified functions or acts, or executes a combination of dedicated hardware and computer instructions.

[0062] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A method for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, comprising: The PCIe controller detecting a link by a first PCIe device; and allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device. method.

2. Allocating the one or more PCIe streams comprises: receiving data from the first PCIe device indicating a number of streams requested for the first PCIe device and a number of PCIe lanes used by the first PCIe device; the one or more PCIe streams are allocated based on the number of requested streams and the number of PCIe lanes.

2. The method of claim 1.

3. the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device; 2. The method of claim 1.

4. the PCIe controller detecting another link with a second PCIe device; allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device.

2. The method of claim 1.

5. allocating the second one or more PCIe streams includes re-allocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. The method of claim 4.

6. Detecting a removal of the first PCIe device; Releasing the first one or more PCIe streams.

2. The method of claim 1.

7. re-allocating one or more of the first one or more PCIe streams to one or more other PCIe devices. The method of claim 6.

8. 1. A multi-port Peripheral Component Interface Express (PCIe) controller, comprising: Detecting a link by a first PCIe device; allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device; configured to perform the steps including: Multi-port PCIe controller.

9. Allocating the one or more PCIe streams comprises: receiving data from the first PCIe device indicating a number of streams requested for the first PCIe device and a number of PCIe lanes used by the first PCIe device; the one or more PCIe streams are allocated based on the number of requested streams and the number of PCIe lanes. The multi-port PCIe controller of claim 8.

10. the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device; The multi-port PCIe controller of claim 8.

11. The steps include: the multi-port PCIe controller detecting another link with a second PCIe device; allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device. The multi-port PCIe controller of claim 8.

12. allocating the second one or more PCIe streams includes re-allocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. The multi-port PCIe controller of claim 11.

13. The steps include: Detecting a removal of the first PCIe device; Releasing the first one or more PCIe streams. The multi-port PCIe controller of claim 8.

14. the steps including reallocating one or more of the first one or more PCIe streams to one or more other PCIe devices.

14. The multi-port PCIe controller of claim 13.

15. 1. An apparatus for distributing PCIe streams in a configurable multi-port Peripheral Component Interface Express (PCIe) controller, comprising: A processor; a PCIe controller operably coupled to the processor; The PCIe controller includes: Detecting a link by a first PCIe device; allocating a first one or more PCIe streams from a pool of PCIe streams for a link between the PCIe controller and the first PCIe device; configured to perform the steps including: Device.

16. Allocating the one or more PCIe streams comprises: receiving data from the first PCIe device indicating a number of streams requested for the first PCIe device and a number of PCIe lanes used by the first PCIe device; the one or more PCIe streams are allocated based on the number of requested streams and the number of PCIe lanes. The PCIe controller of claim 8.

17. the one or more PCIe streams are allocated in proportion to the number of lanes used by the first PCIe device; The PCIe controller of claim 8.

18. The steps include: the PCIe controller detecting another link with a second PCIe device; allocating a second one or more PCIe streams from the pool of PCIe streams to the second PCIe device. The PCIe controller of claim 8.

19. allocating the second one or more PCIe streams includes re-allocating at least one of the first one or more PCIe streams from the first PCIe device to the second PCIe device. The PCIe controller of claim 11.

20. The steps include: Detecting a removal of the first PCIe device; Releasing the first one or more PCIe streams. The PCIe controller of claim 8.

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