Display screen with display pixels having light emitting diodes - Patents.com

Abstract

This specification relates to a display screen (10). The display screen includes display circuits (12) each having a light emitting diode, a controllable current source for powering the light emitting diode, and a driver circuit adapted to deliver a pulse width modulated control signal for controlling the current source. i,j ) and a first electrode (18) connected to a drive circuit. i ), a second electrode (20 j ) and a third electrode (16 j ) and a selection signal (Com i ) to the second electrode; and a circuit (22) for transmitting an analog data signal (Data j ) at the third electrode, and a circuit for providing voltages (Vcc, Gnd) for powering the light emitting diode at the third electrode. Each selection signal or power supply voltage is made up of spaced steps each including a periodic analog signal at each interval, which are used to control a current source.

Description

[Technical field]

[0001] The present disclosure relates generally to display screens with display pixels having light emitting diodes. [Background technology]

[0002] An image pixel corresponds to a unit element of the image displayed by the display screen. To display a color image, the display screen generally comprises at least three light sources, each emitting radiation in a substantially single color (e.g. red, green and blue) to display each pixel of the image. The superposition of the radiation emitted by these three light sources gives the observer a sense of coloring corresponding to the pixel of the displayed image. All the components used to emit all the radiation enabling the display of a pixel of the image, or only all the components used to emit one of the radiations enabling the display of a pixel of the image, are referred to as a display pixel of the display screen, without distinction. The light source of a display pixel may comprise a light emitting diode.

[0003] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (or line) and a column of the array. Typically, each row of display pixels is selected in succession and the display pixels of the selected row are programmed to display a desired image pixel.

[0004] An active array is a screen driving configuration that can keep all pixel rows active for the entire duration of an image, as opposed to an array called passive, where each row is only active for T=Tframe / N (where Tframe is the duration of the image and N is the number of rows on the screen). This allows for increased brightness of the display screen. Furthermore, lower voltage or current levels can be sent to the control lines of the array, thus allowing a larger data flow to be displayed. Summary of the Invention [Problem to be solved by the invention]

[0005] In screens based on micrometer-sized light-emitting diodes, the size of the light-emitting diodes is generally smaller than the surface area available for image pixels in the screen, due to the high inherent brightness of the light-emitting diodes. In a method for manufacturing a display screen, these unit light-emitting diodes are deposited on a support, also called a panel, which includes driving electronics. Another manufacturing method uses display pixels with light-emitting diodes and circuits for controlling these light-emitting diodes. Such display pixels are called smart pixels. This allows the formation of an active array to be simplified, in particular because the control electronics of the light-emitting diodes of the display pixels are largely embedded in the display pixels. An example of a smart pixel is described in the document WO 2018 / 185433.

[0006] It is desirable to make the size of display pixels as small as possible in order to reduce the amount of semiconductor material forming them and therefore the manufacturing costs of these display pixels. However, it can be difficult to bond small sized display pixels to a panel, and in particular to ensure proper electrical connection between the conductive pads of the display pixels and the conductive tracks of the panel. This problem is even more acute as the number of display pixels in screens continues to increase.

[0007] In a smart pixel, the size of the smart pixel is generally determined by the number of conductive pads of the smart pixel used to electrically connect the smart pixel to the panel, particularly the minimum size of these conductive pads and the minimum space provided between these conductive pads, and therefore it is desirable to reduce the number of conductive pads.

[0008] It is known to control light-emitting diodes by pulse width modulation, also called PWM control. In this type of control, a succession of constant intensity current pulses is conducted through the light-emitting diode. The current pulses are repeated periodically, the duty cycle determining the intensity of the light emitted by the light-emitting diode. Such control advantageously makes it possible to operate the light-emitting diode at an optimum operating point where the efficiency of the light-emitting diode, which is equal to the ratio of the optical power emitted by the light-emitting diode to the electrical power consumed by the light-emitting diode, is maximum.

[0009] One example of a PWM control method requires a typically periodic analog reference signal that varies continuously between a minimum and a maximum value. An example of such an analog reference signal includes a series of voltage ramps. Implementation of such a PWM control method using smart pixels has the disadvantage that an additional conductive pad is required for each smart pixel to transmit the analog reference signal.

[0010] It is an object of the embodiments to provide a display pixel with a light emitting diode for a display screen that overcomes all or some of the disadvantages of existing display pixels with light emitting diodes.

[0011] It is another object of an embodiment that the control circuitry of the display screen performs pulse width modulation.

[0012] An object of the embodiment is to reduce the number of conductive pads in a display pixel.

[0013] It is another object of the embodiment that the display pixels have a size of less than 200 μm. [Means for solving the problem]

[0014] An embodiment is a display screen, comprising: a display circuit each having a light emitting diode, a controllable current source for powering said light emitting diode, and a driver circuit adapted to deliver a pulse width modulated control signal to control said current source; a first electrode coupled to the drive circuit; a circuit for transmitting a selection signal to each of the first electrodes; a second electrode coupled to the drive circuit; a circuit for transmitting an analog data signal to the second electrode; It is equipped with the drive circuit of each display circuit includes a storage circuit for storing an analog data signal received by the drive circuit, and a circuit adapted to compare the analog data signal with an interval-by-interval periodic analog signal to provide the pulse width modulated control signal; The display screen comprises: a third electrode coupled to the drive circuit; a circuit for providing a power supply voltage for powering the light emitting diode at the third electrode; It further comprises: Each selection signal or the supply voltage is arranged in spaced steps, each of which comprises a periodic analog signal for each of the intervals, to provide a display screen.

[0015] This makes it possible to reduce the number of electrodes connected to the display circuit, and thus to reduce the number of connection pads provided for each display circuit.

[0016] According to an embodiment, each selection signal comprises a succession of pulses, each display circuit further comprises a detection circuit configured to detect each pulse of the selection signal received by the display circuit, and a storage circuit of the display circuit is configured to store the analog data signal received by the driver circuit upon detection of each pulse, such that the storage of the data signal is controlled by the pulses of the selection signal.

[0017] According to an embodiment, said steps of each selection signal are arranged between two successive pulses in time. The selection signals comprise both pulses used for the selection of the display circuits and periodic analog signals at intervals used for the pulse width modulation control of the light emitting diodes. Thus, it is possible to maintain a substantially constant power supply voltage during the operation of the display screen.

[0018] According to an embodiment, the detection circuit is configured to distinguish, in the selection signal, the pulses from the interval-periodic analog signal. Advantageously, the distinction between the pulses and the interval-periodic analog signal is performed internally by the respective display circuit.

[0019] According to an embodiment, a maximum amplitude of the pulses of the selection signal is greater than a maximum amplitude of the interval-periodic analog signal. Advantageously, the distinction between pulses and interval-periodic analog signals may be made by one or more comparison operations.

[0020] According to an embodiment, the detection circuit comprises two successive inverters with different inversion thresholds.Advantageously, the structure of the detection circuit is particularly simple.

[0021] According to an embodiment, the period of the periodic analog signal per interval in each interval is different from the duration of each pulse, so that the distinction between a pulse and the periodic analog signal per interval does not or hardly depends on the changes in the level of the pulse and the level of the periodic analog signal.

[0022] According to an embodiment, a waveform of a pulse of the selection signal differs from a waveform of the interval-by-interval periodic analog signal over a period of the interval-by-interval periodic analog signal, and thus the distinction between a pulse and the interval-by-interval periodic analog signal does not or hardly depends on changes in the level of the pulse and the level of the periodic analog signal.

[0023] According to an embodiment, the detection circuit comprises a high-pass filter or a low-pass filter.

[0024] According to an embodiment, each driver circuit comprises a circuit for delivering a binary signal comprising pulses coincident with the pulses of said selection signal.

[0025] According to an embodiment, the pulses and the steps of the periodic analog signal per interval have opposite signs with respect to a reference value, thus making it easier to distinguish between the pulses and the periodic analog signal per interval.

[0026] According to an embodiment, the interval-wise periodic analog signal is triangular in shape.

[0027] According to an embodiment, the interval-wise periodic analog signal comprises only successive rising ramps or only successive falling ramps.

[0028] According to an embodiment, the drive circuit is configured to deliver the pulse width modulated control signal in a first state when the analog data signal is greater than the periodic analog signal per interval, and to deliver the pulse width modulated control signal in a second state when the analog data signal is less than the periodic analog signal per interval.

[0029] An embodiment is an electronic system for sending signals to an array of display circuits, each display circuit having a light emitting diode, a controllable current source powering the light emitting diode, and a driver circuit adapted to send a pulse width modulated control signal to control the current source, the array having a first electrode, a second electrode, and a third electrode coupled to the driver circuit, the electronic system comprising: a circuit for transmitting a selection signal to each of the first electrodes; a circuit for transmitting an analog data signal to the second electrode; It is equipped with the drive circuit of each display circuit includes circuitry for storing an analog data signal received by the drive circuit and circuitry adapted to compare the analog data signal with an interval-by-interval periodic analog signal to provide the pulse width modulated control signal; the electronic system further comprising a circuit for providing a power supply voltage to power the light emitting diode at the third electrode; The electronic system further provides, wherein each selection signal or said supply voltage is comprised of spaced steps, each of said steps comprising a periodic analog signal for each of said intervals. [Brief description of the drawings]

[0030] The foregoing and other features and advantages are described in detail in the remainder of the present disclosure of specific embodiments, given by way of non-limiting example with reference to the accompanying drawings, in which:

[0031] [Figure 1] FIG. 2 illustrates, partially and diagrammatically, an example of a display screen. [Diagram 2] FIG. 2 is a highly simplified cross-sectional view of an example display pixel; [Diagram 3] 3 is a bottom view showing the display pixel of FIG. 2. [Figure 4] 3 is a block diagram showing an example of a display pixel of FIG. 2; [Diagram 5] 3 is a timing diagram illustrating example display pixel signals of FIG. 2 for one row of display pixels according to an embodiment of a method of operating a display screen. [Figure 6] 3 is a timing diagram illustrating example signals of the display pixels of FIG. 2 for three consecutive rows of display pixels according to an embodiment of a method of operating a display screen. [Figure 7] 3A-3C are timing diagrams illustrating example signals of the display pixel of FIG. 2 and an embodiment of a method for detecting pulses in the signals. [Figure 8] 3A-3C are timing diagrams illustrating example signals of the display pixel of FIG. 2 and another embodiment of a method for detecting pulses in the signals. [Figure 9]3A-3C are timing diagrams illustrating example signals of the display pixel of FIG. 2 and another embodiment of a method for detecting pulses in the signals. [Figure 10] 5 is an electrical schematic diagram illustrating an embodiment of a portion of the display pixel shown in FIG. 4. [Figure 11] 5 is an electrical schematic diagram illustrating an embodiment of another portion of the display pixel shown in FIG. 4. [Figure 12] 2 for one row of display pixels according to another embodiment of a method of operating the display pixels of FIG. 2; [Figure 13] 2 for one row of display pixels according to another embodiment of a method of operating the display pixels of FIG. 2; [Figure 14] 5 is an electrical schematic diagram illustrating another embodiment of a portion of the display pixel shown in FIG. 4. [Figure 15] 2 for one row of display pixels according to another embodiment of a method of operating the display pixels of FIG. 2; [Figure 16] 5 is an electrical schematic diagram illustrating another embodiment of a current source for the display pixel shown in FIG. 4. [Figure 17] 5 is an electrical schematic diagram illustrating another embodiment of a portion of the display pixel shown in FIG. 4. [Figure 18] FIG. 4 is a timing diagram obtained by simulation of the signals of the display screen during a first operating phase. [Figure 19] FIG. 4 is a timing diagram obtained by simulation of other signals of the display screen during a first operation phase. [Figure 20] FIG. 6 is a timing diagram obtained by simulation of the signals of the display screen during a second operating phase. [Figure 21] FIG. 6 is a timing diagram obtained by simulation of other signals of the display screen during a second operating phase. [Figure 22] 21 is a view similar to FIG. 20 during emission of minimum intensity emitted light by the display pixel; [Diagram 23]22 is a view similar to FIG. 21 during emission of minimum intensity emitted light by the display pixel. [Figure 24] 21 is a view similar to FIG. 20 during emission of maximum intensity emitted light by the display pixel; [Diagram 25] 22 is a view similar to FIG. 21 during emission of maximum intensity emitted light by the display pixel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] In the various figures, similar features are indicated by similar reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have identical structural, dimensional and material characteristics. For clarity, only those steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0033] In the following description, when reference is made to terms defining absolute positions such as "front", "back", "top", "bottom", "left", "right", or relative positions such as "above", "below", "upper" and "lower", or terms defining directions such as "horizontal" and "vertical", the terms refer to the display screen in its drawing orientation or normal position of use, unless otherwise specified.

[0034] Unless otherwise indicated, when referring to two elements connected together, this refers to a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this refers to the two elements being either connected or coupled through one or more other elements.

[0035] Furthermore, a signal that alternates between a first constant state, e.g., a low state denoted as "0," and a second constant state, e.g., a high state denoted as "1," is referred to as a "binary signal." The high and low states of different binary signals of the same electronic circuit may be different. In fact, a binary signal may correspond to a voltage that may not be perfectly constant in the high or low state.

[0036] Furthermore, in the following description, the source and drain of an insulated gate field effect transistor, or MOS transistor, are referred to as the "power terminals" of the insulated gate field effect transistor, or MOS transistor.

[0037] Furthermore, unless otherwise indicated, when referring to the voltage of a conductive pad, the difference between the potential of said conductive pad and a reference potential, e.g. ground, which is taken as 0V, is taken into account.

[0038] Further, as used herein, the terms "insulating" and "conducting" are deemed to refer to "electrically insulating" and "electrically conducting," respectively. The terms "about," "approximately," "substantially," and "to the extent of" refer to within 10%, preferably within 5%, of the applicable value, unless otherwise specified.

[0039] 1 partially and diagrammatically illustrates a known example of a display screen 10. The display screen 10 comprises display pixels 12 arranged, for example, in M ​​rows and N columns. i,j where M is an integer ranging from 1 to 8,000, N is an integer ranging from 1 to 16,000, i is an integer ranging from 1 to M, and j is an integer ranging from 1 to N. As an example, in FIG. 1, M and N are 6. Each display pixel 12 i,j Electrode 14 i via a low reference potential source Gnd, e.g., ground, and the electrode 16 j 1. The electrode 14 is connected to a high reference potential source Vcc via i are shown in FIG. 1 as being aligned along rows, and electrodes 16 j are shown in FIG. 1 as being aligned along a column, although an inverse arrangement is possible. The power supply voltage of the display screen corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd, and is denoted Vcc as high reference potential. The power supply voltage Vcc depends inter alia on the arrangement of the light emitting diodes and the manufacturing technique of the light emitting diodes. By way of example, the power supply voltage Vcc may be around 4V to 5V.

[0040] For each row, 12 display pixels in the rowi,j Row electrode 18 i For each column, the display pixels 12 in the column are connected to i,j is column electrode 20 j The display screen 10 is connected to row electrodes 18. i The selection circuit 22 is coupled to each row electrode 18. i Select the reference signal Com i The display screen 10 is adapted to transmit column electrodes 20. j The data supply circuit 24 is coupled to each column electrode 20. j Data signal j The selection circuit 22 and the data supply circuit 24 are controlled by a circuit 26 which may for example include a microprocessor.

[0041] FIG. 2 shows a display pixel 12 i,j FIG. 3 is a highly simplified cross-sectional view of an example of a display pixel 12. i,j FIG. 1 is a bottom view showing each display pixel 12 i,jThe display pixel comprises a control circuit 30 covered by a display circuit 32. The display circuit 32 comprises at least one light emitting diode LED, three light emitting diodes LED are shown in FIG. 2 as an example. The display pixel has a bottom surface 34 and a top surface 35 opposite the bottom surface 34, the bottom surface 34 and the top surface 35 being preferably planar and parallel. The control circuit 30 further comprises conductive pads 36, not shown in FIG. 2, on the bottom surface 34. The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFT transistors. The display circuit 32 preferably comprises only the light emitting diodes LED and the conductive elements of these light emitting diodes LED, the control circuit 30 comprising all the electronic components necessary to control the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may further comprise other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be two-dimensional light emitting diodes, also called planar light emitting diodes, having a stack of planar layers, or three-dimensional light emitting diodes, each having a three-dimensional semiconductor element covered with an active area. In FIG. 2, the light emitting diodes LED are shown as being connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. By way of example, the light emitting diodes LED may be connected to a common cathode or may be connected independently of each other.

[0042] According to an embodiment, the display pixel 12 i,j The display pixel 12 has three light sources emitting light at a first wavelength, a second wavelength and a third wavelength. According to an embodiment, the first wavelength corresponds to blue light and lies in the range of 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and lies in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and lies in the range of 600 nm to 720 nm. As a variant, the display pixel 12 i,jmay have only a light source emitting light at the first wavelength, the second wavelength or the third wavelength, or may have only two light sources emitting light at two of the first wavelength, the second wavelength and the third wavelength.

[0043] Each conductive pad 36 corresponds to an electrode 14 shown diagrammatically in FIG. i , 16 j , 18 i , 20 j The first conductive pad 36 is connected to a low reference potential source Gnd. The second conductive pad 36 is connected to a high reference potential source Vcc. The third conductive pad 36 is connected to a row electrode 18. i is connected to the selection and reference signal Com i The fourth conductive pad 36 is connected to the column electrode 20 j , and a data signal Data j The size of the conductive pads 36 and their arrangement on the lower surface 34 are particularly i,j Design rules and display pixels 12 of a display screen 10 i,j This is determined by the assembly method.

[0044] FIG. 4 shows a display pixel 12 of a display screen 10. i,j FIG. 1 is a block diagram showing an example of the

[0045] According to the example, display pixel 12 i,j has one or more light emitting diodes, one light emitting diode LED is shown in Fig. 4 as an example. Each light emitting diode LED is connected in series to a controllable current source CS including, for example, a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED is connected to, for example, a conductive pad 36 receiving a high reference potential Vcc, the cathode of the light emitting diode LED is connected to, for example, a terminal of the controllable current source CS, and the other terminal of the controllable current source CS is connected to the conductive pad 36 receiving a low reference potential Gnd.

[0046] Display pixels 12 i,j The display pixel 12 further comprises a drive circuit 40 for driving the controllable current source CS. The drive circuit 40 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage below 4V, for example around 1V or 1.8V, to power at least some of the electronic components of the drive circuit 40, which allows the use of reduced-size low-voltage transistors. To this end, the display pixel 12 i,j may comprise a circuit 42 (Vdd generation) for providing a reduced supply voltage Vdd based on the supply voltage Vcc, which is used in particular to power some of the components of the driver circuit 40. The circuit 42 comprises, for example, a voltage divider.

[0047] According to an embodiment, each display pixel 12 i,j A selection / reference signal Com is received at one of the conductive pads 36 of i is an analog signal. i,j A data signal Data is received at one of the conductive pads 36. j is an analog signal.

[0048] The driver circuit 40 receives the selection and reference signal Com i The interface 44 is coupled to the conductive pad 36 for receiving the selection and reference signal Com i Based on the selection signal Prog, the driver circuit 40 outputs an analog reference signal REF adapted to execute the PWM control. jand a selection signal Prog, the circuit 46 being arranged to send an analogue signal Data to a storage circuit 48 (colour data memory). The storage circuit 48 is arranged to store a colour signal R, a colour signal G and a colour signal B representative of an image pixel to be displayed. The circuit 50 is adapted to control a controllable current source CS linked to the light emitting diode LED with a control signal derived from the analogue control signal R, the analogue control signal G, the analogue control signal B and the analogue reference signal REF. Alternatively, in the case of a monochromatic display pixel, the storage circuit 48 is arranged to store one analogue colour signal and the circuit 50 is adapted to control a controllable current source CS linked to the light emitting diode LED with a control signal derived from the analogue colour signal and the analogue reference signal.

[0049] As described below, display pixel 12 i,j In order to limit the number of conductive pads 36 per signal Com i , the display pixel 12 for storing the data signal Data. i,j This allows both the selection of an analog reference signal to be used for PWM control of the light emitting diodes and the delivery of an analog reference signal to be used for PWM control of the light emitting diodes.

[0050] 5 and 6 show a display pixel 12 in accordance with an embodiment of a method for displaying an image on a display screen 10. i,j 5 is a timing diagram of signals received by a display screen 10. For illustrative purposes, only signals associated with rank 1 rows and rank 1 columns of the display screen 10 are shown in Fig. 5, and only signals associated with rank 1 columns and successive rank 1, rank 2 and rank 3 rows of the display screen 10 are shown in Fig. 6.

[0051] In this embodiment, the potentials Vcc and Gnd, not shown in Figures 5 and 6, are substantially constant during the operation of the display screen 10. The image pixels of a new image to be displayed are displayed successively from the row with rank 1 to the row with rank M. The duration between two successive selections of the same row of the display screen 10 is called the frame duration T. The display pixel 12 of the row with rank i 1,j The display of a new image pixel according to (j ranges from 1 to N) includes a first stage P1 followed by a second stage P2. During the first stage P1, an analog data signal Data j For each display pixel 12 in the row of rank i 1,j Only the data signal Data1 is shown in FIG. i,j is the received analog data signal Data j During the second phase P2, each display pixel 12 stores a new value for the analog color signal R, the analog color signal G or the analog color signal B based on 1,j The light emitting diodes of the display pixels 12 are controlled based on the stored color signals R, G, and B. i,j If the display pixels 12 have light emitting diodes that emit different colors of radiation, i,j are data signals Data corresponding to different colors successively during the phase P1. j Each display pixel can receive 12 1,j During the next second phase P2, the light emitting diode j The control is based on new color signals R, G, and B obtained based on the above.

[0052] During the first phase P1, the selection and reference signal Com i is set to a substantially constant high level, thus forming a voltage pulse. i The pulse of each display pixel 12 in the row of rank i i,j Since the display pixel 12 in this row is detected by the circuit 44, i,jwhile the other rows of display pixels are not selected. According to an embodiment, the duration of each pulse is less than the duration of a frame divided by the number of selected rows, and preferably less than 100 μs. In particular, the circuit 44 delivers a signal Prog to a circuit 46, which in turn delivers, for example, a signal Com i During the first phase P1, the data signal Data j is column electrode 20 j Each data signal is transmitted to j may correspond to an analog signal that can take on a constant value ranging from a minimum value to a maximum value. The circuit 46 selected by the signal Prog in the "1" state outputs the signal Data j The display pixel 12 receives a signal R, a signal G or a signal B having a value depending on 1,j The signal Data stored in the circuit 50 j and display pixel 12 1,1 The signal R stored by 1,1 , and display pixel 12 1,1 The current I across the light emitting diode LED1,1 is shown as an example in FIG. 1,1 , display pixel 12 2,1 and display pixel 12 3,1 The signals R 1,1 , signal R 2,1 and signal R 3,1 , and display pixel 12 1,1 , display pixel 12 2,1 and display pixel 12 3,1 The current I across each of the light-emitting diodes LED1,1 , current I LED2,1 and current I LED3,1 is shown by way of example in Fig. 6. As shown in Fig. 6, the timing diagrams of the signals Com2 and Com3 are similar to the timing diagram of the signal Com1, although shifted in time. The end of the first phase P1 of one row may correspond to the start of the first phase P1 of the next row.

[0053] According to an embodiment, the display pixel 12 1,jThe light-emitting diodes of are controlled by pulse width modulation. For the third purpose, during the first part P2_ON of the second phase P2, the selection and reference signal Com i changes periodically, and each display pixel 12 of the row of rank i i,j 5 shows a series of identical patterns detected by the circuit 44 of FIG. 5. The circuit 44 sets the signal Prog to state "0" and sends a series of patterns (analog reference signal REF) to the circuit 50 for controlling the light emitting diode LED by pulse width modulation. As an example in FIG. 5, each pattern has an increasing voltage ramp followed by a decreasing voltage ramp. According to another example, each pattern has only one increasing voltage ramp or only one decreasing voltage ramp. In general, each pattern has a determined voltage variation curve, for example an exponential growth curve, a sinusoidal curve, etc. The shape of the pattern may include, for example, a luminosity correction, in particular a gamma correction. The pattern repetition frequency of each stage P2_OFF allows 1 to 1,000 pattern cycles per stage P2_OFF.

[0054] Display pixels 12 i,j The circuit 50 controls one or more light emitting diodes LED based on a comparison result between the stored analog signal R, analog signal G, or analog signal B and the analog reference signal REF. By way of example, when the stored analog signal R, analog signal G, or analog signal B is greater than the analog reference signal REF, the current source CS is turned off, resulting in a zero current I. LED When the light emitting diode is powered and the stored analog signal R, analog signal G or analog signal B is less than the analog reference signal REF, the current source CS is turned on, resulting in a current I LED is a constant non-zero value that powers a light emitting diode.

[0055] During the second part P2_OFF of the second phase P2, the selection and reference signal Com iis maintained at a constant level, e.g. a low level, so that the light emitting diodes LED of the display pixels in the row are off. The duration of the second part P2_OFF may vary from 0% to 100% of the duration of the second stage P2. In particular, the second part P2_OFF may not be provided. According to an embodiment, the duration of each stage P2 is equal to the duration of the frame Tframe decreasing by the duration of stage P1.

[0056] 7, 8 and 9 show the signal Com i A signal Com showing an embodiment of a method for detecting a pulse of i FIG.

[0057] According to the embodiment shown in FIG. 7, the signal Com in a series of patterns i The pulse level Vmax_pulse and the signal Com i The difference between the maximum value Vmax_sawtooth and the maximum value Vmax_sawtooth is greater than a threshold value that allows detection of a pulse by the circuit 44, preferably greater than 100 mV, and the signal Com i The detection of the pulse of the signal Com is performed by amplitude detection. i The pulse of the signal Com i is detected when it is greater than a threshold.

[0058] According to the embodiment shown in FIG. i The duration of the pulse Tpulse is equal to or greater than the duration Tsawtooth of the repeating pattern of the series of ramps. i The detection of the pulse of the signal Com i In particular, in this case, the signal Com i The duration Tpulse of the pulse of signal Com may be equal to the duration Tsawtooth. i The pulses of have a different shape from the shape of the pattern of the reference signal REF and can therefore be detected by low pass filtering.

[0059] According to the embodiment shown in FIG.i The duration of the pulse Tpulse is preferably at least 30% shorter than the duration Tsawtooth of the pattern repeated in the series of ramps. i The detection of the pulse of the signal Com i This is done by high-pass filtering of the

[0060] According to an embodiment, the analog reference signal REF is i According to another embodiment, the analog reference signal REF may include only the pattern of the signal Com i In fact, the signal Com i The duration of the pulse of the signal Com i The duration of the repetition of the pattern, i.e. the duration of the first portion P2_ON of stage P2, may be much shorter than the duration of the first portion P2_ON of stage P2, so that when the light-emitting diode is on, the intensity of the light emitted by the light-emitting diode during stage P1 is negligible compared to the intensity of the light emitted during the first portion P2_ON of stage P2.

[0061] FIG. 10 is an electrical schematic diagram of a portion of circuit 40, specifically circuits 46, 48 and 50, an embodiment of circuitry for driving controllable current source CS.

[0062] The circuit 46 of the driver circuit 40 receives the data signal Data j The driver circuit 40 includes a first switch T1 coupling a conductive pad 36 receiving the low reference voltage Gnd to a node N. The first switch T1 is controlled by a signal Prog. According to an embodiment, the first switch T1 is an N-channel MOS transistor whose gate receives the signal Prog. The driver circuit 40 includes a circuit 48 having a capacitor C1 having a first plate coupled, preferably connected, to the node N and a second plate coupled, preferably connected, to a conductive pad receiving the low reference voltage Gnd.

[0063] The circuit 50 of the driver circuit 40 includes a comparator COMP having an input V+, preferably connected to the node N, and a signal Comi The comparator COMP has an input V- for receiving a signal REF, which may be identical to Vref, an input Vref for receiving a constant voltage, which may for example correspond to the reduced reference voltage Vdd when Vdd is present or may be derived from the high reference voltage Vcc when Vdd is not present, an input coupled, preferably connected, to the conductive pad 36 for receiving the high reference voltage Vcc, and an output for delivering a binary signal Vcomp. The comparator COMP may have a differential pair.

[0064] The circuit 50 comprises an inverter INV1 receiving a signal Vcomp and delivering a signal VCS for PWM control of a current source CS. According to an embodiment, the inverter INV1 comprises a P-channel MOS transistor T2 having a source receiving a high reference voltage Vcc, a gate receiving the signal Vcomp and a drain delivering the signal VCS, and an N-channel MOS transistor T3 having a source receiving a low reference voltage Gnd, a gate receiving the signal Vcomp and a drain connected to the drain of the transistor T2.

[0065] According to an embodiment, the current source CS corresponds to an N-channel MOS transistor T4 having a gate receiving the signal VCS, a source receiving the low reference voltage Gnd and a drain coupled to the cathode of the light emitting diode LED, the anode of which receives the high reference voltage Vcc.

[0066] The switch T1 is on when the selection signal Prog is in a state "1" equal to, for example, a voltage Vcc, and is off when the selection signal Prog is in a state "0" equal to, for example, 0 V. When the switch T1 is on, the capacitor C1 is connected to the voltage Data j By turning off switch T1 when the selection signal Prog is in state "0", the discharge of capacitor C1 through switch T1 is prevented. Thus, the signal Data j is stored in the form of a voltage R on capacitor C1.

[0067] The comparator COMP compares the voltage R of the capacitor C1 with the signal REF. The inverter INV1 outputs a signal VCS, which is either in the "1" or "0" state, which is the inverse of the state of the signal Vcomp. The MOS transistor T4 is in the ON state when the signal VCS is "1" and in the OFF state when the signal VCS is "0".

[0068] According to the embodiment, when the voltage R is higher than the voltage REF, the signal Vcomp is "1" and the signal VCS is "0", so the transistor T4 is turned off and the light-emitting diode LED is turned off. When the voltage R is lower than the voltage REF, the signal Vcomp is "0" and the signal VCS is "1", so the transistor T4 is on and the light-emitting diode LED is on.

[0069] FIG. 11 is an electrical schematic diagram of an embodiment of a circuit 44 adapted to implement the embodiment of the detection method shown in FIG.

[0070] The circuit 44 includes a resistor R, which is connected to a select and reference signal Com i and a second terminal coupled, preferably connected, to a node M. Circuit 44 includes four consecutive inverters INV2, INV3, INV4 and INV5 having different inversion thresholds.

[0071] The inverter INV2 has a P-channel MOS transistor T5 having a source receiving the high reference voltage Vcc, a gate coupled, preferably connected, to node M, and a drain coupled, preferably connected, to node Q, and an N-channel MOS transistor T6 having a gate coupled, preferably connected, to node M, and a drain coupled, preferably connected, to node Q. The circuit 44 has two N-channel MOS transistors T7 and T8, each assembled with a diode, and arranged in series between the low reference potential source Gnd and the source of the transistor T6.

[0072] The inverter INV3 comprises a P-channel MOS transistor T9 having a gate, preferably connected to a node Q, and a drain, preferably connected to a node W, and an N-channel MOS transistor T10 having a gate, preferably connected to a node Q, a drain, preferably connected to a node W, and a source, preferably connected to a low reference potential source Gnd. The circuit 44 comprises a P-channel MOS transistor T11, which is constructed as a diode and is arranged in series between the high reference potential source Vcc and the source of the transistor T9.

[0073] The inverter INV4 has a P-channel MOS transistor T12 having a gate, preferably connected to the node W, a source, preferably connected to the high reference potential source Vcc, and a drain, preferably connected to the node X, and an N-channel MOS transistor T13 having a gate, preferably connected to the node W, a drain, preferably connected to the node X, and a source, preferably connected to the low reference potential source Gnd. The inverter INV5 has a P-channel MOS transistor T14 having a gate, preferably connected to the node X, a source, preferably connected to the high reference potential source Vcc, and a drain, preferably connected to the node Y, and an N-channel MOS transistor T15 having a gate, preferably connected to the node X, a drain, preferably connected to the node Y, and a source, preferably connected to the low reference potential source Gnd. The node Y delivers a signal Prog.

[0074] The circuit 44 operates as follows: the potential at node M varies in accordance with the operation of the inverter INV2 while the selection and reference signal Com i Considering that all MOS transistors are the same size, the inversion threshold of the inverter INV2 is substantially equal to Vcc / 2+2Vd, where Vd is the gate-source voltage of the diode-constructed transistor T7, and Vd is also equal to the drain-source voltage. The inversion threshold of the inverter INV3 is substantially equal to Vcc / 2-Vd. The inversion thresholds of the inverters INV4 and INV5 are substantially equal to Vcc / 2. The signal Com i When the signal Com is at the voltage Vmax_pulse, the voltage at the node M is in the range of Vcc / 2+2Vds to Vcc. i When the signal Com is at a voltage Vmax_sawtooth, the voltage at node M is lower than Vcc / 2+2Vds. iWhen is at voltage Vmax_pulse during the pulse of phase P1, the voltage at node Q is at level "0", the voltage at node W is at level "1", the voltage at node X is at level "0" and the voltage at node Y is at level "1". Thus, the signal Prog is at "1". During the first part P2_ON of phase P2, during the sequence of patterns, the signal Com i remains lower than the voltage Vmax_sawtooth. Therefore, the voltage at node Q is at level "1", the voltage at node W is at level "0", the voltage at node X is at level "1" and the voltage at node Y is at level "0". The signal Prog is therefore at "0". The inverters INV3, INV4 and INV5 have in particular the purpose of ensuring that the signal Prog exhibits sufficiently sharp rising and falling edges.

[0075] In the embodiment described above in relation to FIG. 5 and FIG. 6, the voltage Data j is higher than the analog reference signal REF, i,j The light emitting diode LED is turned off. This is because the stored signal Data j A higher value of means that the intensity of the light emitted by the light emitting diode LED is lower. In one application, the stored signal Data j Each display pixel 12 is configured such that the higher the value of , the higher the intensity of the light emitted by the light emitting diode LED. i,j It may be desirable to control a light emitting diode LED.

[0076] FIG. 12 is a diagram similar to FIG. 5 showing a display pixel 12 for another embodiment of a method for displaying an image on the display screen 10. i,j 12 is a timing diagram of signals received by .For illustrative purposes, only rows of rank 1 are considered in FIG.

[0077] 12 is inverted with respect to the polarity of the signal Com1 in FIG 5. Therefore, during phase P2, when the stored analog signal R is lower than the voltage REF, each display pixel 12 i,j The light emitting diode LED is off, which means zero current I LED When the stored analog signal R is higher than the voltage REF, the light emitting diode LED is on, which causes a high level of current I LED The higher the value of the analog signal R, the higher the intensity of the light emitted by the light emitting diode LED 1. The driving circuit 40 may be identical to the driving circuit previously described in connection with FIGS.

[0078] FIG. 13 is a diagram similar to FIG. 5 showing a display pixel 12 for another embodiment of a method for displaying an image on the display screen 10. i,j 13 is a timing diagram of signals received by .For illustrative purposes, only rows of rank 1 are considered in FIG.

[0079] The signal Com1 in FIG. 13 is identical to the signal Com1 in FIG. 5, except that during the first part P2_ON of the phase P2, the signal Com1 varies between a value of zero and a maximum negative value -Vmax_sawtooth.

[0080] FIG. 14 is a schematic diagram similar to FIG. 10 and is an electrical diagram of an embodiment of a portion of circuit 40, in particular circuits 46, 48 and 50, for driving controllable current source CS, adapted for implementing the embodiment of the control method shown in FIG. 13.

[0081] The driver circuit 40 shown in FIG. 14 includes all of the elements of the driver circuit 40 shown in FIG. 10 and further includes a capacitor C2 having a first plate coupled, preferably connected, to the conductive pad 36 receiving the high reference voltage Vcc and a second plate coupled, preferably connected, to the input V- of the comparator COMP, a capacitor C3 having a first plate coupled, preferably connected, to receive the signal Com1 and a second plate coupled, preferably connected, to the negative input V- of the comparator COMP, and a capacitor C4 having a first plate coupled, preferably connected, to the negative input V- of the comparator COMP and a second plate coupled, preferably connected, to a low reference potential source Gnd.

[0082] During operation, the signal at the input V- of the comparator COMP varies between two positive voltage extremes while the signal Com i The advantage of such an embodiment is that the signal Com i can be used directly to control the gate of transistor T1, so that circuit 44 does not need to be provided.

[0083] According to another embodiment, the analog reference signal REF is i , but exists at the high reference voltage Vcc or the low reference voltage Gnd.

[0084] FIG. 15 is a diagram similar to FIG. 5, showing display pixel 12 for another embodiment of a method for displaying an image on display screen 10. i,j 15 is a timing diagram of signals received by .For illustrative purposes, only rows of rank 1 are considered in FIG.

[0085] The signal Com1 in Fig. 15 is identical to the signal Com1 in Fig. 5, except that it does not have a sequence of patterns during phase P2 and remains at a value of zero during phase P2. In Fig. 15, the high reference voltage Vcc is constant at a value Vcc_max except during a first part P2_ON of phase P2, which shows a repetition of a pattern between a maximum value Vcc_max and a positive minimum value Vcc_min. The driving circuit 40 may have the structure shown in Fig. 13. The driving circuit 40 may further comprise a circuit for providing a stable high reference voltage based on the signal Vcc.

[0086] Figure 16 shows another embodiment of the controllable current source CS. The controllable current source CS has the same structure as that shown in Figure 10, except that it comprises an N-channel MOS transistor T16 in series with a MOS transistor T4, the drain of the transistor T16 is coupled, preferably connected, to the drain of the transistor T4, the source of the transistor T16 is coupled, preferably connected, to a low reference potential source Gnd, and the gate of the transistor T16 receives a constant voltage Vbias. The structure of the current source CS shown in Figure 16 allows for a more precise current control of the light emitting diode LED.

[0087] Fig. 17 shows another embodiment of a circuit 40 for driving a controllable current source CS. The circuit 40 has all the elements shown in Fig. 10, except that the comparator COMP is replaced by an N-channel MOS transistor T17, whose source receives the signal REF, whose gate is coupled, preferably connected, to node M, and whose drain is coupled, preferably connected, to the gates of transistors T2 and T3, and two N-channel MOS transistors T18 and T19, assembled in series between the drain of transistor T17 and a high reference voltage source Vcc, and whose gates are coupled, preferably connected, to the high reference voltage source Vcc. The driving circuit 40 is particularly adapted for the case where the MOS transistors are replaced by thin film transistors, also called TFT transistors.

[0088] A simulation was carried out in which the driver circuit 40 had the structure shown in FIGS.

[0089] Figures 18 and 19 are timing diagrams of the signals during phase P1. More precisely, Figure 18 shows the curve of variation of the voltage R of the capacitor C1, and Figure 19 shows the curves of variation of the signals Com1 and Prog during phase P1.

[0090] Figures 20 and 21 are timing diagrams of the signals during phase P2: more precisely, Figure 20 shows the curve of variation of the gate voltage VCS of transistor T4, and Figure 21 shows the curves of variation of signals Com1 and Prog.

[0091] Figures 22 and 23 are similar to Figures 20 and 21 respectively for the case where the data signal sent to the display pixel has a maximum value, which corresponds to the intensity of light received by the display pixel being zero (VCS is constant and equal to 0V and the light emitting diode is off throughout stage P2).

[0092] Figures 24 and 25 are similar to Figures 20 and 21 respectively for the case when the data signal sent to the display pixel has a minimum value, which corresponds to the intensity of the light received by the display pixel being at a maximum value (VCS is constant and equal to 5V and the light emitting diode is on throughout phase P2).

[0093] A specific embodiment has been described. Various modifications and adjustments will occur to those skilled in the art. Moreover, various embodiments with various variations have been described above. It should be noted that various elements of these various embodiments and variations may be combined. As an example, the embodiment of the controllable current source CS shown in FIG. 16 may be implemented using the drive circuit 40 shown in FIG. 10, FIG. 14 or FIG. 17.

[0094] This patent application claims priority from French Patent Application No. 21 / 14277, which is incorporated herein by reference.

Claims

1. A display screen (10), comprising: A display circuit (12) each having a light emitting diode (LED), a controllable current source (CS) for powering the light emitting diode, and a driver circuit (40) adapted to deliver a pulse width modulated control signal (VCS) for controlling the current source. i,j ) and, A first electrode (18) connected to the drive circuit i ) and, The display circuit (12) is connected to the first electrode. i,j ) selection signal (Com i a circuit (22) for delivering a signal to each of the first electrodes; A second electrode (20) connected to the drive circuit (40) j ) and, An analog data signal (Data j ) and a circuit (24) for transmitting Equipped with Each display circuit (12 i,j The drive circuit (40) of the display circuit (12 i,j a storage circuit (48) configured to store an analog data signal received by said driver circuit when said drive circuit is selected, and a circuit (COMP) adapted to compare said analog data signal with an interval-by-interval periodic analog signal (REF) to generate said pulse width modulated control signal (VCS), The display screen comprises: A third electrode (16) connected to the drive circuit (40) j ) and, a circuit for supplying a power supply voltage (Vcc, Gnd) for powering the light emitting diode at the third electrode; It further comprises: Each selection signal (Com i ) or the power supply voltage (Vcc, Gnd) is configured with spaced steps (P2_ON), ​​each of which includes a periodic analog signal for each of said intervals.

2. Each selection signal (Com i ) has a series of pulses, Each display circuit (12 i,j ) further comprises a detection circuit (44) configured to detect each pulse of the selection signal received by the display circuit; A storage circuit (48) of the display circuit stores an analog data signal (Data) received by the driver circuit upon detection of each pulse. j 2. The display screen of claim 1, configured to store:

3. Each selection signal (Com i 3. A display screen according to claim 2, wherein said phase (P2_ON) of (P1_ON) is provided between two successive pulses in time.

4. The detection circuit (44) detects the selection signal (Com i 4. The display screen of claim 3, wherein said display screen is configured to distinguish said pulses from a periodic analog signal every said interval within said period.

5. The selection signal (Com i 5. The display screen of claim 4, wherein the maximum amplitude (Vmax_pulse) of the pulse of said periodic analog signal (REF) per said interval (Vmax_sawtooth) is greater than the maximum amplitude (Vmax_sawtooth) of said periodic analog signal (REF) per said interval.

6. 6. A display screen as claimed in claim 5, wherein the detection circuit (44) comprises two successive inverters (INV2, INV3) having different inversion thresholds.

7. 5. A display screen as claimed in claim 4, wherein the period of the interval-by-interval periodic analog signal (REF) in each interval is different from the duration of each pulse.

8. The selection signal (Com i5. The display screen of claim 4, wherein a waveform of the pulses of said first periodic analog signal (REF) differs from a waveform of said second periodic analog signal (REF) over a period of said first periodic analog signal.

9. 10. A display screen according to claim 8 or 9, wherein the detection circuit (44) comprises a high-pass filter or a low-pass filter.

10. Each drive circuit (40) receives the selection signal (Com i 10. A display screen according to claim 2, further comprising a circuit for emitting a binary signal (Prog) comprising pulses coincident with the pulses of (A).

11. A display screen as claimed in any one of claims 2 to 10, wherein the pulses and the steps of the periodic analogue signal per interval have opposite signs relative to a reference value.

12. A display screen according to any one of the preceding claims, wherein said interval-wise periodic analog signal (REF) is triangular in shape.

13. A display screen according to any one of the preceding claims, wherein said interval-wise periodic analog signal (REF) comprises only successive rising ramps or only successive falling ramps.

14. The driving circuit (40) receives the analog data signal (Data j 13. The display screen of claim 1, configured to deliver said pulse width modulated control signal (VCS) in a first state when said analog data signal is greater than said interval periodic analog signal (REF) and to deliver said pulse width modulated control signal (VCS) in a second state when said analog data signal is less than said interval periodic analog signal (REF).

15. Display circuit (12 i,j 2. An electronic system for transmitting signals to an array of Each display circuit includes a light emitting diode (LED), a controllable current source (CS) for powering the light emitting diode, and a driver circuit (40) adapted to deliver a pulse width modulated control signal (VCS) for controlling the current source, and the array includes a first electrode (18) coupled to the driver circuit. i ), a second electrode (20 j ) and a third electrode (16 j ) The electronic system comprises: A selection signal (Com i ) and a circuit (22) for transmitting An analog data signal (Data j ) and a circuit (24) for transmitting Equipped with Each display circuit (12 i,j said driver circuit (40) of said driving circuit (40) having a circuit (48) for storing an analog data signal received by said driver circuit, and a circuit (COMP) adapted to compare said analog data signal with an interval-by-interval periodic analog signal (REF) to deliver said pulse width modulated control signal (VCS); The electronic system further comprises a circuit for providing a power supply voltage (Vcc, Gnd) for powering the light emitting diode at the third electrode; Each selection signal (Com i ) or the power supply voltage (Vcc, Gnd) is comprised of spaced steps (P2_ON), ​​each of said intervals comprising a periodic analog signal.

16. Each selection signal (Com i 16. The electronic system of claim 15, wherein the signal comprises a series of pulses.

17. Each selection signal (Com i 17. The electronic system according to claim 16, wherein said phase (P2_ON) of is provided between two successive pulses in time.

18. The selection signal (Com i 20. The electronic system of claim 17, wherein a waveform of the pulses of said first input signal is different from a waveform of the periodic analog signal for each said interval over the period.

19. The selection signal (Com i 17. The electronic system of claim 16, wherein a maximum amplitude (Vmax_pulse) of the pulse of said periodic analog signal (REF) per said interval (Vmax_sawtooth) is greater than a maximum amplitude (Vmax_sawtooth) of said periodic analog signal (REF) per said interval.

20. 17. The electronic system of claim 16, wherein the period of the interval-by-interval periodic analog signal (REF) in each interval is different from the duration of each pulse.

21. The electronic system of any one of claims 16 to 20, wherein the pulses and the steps of the periodic analog signal per interval have opposite signs relative to a reference value.

22. The electronic system according to any one of claims 16 to 21, wherein the interval-wise periodic analog signal (REF) is triangular in shape.

23. The electronic system according to any one of claims 16 to 21, wherein the interval-wise periodic analog signal (REF) comprises only successive rising ramps or only successive falling ramps.

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