SYSTEM AND METHOD FOR PROCESSING VARIABLE CODED MODULATION (VCM) BASED COMMUNICATION SIGNAL USING FEEDFORWARD CARRIER AND TIMING RECOVERY - Patent application

Abstract

A system is provided for implementing a digital bitstream processing and method. The method includes splitting the digital bitstream into a plurality of data packets. Performing a carrier recovery error calculation on a first portion of the plurality of data packets in a first processing block includes performing a first phase-locked loop (PLL) function on decimated data of the data packet and performing a carrier recovery operation on the first portion of the plurality of data packets. In parallel with the processing of the first portion of the plurality of packets, performing a carrier recovery error calculation on a second portion of the plurality of data packets in a second processing block includes performing a first PLL function on the decimated data of the data packet and performing a carrier recovery operation on the second portion of the plurality of data packets.

Description

[Technical field]

[0001] This disclosure relates to signal processing, and more particularly to implementing distributed computing using general purpose processors (GPPs) to achieve high speed processing. [Background technology]

[0002] 2. Description of Related Art In some examples, satellite communication signals may require large ground stations and other facilities to transmit and / or receive and process data locally, which may include large antenna arrays, associated radio frequency terminals (RFTs), and significant electronics (modems, signal processors, etc.) to receive data from associated satellites and to process and use the received data. Summary of the Invention

[0003] The following summary is not intended to define all aspects of the invention, and other features and advantages of the disclosure will become apparent from the following detailed description, including the drawings. It should be understood that the disclosure is intended to be linked as an integrated document, and that all combinations of features described herein are contemplated, even if the combinations of features are not found together in the same sentence, paragraph, or section of the disclosure. Moreover, the disclosure includes, as an additional aspect, all embodiments of the invention that are narrower in scope in any respect than the variations specifically mentioned herein.

[0004] The present disclosure addresses systems and methods for satellite communications using downlink site diversity and uplink transmit power management. Multiple ground stations can include piggyback signals in their transmissions to ensure coherent reception of multiple versions of the signal using site diversity.

[0005] As disclosed herein, digital signal processing (DSP) can be performed in many different ways using a general purpose processor or a central processing unit (CPU). Exemplary techniques implemented on a general purpose processor to achieve high speed processing capable of performing the disclosed functions include: Use parallel processing across multiple CPUs and many cores on each CPU; Adopting single instruction multiple data (SIMD) technology; Feed-forward processing to break the feedback loop; and Pre-calculating metadata (or state information) to split the heavy lifting among several CPUs, Combining multiple functions into a single function in a way that improves CPU performance or reduces memory bandwidth usage; These include, but are not limited to:

[0006] One way to increase the throughput of a general purpose CPU is to utilize as many cores present on the CPU as possible. This allows for increased processing throughput by adding more CPU cores, although great care must be taken to ensure that data is properly shared between the several cores in the CPU. It is also possible to use several CPUs on the same system, with each CPU containing multiple cores. All embodiments within this disclosure take advantage of using multiple cores in a CPU, and some embodiments take advantage of having multiple CPUs per system and / or even per group of systems in a server environment.

[0007] Another way to achieve high processing speed is to take advantage of the single instruction multiple data (SIMD) capabilities of general-purpose CPUs. This allows a single CPU core to perform up to 16 floating-point operations in a single instruction, as in the case of AVX512 SIMD operations. One example of employing SIMD is using a finite impulse response (FIR) filter function that calculates 16 floating-point results at once. Another example is when multiplying complex numbers. Instead of calculating one pair of orthogonal signals (IQ data), in AVX512 it is possible to calculate eight IQ pairs at once. Complex multiplication is used in almost all of the processing algorithms described in this disclosure.

[0008] Some processing systems implement various forms of feedback, often including a phase-locked loop (PLL) or a delay-locked loop (DLL). However, as with traditional PLLs and DLLs, feedback before decimation can generally be problematic because the very nature of the feedback creates a bottleneck. The feedback loop forces all incoming data to be processed in a single (e.g., linear) process that cannot be easily split or otherwise separated. In addition to feedback, there are other obstacles to overcome using PLLs and DLLs, including the frequency with which the error term is calculated. The feedback loop can be replaced by a feedforward loop, which processes an error condition on a block of data, and then the calculated error term is fed forward to another block that applies the error term. In some implementations, with appropriate overlap, the calculation of the error and the application of the term can be split across several CPU cores to further improve throughput.

[0009] In addition to the feed-forward approach to processing the data, it can also be beneficial to perform metadata pre-calculation in a single block and then split the processing of the data across several CPU cores. This method is similar to the feed-forward method already described, but in this case we do not break the loop (such as a feedback loop) but simply take advantage of more CPU cores to increase the amount of data that can be processed. In this way, the block performing the pre-calculation does not perform CPU-intensive operations but instead calculates the necessary steps such as iterations in a for loop, the starting index, and the slope point between the interpolation phase values.

[0010] Another technique that can be employed in a general-purpose CPU to achieve high throughput is the way in which the feature set is used and the type of memory used. In some cases, memory bandwidth is the limiting factor for performance. In this case, the objective is to limit the amount of data that needs to be transferred to and from random access memory (RAM) (not faster memory like the CPU cache). To do this, functions need to be folded so that they are executed all together instead of executed individually, with the goal of making as few accesses to the slower RAM as possible compared to accessing the faster CPU cache. Another way to reduce memory bandwidth is to utilize well-spaced memory types, for example using int8 instead of float or double when possible.

[0011] In one embodiment, a method and a system implementing the method are provided for processing a digital bit stream, the digital bit stream being a digitized communication signal. The method includes splitting the digital bit stream into a plurality of data packets at one or more processors, performing a carrier recovery error calculation on a first portion of the plurality of data packets at a first processing block of a plurality of processing blocks in the one or more processors, the performing including performing a first phase-locked loop (PLL) function on decimated data of the first portion of the plurality of data packets, performing a carrier recovery operation on the first portion of the plurality of data packets, performing a carrier recovery error calculation on a second portion of the plurality of data packets at a second processing block of the plurality of processing blocks in the one or more processors in parallel with the processing of the first portion of the plurality of packets, the performing a carrier recovery operation on the second portion of the plurality of data packets, and combining the first and second portions based on phase stitching.

[0012] In a further aspect, the method includes performing, at a third processing block in the one or more processors, a timing recovery error calculation on a first portion of the plurality of data packets and performing a timing recovery operation on the first portion of the plurality of data packets, and in parallel with the processing of the third portion of the plurality of packets, performing, at a fourth processing block in the one or more processors, a timing recovery error calculation on a second portion of the plurality of data packets and performing a timing recovery operation on the second portion of the plurality of data packets.

[0013] In a further aspect, the timing recovery error calculation includes performing a second PLL function on the decimated data of the first and second portions of the plurality of data packets.

[0014] In a further aspect, the timing recovery error calculation includes receiving a data packet as samples of a downlink signal, the samples having an unknown symbol rate and frequency, determining a timing error of the samples based on an estimate of the symbol rate, decimating the samples with a decimation filter, performing a second PLL function on the decimated symbols to determine a phase, frequency, and Doppler velocity of the symbols, and updating the estimate of the symbol rate.

[0015] In a further aspect, the PLL function is one of a second order PLL, a third order PLL, a reversible PLL, and a reversible iterative PLL. And in a further aspect, each of the data packets of the plurality of data packets includes duplication of data from adjacent packets and the PLL function is a second order PLL. And in a further aspect, each of the data packets is a framed data packet and the PLL function is one of a reversible PLL and a reversible iterative PLL.

[0016] In a further aspect, the method further includes locating a frame boundary of each framed data packet by detecting a frame marker, and performing a carrier recovery error calculation on the first and second portions of the plurality of data packets based on the located frame boundary. And in a further aspect, the method includes performing, in a third processing block in the one or more processors, a timing recovery error calculation on the first portion of the plurality of data packets, performing a timing recovery operation on the first portion of the plurality of data packets, and in parallel with the processing of the third portion of the plurality of packets, performing, in a fourth processing block in the one or more processors, a timing recovery error calculation on the second portion of the plurality of data packets, and performing a timing recovery operation on the second portion of the plurality of data packets, and the locating of the frame boundary is performed on the combined first and second portions.

[0017] In a further aspect, the multiple processing blocks include multiple central processing unit (CPU) cores.

[0018] In a further aspect, the carrier recovery error calculation includes receiving a symbol associated with a synchronized sample of the downlink signal, determining a carrier error for the symbol based on an estimate of the frequency of the downlink signal and a product of the symbol raised to the power of n, where n is an integer, decimating the symbol with a decimation filter, performing a first PLL function on the decimated symbols to determine a phase, frequency, and Doppler velocity of the symbol, and updating the frequency estimate.

[0019] In a further aspect, one or more of the processors employ single instruction multiple data (SIMD) technology to achieve high throughput.

[0020] In a further aspect, a system is provided for processing a digital bitstream representing a communication signal, the system including a digitizer configured to convert a received analog signal into a digital bitstream, and one or more processors communicatively coupled to the digitizer, the one or more processors having a plurality of processing blocks and operable to perform a method as described in any one of the methods described above.

[0021] In a further aspect, a non-transitory computer-readable medium for processing a digital bitstream of a satellite downlink signal is provided, the non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the methods described above.

[0022] The details of the present invention, both as to their structure and operation, can be gleaned in part from study of the accompanying drawings, in which like reference numerals refer to like parts and in which: [Brief description of the drawings]

[0023] [Figure 1] 1 is a graphical representation of an example of a communication system according to embodiments disclosed herein. [Diagram 2] 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of FIG. 1. [Diagram 3] 1 is a graphical representation of an example of feedforward or pre-computed signal processing according to embodiments disclosed herein. [Figure 4] 4 is a graphical representation of another example of the feedforward or pre-computed signal processing of FIG. 3 according to embodiments disclosed herein. [Diagram 5] 1 is a functional block diagram of an example system and method for signal processing of a received downlink signal according to embodiments disclosed herein. [Figure 6] 4 is a functional block diagram of another example system and method for signal processing of a received downlink signal according to embodiments disclosed herein. [Figure 7] FIG. 2 is a functional block diagram of an example of a timing recovery error algorithm according to embodiments disclosed herein. [Figure 8] FIG. 2 is a functional block diagram of an example of a carrier recovery error algorithm according to embodiments disclosed herein. [Figure 9] FIG. 2 is a functional block diagram of an example of timing and carrier recovery error operation according to embodiments disclosed herein. [Figure 10] 2 is a functional block diagram of an example phase-locked loop (PLL) function according to an embodiment disclosed herein. [Figure 11] FIG. 2 is a functional block diagram of another example of a PLL function according to embodiments disclosed herein. [Figure 12] 4 is an example of a graph of a loop response of an exemplary PLL function according to an embodiment disclosed herein. [Figure 13] 4 is an example of a graph of a loop response of an exemplary PLL function according to an embodiment disclosed herein. [Figure 14] 2 is a functional block diagram of one embodiment of another system and method for signal processing of a received downlink signal in accordance with embodiments disclosed herein. [Figure 15] FIG. 2 is a functional block diagram of one embodiment of a system and method for carrier and frame acquisition of a received downlink signal in accordance with embodiments disclosed herein. [Figure 16] FIG. 1 is a functional block diagram of one embodiment of a system and method for carrier frequency acquisition according to embodiments disclosed herein. [Figure 17] FIG. 1 is a functional block diagram of one embodiment of a system and method for carrier frequency acquisition according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] An embodiment of an improved communication system is disclosed that uses a general-purpose processor to achieve high-speed processing. The embodiments disclosed herein provide an improved communication system that can utilize a general-purpose processor to efficiently achieve high-speed signal processing. After reading this description, it will become apparent to one skilled in the art how the invention can be implemented in various alternative embodiments and alternative applications. However, while various embodiments of the invention are described herein, it is understood that these embodiments are presented by way of example and illustration only, and not limitation. As such, this detailed description of various embodiments should not be construed as limiting the scope or breadth of the invention, as set forth in the appended claims.

[0025] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Although communication systems are used as the primary example throughout the description, the application of the disclosed methods is not limited thereto. For example, any wireless or radio communication system requiring the use of digital signal processing, modems, etc., may implement the systems, methods, and computer-readable media described herein.

[0027] The present disclosure provides systems and methods for performing digital signal processing using general purpose central processing units (CPUs) in either standard server or virtual cloud environments. In some examples, the systems can employ single instruction multiple data (SIMD) techniques to achieve high throughput, including SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX512 instruction sets. The present disclosure describes how data processing is managed across multiple processing cores of a processor (such as a CPU) to achieve the required throughput without the use of dedicated signal processing hardware, such as field programmable gate arrays (FPGAs), or high performance computing (HPC) hardware, such as graphics processing units (GPUs). Because this processing can be performed on general purpose server CPUs, including but not limited to x86 architectures from Intel and AMD microprocessors, as well as ARM processors such as Cortex-A76, NEON, and AWS Graviton and Graviton2, these functions can be deployed in general purpose cloud processing environments using virtualized processing architectures without the need for dedicated hardware. Processing in the general purpose CPU is made possible by a digital IF appliance that samples the analog signal and provides digitized samples to the CPU via an Ethernet connection. The digital IF appliance can also accept digitized samples and convert them to an analog signal, similar to that described in U.S. Patent No. 9,577,936, entitled "Packetized Radio Frequency Transport System," issued February 21, 2017, the contents of which are incorporated by reference in their entirety.

[0028] No. 10,790,920, the disclosure of which is incorporated herein in its entirety, provides a method and system for demodulating a digitized downlink signal to achieve high speed processing. For example, U.S. Pat. No. 10,790,920 provides a timing recovery process and a carrier recovery process that are performed on overlapping portions of adjacent blocks of data to synchronize the digitized downlink signal. To perform carrier or timing recovery using feed-forward signal processing, for example, as described below in connection with FIGs. 3 and 4, the blocks of data must be processed to obtain the appropriate phase information. In the case of timing recovery, the information obtained is timing phase information, and in the case of carrier recovery, the information is carrier phase information. There are several approaches to deriving the phase information. For example, as described in U.S. Pat. No. 10,790,920, the signal may be fed into a phase detector and then filtered and decimated before being fed into a curve-fitted filter calculator. This approach works well for stable signals. However, actual downlink signal implementations may have discrepancies that cause phase jumps, which may prove problematic for the curve-fitted filter calculator. For example, the phase of the carrier and timing of the downlink signal may jump quickly due to imperfections in the transmitter or any number of reasons, so that a curve-fitting filter may be insufficient to use for tracking, i.e., a curve fit (e.g., linear, quadratic, parabolic, or any other algebraic equation) that can account for such phase jumps cannot be determined.

[0029] Accordingly, the embodiments described herein provide methods and systems configured to demodulate digitized downlink signals to achieve high speed processing capable of handling phase jumps, phase noise, and / or mismatches in the downlink signals. For example, the embodiments described herein perform a phase-locked loop (PLL) function on the decimated data. As used herein, a "PLL function" may refer to any type of PLL, such as, for example, a second order PLL, a third order PLL, or any PLL function known in the art. Other exemplary PLLs include, but are not limited to, a reciprocal PLL (RPLL) and a reciprocal iterative PLL (RIPPL), both of which are described below in connection with FIG. 11. Performing a PLL function on the decimated data may provide several advantages, such as, but not limited to, operating similarly to standard feedback receive employing a PLL, which is a common receiver implementation, and is beneficial to maintain consistency with that approach, and can handle rapid and unpredictable phase jumps or phase noise that curve-fitting filters simply cannot handle.

[0030] When estimating the carrier and timing phase of a downlink signal, it may be necessary to calculate three components for each block of data in the downlink that is processed. For example, it may be necessary to calculate the average starting phase, the average frequency (also called Doppler), and the average rate of change of frequency (also called Doppler velocity). Estimation of each component may be possible prior to processing via one or more carrier and frame acquisition techniques, for example as described below in connection with FIG. 15n. In some implementations, it may be sufficient to assume that the Doppler and Doppler velocity are known so that the PLL does not cycle slip at run time.

[0031] One drawback of using a PLL to estimate phase is the initial loop response (e.g., but not limited to, impulse response, step response, ramp response, etc.) that occurs at PLL startup, which is common to all feedback loops. Embodiments herein provide systems and methods to account for the initial loop response or otherwise remove loop response drawbacks from the process.

[0032] One approach to solving the loop response of the PLL is to process blocks of samples consecutively. However, this cannot be scaled to run simultaneously on multiple processors because the PLL is a state machine and cannot execute a subsequent block of samples until the current block of samples has been processed, and is therefore speed limited. Preferably, each block of samples in the downlink is processed independently, so that it can run on as many processors as necessary, without regard to adjacent data blocks, to achieve the desired throughput.

[0033] Another approach to solving the initial loop response is to utilize overlap between adjacent blocks of data to ensure that the PLL is stable by the time the non-overlapping data is processed. In this approach, the overlapping data from a block of processed data can be used to synchronize a subsequently processed adjacent block of data while the loop response of the PLL is stable. This can be an effective method and computationally efficient when the mount of overlapping data is small compared to the overall size of the block of data being processed. Regardless of which implementation may be used with any PLL function, such as, but not limited to, a third order PLL, a RPLL, a RIPLL, or any other PLL known in the art, the various embodiments disclosed herein utilize a second order PLL with the overlapping data approach. However, as the size of the block of data decreases, the ratio of overlapping data to non-overlapping data increases, and the time of the PLL loop response does not change for a certain time with a fixed loop bandwidth. The increase in the ratio may adversely affect the performance of the CPU because the overlapping data must be processed at the sample rate or symbol rate before decimation. According to some embodiments disclosed herein, the degree of overlap can be reduced and even eliminated, for example, by using a reversible PLL (RPLL) and / or a reversible iterative PLL (RIPLL), which are described in more detail below.

[0034] In certain cases, overlapping blocks of data may not be feasible. For example, certain types of waveforms prohibit overlapping data. Examples of such waveforms include, but are not limited to, burst waveforms and framed waveforms. For burst waveforms, signals come and go, each containing blocks or bursts of data packets, and overlapping data may not be an option. One example of a burst waveform is Time Division Multiple Access (TMDA). In TDMA, many users share the same frequency and are assigned time slots to transmit. For burst waveforms such as TDMA, each time a user transmits, acquisition is desirable to start from the beginning and recover all data transmitted, even data at the beginning. In some cases, there is a preamble that allows time for the receiver to lock, but this is not always the case. In those cases, loop response must be considered. TMDA is an example, and any burst waveform may be used in accordance with the embodiments disclosed herein. In the case of framed waveforms, such as but not limited to DVB-S2, DVB-S2x, certain CCSDS waveforms utilizing LDPC or Reed-Solomon forward error correction (FEC), or any other type of framed waveform, contain framed data packets that may cause problems due to the use of overlapping data for synchronization. For example, certain framed waveforms may change modulation and coding type from frame to frame at frame boundaries, thus inhibiting synchronization over the overlapping portions. Therefore, it may be beneficial to recover carrier information on a frame-by-frame basis independently, without using the overlapping portions. In this specification, burst waveforms and framed waveforms are collectively referred to as framed waveforms, and blocks of data contained thereby are referred to as blocks of framed data packets, framed data packets, or framed data. Each block of framed data may be referred to as a frame of data.

[0035] Before carrier recovery of a block of framed data can be performed, the frame boundaries of the frames of data may need to be located. The frame boundaries of each frame may be located by detecting a known pattern (herein referred to as a frame marker) placed at the beginning of the frame of data. In the case of a framed waveform, the frame marker may be an attached synchronization marker (ASM). In the case of DVB-S2 and DVB-S2x, the frame marker may be the PLHEADER, and the frame boundaries may be found by detecting the PLHEADER for each frame of data.

[0036] Once the frame boundaries are located, the phase can be calculated using a phase detector. Each frame of data may have a different modulation type, and the phase detector needs to be able to accommodate all possible modulation types. For example, for a QPSK waveform, the signal is raised to the fourth power, resolving the four IQ constellation dots into one dot. The phase is then calculated by taking the arctangent of the signal. There are many approaches to calculating the phase, as known in the art. For DVB-S2, the modulation types include QPSK, 8PSK, 16APSK, and 32APSK, and the frames are called PLFRAMES and can vary in size. In the general case, any modulation type can be used, not just fixed or variable size frames. In embodiments that utilize overlapping data, the modulation type is assumed to be a fixed modulation type that is common to each block of data. Thus, embodiments that utilize overlapping do not need to change the phase detector between adjacent blocks of data. In these cases, overlapping of data is a viable option for synchronizing blocks of processed data. However, with framed data, a change in modulation type would require a different phase detector.

[0037] 1 is a graphical representation of an embodiment of a communication system. The communication system (system) 100 may include a platform 110 and a satellite 111 in communication with multiple ground stations. The platform 110 may be an aircraft (e.g., an airplane, a helicopter, or an unmanned aerial vehicle (UAV), a missile, a boat, etc.). The multiple ground stations 120, 130, 140 may be associated with a terrestrial radio frequency (RF) antenna 122 or one or more satellite antennas 132, 142. The ground station 120 may include an antenna 122 coupled to a digitizer 124. The digitizer 124 may include one or more analog-to-digital (A2D) converters for converting analog signals received at the antenna 122 into a digital bit stream for transmission over a network. The digitizer 124 may also include a corresponding digital-to-analog (D2A) converter for operation on the uplink to the platform 110 and the satellite 111.

[0038] Similarly, ground station 130 may have an antenna 132 and a digitizer 134 , and ground station 140 may have an antenna 142 and a digitizer 144 .

[0039] In the receive chain, the ground stations 120, 130, 140 can receive downlink signals 160 (labeled 160a, 160b, 160c) from the platform 110 and downlink signals 170 (labeled 170a, 170b, 170c) from the satellite 111, respectively. In the transmit chain, the ground stations 120, 130, 140 can also transmit uplink signals via antennas 122, 132, 142, respectively. The digitizers 124, 134, 144 can digitize the received downlink signals 160, 170 as digital bit streams 154 for transmission. The digital bit streams 154 can then be transmitted to the cloud processing system via the network 152. The digital bit streams 154 can be transmitted to the cloud processing system as packets that are collected at the cloud processing system into data packet blocks for processing.

[0040] In some examples, the ground stations 120, 130, 140 can process all of the data (e.g., contained in the downlink signal) locally, but this can be very expensive in terms of time, resources, and efficiency. Thus, in some embodiments, the downlink signal can be digitized and transmitted as a digital bit stream 154 to a remote signal processing server (SPS) 150. In some implementations, the SPS 150 can be located in a physical location, such as a data center located in an off-site facility accessible via a wide area network (WAN). Such a WAN can be, for example, the Internet. The SPS 150 can demodulate the downlink signal from the digital bit stream 154 and output data or information bits from the downlink signal. In some other implementations, the SPS 150 can use cloud computing or cloud processing to perform the signal processing and other methods described herein. The SPS 150 can also be referred to as a cloud server.

[0041] The SPS 150 can then provide the processed data to a user or transmit it to another site. The data and information can be mission dependent. Additionally, the information contained in the data can be the primary purpose of the satellite, including weather data, image data, and satellite communications (SATCOM) payload data. As mentioned above, although SATCOM is used as the primary example herein, any communications or signal processing system that uses a DSP can implement the methods described herein.

[0042] To achieve high processing speeds in software, traditional phase-locked loop (PLL) or delay-locked loop (DLL) approaches can be problematic due to feedback in the loop before decimation. The feedback loop forces all incoming data (e.g., downlink signals 160 and / or 170) to be processed by a single (e.g., linear) process that cannot be easily divided or otherwise separated. In addition to feedback, there are other obstacles to overcome using a PLL / DLL, including, for example, the frequency at which error terms must be calculated.

[0043] Figure 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of Figure 1. A processing device (device) 200 may be implemented, for example, as the SPS 150 of Figure 1. The device 200 may be implemented as needed to perform one or more of the signal processing methods or steps disclosed herein.

[0044] The device 200 may include a processor 202 that controls the operation of the device 200. The processor 202 may also be referred to as a CPU. The processor 202 may, for example, direct and / or execute functions attributed to the SPS 150. Certain aspects of the device 200, including the processor 202, may be implemented as various cloud-based elements, such as cloud-based processing. Thus, the processor 202 may represent cloud processing distributed across several different processors over a network (e.g., the Internet). Alternatively, certain components may be implemented in hardware. The processor 202 may be implemented by any combination of one or more of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gate logic, discrete hardware components, a dedicated hardware finite state machine, or any other suitable entity capable of performing calculations or other manipulations of information.

[0045] The processor 202 may have one or more cores 204 (illustrated as cores 204a through 204n) capable of performing computations. In implementations using cloud processing, the cores 204 may represent multiple iterations of distributed cloud processing. In some embodiments, the processor 202 may be a complex integrated circuit that uses hardware to perform all computations for the receiver. As used herein, each core 204 may be one processing element of the processor 202. The processor 202 may implement multiple cores 204 to perform the parallel processing required for the methods disclosed herein. In some embodiments, the processor 202 may be distributed across multiple CPUs, such as in cloud computing.

[0046] The device 200 may further include a memory 206 operably coupled to the processor 202. The memory 206 may be a cloud-based storage or a local hardware storage. The memory 206 may include both read-only memory (ROM) and random access memory (RAM) and may provide instructions and data to the processor 202. A portion of the memory 206 may also include non-volatile random access memory (NVRAM). The processor 202 typically performs logical and arithmetic operations based on program instructions stored in the memory 206. The instructions in the memory 206 may be executable to implement the methods described herein. The memory 206 may further include a removable medium or a plurality of distributed databases.

[0047] The memory 206 may also include a machine-readable medium for storing software. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or the like. The instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable code format). The instructions, when executed by the processor 202 or one or more cores 204, cause the device 200 (e.g., SPS 150) to perform various functions described herein.

[0048] The device 200 may also include a transmitter 210 and a receiver 212 to enable transmission and reception of data between the communication device 200 and a remote location. Such communication may occur between the ground station 120 and the SPS 150, for example, via the network 152. Such communication may be wireless or wired communication. The transmitter 210 and the receiver 212 may be combined into a transceiver 214. The transceiver 214 may be communicatively coupled to the network 152. In some examples, the transceiver 214 may include or be part of a network interface card (NIC).

[0049] The device 200 may further include a user interface 222. The user interface 222 may include a keypad, a microphone, a speaker, and / or a display. The user interface 222 may include any element or component that communicates information to and / or receives input from a user of the device 200.

[0050] The various components of the device 200 described herein may be coupled together by a bus system 226. The bus system 226 may include, for example, a power bus, a control signal bus, and a status signal bus in addition to a data bus. In some embodiments, the bus system 226 may be communicatively coupled to the network 152. The network 152 may provide, for example, a communication link between the device 200 (e.g., the processor 202) and the ground station 120. Those skilled in the art will appreciate that the components of the device 200 may be coupled together or may accept or provide input to each other using some other mechanism, such as a local area network or a wide area network for distributed processing.

[0051] 3 is a schematic block diagram graphical depiction of one embodiment of feedforward or pre-computed signal processing 300. Method 300 can be performed as a generalized process incorporating multiple functions, for example, by processor 202. Processor 202 can execute multiple functions in a serial or parallel arrangement, as shown, to perform one or more desired processes. Each function may refer to a block or collection of instructions or software executable by processor 202 and stored in memory 206.

[0052] The first function 302 may be executed by the processor 202. In some embodiments, the second function 304 may be executed sequentially following the first function 302. Thus, the processor 202 may execute the first function 302 and the second function 304 by dividing a block of data with different functions for processing across multiple cores 204.

[0053] The processor 202 can perform distributed processing of the third function 306 (illustrated as 306a, 306b, ... 306n) in parallel following the second function 304. To indicate that various numbers of functions 306a-306n may operate in parallel, three paths are depicted with three vertical dots between them, indicating that any number of paths may be included, such as but not limited to 4, 5, 6, etc. The parallel processing of the third function 306 may include, for example, dividing a block of data associated with the same function across several cores 204 (e.g., processing blocks) of the processor 202. For example, a "block of data" may refer to a group of samples that need to be processed.

[0054] The term "parallel" is used herein to describe processing occurring simultaneously in blocks 306a-306n. Because packets being processed may be of different lengths from one block 306a-306n to another, processing of packets may have the same rate or speed from one block 306a-306n to the next. As shown below, some of the blocks 306a-306n may proceed faster or slower than other blocks. Thus, the term parallel should not be limited to simultaneous or parallel processing within blocks 306a-306n.

[0055] The processor 202 may then sequentially execute a fourth function 308 and a fifth function 309. Similar to the first function 302 and the second function 304, the sequential execution of the fourth function 308 and the fifth function 309 may include dividing up blocks of data associated with different functions for processing across multiple cores 204. In general, each of the first function 302, the second function 304, the third function 306, the fourth function 308, and the fifth function 309 may be executed in a different processing block. As used herein, a processing block may refer to a particular task performed on a block of data. A processing block may be associated with one or more cores 204, for example.

[0056] Thus, method 300 may, for example, divide blocks of data with the same function for processing across multiple cores 204. Similarly, method 300 may divide blocks of data with different functions for processing across multiple cores 204.

[0057] In some other implementations of method 300, the same processing block (e.g., core 204), whether the same function or a different function, may perform single instruction multiple data (SIMD) processing of data.

[0058] In some implementations, embodiments of the method 300 can support processing of data blocks with minimal state information by using duplicated data. As used herein, state information can include variables required during feedback (e.g., feedback processing), data frame boundaries, etc. For example, in the case of a feedback loop, the state information can include variables calculated within the loop required during feedback when processing a continuous data stream. The state information can also include the location of frame boundaries within the data stream. Other examples can include things such as FIR filters, where the state information includes buffered values ​​(e.g., potentially many delay elements) required to maintain a continuous data flow.

[0059] By ignoring state information and overlapping portions of adjacent data blocks, processes can use variable levels of overlap between data blocks to exploit parallelism.

[0060] In other implementations, embodiments of the method 300 may support processing framed data. For example, certain framed waveforms may change modulation and coding type at frame boundaries, thus inhibiting synchronization. Therefore, it may be beneficial to recover carrier information for each frame independently, without using overlapping portions. By ignoring overlapping portions of adjacent blocks of data, the process can take advantage of parallel processing by recovering carrier information for each frame of data independently of other frames of data. Processing frames of data consecutively and independently may be utilized to modify the loop response of the PLL.

[0061] Figure 4 is a graphical depiction of one embodiment of the method for feedforward or pre-computed signal processing of Figure 3. The method 400 can use the principles of the method 300 for serial-parallel and / or parallel-serial processing for multiple functions grouped as processes 315. In one example, the first function 302 (Figure 3) can be a data capture function 305 where the processor 202 receives data for processing. The second function 304 (Figure 3) can be a data partitioning function 310 where the processor 202 can parse the data in data blocks.

[0062] In some embodiments, the data splitting function 310 parses the data into overlapping data blocks. The overlapping data blocks can then be processed in parallel in various parallel iterations of multiple functions as processing blocks 315a-315n. For example, a first data block can be processed by a group of functions in processing block 315a, and another block of data can be processed by a group of functions in another processing block 315b-315n executed in parallel with processing block 315a. Multiple processing blocks 315a-315n can be executed in parallel and are not limited to two such processing blocks. The overlap in the data blocks can provide a level of redundancy that relies less (or not at all) on state information. The less state information required, the easier it is to process the data blocks in parallel as opposed to a continuous stream. To show that various numbers of processing blocks 315a-315n can operate in parallel, three paths are depicted with three dots in a vertical direction between them, indicating that any number of paths can be included, such as, but not limited to, 4, 5, 6, etc.

[0063] In the case of a framed waveform, blocks of data may be received, each including a frame marker indicating each frame of data to be captured by block 305. Block 310 identifies the frame markers within the blocks of data and then assigns one frame of data per processing block 315a-315n. The frames of data may then be processed independently and in parallel at various parallel iterations of multiple functions as processing blocks 315a-315n. For example, a first frame of data may be processed by a group of functions within processing block 315a, and another frame of data may be processed by a group of functions within another processing block 315b-315n that was executed in parallel with processing block 315a. Multiple processing blocks 315a-315n may be executed in parallel and are not limited to two such processing blocks. As mentioned above, three paths are depicted with three vertical dots between them to indicate that various numbers of processing blocks 315a-315n may operate in parallel, and may include any number of paths.

[0064] The term "parallel" is used herein to describe processing occurring simultaneously in the processing blocks 315a-315n. Because the packets being processed may be of different lengths from one processing block 315a-315n to another, the processing of the packets may have the same rate or speed from one processing block 315a-315n to the next. As will be shown below, some of the blocks 315a-315n may proceed faster or slower than other blocks. Thus, the term parallel should not be limited to simultaneous or parallel processing within the processing blocks 315a-315n.

[0065] The method 400 may further include a data combining function 320, similar to the fourth function 308 (FIG. 3), for combining the processed data, and a data output function 325, similar to the fifth function 309 (FIG. 3).

[0066] In a further example, the adjustable series-parallel or parallel-series arrangement of the various functions of method 300 provides several ways of implementing feedforward processing to replace feedback loops, which is advantageous as it can increase throughput and avoid bottlenecks caused by delays in feedback processing.

[0067] An additional advantage of the serial-parallel or parallel-serial processing provided by methods 300 and 400 is that placing one or more desired algorithms within a processing block (e.g., one of the five processing blocks of method 300) allows processor 202 to distribute the processing load (e.g., across multiple cores 204) without concern for the speed of a given algorithm within a processing block (e.g., core 204). Thus, each core 204 shares the exact same processing load, eliminating bottleneck problems caused by individual algorithms.

[0068] Further advantages of embodiments of the method 300 may include customizing the ordering of specialized algorithms (e.g., processing blocks) to reduce computational load within the processor 202. As described below, the overall multi-step processing of a given process may not depend on the ordering of multiple sub-processes. Thus, in some examples, ordering the fourth function 308 may have certain advantages if performed before the third function 306.

[0069] The method 300 can further implement different variable types, such as int8, int16, and float, for memory bandwidth optimization, which can accelerate certain algorithms (e.g., algorithms based on type), and can further improve flexibility and maximize memory bandwidth.

[0070] 5, 6, and 14 are functional block diagrams of embodiments of signal processing of a downlink signal according to various embodiments disclosed herein. Methods 500, 600, and / or 1400 may include feedforward block processing as described above in connection with FIGS. 3 and 4. Methods 500, 600, and / or 1400 may include multiple blocks. In some examples, each block may represent a functional block and perform functions similar to functional blocks 306a, 306b, ... 306n (FIG. 3), etc. In another example, two or more of the multiple blocks in FIG. 5 and / or FIG. 6 may be grouped together as a single "process" 315 that performs functions similar to processing blocks 315a, 315b, ... 315n (FIG. 4), etc.

[0071] FIG. 15 is a functional block diagram of an embodiment of carrier and frame acquisition of a received downlink signal according to an embodiment disclosed herein. Method 1400 may include the feedforward block processing described above in connection with FIG. 3 and FIG. 4. Method 1400 includes a number of blocks. In some examples, each block may represent a functional block and perform a function similar to functional blocks 306a, 306b, ... 306n (FIG. 3), etc. In another example, two or more of the blocks of FIG. 9 may be grouped together as a single "process" 315 that performs a function similar to processing blocks 315a, 315b, ... 315n (FIG. 4), etc.

[0072] In block 305, the SPS 150 may capture or otherwise receive (e.g., over the network 152) the digital bitstream 154. The data capture in block 305 may receive the digital bitstream data from a network connection (e.g., Ethernet).

[0073] At block 310, the data may be split into parallel data streams by a data splitter. In some embodiments, the processor 202 may perform the data splitting functions required at block 310. In some other embodiments, a separate data splitting component (e.g., a data splitter) may be included in the device 200 (FIG. 2). Splitting the data into multiple parallel streams may enable parallel processing of downlink signals, such as downlink signals 160, 170. Thus, the method 300 may utilize feed-forward or pre-computation processing, splitting the incoming digitized signal data into smaller portions before processing by multiple cores 204.

[0074] In some implementations, the digital bit stream 154 may be split to form overlapping packets in in-phase / quadrature (I / Q) pairs. In some embodiments, an "overlapping packet" may include data packets where successive packets overlap adjacent data packets. In some embodiments, the data packets may all be of the same length, but may overlap. The overlap in a data packet may be at the beginning or end of the data packet. Furthermore, a data packet may overlap both a preceding data packet and a following data packet. The data packets may also have different lengths (e.g., varying amounts of data). Thus, a first packet sent to processing block 315a may overlap or otherwise repeat certain data of a second packet sent to processing block 315b.

[0075] The amount of overlap, or overlap size, between packets is programmable and can be set as needed. In some examples, the overlap can be set to one percent (1%) of the packet size. This overlap size can be increased or decreased as needed. For example, one particular parameter that can affect the overlap size is the uncertainty of the symbol rate in the digital bit stream 154. For most signals, the worst case uncertainty is less than 1%, so a 1% overlap covers most cases. In some other embodiments, the overlap can be as high as 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%, or anywhere in between, as needed. It is also possible to have an overlap of less than 1% as well. If the uncertainty in the data rate is less than 0.1%, the overlap can be 0.1% or less.

[0076] In another implementation, the digital bit stream 154 may be divided into framed data packets according to frame markers included with the blocks of data in the digital bit stream 154. In some embodiments, the blocks of data on the digital bit stream 154 may include one or more frame markers. In some embodiments, a frame of data may be distributed across multiple blocks of data, e.g., a frame marker indicating the beginning of a frame is in a first block of data and a frame marker indicating the end of a frame is included in a subsequent block of data. In some embodiments, a "framed data packet" may include data packets where successive packets have a variable coded modulation (VCM), such as DVB-S2, DVB-S2x, etc. In some embodiments, each frame of a data packet may vary between each other, e.g., phase, modulation, and length variations.

[0077] The processor 202 can implement single instruction multiple data (SIMD) processing on the digital bit stream 154. In some examples, SIMD can include Advanced Vector Extensions (AVX-512) using 512 bits, which allows 16 floating point operations on a single CPU core with a single CPU instruction. For example, AVX-512 allows a CPU (e.g., CPU 202) to process vast amounts of data. For example, the processor 202 (and device 200) can receive a data stream with a 500 MHZ bandwidth. The 500 MHz bandwidth is significant in some respects because it is the commonly accepted practical limit of a 10 Gigabit Ethernet link. Sampling data at 500 MHz with 8-bit samples for the I / Q pairs, including the parity bits, can saturate a 10 Gbit Ethernet link. The 500 MHz example is not limiting of the disclosure. Data pipes larger than a 10 Gbit Ethernet link are possible. Furthermore, the process can be divided into n parallel blocks (eg, block 315) to accommodate any amount of data.

[0078] Process 315 is shown as a dashed line and illustrates processing steps of method 300. Process 315 is shown to be performed in multiple parallel steps or processing blocks 315a, 315b, ... 315n.

[0079] A process 315 as used herein may refer to a collection of processing functions performed by, for example, the processor 202. The digital bitstream 154 may be sent to multiple parallel processing blocks 315a, 315b, ... 315n to distribute the processing load across several cores 204. Each individual processing block 315a, 315b, ... 315n may represent an individual iteration of cloud processing. Thus, each processing of the processing blocks 315a-315n may be associated with a (cloud-based) core 204a-204n. The number of processing blocks 315a-315n required varies based on the amount of data to be processed. In some embodiments, the number of processing blocks 315a-315n may be limited by the number of available logical cores, either over the network 152 or within the processor 202 in the case of local hardware processing. In some other embodiments, memory bandwidth constraints may cause a bottleneck during signal processing. Memory bandwidth may refer to the rate at which data can be read from or stored in a semiconductor memory (eg, memory 206) by a processor (eg, processor 202).

[0080] In some embodiments, the number of processing blocks 315a-315n may vary. In general, the fewer processing blocks 315a-315n there are, the more appropriate it is to limit the number of cores required for the entire process. This further allows the system to fit into smaller virtual private cloud (VPC) machines that are less expensive to operate. A VPC may include, for example, an SPS 150 with several CPUs. In some embodiments, eight processing blocks 315a-315n may be used for a 10 Gbit Ethernet link. Such an embodiment may not include a forward error correction processing block. In other embodiments, the only practical limit to the number of processing blocks 315a-315n required is the bit rate and bandwidth (e.g., pipe size) of the communication link. However, any number (n) of processing blocks 315a-315n is possible. However, in some embodiments, a practical limit to the number (n) of processing blocks 315a-315n may exist based on the number of threads that can run on a CPU or the number of cores 204 in the processor 202. However, if limitations are reached within a single CPU, multiple CPUs (e.g., processors 202) within the SPS 150 (e.g., VPC) together can have an unlimited number of cloud-based CPUs or cores 204 to perform processing. Additionally, processor 202 can create new processing blocks 315a-315n as needed. Processing cores 204 can be distributed across multiple distributed processors (e.g., processors 202) as needed for throughput and efficiency.

[0081] In another example, the number of processing blocks 315a-315n may be based on the ingestion rate at which the block 305 captures blocks or frames of data, and the processing capability (e.g., processing rate) of each processing block 315a-315n, which is the rate at which each block can process blocks or frames of data. For example, the number of processing blocks 315a-315n may be determined by dividing the ingestion rate by the processing rate. As an illustrative example, if the ingestion rate is 20 blocks or frames of data captured per microsecond and each processing block 315a-315n takes 1 microsecond to process each block or frame of data, then 20 processing blocks 315a-315n may be the minimum number (n) of processing blocks. If fewer than 20 processing blocks are used, then a bottleneck may occur and blocks may be held in a buffer while a process block completes a process. In some embodiments, the processing rate may be the average processing rate of all processing blocks. In another example, the lowest processing rate may be used as the overall processing rate to ensure that all processing blocks are completed.

[0082] The processing blocks 315a-315n are arranged in such a way that it does not matter which processing block 315a, 315b, ... 315n executes slowest (or fastest). The method 300 can share the processing load across the processing blocks 315a-315n, thereby mitigating any processing delays caused by bottleneck problems in the individual processing blocks 315a-315n. For example, the individual sub-processes of the processing blocks 315a-315n (see the description of FIG. 4 below) may not or may not execute at equal speeds (e.g., some faster than others). Thus, for example, the larger processes of the method 400 (FIG. 4) may be the main source of variation in performance or processing time. Processing blocks 315 can be created as many times as necessary to process the incoming data.

[0083] In some embodiments, each processing block 315a-315n may represent a collection of signal processing algorithms executed by the processor 202. As used herein, an algorithm may refer to a minimum collection of functions or method steps that perform a desired function. Several exemplary algorithms are described herein.

[0084] An exemplary advantage of method 300 is the ability to create more processing blocks 315a-315n as needed. In general, processing blocks 315a-315n can be implemented in software and therefore can be created or removed as needed to suit a given data rate or processing load. Each processing block 315a-315n can be rearranged to suit the needs of different received waveforms (e.g., downlink signals 160 and / or 170) and associated digital bitstream 154.

[0085] In block 320, the processed signal data from the multiple processing blocks 315 may be recombined to form the original data encoded and modulated on the downlink signal 160, 170. In some embodiments, the processor 202 may perform the function of a data recombiner. In other embodiments, the device 200 may have additional components for performing such functions. Each data packet or processed data block may have a timestamp. The data recombiner (e.g., the processor 202) may order the data blocks based on the timestamp and compare the phase between the ordered blocks. The recombiner may further adjust the phase of adjacent blocks to reorder the data stream. In some embodiments, the phase of a subsequent data block may be adjusted to match the phase of a preceding data block.

[0086] Every processing block shown in process 315 has at least four options for execution. 1) Execution of multiple blocks, where each sub-element within a processing block 315 (e.g., each block 315a-315n) gets its own core (e.g., cores 204a-204n); 2) execution of multiple blocks, where the processing block 315 gets only one dedicated core for the entire block; 3) single block execution, where each subelement in the processing block gets its own core; and 4) Single block execution, where the processing block gets only one dedicated core for the entire block.

[0087] The more cores you can run on, the faster the speeds you can achieve.

[0088] In block 325, the device 200 may output the data to an appropriate receiver. In some examples, such receivers may be one or more mission operations centers. This data may be mission dependent (e.g., the purpose of the satellite) and may include weather data, image data, and SATCOM payload data, among others.

[0089] In a general-purpose CPU, there are at least three main factors that can limit high-speed performance: 1) data ingestion, 2) CPU capacity, and 3) memory bandwidth utilization. Data ingestion refers to how fast data can be fed to the CPU. CPU capacity is determined by the CPU clock speed and the number of cores in the CPU. Memory bandwidth refers to how fast data can be transferred between the CPU and external DDR RAM (not the CPU cache). Memory bandwidth may be determined by the number of memory lanes and the clock speed of the DDR RAM. In certain cases, the limiting factor for achieving high-speed processing is CPU capacity, while in other cases it is memory bandwidth. Care must be taken to determine which of the above cases is affecting performance, and if memory bandwidth is limited, the embodiments described below are non-limiting examples of how to reduce memory bandwidth utilization within the proposed patent approach.

[0090] The function calls within a given processing block can be arranged in such a way as to optimize the utilization of CPU computation or memory bandwidth. For example, with reference to the function calls shown in FIG. 5 (illustrated as blocks), for the given example, the various function calls (e.g., timing recovery error calculation block, timing recovery block, carrier recovery error calculation block, and carrier recovery block) can be grouped to minimize memory bandwidth. These function calls can be called independently so that each function is completed on the data set before another function begins, thus simplifying each function. In another example, multiple or all function calls can be combined into one block, so that data is not transferred to RAM after each function execution, and the memory bandwidth of the combined functions is much smaller than if they were called independently. If the functions were called independently, the first function call (e.g., timing recovery error calculation) can be performed over the entire data set before the second function call (e.g., timing recovery) would occur. If combined, only a portion of the data would be processed in the first function call before the second function call is executed. In this way, memory bandwidth is reduced. This method may be applied to any grouping of functions, not just the functions shown in FIG. 5. For example, the method may be applied to the method shown in FIG. 6 or any other grouping for function calls performed in the blocks disclosed herein (e.g., the various function call blocks shown in FIGS. 7-9, 14, and 15).

[0091] Another way to improve memory bandwidth utilization may be to collapse some function call blocks into one block, similar to the approach above. For example, multiple functions may be required to perform timing and / or carrier recovery, as described in more detail below with reference to Figures 5, 6, 14, and 15. Typically, for ease of operation and CPU optimization, each function may require its own block, but to reduce memory bandwidth utilization, the functions may be grouped into one or more processing blocks, each of which contains multiple function blocks. This tradeoff results in reduced memory bandwidth utilization in exchange for a CPU hit performance.

[0092] 5 is a functional block diagram of an example of a method for signal processing of a received downlink signal according to an embodiment disclosed herein. For example, FIG. 5 shows a method 500 including a plurality of blocks, one or more of which may be implemented as a process 315, such that a grouping of blocks is processed in each of the processing blocks 315a-315n of FIG. 4. Each of the blocks of the method 500 may also be implemented as a function 306, such that a single block may perform across the functions 306a-306n of FIG. 3. The execution of the blocks according to FIG. 3 may be performed separately or in combination with the execution of the process according to FIG. 4.

[0093] Method 500 can be used for standard waveform processing, as opposed to offset waveforms described below. For example, standard waveform processing can be used for waveforms that map bits to symbols and then modulate those symbols onto a carrier. Examples of standard waveforms include binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 8PSK, 16APSK, 32APSK, and 64APSK, as well as quadrature amplitude modulation (QAM) waveforms.

[0094] In block 505, the processor 202 (e.g., one or more of the cores 204) can perform a timing recovery error calculation on a received data packet (e.g., samples of the digitized bit stream 154, or the digitized downlink signals 160 and / or 170 received by the receiver 212). The timing recovery error calculation can provide the phase information necessary to properly align a matched filter to the incoming data stream (e.g., the digitized bit stream 154). The matched filter is used to match the transmitted waveform in the time domain, and is aligned with the timing error to capture all the energy in the received signal and optimize performance. An example of the process of block 505 is described in connection with FIG. 7. The result of the timing recovery error calculation may include three parameters: 1) starting phase (in degrees), 2) frequency adjustment (in Hertz (Hz)), and 3) Doppler velocity adjustment (in Hz / sec). The units listed above are exemplary and are not limiting of the present disclosure. Other equivalent units are possible.

[0095] In block 510, the processor 202 (e.g., one of the cores 204) can perform timing recovery on the packet to align the internally generated matched filters to the received samples generated by the respective matched filters of the modulators. The alignment is based on the calculations of block 505. The output of block 510 are synchronized (e.g., time corrected) symbols in the data packet received in block 505.

[0096] In block 520, a processor 202 (e.g., one of the cores 204) may perform carrier recovery error calculations on the packet to determine phase and frequency information. A more detailed description of one example of the functions performed in block 415 is described below in connection with FIG.

[0097] In block 525, the processor 202 (e.g., one of the cores 204) may perform carrier recovery on the packet based on the calculations of block 520. Carrier recovery compensates for unknown frequency, Doppler velocity, and phase offsets in the downlink signals (e.g., downlink signals 160 and / or 170) from the satellite 111 and / or platform 110. The two most common sources of uncertainty are Doppler effects due to satellite / platform motion and Doppler effects due to imperfect oscillators internal to the satellite / platform. In block 525, the processor 202 may apply the phase, frequency, and Doppler velocity corrections from block 520 to form synchronization symbols corresponding to the modulated data of the downlink signal at the output of block 525.

[0098] As mentioned above, the multiple blocks of method 500 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, in the illustrative example, block 505 may be implemented as function 306 of FIG. 3, such that an input example may be divided into blocks of data and processed by parallel functions 306a-306n. Similarly, blocks 510, 520, and / or 525 may be implemented as separate functions 306 and may be executed as multiple functions 306a-306n, respectively, to process multiple blocks of data in parallel.

[0099] In another example, alone or in combination, multiple blocks shown in FIG. 5 can be grouped together as a single "process" 515 that performs functions in a manner similar to process 315 of FIG. 4. That is, multiple blocks of FIG. 5 can be grouped together as process 515 and executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (FIG. 4). For example, different portions of method 500 can be grouped together as process 515 (e.g., in this example, blocks 505-525) and executed in serial-parallel and / or parallel-serial processing, as described above in connection with FIG. 4. With respect to FIG. 4, in the illustrative example shown in FIG. 5, input samples can be taken at block 305 and split into overlapping blocks of samples at block 310, and each overlapping block of data can be processed in multiple parallel iterations of process 515 as processing blocks 315a-315n. The processed overlapping data blocks are then output to a data combiner 320 for combining the processed data before being output by block 325 for processing by subsequent blocks of the method 500 .

[0100] Although a particular example of blocks are shown grouped together as process 515, this example is not intended to be limiting, and any grouping of one or more blocks of method 500 may be grouped together as process 515 and executed in parallel, as described above in connection with FIG. 4. For example, multiple blocks shown in FIG. 5 may be grouped together as multiple "processes," each of which may perform functions similar to process 315 of FIG. 4. As an illustrative example, blocks 505 and 510 of method 500 may be grouped together as a first process 515, and blocks 520 and 525 may be grouped together as a second process 515, each of which may be executed in serial-parallel and / or parallel-serial processing, as described above in connection with FIG. 4.

[0101] In various examples, the blocks of Figure 5 may be implemented using SIMD processing techniques described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the capabilities of each processing block performed using SIMD techniques may help to enhance the minimization of memory bandwidth requirements.

[0102] 6 is a functional block diagram of one embodiment of another method for signal processing of a received downlink signal according to embodiments disclosed herein. Method 500 is similar to method 400 (FIG. 4), with some of the steps being combined and rearranged. For example, FIG. 6 shows method 600 including multiple blocks, one or more of which may be implemented as a process 315, such that a grouping of blocks is processed in each of processing blocks 315a-315n of FIG. 4. Each of the blocks of method 600 may also be implemented as a function 306, such that a single block may perform across functions 306a-306n of FIG. 3. The execution of the blocks according to FIG. 3 may be performed separately or in combination with the execution of the process according to FIG. 4.

[0103] The method 600 can be used for offset waveform processing, for example, for waveforms that have an offset or shift between the in-phase (I) and quadrature (Q) channels, such as offset quadrature phase shift keying (OQPSK), minimum shift keying (MSK), Gaussian minimum shift keying (GMSK), and shaped offset quadrature shift keying (SOQPSK).

[0104] In block 605, the processor 202 may perform timing and carrier recovery error calculations on the packet. The timing and carrier recovery error calculations are similar to those performed in blocks 505 and 520 (FIG. 5). However, in method 600, carrier recovery is performed before timing recovery of the symbols. The input to method 500 is the data samples and the output is the corrected synchronization symbols. The sub-steps of block 605 are described below in conjunction with FIG. 9.

[0105] In block 625, the processor 202 may perform carrier recovery operations based on the calculations from block 605. The carrier recovery operations may be similar to those performed in block 525 (FIG. 5).

[0106] In block 610, the processor 202 may perform timing recovery operations based on the calculations from block 505. The timing recovery operations may be similar to those performed in block 510 (FIG. 5).

[0107] As mentioned above, the blocks of method 600 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, any one or more of blocks 605, 610, and 625 may be implemented as function 306 of FIG. 3, such that an example input may be divided into blocks of data and processed by parallel functions 306a-306n.

[0108] In another example, either alone or in combination, multiple blocks shown in FIG. 6 may be grouped together as a single "process" 615 that performs functions in a manner similar to process 315 of FIG. 4. That is, multiple blocks of FIG. 6 may be grouped together as process 615 and executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (FIG. 4). For example, different portions of method 600 may be grouped together as process 615 and executed in serial-parallel and / or parallel-serial processing as described above in connection with FIG. 4. In the illustrative example shown in FIG. 6 with respect to FIG. 4, input symbols may be taken in block 305 and divided into overlapping blocks of symbols in block 310, and each overlapping block of data may be processed in multiple parallel iterations of process 615 as processing blocks 315a-315n. The processed overlapping data blocks are then output to data combiner 320 to combine the processed data before being output by block 325 for processing by subsequent blocks of method 600.

[0109] Although a particular example of blocks is shown grouped together as process 615, this example is not intended to be limiting, and any grouping of one or more blocks of method 600 may be grouped together as process 615 and performed in parallel, as described above in connection with Figure 4. For example, blocks 625 and 610 of method 600 may be grouped together as process 615 and performed in serial-parallel and / or parallel-serial processing, as described above in connection with Figure 4.

[0110] In various examples, the blocks of Figure 6 may be implemented using SIMD processing techniques described throughout this disclosure. SIMD techniques may increase throughput and minimize memory bandwidth requirements. Increasing the capabilities of each processing block performed using SIMD techniques may help to further minimize memory bandwidth requirements.

[0111] 7 is a functional block diagram of an example method for a timing recovery error algorithm according to an embodiment disclosed herein. FIG 7 shows method 700, an example method for the timing recovery error calculation of block 505 of FIG 5 utilizing a phase-locked loop (PLL) function.

[0112] In block 705, the processor 202 may apply a Gardner timing error detector to the incoming data to create timing information, as is known in the art. In another embodiment, the incoming sample stream may be delayed by one sample. The undelayed data may then be multiplied by the conjugate of the delayed data (conjugate multiplication). Which one may be implemented is an engineering tradeoff, as both have advantages and disadvantages.

[0113] Both the Gardner timing error detector and the conjugate multiplication can result in timing spikes in the frequency domain. A "timing spike" appears as a single frequency tone in the frequency domain. The timing spike contains timing estimation information including the starting phase in cycles, degrees, or radians, the timing frequency offset in Hz, and the timing Doppler estimate in Hz / sec. The timing spike can be mixed to DC by the estimated symbol rate and then filtered and decimated to improve the signal-to-noise ratio and improve the accuracy of the phase, frequency, and Doppler velocity estimates. Carrier frequency and symbol rate estimates are first derived from the acquisition function. The carrier frequency and symbol rate estimates are calculated similarly to the feedforward error recovery algorithm. There are two main differences: 1) decimation is much less to allow a wider frequency range to be detected, and 2) the phase unwrap and curve fit calculations are replaced by an FFT followed by a peak search calculation. Once the initial estimates are derived, the estimates are updated later (e.g., in block 630).

[0114] Both methods have the advantage of being largely insensitive to carrier uncertainties, and therefore can be performed before carrier recovery. Another advantage of performing the timing recovery step first is that this reduces the sample rate from approximately twice (2x) the symbol rate to exactly 1x the symbol rate, so the carrier recovery algorithm runs as slowly as possible. Another advantage is that the carrier recovery loop can operate with an improved signal-to-noise ratio, since the sample rate is now half the original sample rate.

[0115] In block 710, the processor 202 may mix the timing spikes generated in block 705 with a timing estimate or an estimate of the symbol rate. When the method 700 begins, certain information about the downlink signal 152 may not be known. Thus, in block 710, the processor 202 may use an initial estimate of the symbol rate to mix with the timing spikes from block 705. This estimate is updated later, as described below. This process may mix the time spikes to DC, so that they can be easily filtered by a decimation filter. Blocks 705 and 710 may provide the timing error of the data packet / data sample.

[0116] In block 715, the processor 202 can decimate the mixed signal to reduce the sampling rate. Decimation can improve the signal-to-noise ratio because the timing spike (signal) power passes through the filter perfectly, but the noise power decreases proportionally to the decimation rate.

[0117] In block 720, the processor 202 may perform a PLL function on the decimated samples to obtain phase, frequency, and Doppler velocity offset information that can be output (e.g., to timing recovery block 510) and applied to update timing estimates in block 730. In the case of overlapping data, the PLL function may be a second order PLL. However, other PLL functions may be utilized, such as, but not limited to, a third order PLL, a higher order PLL, a RPLL, or a RIPLL. Block 720 receives the decimated samples and uses the overlap of data between data packets to ensure that the PLL is stable based on the programmed loop bandwidth by the time the non-overlapping data of the data block is processed. In some embodiments, the PLL function 720 may be pre-seeded using estimates of phase, frequency, and Doppler velocity offset information obtained through carrier acquisition techniques (such as those described in connection with block 1430 of FIG. 14 and blocks 1506 and 1520 of FIG. 15). As another example, in the case of framed data, the PLL function may be pre-seeded by calculating the frame marker phase and using this information to pre-seed the PLL function so that it starts with phase ambiguity removed. A more detailed description of one example of the functions performed in block 720 is described below in conjunction with FIG.

[0118] Although the timing recovery error algorithm of Figure 7 is described using a PLL function, the scope of the present disclosure is not intended to be limited to only such implementations. For example, in some implementations, block 720 may be replaced with a phase unwrap calculation performed on the decimated samples, as well as a curve fitting calculation to determine phase, frequency, and Doppler velocity offset information. An example of this is described in U.S. Patent No. 10,790,920.

[0119] The output of method 700 is the originally received sample and associated metadata (e.g., phase, frequency, and Doppler velocity information). Utilizing a PLL function in block 720 may provide several advantages as discussed above. First, utilizing a PPL for the feedforward processing disclosed herein may operate similarly to a standard feedback receiver using a PLL, thereby maintaining consistency. Second, utilizing a PPL for the feedforward processing disclosed herein handles rapid and unpredictable phase jumps that curve-fitting filters cannot account for.

[0120] Figure 8 is a functional block diagram of an example of a method for a carrier recovery error algorithm according to an embodiment disclosed herein. Figure 8 shows method 800, an exemplary method for the carrier recovery error calculation of block 520 of Figure 5 that utilizes a PLL function. Method 800 can be used to calculate the required phase, frequency, and Doppler velocity information and create a mixing signal to properly demodulate the incoming symbol synchronization signal.

[0121] In block 805, the incoming signal may be raised to a particular power based on the modulation type (e.g., BPSK is raised to the power of 2, QPSK is raised to the power of 4, 8PSK is raised to the power of 8). Raising a signal to a power may involve multiplying the signal by itself n times, where n is an integer. This may also be referred to herein as exponentiating the signal. The result of such a calculation is a carrier spike in the frequency domain (e.g., a continuous wave signal) that may be mixed to DC with a carrier estimate in block 810. The estimate may be generated using a center frequency for where the carrier spike will land in the frequency domain, e.g., an acquisition function described below in connection with FIG. 15.

[0122] In block 815, the processor 202 can decimate the mixed signal to reduce the sampling rate, similar to block 715 (FIG. 7) above. Decimation can improve the signal to noise ratio because the timing spike (signal) power passes through the filter perfectly, but the noise power is reduced proportional to the decimation rate.

[0123] In block 820, the processor 202 may perform a PLL function on the decimated samples, similar to block 720 (FIG. 7) above, to obtain phase, frequency, and Doppler velocity offset information that can be applied to update the carrier recovery algorithm (block 520 of FIG. 5).

[0124] In block 830 , the output from block 820 can be used to update (improve) the carrier frequency estimate of block 810 .

[0125] FIG. 9 is a flow chart of a method for timing and carrier recovery error algorithms according to an embodiment disclosed herein. FIG. 9 illustrates a method 900, which is an example method for timing and carrier recovery error calculations of block 605 of FIG. 6 utilizing a PLL function. For waveforms with a half-symbol offset between the I and Q intervals, timing and carrier recovery can be performed together. Some such waveforms may include, for example, OQPSK, MSK, GMSK. The digitized bit stream 154 can be squared (to a power of 2) in block 905. This can create two spikes in the frequency domain. Each spike can then be mixed near 0 Hz with a mixing signal created from a composite estimate of the carrier frequency and the symbol rate. The estimates can be generated using an acquisition function described below in connection with FIG. 15.

[0126] In block 910, both mixed signals are then decimated in block 915 to reduce the sampling rate.

[0127] In block 920, the processor 202 can perform a PLL function on both mixed signals, similar to block 720 of FIG. 7 and block 820 of FIG. 8. In block 820, there is a PLL function that occurs. The sum of the outputs from the two PLL functions is the carrier phase information of the signal, and the difference is the timing phase information of the signal. The output of the method 900 is the originally received samples and associated metadata (e.g., phase, frequency, and Doppler rate information). However, unlike blocks 720 and 820, the system can output both carrier estimate and timing estimate data.

[0128] In block 930, this information is updated (as in blocks 730 and 830) and passed to the carrier and timing recovery algorithms in the order shown in FIG.

[0129] FIG. 10 is a functional block diagram of an example PLL function according to an embodiment disclosed herein. In an example embodiment herein, FIG. 10 illustrates a second order PLL 1000. The second order PLL may be implemented as the PLL function of block 720 (FIG. 7), block 820 (FIG. 8), and / or block 920 (FIG. 9). As mentioned above, the PLL functions of blocks 720, 820, and 920 are not limited to the second order PLL illustrated in FIG. 10, but may be implemented as any PLL, such as a third order PLL.

[0130] PLL 1000 is an illustrative example of a second-order PLL that may be used to synchronize a received waveform with a reference waveform and output the phase information described above. PLL 1000 adjusts the input signal s[n] to an oscillator based on the phase error so that the phase error converges to zero, thereby reaching a steady state.

[0131] 10, the PLL 1000 includes a phase error detector configured to receive an input signal s[n] and determine a phase difference between a reference input waveform and a locally generated waveform. DCalculate the phase error, labeled [n] error, for the signal e D [n] is then the noise and unwanted frequency components (e.g., e D The loop filter is provided to remove the signal e F [n] to a numerically controlled oscillator (NCO) that generates a waveform that has a phase as close as possible to the reference signal. F [n] represents the frequency adjustment to the NCO at a given decimated data time slice n. The generated waveform is then fed back to the phase error detector.

[0132] In some embodiments, the reference input waveform of the PLL function 1000 may be pre-seeded using estimates of phase, frequency, and Doppler velocity offset information obtained through carrier acquisition techniques (e.g., block 1435 of FIG. 14 and blocks 1506 and 1520 of FIG. 15). As another example, in the case of framed data, the PLL function may be pre-seeded by calculating the frame marker phase and pre-seeding the PLL function with this information, so that the PLL function starts with phase ambiguity removed.

[0133] From the PLL function 1000, phase information may be output following the NCO. The phase output is an array or vector of phase elements reflecting the phase, frequency, and Doppler velocity offset information of the input signal s[n]. For example, for method 700, the PLL function at block 720 receives the decimated samples as the input signal s[n] and obtains phase, frequency, and Doppler velocity offset information that can be applied to update timing estimates at block 630 and output downstream for timing recovery at block 510 of FIG. 5. Similarly, for method 800, the PLL function at block 820 receives the decimated symbols as the input signal s[n] and obtains phase, frequency, and Doppler velocity offset information that can be applied to carrier recovery at block 525 of FIG. 5. Still further, for method 900, a PLL function at block 920 receives the decimated samples as an input signal s[n] and obtains phase, frequency, and Doppler velocity offset information that can be applied to carrier recovery at block 610 of FIG.

[0134] 11 is a functional block diagram of another example PLL function according to an embodiment disclosed herein, which illustrates a PLL function 1100 that may be implemented as the PLL function of block 720 (FIG. 7), block 820 (FIG. 8), and / or block 920 (FIG. 9).

[0135] In the illustrative example of FIG. 11, the PLL function 1110 includes a RIPLL 1120. The RIPLL 1120 includes a RPLL 1122 and a fine Doppler and Doppler velocity estimator 1124. The RIPLL 1120 receives an input signal from an estimator 1110. The estimator 1110 receives an input signal, e.g., decimated data, with reference to FIG. 7, FIG. 8, or FIG. 9. For method 700, the estimator 1110 receives decimated samples as an input signal. For method 800, decimated symbols are provided as an input signal. In the estimator 1110, the coarse Doppler and Doppler velocity estimator 1110 processes the input signal to obtain a rough estimate of phase, frequency, and Doppler velocity offset information. In some embodiments, the estimator 1105 may be implemented as a carrier and frame acquisition method, such as the method described in connection with blocks 1430 of FIG. 14 and 1520 of FIG.

[0136] The rough estimates of phase, frequency, and Doppler velocity offset information are input to the RPLL 1122. In the RPLL 1122, a PLL (such as, for example, the second order PLL 1000 of FIG. 10) may run both forward and backward on the received information. A classical PLL runs forward in time because it can only process one input signal at a time. With the feedforward process disclosed herein, this constraint is removed because, for a classical analog PLL, entire blocks of data are processed after data collection, not in real time. Thus, the RPLL 1122 may be able to correct shortcomings in the initial loop response of a conventional PLL by running twice through the entire input signal. After processing the input data forward according to the time ordering of the data (e.g., processing the portion of the signal received first in time before the portion received later in time), the conventional PLL is reversed and runs backward (e.g., processing the portion of the signal received last in time before the portion received first). PLL state information, such as the integrator value in the loop filter (e.g., the loop filter of FIG. 10) and the phase accumulator value in the NCO (e.g., the NCO of FIG. 10), is saved from the forward path and used to seed the PLL for the reverse path.

[0137] Once the RPLL 1122 is running, it outputs estimates of phase, frequency, and Doppler velocity offset information that can be analyzed and refined to improve both the Doppler and Doppler velocity estimates. For example, the output from the RPLL 1122 may be run through a precision Doppler and Doppler velocity estimator 1123. For example, the estimator 1123 may perform a polyfit function on the phase vector output from the RPLL 1122, as is known in the art. After the refined Doppler and Doppler velocity are measured and pre-compensated by the estimator 1123, the RPLL 1123 may be run a second time (e.g., second iteration) on the data. This process is referred to herein as a reversible iterative PLL, i.e., the RPLL 1122 and the estimator 1124 may be grouped as a RIPLL 1124.

[0138] While the above example refers to running the RPLL 1123 two iterations, it should be understood that the RPLL 1123 may be run as many iterations as desired to reduce the loop response and bring the response as close to zero as possible. Additionally, while the illustrative example of FIG. 11 shows the RIPLL 1120, the embodiments herein are not limited to the RIPLL 1120. The iterative nature of the RIPLL 1120 may be eliminated such that a single iteration of the RPLL 1122 is run to obtain a phase vector containing Doppler and Doppler rate information without processing by the estimator 1124 or iterative running of the RPLL 1122. Thus, references herein to an RPLL are understood to refer to either the RPLL or the RIPLL.

[0139] By running RPLL 1122 alone or RIPLL 1120, substantially all of the errors caused by the loop response of a conventional PLL can be eliminated because in both cases, most error-inducing effects in a conventional PLL are compensated for, and all that remains are the nonlinear effects of a conventional PLL adapted to track phase, frequency, and Doppler velocity offset information.

[0140] 12 and 13 are example graphs of loop responses of an exemplary PLL function according to embodiments disclosed herein. For example, FIGS. 12 and 13 show loop responses for multiple iterations of an exemplary RIPLL (e.g., RIPLL 1120). FIGS. 12 and 13 show the same loop response in terms of phase output error in radians (e.g., Doppler and Doppler velocity error) plotted against time in seconds. FIG. 13 shows an enlarged portion of the loop response shown in FIG. 12. FIGS. 12 and 13 show loop responses for two iterations of an RPLL (e.g., two iterations RIPLL 1120 of FIG. 11). Line 1205 shows the phase error of the first iteration of a forward second order PLL (e.g., a conventional PLL such as PLL 1000 of FIG. 10). Line 1210 shows the phase error of the first iteration of a reverse second order PLL (e.g., an implementation of an RPLL such as RPLL 1122 of FIG. 11). That is, line 1210 shows an example Doppler and Doppler velocity error from the output of a single iteration of the RPLL, and line 1215 shows the phase error after a second iteration of the RPLL is run in the reverse direction (note that the second iteration's forward direction is not shown to improve readability of FIGS. 12 and 13).

[0141] As shown in Figures 12 and 13, the loop response of line 1205 takes approximately 9 microseconds to stabilize (note that the time scales shown in Figures 12 and 13 are for illustrative purposes only and may vary). As described above in connection with Figures 7-9, some embodiments disclosed herein account for the loop response of the PLL function by utilizing the overlap between adjacent blocks of data while the PLL loop response stabilizes. That is, the overlap from the previous data block may be used to process the adjacent block of data, ensuring that the PLL is stable until the time when the non-overlapping data is processed. Thus, the time for the loop response to stabilize in the adjacent block may be eliminated. This may be an effective method and computationally efficient when the amount of overlap is small compared to the size of the block of data being processed.

[0142] However, in some implementations, the size of adjacent data blocks may shrink, and as the size decreases, the percentage of overlap increases because the loop response of the PLL does not change in time at a fixed loop bandwidth. This increase may adversely affect CPU performance because the overlapped data must be processed at the sample rate or symbol rate before decimation. However, the percentage of overlap can be minimized and even reduced to zero using an RPLL or RIPLL.

[0143] For example, as shown in Figures 12 and 13, line 1205 shows a large phase error in the forward pass of the first iteration. After the first iteration runs backward (e.g., line 1210), the phase error is significantly improved as compared to the forward pass of the first iteration. Furthermore, following the run of the reverse pass of the second iteration, the phase error is near zero phase. Thus, Figures 12 and 13 show the significant improvement that can be achieved by utilizing an RPLL (e.g., RPLL 1122 of Figure 11), and the further improvement achieved by a RIPLL (e.g., RIPLL 1120 of Figure 11).

[0144] As described above in connection with FIG. 10, some embodiments may use a third order PLL to obtain phase, Doppler, and Doppler velocity information. A third order PLL can account for Doppler velocity errors, but the RPLL described herein maintains advantages over a conventional PLL because initial loop response drawbacks may still apply. Although the example RPLL and RIPLL of FIG. 11 are described using a second order PLL, the embodiments herein are not intended to be limited to only second order RPLLs and RIPLLs. A third order RPLL and / or a third order RIPLL may be utilized to enhance performance and may be implemented in a manner substantially similar to that described above in FIG. 11.

[0145] Figure 14 is a functional block diagram of one embodiment of another method for signal processing of a received downlink signal according to embodiments disclosed herein. Figure 14 illustrates a method 1400 that may be implemented in accordance with the methods for signal processing of Figure 3 and / or Figure 4. Method 1400 may be utilized to process framed data with minimal or no overlap between blocks of adjacent data packets. Method 1400 may be used for standard waveform processing, as opposed to the offset waveforms described above.

[0146] Method 1400 includes a number of blocks, one or more of which may be implemented as a process 315, such that a grouping of blocks is processed in each of processing blocks 315a-315n of Figure 4. Each of the blocks of method 1400 may also be implemented as a function 306, such that a single block performs across functions 306a-306n of Figure 3. The execution of the blocks according to Figure 3 may be performed separately or in combination with the execution of a process according to Figure 4.

[0147] Method 1400 includes a process 1415 in which processor 202 (e.g., one or more of cores 204) can perform timing recovery error calculation block 1405 and timing recovery block 1410 on a received data packet (e.g., samples of digitized bit stream 154, or digitized downlink signals 160 and / or 170 received by receiver 212). Blocks 1405 and 1410 are similar to and perform similar functions as blocks 505 and 510 (FIG. 5), respectively. An example of timing recovery error calculation 1405 is described in connection with FIG. 7 above.

[0148] As mentioned above, a PLL function (e.g., RPLL or RIPLL) may be applied at block 1405 (e.g., as PLL function 720 in FIG. 7) to reduce dependency on overlap between data packets. One non-limiting advantage of performing timing recovery using a PLL function, such as an RPLL (or RIPLL), is that less latency may be achieved. Blocks of data must be acquired over time and cannot be processed until all samples have been collected. For example, if the symbol rate is 1 million symbols per second (sps) and the required block size is 100,000 symbols, the time to collect enough symbols to process is 100 ms. In addition to the acquisition time, the processing time also contributes to the total latency. Therefore, it may be beneficial for timing recovery to utilize a RIPLL as described above.

[0149] 7, the timing recovery error calculation block 1405 may be implemented by replacing the PLL function 720 with a phase unwrap calculation on the decimated samples and a curve fitting calculation to determine the phase, frequency, and Doppler velocity offset information, an example of which is provided in U.S. Patent No. 10,790,920.

[0150] As noted above, blocks 1405 and 1410 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, in an illustrative example, block 1405 may be implemented as function 306 of FIG. 3, such that an input example may be split into blocks of data and processed as parallel functions 306a-306n. Similarly, block 1410 may be implemented as a separate function 306 and may be executed as multiple functions 306a-306n, respectively, to process multiple blocks of data in parallel.

[0151] In another example, alone or in combination, blocks 1405 and 1410 may be grouped together as a single "process" 1415 that performs functions in a manner similar to process 315 of FIG. 4. That is, blocks 1405 and 1410 may be grouped together as process 1415 and executed in multiple parallel iterations as processing blocks 1415a...1415n. For example, blocks 1405 and 1410 may be grouped together as process 1415 and executed in serial-parallel and / or parallel-serial processing as described above in connection with FIG. 4. With respect to FIG. 4, in the illustrative example shown in FIG. 14, input samples may be taken at block 305 and divided into multiple blocks of samples at block 310, and each block of samples may be processed in multiple parallel iterations of process 1415 as processing blocks 1415a-1415n. The blocks of processed samples are then output to a data combiner 320 for combining the processed data before being output by block 325 for processing by subsequent blocks of the method 1400 .

[0152] In various embodiments, each processing block 1415a-1415n may process a block of samples at any given time. For example, processing block 1415a receives a first portion (e.g., a first block of data) of samples, processing block 1415b receives a second portion (e.g., a second block of data), etc. Each processing block 1415a-1415n processes each block and outputs time-corrected symbols for each respective block, all of which are combined by data combiner 320 (FIG. 4) before processing a subsequent block.

[0153] In some embodiments, the number of processing blocks 1415a-1415n may be based on the ingest metric and processing speed, as described above in connection with Figure 4. For example, if the process 1415 ingests 20 blocks per second and takes 1 second to process each block, then at least 20 processing blocks may be required; otherwise, the blocks will be held in a buffer while the process completes. While the above represents a fraction of the number of processing blocks, more than 20 processing blocks may be utilized if desired.

[0154] The output of process 1415 is a block of time-corrected symbols within the blocked data packets received by process 1415. The combined output from process 1415 (e.g., following data combining process 320) is provided to a PLHEADER frame synchronization block 1430, which takes the output stream of blocks of data (e.g., blocks of symbols from process 1415) and outputs a frame of data (e.g., a frame of symbols).

[0155] For example, each block of time-corrected symbols from process 1415, including one or more frame markers attached thereto (e.g., as metadata), is output to block 1430. Block 1430 locates frame boundaries by detecting frame markers within each block of data. For example, block 1430 searches for frame markers contained in each block and performs a correlator and frequency tracking process (block 1435) to locate frame boundaries and track carrier frequencies. In some embodiments, block 1435 may perform functions similar to those described below in connection with FIG. 16 to detect frame markers. For example, with reference to FIG. 16, block 1435 calculates different frequency trial bins (e.g., block 1605) that are then mixed by a coarse carrier frequency provided by a differential conjugate calculation (if provided) in a sub-function block (e.g., block 1610). From the mixed signal, block 1435 detects start of frame (SOF) (e.g., block 1615) to identify possible candidate frame markers within angular frequency trial bins. Once a possible candidate frame marker is found, all frame marker possibilities are correlated against the candidate frame marker, and if the correlation result is strong enough, the frame marker of the beginning of the frame is detected from the correlation (e.g., block 1620).

[0156] For example, method 1430 may detect an Attached Sync Marker (ASM) in case of a framed waveform, or detect a PLHEADER in case of DVB-S2, DVB-S2x, etc. For example, in case of DVB-S2, block 1430 searches the PLHEADER of each block and executes a correlator and frequency acquisition / tracking block 1435 to locate frame boundaries and track carrier frequencies. As an illustrative example, block 1435 detects a start of frame (SOF) within the located PLHEADER to identify possible candidate PLHEADERs. Once a possible candidate PLHEADER is found, all PLHEADER possibilities are correlated against the candidate PLHEADER, and if the correlation result is strong enough, the PLFRAME is detected from the correlation. In case of a burst waveform, the ASM may be located by block 1435 performing correlation using FFT and IFFT techniques, as known in the art. In some embodiments, block 1435 may be a function performed similarly to the function described below in connection with block 1520 of FIG.

[0157] In some implementations, block 1430 may not be distributed across multiple processing or functional blocks. Block 1430 may receive time corrected symbols for every frame such that frame boundaries may be located between adjacent frames of data and all frames of data may be synchronized accordingly.

[0158] In some examples, a frame of data may be spread across multiple contiguous blocks of data. In this case, block 1430 identifies frame markers indicating the beginning and end of a frame and copies portions of each block of data between the frame markers to form a collected block of data. The collected blocks are then inserted into the stream of blocks of data between the multiple contiguous blocks and processed as described above in connection with regular blocks of data. The contiguous blocks are not altered, but the portions that were bookends of the collected block are ignored when processing the frame of data.

[0159] Once the frame boundaries are found, a frequency locked loop (FLL) function (or FLL) can be implemented in block 1430. The FLL compares the phase difference between two adjacent frame markers by performing (and calculating the phase as) arctan(A*conj(B)) / (2*pi)*FR, where A is the IQ value of the previously folded frame marker, B is the IQ value of the currently folded frame marker, and FR is the update rate of the frame marker. The phase represents the frequency difference of the two frames and can be fed into a second order FLL to find the Doppler and Doppler velocity of the signal. Because the frame markers are separated by many symbols, the frequency estimate can be quite accurate, but for the same reason the update rate of this calculation is small, so the exact frequency may be in a non-zero Nyquist zone. There are two ways to resolve the Nyquist zone ambiguity: 1) exploit the characteristics of the waveform, or 2) collect several frames of data. For option 1, some waveforms, such as DVB-S2, allow the transmission of pilots in the frame to improve the frequency estimation to find the appropriate Nyquist zone. For DVB-S2, a precision frequency estimator or pilot-aided linear interpolation can be used. For option 2, if the waveform does not incorporate available frequency aiding, it is possible to collect several frames of data of the same modulation type and perform a carrier folding algorithm, similar to the method described below in connection with FIG. 17. In this case, the Doppler rate can be provided by the FLL, thus simplifying the calculations. In either case, once the Nyquist zone is known, the frequency estimate can simply be offset by the amount of the Nyquist zone and processing can continue. A PLL can be added after the FLL to further enhance tracking and provide improved phase, Doppler, and Doppler estimates to block 1420.

[0160] Once the frame boundaries are located, the frames are synchronized in block 1430 and output as a frame of time corrected symbols. The processor 202 may perform a carrier recovery error calculation block 1420 and a carrier recovery block 1425 on the received frame of time corrected symbols. Blocks 1420 and 1425 are similar to and perform similar functions as blocks 520 and 525 (FIG. 5), respectively. An example of a carrier recovery error calculation 1420 is described in connection with FIG. 8 above.

[0161] As noted above, blocks 1420 and 1425 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, in an illustrative example, block 1420 may be implemented as function 306 of FIG. 3, such that an input example is divided into frames of data, each assigned to a function 306a-306n, and processed as parallel functions 306a-306n. Similarly, block 1425 may be implemented as a separate function 306, each executed as multiple functions 306a-306n to process multiple blocks of data in parallel.

[0162] In another example, alone or in combination, blocks 1420 and 1425 may be grouped together as a single "process" 1417 that performs functions in a manner similar to process 315 of FIG. 4. That is, blocks 1420 and 1425 may be grouped together as process 1417 and executed in multiple parallel iterations as processing blocks 1417a...1417n. For example, blocks 1420 and 1420 may be grouped together as process 1417 and executed in serial-parallel and / or parallel-serial processing as described above in connection with FIG. 4. With respect to FIG. 4, in the illustrative example shown in FIG. 14, input samples may be taken at block 305 and divided into frames of samples at block 310, each frame assigned to a processing block 1417a-1417n, and each frame of samples may be processed in multiple parallel iterations of process 1415 as processing blocks 1417a-1417n. The processed frames of data are then output to a data combiner 320 for combining the processed data before being output by block 325 for processing by subsequent blocks of the method 1400 .

[0163] Once the frame boundaries are located in block 1430, as described above, a phase detector may be used to detect the phase (e.g., block 805 of FIG. 8). Each frame of data may have a different modulation type, and the phase detector must be able to accommodate all possible modulation types. Additionally, a different phase detector calculation may be used for each modulation type, which impacts how the carrier phase information is calculated. Thus, unlike the case of overlapping data, and referring to FIG. 8, carrier recovery error calculation 1420 exponentiates the incoming signal based on the modulation type of each incoming frame of data, which changes for each frame of data in the incoming signal. The modulation type may be provided by block 1430, for example, as metadata included in the output symbols, since the detected frame marker may contain this information. Carrier recovery error calculation block 1420 may exponentiate the incoming to a particular power based on the modulation type indicated in the metadata, for example, as described in block 805 of FIG. 8. Blocks 810-830 of method 800 are then performed in substantially the same manner as described above.

[0164] In some embodiments disclosed herein, for QPSK waveforms, since the PLL function (e.g., block 820 of FIG. 8 as performed in block 1420 of FIG. 14) is performed after collapsing the IQ constellation into a single tone (e.g., as performed in block 805 of FIG. 8), carrier recovery ambiguity may exist regarding proper phase alignment of the signal. For example, if the modulation type of a given frame of data is QPSK, the PLL function will start with four different phase possibilities, only one of which is properly aligned. For framed waveforms, it is possible to use frame markers to properly phase align the frames. This may be accomplished perhaps by calculating a frame marker phase and using this information to pre-seed the PLL function so that the PLL function starts with the phase ambiguity removed, or by correcting the phase information output from the PLL function before performing carrier recovery (e.g., block 1425) (referred to herein as post-correction). For DVB-S2 and post-correction, the frame markers can have four different phase ambiguity values, and therefore the phase output of the PLL function is scaled by four different phase values: 0, π / 4, π / 2, or π*3 / 4.

[0165] Block 1425 outputs phase and timing correction symbols for downstream processing by one or more operations that output bits corresponding to the received downlink signal. For example, the operations may include, but are not limited to, frame decoding, forward error correction, descrambling, deinterleaving, derandomization, etc. Each operation is illustratively illustrated in FIG. 14 as an operation block 1440a-1440n that may be performed by processor 202 (e.g., one or more of cores 204).

[0166] As mentioned above, blocks 1440a-1440n may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, in an illustrative example, block 1440a may be implemented as function 306 of FIG. 3, such that an input example may be divided into blocks of data and processed by parallel functions 306a-306n.

[0167] In another example, alone or in combination, blocks 1440a-1440n may be grouped together as a single "process" 1419 that performs functions in a manner similar to process 315 of FIG. 4. That is, one or more of blocks 1440a-1440n may be grouped together as process 1419 and executed in multiple parallel iterations as processing blocks 1419a...1419n. For example, as shown in the illustrative example of FIG. 14, blocks 1440a-1440n may be grouped together as process 1419 and executed in serial-parallel and / or parallel-serial processing as described above in connection with FIG. 4. With respect to FIG. 4, input samples may be taken at block 305 and split into multiple frames of samples at block 310, and each frame of samples may be processed in multiple parallel iterations of process 1419 as processing blocks 1419a-1419n. The frames of processed data are then output to a data combiner 320 for combining the processed data before being output by block 325 and output as bits.

[0168] 14 shows all of blocks 1440a-1440n grouped into process 1419, embodiments herein are not limited to such implementations. For example, a subset of blocks 1440a-1440n may be grouped into multiple processes.

[0169] In various examples, the blocks of FIG. 14 may be implemented using SIMD processing techniques described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the capabilities of each processing block performed using SIMD techniques may help to enhance the minimization of memory bandwidth requirements.

[0170] In some implementations, another method for improvement is to vary the loop bandwidth required to perform the PLL function for each pass or iteration. Varying the use of loop bandwidth may allow for faster acquisition times to improve the initial Doppler and Doppler rate estimates (e.g., from the carrier and frame acquisition techniques described in connection with FIG. 15).

[0171] In some implementations, as described above, the PLL function disclosed herein can be run forward and backward on the data as many times as necessary. The more iterations that are run, the smaller the error from the initial loop response and the smaller the tracking problems caused by having an improper Doppler and Doppler velocity estimate of the PLL function. For example, in the case of carrier recovery, the PLL function can be run forward and backward once on the data (e.g., a single RPLL), and then the function can be run to calculate and compensate for the Doppler and Doppler velocity (e.g., in the precision Doppler and Doppler velocity estimator 1124 of FIG. 11). Once compensated, the RPLL can be run again, this time moving forward and backward for two or more iterations (e.g., RIPLL), and then the Doppler and Doppler velocity can be calculated and compensated, and the RPLL can be run again. This process can be run as many times as necessary, changing the loop bandwidth requirements of the loop to improve performance.

[0172] There are many techniques for carrier and frame acquisition, and embodiments herein provide for implementing such techniques using multiple CPUs and / or SIMD instructions.

[0173] FIG. 15 is a functional block diagram of one embodiment of a method for carrier and frame acquisition of a received downlink signal according to an embodiment disclosed herein. FIG. 15 illustrates a method 1500 that may perform one or more carrier and frame acquisition techniques in accordance with the signal processing methods of FIG. 3 and / or FIG. 4. FIG. 15 illustrates a method 1500 that may be used for standard waveform processing, as opposed to offset waveforms, as described above. In various examples, the method 15 may be implemented using SIMD processing techniques described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block performed using SIMD techniques may help to enhance the minimization of memory bandwidth requirements.

[0174] Method 1500 includes a number of blocks, one or more of which may be implemented as processes 315, such that a grouping of blocks is processed in each of processing blocks 315a-315n of Figure 4. Each of the blocks of method 1500 may also be implemented as functions 306, such that a single block performs across functions 306a-306n of Figure 3. The execution of the blocks according to Figure 3 may be performed separately or in combination with the execution of the process according to Figure 4.

[0175] Method 1500 includes a process 1515 in which processor 202 (e.g., one or more of cores 204) can perform a timing recovery error calculation block 1505 and a timing recovery block 1510 on a received data packet (e.g., samples of digitized bit stream 154, or digitized downlink signals 160 and / or 170 received by receiver 212). Blocks 1505 and 1510 are similar to blocks 1405 and 1410 (FIG. 14), respectively, and perform similar functions as blocks 1405 and 1410 (FIG. 14).

[0176] As mentioned above, blocks 1505 and 1510 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). Similarly, alone or in combination, blocks 1505 and 1510 may be grouped together as a single "process" 1515 that performs the function in a manner similar to process 315 of FIG. 4. That is, blocks 1505 and 1510 may be grouped together as process 1515 and executed in multiple parallel iterations as processing blocks 1515a...1515n, e.g., as described above in connection with process 1415.

[0177] In block 1506, the processor 202 (e.g., one or more of the cores 204) may perform carrier and frame acquisition on the output from process 1515. As with the embodiments described above, the block 1506 may represent a function and may be implemented as one or more of the functions 306a, 306b, ... 306n (FIG. 3). For example, in an illustrative example, the carrier and frame acquisition may be implemented as a function block 1506, such that input symbols may be divided into blocks of data and processed by parallel functions 1506a-1506n.

[0178] Many approaches could be used for carrier acquisition, such as frequency domain analysis in the sample domain, differential phase calculation (e.g. mean(x[n]*conj(x[nm]) where n is the block of data and m is the amount of delay), etc. It is also possible to estimate the carrier frequency information after timing recovery as shown in Figure 15. In case of framed data, it is also possible to correlate frames based on detecting frame markers as described above.

[0179] In the illustrative example of FIG. 15, once timing recovery is performed in process 1515, the frame of data is copied and sent to many of the multiple functions 1506a-1506n ​​shown in FIG. 15. Each function block correlates with each other in a narrow frequency band, and by using an increased number of function blocks, acquisition time is reduced. Since carrier frequency estimation and frame boundary identification are computationally expensive, the more CPU cores (e.g., cores 204 each performing a function 1506a-1506n) that can be used, the better. For example, if the uncertainty range of the frequency of the received signal is + / -1 MHz and each function 1506 can cover + / -100 kHz, it is possible to use 10 CPU cores to search across the entire frequency range at once. Using SIMD techniques, acquisition time is further improved.

[0180] While FIG. 15 shows both a timing recovery block and a carrier and frame acquisition block, the embodiments described above may receive carrier and frame estimates via process 1506 (e.g., block 520 performs functions 1506a-1506n). For example, as described in connection with FIG. 720, carrier and frame acquisition (such as that performed in block 1506) may be used to preseed the PLL function. In these cases, timing recovery of process 1515 may not be required for preseeding. As another example, function 1506 may be implemented to estimate carrier as part of estimator 1105 of FIG. 15 or in block 810 of FIG. 8.

[0181] 16 and 17 are functional block diagrams of an exemplary method for carrier frequency acquisition according to an embodiment disclosed herein. FIG. 16 illustrates method 1600, an exemplary method for carrier frequency acquisition that may be implemented in block 1520 of FIG. 15 for framed data (or data where the modulation type is unknown or variable). FIG. 17 illustrates system and method 1700, another exemplary method for carrier frequency acquisition that may be implemented in block 1520 of FIG. 15 for unframed data (or data where the modulation type is known or static between adjacent blocks of data). Although method 1700 may be implemented for unframed data, it should be understood that method 1600 is more suitable for such data, although method 1700 may also be applied to framed data. Although FIG. 16 and 17 illustrate a specific example of a method for carrier frequency acquisition in block 1520, it should be understood that the embodiment of block 1520 is not limited to only methods 1600 and 1700. Block 1520 may be implemented as any known method for estimating the carrier frequency of a streaming block of data packets. Methods 1600 and 1700 are used as illustrative examples.

[0182] As with the above-described embodiments, method 1600 may represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, in an illustrative example, carrier and frame acquisition method 1600 may be implemented as function block 1506 of FIG. 15, such that input symbols may be divided into blocks of data and processed by parallel functions 1506a-1506n. Similarly, method 1700 may represent a function and may be implemented as function block 1506 of FIG. 15.

[0183] Referring initially to method 1600, an illustrative example of method 1600 includes multiple sub-function blocks, including, but not limited to, a frequency trial calculator function block 1605, a mixing with coarse carrier estimate function block 1610, a start of frame (SOF) detector function block 1615, a frame marker detector function block 1620, and a frame marker folding and frequency detector function block 1625.

[0184] In some embodiments, in addition to finding the frame markers, the method 1600 may also perform coarse frequency and tracking of the received time-corrected symbols. The coarse frequency acquisition may be performed by detecting the start of frame (SOF) within several different frequency trial bins. For example, in sub-function block 1605, as described above, the processor 202 receives the time-corrected symbols including one or more frame markers (e.g., as metadata) appended to the time-corrected symbols (e.g., as output from a timing recovery process, such as those described in connection with FIG. 14 and FIG. 15) and calculates the different frequency trial bins. If the SOF detection can only work in a limited frequency range and the carrier frequency uncertainty (CFU) is larger than that of the frequency range, the CFU is divided into several frequency trial bins such that each trial covers only the SOF frequency detection range.

[0185] In block 1610, the frequency trial bins are mixed with a coarse carrier frequency provided, for example, by a differential conjugate calculation. From the mixed signal, block 1615 detects the SOF for each frequency trial bin to identify possible candidate frame markers that indicate the beginning of a frame. Once a possible candidate frame marker is found, all frame marker possibilities are correlated against the candidate frame markers, and if the correlation result is strong enough, the frame marker for the beginning of the frame is detected from the correlation (block 1620).

[0186] Once a frame marker is found, block 1625 further refines the frequency estimate by folding the frame marker (e.g., of length 90 symbols) onto the carrier. For example, in block 1625, processor 202 takes an FFT of the symbols of each frame and calculates the frequency offset. Frequency tracking may be performed by comparing the phase difference between two consecutive folded frames, as is known in the art. Block 1625 then outputs Doppler, Doppler velocity, and frame boundary information (e.g., as metadata attached to each frame of symbols).

[0187] 17 illustrates another example carrier frequency acquisition method 1700. The illustrative example of the method 1700 includes multiple sub-function blocks, including, but not limited to, a power-N function block 1705, a mix with coarse carrier estimate function block 1710, a decimate function block 1715, an FFT trial function block 1720, and a peak detection function block 1725.

[0188] In sub-function block 1005, the symbols are input to carrier frequency acquisition block 1700 in block 1705, exponentiated appropriately based on the number of symbols (N) in the outer ring of the constellation (2 for BPSK, 4 for QPSK / OQPSK, 8 for 8PSK, 12 for 16APSK, etc.), and then mixed by the coarse carrier frequency provided by the differential conjugate calculation (if provided) in sub-function block 1710. The mixed signal is then decimated in sub-function block 1715, and an FFT is performed on the signal in sub-function block 1720 to determine the peak-to-average ratio of the selected modulation type in sub-function block 1725. This process is then repeated for all of the desired modulation types detected. The result with the highest peak-to-average is the most likely modulation type. As a way to minimize memory bandwidth, sub-function block 1705, sub-function block 1710, and sub-function block 1715 may be combined to form one sub-function block, which may reduce memory bandwidth. To further increase the data rate, each modulation type trial in sub-function block 1720 can be executed in its own thread to further increase throughput.

[0189] The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope of the present disclosure. The various components shown in the figures may be implemented, for example, but not limited to, as software and / or firmware on a processor or dedicated hardware. Also, the features and attributes of certain exemplary embodiments disclosed above may be combined in various ways to form additional embodiments, all of which are within the scope of the present disclosure.

[0190] The foregoing method descriptions and process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "then," "then," and "next" are not intended to limit the order of operations; these words are merely used to guide the reader through the method description. Additionally, any reference to a claim element in the singular form, e.g., using articles "a," "an," or "the," should not be construed as limiting the element to the singular form.

[0191] The operations of the various illustrative logic blocks, modules, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the inventive concept.

[0192] The hardware used to implement the various exemplary logic, logic blocks, and modules described in connection with the various embodiments disclosed herein may be implemented or performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof intended to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of a DSP and a receiving device, such as, for example, a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such combination of components. Alternatively, some operations or methods may be performed by circuitry dedicated to a given function.

[0193] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The operations of the methods or algorithms disclosed herein may be embodied in processor-executable instructions that may reside on a non-transitory computer-readable storage medium or a processor-readable storage medium. A non-transitory computer-readable storage medium or a processor-readable storage medium may be any storage medium that can be accessed by a computer or a processor. By way of example and not limitation, such non-transitory computer-readable storage medium or a processor-readable storage medium may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. These disks usually reproduce data magnetically, while discs reproduce data optically by lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Furthermore, the operations of a method or algorithm may reside in a non-transitory processor-readable and / or computer-readable storage medium that may be embodied in a computer program product as one or any combination or set of code and / or instructions.

[0194] It is understood that the specific order or hierarchy of blocks in the disclosed processes / flowcharts is illustrative of example approaches. It is understood that the specific order or hierarchy of blocks within the processes / flowcharts can be rearranged based on design preferences. Also, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0195] The previous description is provided to enable one skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects.

[0196] Accordingly, the claims are not intended to be limited to the embodiments shown herein, but are intended to be accorded the full scope consistent with the language of the claims, and references to elements in the singular are not intended to mean "one and only one," unless expressly so stated, but rather "one or more."

[0197] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Unless otherwise stated, the term "some" refers to one or more.

Claims

1. 1. A method for processing a digital bit stream, the digital bit stream being a digitized communication signal, comprising: splitting, with one or more processors, the digital bitstream into a plurality of data packets; a first processing block within the one or more processors; performing a carrier recovery error calculation on a first portion of the plurality of data packets, the performing including performing a first phase-locked loop (PLL) function on decimated data of the first portion of the plurality of data packets; performing a carrier recovery operation on the first portion of the plurality of data packets; In parallel with the processing of the first portion of the plurality of packets, in a second processing block within the one or more processors: performing the carrier recovery error calculation on a second portion of the plurality of data packets, the performing including performing the first PLL function on decimated data of the second portion of the plurality of data packets; performing the carrier recovery operation on a second portion of the plurality of data packets; combining the first portion and the second portion based on phase stitching; The method comprising:

2. a third processing block within the one or more processors; performing a timing recovery error calculation on the first portion of the plurality of data packets; performing a timing recovery operation on the first portion of the plurality of data packets; In parallel with the processing of the first portion of the plurality of packets, a fourth processing block within the one or more processors: performing the timing recovery error calculation on the second portion of the plurality of data packets; performing the timing recovery operation on a second portion of the plurality of data packets; The method of claim 1 further comprising:

3. 3. The method of claim 2, wherein the timing recovery error calculation comprises performing a second PLL function on decimated data of the first and second portions of the plurality of data packets.

4. Calculating the timing recovery error receiving a data packet as samples of a downlink signal, the samples having an unknown symbol rate and frequency; determining a timing error for the samples based on the estimate of the symbol rate; decimating the samples with a decimation filter; performing the second PLL function on the decimated symbols to determine a phase, a frequency, and a Doppler velocity of the symbols; updating the estimate of the symbol rate; and The method of claim 2 , comprising:

5. 2. The method of any one of the preceding claims, wherein the PLL function is one of a second order PLL, a third order PLL, a reversible PLL, and a reversible repeating PLL.

6. The method of any one of claims 1 to 4, wherein each of the data packets of the plurality of data packets includes a duplication of data from an adjacent packet, and the PLL function is a second order PLL.

7. The method of any one of claims 1 to 4, wherein each of the data packets is a framed data packet, and the PLL function is one of a reversible PLL and a reversible repeating PLL.

8. combining the outputs of the third processing block and the fourth processing block into a block of time corrected symbols; Locating the frame boundaries of each block by detecting frame markers; Further comprising: performing the carrier recovery error calculation for the first and second portions of the plurality of data packets based on the located frame boundaries. The method of claim 2.

9. The method of any of claims 1 to 4, wherein the multiple processing blocks include multiple central processing unit (CPU) cores.

10. said carrier recovery error calculation comprising: receiving the symbols associated with the synchronized samples of the downlink signal; determining a carrier error for the symbol based on an estimate of a frequency of the downlink signal and a product of the symbol raised to the power of n, where n is an integer; decimating the symbols with a decimation filter; performing the first PLL function on the decimated symbols to determine a phase, a frequency, and a Doppler velocity of the symbols; updating the estimate of the frequency; and The method according to any one of claims 1 to 4, comprising:

11. The method of any of claims 1 to 4, wherein the one or more processors employ Single Instruction Multiple Data (SIMD) technology to achieve high throughput.

12. 1. A method for processing a digital bit stream, the digital bit stream being a frame-based digitized communication signal, comprising: splitting, with one or more processors, the digital bitstream into a plurality of data packets; a first processing block within the one or more processors; performing a timing recovery error calculation on the first portion of the plurality of data packets, the performing including performing a first phase-locked loop (PLL) function on decimated data of the first portion of the plurality of data packets; performing a timing recovery operation on the first portion of the plurality of data packets; In parallel with the processing of the first portion of the plurality of packets, in a second processing block within the one or more processors: performing the timing recovery error calculation on the second portion of the plurality of data packets, the performing including performing the first PLL function on decimated data of the second portion of the plurality of data packets; performing the timing recovery operation on a second portion of the plurality of data packets; combining the outputs of the first processing block and the second processing block into a block of time-corrected symbols including one or more frame markers; searching the blocks of time-corrected symbols for the one or more frame markers included in each block of time-corrected symbols; running a correlator process and a frequency tracking process to locate the frame boundaries and track the carrier frequency; outputting a frame of time corrected symbols; The method comprising:

13. performing a correlator process and a frequency tracking process; Implementing a frequency locked loop (FLL) function to compare the phase difference between two adjacent frame markers. The method of claim 12, comprising:

14. performing a FLL function to compare the phase difference between two adjacent frame markers; calculating arctan(A*conj(B)) / (2*pi)*FR, where A is the IQ value of the previously folded frame marker, B is the IQ value of the currently folded frame marker, and FR is the update rate of the frame marker; performing a secondary FLL function using said calculated values ​​to determine the Doppler and Doppler velocity of said carrier; The method of claim 13, comprising:

15. splitting, with one or more processors, the frame of time-corrected symbols into a plurality of time-corrected symbols; a third processing block within the one or more processors; performing a carrier recovery error calculation on a first portion of the plurality of data packets, the performing including performing a second phase locked loop (PLL) function on decimated data of the first portion of the plurality of time corrected symbols; performing a carrier recovery operation on the first portion of the plurality of time corrected symbols; In parallel with the processing of the first portion of the plurality of time corrected symbols, in a fourth processing block within the one or more processors: performing the carrier recovery error calculation on the second portion of the plurality of time corrected symbols, the performing including performing the second PLL function on decimated data of the second portion of the plurality of time corrected symbols; performing the carrier recovery operation on a second portion of the plurality of time corrected symbols; combining the first portion and the second portion based on phase stitching; 15. The method of claim 14, comprising:

16. 14. The method of claim 13, further comprising performing a PLL function after the secondary FLL function to further enhance tracking and provide improved phase, Doppler, and Doppler estimates for use in the carrier recovery error calculation.

17. 1. A method for processing a digital bit stream, the digital bit stream being a frame-based digitized communication signal, comprising: splitting, with one or more processors, the digital bitstream into a plurality of data packets; a first processing block within the one or more processors; performing a timing recovery error calculation on the first portion of the plurality of data packets, the performing including performing a first phase-locked loop (PLL) function on decimated data of the first portion of the plurality of data packets; performing a timing recovery operation on the first portion of the plurality of data packets; In parallel with the processing of the first portion of the plurality of packets, in a second processing block within the one or more processors: performing the timing recovery error calculation on the second portion of the plurality of data packets, the performing including performing the first PLL function on decimated data of the second portion of the plurality of data packets; performing the timing recovery operation on a second portion of the plurality of data packets; The method comprising:

18. combining the outputs of the first processing block and the second processing block into a block of time-corrected symbols including one or more frame markers; Locating the frame boundaries of each block by detecting frame markers; 20. The method of claim 17, further comprising:

19. Locating frame boundaries is running a correlator process and a frequency tracking process to locate the frame boundaries and track the carrier frequency; outputting a frame of time corrected symbols; 20. The method of claim 18, further comprising:

20. 1. A system for processing a digital bit stream representing a communication signal, comprising: a digitizer configured to convert a received analog signal to said digital bit stream; one or more processors communicatively coupled to the digitizer, the one or more processors having a plurality of processing blocks, the one or more processors operable to perform a method according to any one of the preceding claims; The system comprising:

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