SYSTEM AND METHOD FOR REDUCING POWER DOWN ENTRY AND EXIT LATENCY - Patent application

Abstract

A system and method for fast save / restore is disclosed that includes one or more logic units (LUs) residing in independent power domains, one or more digital frequency synthesizers (DFSs) each associated with one of the one or more LUs, the one or more DFSs configured to lock a system complex frequency and ramp the one or more LUs to the system complex frequency, and one or more slave fast save / restore control (FSRC) units associated with any of the one or more LUs and configured to save / restore an FSRC state of the one or more LUs.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 553,657, filed December 16, 2021, the contents of which are incorporated herein by reference. [Background technology]

[0002] A system complex consists of one or more logical units (LUs). The time required for a system complex to enter and exit a powered down state affects the residency of that state. Shorter entry and exit latencies increase both the residency in and the probability of entering a state, resulting in overall power reduction.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Diagram 2] FIG. 2 is a block diagram of elements of a device showing additional details relevant to features of the present disclosure. [Diagram 3] FIG. 1 illustrates a high-level system for fast save / restore. [Figure 4] FIG. 4 illustrates a method for low power exit in the system of FIG. 3. [Diagram 5] FIG. 4 illustrates a method for low power entry in the system of FIG. [Figure 6] FIG. 2 illustrates an overall latency and frequency plot of a system and method for providing fast save restore. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] A system and method for reducing power down entry and exit latency are described. The system includes one or more logical units with independent power domains and a digital frequency synthesizer (DFS). A controller in the system manages the power state of the logical units and supports a power down state of the system. The power down state of the system requires that the state of the controller is saved on power down entry and restored on power down exit. A method is described for maximizing entry and exit frequencies while supporting lower frequencies that are inactive. Higher frequencies during state saving and restoration significantly reduce power down entry and exit latency without compromising overall power efficiency.

[0006] Entry into a SOC low power state is limited by the total state transition latency, which includes both the entry latency and the exit latency. By reducing the total latency, additional SOC low power state entries become available, resulting in longer SOC low power state residency per entry, lower overall SOC power consumption, and longer battery life. Previous solutions often included high exit latencies. For example, the low power entry / exit sequence in some solutions occurs at 1.4 GHz with a restore latency of 300 μs.

[0007] The described system and method can be adopted in next generation SOCs to improve total state transition latency and benefit logical units (LUs), such as CPU cores, graphics cores, etc. A system and method for fast save / restore is disclosed. The system and method includes one or more LUs residing in independent power domains, one or more DFSs, each associated with one of the one or more LUs, where the one or more DFSs are configured to lock a system complex frequency and ramp the one or more LUs to the system complex frequency, and one or more slave fast save / restore control (FSRC) units, where each slave FSRC is associated with one of the one or more LUs, where each slave FSRC is configured to restore the FSRC state of the one or more LUs.

[0008] In a low power exit, the system and method include: locking a system composite frequency using a system DFS; ramping the LUs to the system composite frequency by using a system DFS in communication with at least one DFS associated with any of the LUs; restoring a LU FSRC state using a slave FSRC unit associated with any of the LUs; exiting from a low power state at the restored frequency for any of the LUs that are awake; ramping down to a minimum low frequency state for any of the LUs that are not awake; and reinitiating a reset sequence for any of the LUs. The low power exit can include a producer outputting a data packet to an LU that is inconsistent in bandwidth with a consumer that receives the data packet. The low power exit can include a producer outputting a data packet to an LU that is inconsistent in throughput with a consumer that receives the data packet.

[0009] In the low power entry, the system and method include using the system DFS to ramp the plurality of LUs to the system frequency, using a slave FSRC unit associated with any of the plurality of LUs to save an FSRC state for awake LUs of the plurality of LUs, exiting from the low power state at the operating frequency, ramping down to a minimum low frequency state for any of the plurality of LUs that are not awake, and reinitiating a reset sequence for any of the plurality of LUs. The low power entry may include a producer that outputs data packets to an LU that is inconsistent in bandwidth with a consumer that receives the data packets. The low power entry may include a producer that outputs data packets to an LU that is inconsistent in throughput with a consumer that receives the data packets.

[0010] The system and method may include one or more LUs including a CPU core, a graphics core, or other processor. Each DFS of the one or more DFSs may be uniquely matched with any of the one or more LUs. Each slave FSRC unit of the one or more slave FSRC units may be uniquely matched with any of the one or more LUs. Each slave FSRC unit of the one or more slave FSRC units may be uniquely matched with any of the one or more DFSs. The system and method includes a master fast save restore control (FRSC) unit configured to interface with one or more slave FSRC units in each LU via the DFS. The master / slave FSRC units may control system and slave FSRC unit clocks during low power entry / exit sequences. The master FSRC unit may operate with each slave FSRC unit to control LU frequency. The master FSRC unit may enable maximum frequency in the LU DFS at the beginning of the power sequence. The power sequence may be one of power down entry and power down exit. Each slave FSRC unit tracks LU context save or restore and can enter the low frequency state after inactive LUs have completed save or restore, and enters the operating frequency state after active LUs have completed save or restore. Power down entry and exit latency is reduced by operating the LUs and the system at maximum frequency during state save and restore.

[0011] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, a server, a tablet computer, or other type of computing device, etc. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also include optional input drivers 112 and output drivers 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0012] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102 or is located separately from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0013] Storage devices 106 include fixed or removable storage devices (e.g., hard disk drives, solid state drives, optical disks, flash drives). Input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more optical, antennae, or network connections (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0014] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates in the same manner when the input driver 112 and the output driver 114 are not present. The output driver 116 includes an accelerated processing device (APD) 116 coupled to a display device 118. The APD accepts computational and graphics rendering commands from the processor 102, processes the computational and graphics rendering commands, and provides pixel output to the display device 118 for display. As described in more detail below, the APD 116 includes one or more parallel processing units that perform computations according to a single-instruction-multiple-data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with APD 116, in various alternatives, the functions described as being performed by APD 116 may additionally or alternatively be performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor 102) to provide graphical output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may also perform the functions described herein.

[0015] FIG. 2 is a block diagram 200 of elements of device 100 showing additional details relevant to features of the present disclosure. Diagram 200 includes multiple CPUs 210 (represented individually by CPU 2101 and CPU 2102) and multiple GPUs 220 (represented individually by GPU 2201 and GPU 2202). Additionally or alternatively, while a CPU and a GPU are shown, one skilled in the art will understand that other IPs may be utilized in conjunction with or in place of either or both of (a) the CPU and (a) the GPU. Each of the multiple CPUs 210 and multiple GPUs 220 is connected to a system management network (SMN) router 230 via one or more network buses 240. The SMN routers 230 may be interconnected by another series of buses. Some of the illustrated network buses 240 may have different widths and operate using different clock frequencies. The SMN router 230 may be a single device. That is, although the series of SMN routers 230 is shown using several separate boxes in Figure 2, it may be a single SMN router 230. Alternatively, the SMN router 230 may be a series of interconnected routers that are communicatively coupled.

[0016] The system includes one or more LUs with independent power domains and DFS. A controller in the system manages the power states of the logical units and supports a power down state of the system. The power down state of the system requires the state of the controller to be saved at power down entry and restored at power down exit. A method is described for maximizing the entry and exit frequency while supporting a lower frequency of inactivity. The higher frequency during state saving and restoration significantly reduces the power down entry and exit latency without compromising the overall power efficiency. The system and method can benefit the LU (processor) described above with respect to Figures 1 and 2 by maximizing the entry and exit frequency to enable the LU to reduce the power down entry and exit latency without compromising the overall power efficiency of the LU.

[0017] Low power entry / exit latency issues can result from inconsistent network throughput and / or inconsistent network bandwidth. Inconsistent network throughput can occur when one side has a lower throughput than the other. Inconsistent network bandwidth can occur when one side has a lower bandwidth than the other. Additionally or alternatively, during low power entry and exit transitions, the bandwidth and throughput can be the same, but the frequencies can be inconsistent.

[0018] As an example, a system includes one or more LUs, each of which is connected using a network with the same bandwidth capabilities. Because register accesses are serialized, each LU requires multiple cycles to process a save / restore burst sequence. As a result, the system throughput is higher than the throughput of an individual LU. This imbalance is exacerbated when the LU frequency is slower than the system frequency. As shown in FIG. 3, to overcome this network throughput imbalance, the FSRC unit increases the throughput on demand without affecting the nominal operating power and minimal hardware support. More specifically, the master FSRC unit 340 detects the beginning of a low power entry / exit sequence. For an exit sequence, the master FSRC unit 340 waits until the PLL locks (PLL lock is not required for an entry sequence). For both exit / entry, the master FSRC unit 340 ramps both the master DFS 350 and the slave DFS 320 to the same frequency. The restore / save sequence begins with the LU 310 locked to a higher frequency than the low power state. When the restore / save is finished, the slave FSRC unit 360 detects the end of the restore / save sequence and requests the master FSRC unit 340 to restore the low power frequency since the LU 310 is still in a low power state during the sequence. Since the LU 310 and the system 300 are in the same power domain, no increased voltage is required to increase the frequency. Since the frequency is only increased during the save / restore, this allows for an increase in the save / restore throughput, which reduces latency and therefore has no impact on the nominal operating power.

[0019] Similarly, the system network data rate is 16 bits. The SOC network data rate is 32 bits. As described, to overcome this network bandwidth mismatch, the system internal clock can be increased by twice the SOC network clock. Specifically, the maximum frequency uplift is specified by the bus width mismatch. For example, if the producer bus width is N bits and the consumer bus width is M bits, the maximum frequency uplift multiplication factor is M / N. Specifically, for example, for a 32-bit producer and a 64-bit consumer, the maximum frequency uplift multiplication factor is 2. The maximum frequency uplift allowed is implementation specific since the implementation must meet the timing for the maximum frequency case. If the implementation supports a maximum frequency uplift M / N, the system FRSC can increase the frequency divisor closest to the M / N factor of the consumer or producer frequency, based on which it is implemented with a lower bus width before the save / restore sequence begins and scaled back to the previous divisor when the post sequence ends.

[0020] FIG. 3 illustrates a high-level system 300 for fast save / restore. System 300 includes one or more LUs 310, which may reside in independent power domains. As shown in FIG. 3, logical units include LU0 310.0, LU1 310.1, LU2 310.2 through LUn 310.n (collectively referred to as LUs 310). It should be understood that LUs 310 may be, for example, CPU cores, graphics cores, or other processors. LUs 310 may interact with shared units, such as, for example, L2 or L3 caches (not shown), chip pervasive logic (CPL) including PLLs, clock or reset logic for sequencing system units, etc.

[0021] Each of the LUs 310 has an associated DFS 320. As shown in Figure 3, the digital frequency synthesizer includes DFS0 320.0, DFS1 320.1, DFS2 320.2 through DFSn 320.n (collectively referred to as DFS 320). As shown, DFS 320 is uniquely matched to LU 310, however, it is understood that other configurations of DFSs matching LUs are envisioned and are included herein.

[0022] A slave fast save restore control (FSRC) unit 360 is associated with each of the LUs 310 / DFSs 320. As shown (and understood) in Fig. 3, the slave fast save restore control includes slave FSRC unit 0 360.0, slave FSRC unit 1 360.1 (as will be understood but not specifically shown), slave FSRC unit 2 (as will be understood but not specifically shown) through slave FSRC unit n (as will be understood but not specifically shown) (and collectively referred to as slave FSRC units 360). As shown, slave FSRC unit 360 is uniquely matched to LUs 310 and DFSs 320, although it will be understood that other configurations of LU / DFS matching FSRC units may be envisioned and are included herein.

[0023] The system 300 includes a master fast save restore control (FRSC) 340 that interfaces with a slave FSRC unit 360 in each LU 310 via the DFS 320. The master / slave FSRC units 340 / 360 control the system and slave FSRC unit 360 clocks during low power entry / exit sequences. The master FSRC unit 340 communicates with each slave FSRC unit 360 to control the LU 310 frequency. At the start of a power down entry or exit sequence, the master FSRC unit 340 enables the maximum frequency in the LU DFS 320. The master FSRC unit 340 detects the start of a power down entry or exit sequence, detects completion of phase lock loop (PLL) relock when exiting power down, and enables each LU 310 DFS 320 at the same frequency as the system DFS 350. The PLL and DFS control 330 provides control to the PLL, clocks, and DFS 320. The master FSRC unit 340 communicates via a configuration bus 370 for incoming and outgoing communications external to the system 300 .

[0024] Each slave FSRC unit 360 keeps track of the save or restore of the LU 310 context, and enters the low frequency state after completing the save or restore for an inactive LU, and enters the working frequency state after completing the save or restore for an active LU.

[0025] In a specific configuration, the system 300 and its LUs 310 reside in independent power domains, thus enabling independent LU 310 power states. A controller in the power domain of the system 300 must manage the power states of the LUs 310. The controller is a clock and reset control for each of the slave FSRC units 360 and the master FSRC unit 340. A master clock and reset controller in the system 300 interacts with each distributed LU 310 clock and reset controller. The controllers together handle, for example, initialization, low power entry / exit, P-state change requests. The slave / master FSRC units 360 / 340 include a clock and reset controller in each LU 310 and the system 300 to improve low power entry / exit latency efficiency.

[0026] When an LU 310 enters a power gated state, the controller enters a low frequency state to reduce power consumption. When an LU 310 exits a power gated state, the controller exits the low frequency state. When all LUs 310 enter a power gated state, the system 300 can be powered down. As part of the power down entry and exit process, the controller state is saved and restored. When an LU 310 is power gated, the controller is in a low frequency state, so the save and restore occurs at a low frequency, thus impacting latency. The present system provides a method and system for reducing power down entry and exit latency without compromising overall power efficiency.

[0027] Power down entry and exit latency is reduced by operating the LU 310 and the system at maximum frequency during state save and restore. If LU 310 saves and restores occur serially, the power down entry and exit latency improvement increases with LU 310 count. LU 310 saves and restores occurring in parallel provide the same latency improvement until the system bandwidth is saturated.

[0028] As shown, the present system and method balances system performance with low power. The system 300 complex adjusts frequency only for the duration of the power down entry / exit sequence. Each slave FSRC unit 360 enters the low frequency state after completing the save or restore of inactive LUs. Each slave FSRC unit 360 enters the operating frequency state after completing the save or restore of active LUs.

[0029] Figure 4 illustrates a method 400 of low power exit in the system 300 of Figure 3. The method 400 includes entering a low power exit in step 405. Entering the low power exit in step 405 may occur, for example, via an interrupt.

[0030] In step 410, the method 400 includes locking the PLL to the system frequency. After exit, the PLL is locked to the nominal operating frequency of the system.

[0031] In step 415, the method 400 includes ramping the LU slave FSRC unit to the system frequency. In step 415, the master FSRC unit aligns the slave LU FSRC unit frequency to the system frequency. In older systems, the slave FSRC unit in the LU stays in a low power state at a slower frequency than the master FSRC unit in the system. The slower frequency of the slave FSRC unit may cause restoration latency in older systems.

[0032] At step 420, the method 400 includes restoring the LU slave FSRC state. The restoration of the LU slave FSRC context occurs with matching master and slave FSRC unit frequencies. In older systems, the restoration of the LU slave FSRC context occurs with mismatched master and slave FSRC unit frequencies. The slower frequency of the slave FSRC unit may cause restoration latency in older systems.

[0033] In step 425, the method 400 includes exiting a system reset.

[0034] In step 430, method 400 includes determining whether the LU is waking up. Waking up can include, for example, transitioning to full functional operation. Step 430 can occur individually across the LUs, for example, from zero LUs to all LUs. Such a determination in step 430 can be based, for example, on an interrupt that forced entry into a low power exit.

[0035] If it is determined in step 430 that the LUs (from 0 LUs to all LUs) are awake, the method 400 includes exiting the low power state of the LUs (the awake LUs (from 0 LUs to all LUs)) using the restored frequency from step 415 in step 435 and initiating a reset sequence for the LUs in step 440. After restoration, the LU slave FSRC unit transitions to the operating frequency or the low power frequency depending on its wake state.

[0036] If, at step 430, it is determined that the LU is not awake, the method 400 includes ramping down the slave FSRC unit to a minimum frequency at step 445 and leaving the LU in a low power state at step 450. After recovery, the LU slave FSRC unit transitions to an operating frequency or a low power frequency depending on its wake state.

[0037] Figure 5 illustrates a method 500 of low power entry in the system 300 of Figure 3. The method 500 includes entering a low power entry at step 505. The low power entry may occur due to an event, such as, for example, monitoring a bit timer.

[0038] In step 510, the method 500 includes ramping the LU slave FSRC unit to the system frequency. During low power entry, the system master FSRC unit ramps the LU slave FSRC unit to the system frequency. In older systems, during context save, the slave FSRC unit in the LU is in a low power state, so its frequency is slower than the master FSRC unit in the system. In such systems, the save latency is limited by the slower LU slave FSRC unit frequency.

[0039] In step 515, the method 500 includes saving the LU slave FSRC state. The saving of the LU slave FSRC context occurs with matching master and slave FSRC unit frequencies. In older systems, the saving of the LU slave FSRC context occurs with mismatched master and slave FSRC unit frequencies. In such systems, the saving latency is limited by the slower LU slave FSRC unit frequency.

[0040] In step 520, method 500 includes determining whether an LU is awake. An LU waking up can include, for example, transitioning to full functional operation. Step 520 can occur across the LUs individually, for example, from zero LUs to all LUs. Such a determination in step 520 can be based, for example, on an event that forced a low power entry. Although shown as occurring after completion of the save in step 515, the determination in step 520 of whether an LU is awake can occur even before completion of the save in step 515.

[0041] If, at step 520, it is determined that the LU is awake, method 500 includes exiting (aborting) the low power state for the LU using the operating frequency at step 525 and initiating a reset sequence for the LU at step 530. Once the context save is complete, the LU slave FSRC unit transitions to the operating frequency or the low power frequency depending on its wake state.

[0042] If, at step 520, it is determined that no LUs (from 0 LUs to all LUs) are awake, the method 500 includes ramping down the slave FSRC unit to a minimum frequency at step 535 and entering a low power state at step 540. Once the context save is complete, the LU slave FSRC unit transitions to an operating frequency or a low power frequency depending on its wake state.

[0043] Reducing power down entry / exit latency using system 300 and methods 400 and 500 allows for deeper power states and longer residency, improving battery life and providing a better user experience due to lower exit latency.

[0044] 6 illustrates an overall latency and frequency plot 600 of a system and method for providing fast save and restore. Specifically, plot 600 includes a representation of a frequency curve 620 (expressed in GHz) and a latency curve 610 (expressed in μs) for the described fast save / restore. As shown, latency curve 610, which represents latency, decreases exponentially as frequency curve 620, which represents a linearly increasing frequency, increases linearly.

[0045] The overall latency of the present system and method depends on various factors. Producers are generally more throughput limited since reads / writes to registers require more cycles to gain context. The present embodiment supports serialized register access. Even if the network supports burst transactions, each transaction is serialized internally in the logical unit. The burst throughput of the logical unit scales approximately linearly with frequency. The producer-consumer network bandwidth is taken into account, i.e., if the consumer has a very high bandwidth, the producer will not saturate quickly. Higher voltage ramp-up times can be accounted for using a higher operating frequency. Additional overhead associated with save / restore sequences is also included. As can be seen, consumers input data packets and producers output data packets. The consumer / producer identities are not fixed roles as consumers / producers can change their roles based on state. For example, in low power entry, the producers are the LU and the system and the consumer is the SOC network, while in low power exit, the producer is the SOC network and the consumer is the LU and the system. Also, the system complex and the LU can be considered as producers / consumers with respect to each other in the exit / entry cases, respectively.

[0046] Overall, at lower frequencies, latency is expected to be higher as the producer cannot saturate the consumer bandwidth (as it is designed to handle higher frequencies during normal operation). Latency is reduced as frequency increases, but at higher frequencies the system saturates where the consumer can saturate the producer's bandwidth.

[0047] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0048] Various functional units shown in the figures and / or described herein, including but not limited to the processor 102, input driver 112, input device 108, output driver 114, output device 110, acceleration processing device 116, scheduler 136, graphics processing pipeline 134, computation unit 132, SIMD unit 138, LU 310, FSRC units 340, 360, may be implemented as a general purpose computer, processor or processor core, or as a program, software or firmware stored in a non-transitory computer-readable storage medium or another medium executable by a general purpose computer, processor or processor core. The methods provided may be implemented in a general purpose computer, processor or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data including netlists (instructions that can be stored on a computer readable medium). The result of such processing can be a mask work that is used in a subsequent semiconductor manufacturing process to manufacture a processor implementing features of the present disclosure.

[0049] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for low power exit, comprising: Utilizing a system digital frequency synthesizer (DFS) to lock a system complex frequency; ramping a plurality of logical units (LUs) to the system composite frequency by utilizing a system DFS in communication with at least one DFS associated with any of the plurality of LUs; restoring a fast save / restore control (FSRC) state for each of the plurality of LUs utilizing at least one slave FSRC unit associated with any of the plurality of LUs; exiting a low power state at a ramped frequency for at least one LU of the plurality of LUs that is woken up and restored, and ramping down to a minimum low frequency state for at least one LU of the plurality of LUs that is not woken up; and resuming a reset sequence for at least one LU that is awake among the plurality of LUs. method.

2. The low power exit includes a producer that outputs a data packet to the LU being bandwidth mismatched with a consumer that receives the data packet.

2. The method of claim 1.

3. The low power exit includes a producer that outputs a data packet to the LU being inconsistent in throughput with a consumer that receives the data packet.

2. The method of claim 1.

4. 1. A method for low power entry, comprising: Utilizing a system digital frequency synthesizer (DFS) to ramp a number of logical units (LUs) to a system frequency; storing a fast save / restore control (FSRC) state for each of the plurality of LUs utilizing at least one slave FSRC unit associated with any of the plurality of LUs; exiting a low power state at the system frequency for at least one LU of the plurality of LUs that is awake and ramping down to a minimum low frequency state for at least one LU of the plurality of LUs that is not awake; and resuming a reset sequence for the at least one LU of the plurality of LUs. method.

5. The low power entry includes a producer that outputs a data packet to the LU being inconsistent in bandwidth with a consumer that receives the data packet. The method of claim 4.

6. The low power entry includes a producer that outputs a data packet to the LU being incompatible in throughput with a consumer that receives the data packet. The method of claim 4.

7. 1. A system for fast save / restore, comprising: one or more logical units (LUs) residing in independent power domains; one or more digital frequency synthesizers (DFSs), each associated with one of the one or more LUs, the one or more DFSs configured to lock a system complex frequency and ramp the one or more LUs to the system complex frequency; one or more slave fast save / restore control (FSRC) units, each slave FSRC unit associated with one of the one or more LUs and configured to save / restore an FSRC state of the one or more LUs; system.

8. The one or more LUs are a CPU core, a graphics core, or other processor. The system of claim 7.

9. the one or more LUs interact with another computer unit shared between the one or more LUs; The system of claim 7.

10. Each DFS of the one or more DFSs is uniquely matched with one of the one or more LUs. The system of claim 7.

11. each slave FSRC unit of the one or more slave FSRC units is uniquely matched with one of the one or more LUs; The system of claim 7.

12. each slave FSRC unit of the one or more slave FSRC units is uniquely matched with one of the one or more DFSs; The system of claim 7.

13. a master fast save restore control (FRSC) unit configured to interface with the one or more slave FSRC units associated with each LU via the DFS; The system of claim 7.

14. The master / slave FSRC unit controls the clocks of the system and slave FSRC units during low power entry / exit sequences. The system of claim 13.

15. The master FSRC unit operates with each slave FSRC unit to control the frequency of the LU. The system of claim 13.

16. The master FSRC unit enables the maximum frequency of the LU DFS at the beginning of a power sequence. The system of claim 13.

17. the power sequence being one of a power down entry and a power down exit; 17. The system of claim 16.

18. Each slave FSRC unit tracks LU context during low power entry / exit sequence, and for inactive LUs, enters low frequency state after completion, and for active LUs, enters operating frequency state after completion. The system of claim 7.

19. Power down entry and exit latency is reduced by operating the LU and the system at full frequency during state save and restore. The system of claim 7.

20. The low power sequence includes any one of the following: a producer that outputs a data packet to the LU is inconsistent in bandwidth with a consumer that receives the data packet; and a producer that outputs a data packet to the LU is inconsistent in throughput with a consumer that receives the data packet. The system of claim 7.

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