A multi-cycle scheduler with speculative picking of micro-operations

Abstract

A multi-cycle scheduler for a processor includes an early wake circuit, a delayed wake circuit, and a picker circuit. In a first cycle of the clock, the early wake circuit speculatively identifies a child micro-operation as being ready whose dependencies are satisfied by a set of ready parent micro-operations. In a second cycle of the clock, the picker circuit picks at least one of the identified child micro-operations as being ready for issuance to the execution circuitry. Additionally, the delayed wake circuit blocks issuance of at least one picked child micro-operation speculatively identified as being ready upon determining that the respective parent micro-operation has not been issued to the execution circuitry.

Description

[Background technology]

[0001] In some electronic devices, a processor executes instructions from a program code (e.g., an application, an operating system, firmware, etc.) that causes the processor to perform a corresponding operation. Before executing some or all of an instruction, which may be referred to as a macroinstruction, the processor decodes the instruction into one or more micro-operations (i.e., μops or uops). Each micro-operation is a simpler, lower-level processor instruction that, when executed by the processor's execution units, causes the processor to perform a respective portion of the overall operation of the macro-instruction into which the micro-operation was decoded. For example, an ADD macroinstruction may be decoded into several micro-operations that cause the processor to perform corresponding portions of the ADD operation (e.g., getting data, adding the data together, storing the result, etc.).

[0002] In some processors, after decoding a micro operation, a decode function block in the processor transfers the micro operation to a scheduler function block in the processor, which schedules the micro operation for execution on an execution unit in the processor. The scheduler function block temporarily stores / buffers the received micro operation in a scheduler entry until an execution unit is available to execute the micro operation. The scheduler function block also ensures that previous micro operations on which the micro operation has a dependency have completed execution or will complete by the time the micro operation is being executed, so that the inputs required to execute the micro operation are available. In other words, the scheduler function block ensures that the dependencies of a micro operation are resolved before the micro operation is allowed to be picked from a scheduler entry and issued to an execution unit for execution. Thus, if these two conditions are met, i.e., all dependencies on the micro operation are resolved and an execution unit is available to execute the micro operation, the micro operation is "ready" and the scheduler can pick the ready micro operation from the respective scheduler entry for issue to the execution unit. Since there are typically only a relatively small number of execution units, and therefore there may be more ready micro-operations than there are execution units, the scheduler function block must select among the ready micro-operations to find a micro-operation to be picked. The operations to identify ready micro-operations and pick ready micro-operations to be issued to execution units are complex and time consuming. Thus, schedulers have proven difficult to design for higher throughput processors. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram illustrating an electronic device according to some embodiments. [Diagram 2]FIG. 2 is a block diagram illustrating a processor according to some embodiments. [Diagram 3] FIG. 2 is a block diagram illustrating a scheduler according to some embodiments. [Figure 4] FIG. 2 is a block diagram illustrating a dependency matrix, according to some embodiments. [Diagram 5] FIG. 1 is a block diagram illustrating an elapsed time matrix, according to some embodiments. [Figure 6] FIG. 2 is a block diagram illustrating a reduced form of an elapsed time matrix according to some embodiments. [Figure 7] 5 is a flowchart illustrating a process for speculatively identifying a micro-operation as being ready to be picked for execution in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Throughout the drawings and description, like numbers refer to the same drawing elements.

[0005] The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles described herein may be applied to other embodiments and applications. Thus, the described embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features described herein.

[0006] In the following description, various terms are used to describe the embodiments. Below are simplified general descriptions of some of the terms. Please note that these terms may have important additional aspects that are not listed here for clarity and conciseness, and therefore the description is not intended to be limiting of these terms.

[0007] Functional Block: A functional block refers to a set of interrelated circuitry, such as integrated circuitry, discrete circuitry, etc. The circuitry is "interrelated" in that the circuit elements in the circuitry share at least one characteristic. For example, the circuits may be contained in, fabricated on, or otherwise coupled to a particular integrated circuit chip, substrate, circuit board, or portion thereof, may be involved in performing particular operations (e.g., computational operations, control operations, storage operations, etc.), may be controlled by a common control element and / or a common clock, etc. The circuitry of a functional block may have any number of circuit elements, from a single circuit element (e.g., a single integrated circuit logic gate or discrete circuit element) to millions or billions of circuit elements (e.g., integrated circuit memory). In some embodiments, the functional block performs operations "in hardware" using circuitry that performs operations without executing program code.

[0008] Data: Data is a generic term referring to information that can be stored in memory and / or used in a calculation, control and / or other operation. Data includes information such as actual data (e.g., results of a calculation or control operation, outputs of processing circuitry, inputs for a calculation or control operation, variable values, sensor values, etc.), files, program code instructions, control values, variables, and / or other information.

[0009] In a described embodiment, an electronic device includes a processor having execution units used to execute micro-operations decoded from macro-instructions. For example, the execution units may include N integer execution units, where N=4, 6, or another number, each used to execute an integer micro-operation. The electronic device also includes a scheduler that performs operations associated with scheduling micro-operations for execution by the execution units. The scheduler receives micro-operations from upstream circuitry (e.g., decode circuitry, etc.), stores each received micro-operation in a respective scheduler entry, and waits to be issued for execution until an execution unit is available to execute the micro-operation and all dependencies have been resolved for the micro-operation. In other words, the scheduler ensures that an execution unit is available to execute each issued micro-operation, and ensures that all inputs to each micro-operation are / will be available to execute the micro-operation before determining that the micro-operation is ready for issue to an execution unit. The scheduler includes a wake circuit that performs operations associated with identifying a ready micro-operation stored in a scheduler entry that is ready to be picked for execution, and a picker circuit that performs operations associated with picking a ready micro-operation from a scheduler entry to be issued to an execution unit for execution. The scheduler is a two-cycle or "pipelined" scheduler. Thus, some of the above operations for scheduling a micro-operation for execution are performed by the wake circuit and / or the picker circuit on two consecutive cycles of the control clock.

[0010] In the described embodiment, the scheduler performs operations to speculatively identify micro-operations as being ready to be issued to an execution unit. A micro-operation speculatively identified as ready may be picked for issue to an execution unit in the next clock cycle (i.e., as soon as possible). More specifically, child micro-operations of ready parent micro-operations are speculatively identified as being ready to be picked for execution before it is known whether or not the ready parent micro-operation itself has been picked for execution. Thus, the "speculation" is that all ready parent micro-operations will be picked for execution. This may not be true since due to the limited number of execution units that can issue parent micro-operations and the fact that there may be many ready parent micro-operations, not all ready parent applications may be picked for execution. Thus, the scheduler subsequently recovers from the erroneous speculation on a ready child micro-operation by blocking the improperly picked / not ready child micro-operation from being issued to an execution unit for execution, however, the scheduler allows other picked child micro-operations that were speculatively identified as ready to be issued to an execution unit.

[0011] With respect to the operation of the scheduler described above, in a first cycle of the clock, an early wake circuit in the wake circuit speculatively identifies a child micro operation as ready whose dependencies are satisfied by a set of ready parent micro operations. The early wake circuit then generates an early ready signal to a picker circuit that identifies each scheduler entry in which a ready child micro operation is stored. The early wake circuit does this before it is known which of the ready parent micro operations have been picked for issuance to the execution units. In other words, the early wake circuit speculatively identifies the child micro operation as ready as if all ready parent micro operations have been picked for issuance to the execution units and thus the dependencies of the child micro operation have been / will be resolved, even though some of the ready parent micro operations may not be picked. In a second cycle of the clock, the picker circuit picks a child micro operation from among the child micro operations speculatively identified as ready for issuance to the execution units. In addition, in a second cycle of the clock, a delayed wake circuit in the wake circuit receives an identification of a parent micro operation picked for issue (in the first cycle) and determines, based on the identification, a child micro operation that was erroneously identified as ready by the early wake circuit. In other words, the delayed wake circuit determines a ready parent micro operation that was not issued for execution, and thus determines a child micro operation speculatively identified as ready that was not ready due to a dependency on a parent micro operation that was not issued. The delayed wake circuit then generates a delayed ready signal, which is used by the blocking circuit to block issuance of the picked child micro operation that was erroneously identified as speculatively ready, while other picked child micro operations that were speculatively identified as ready are allowed to issue to the execution units.

[0012] In some embodiments, the scheduler includes M scheduler entries, where each scheduler entry is used to store a micro-operation until the micro-operation is ready and can be picked for issue to an execution unit (where M=96, 125, or another number). The scheduler also includes a dependency matrix that is used to track dependencies between the micro-operations stored in the scheduler entries. The dependency matrix includes a dependency record for each scheduler entry that includes storage elements for storing information about dependencies of the micro-operations stored in that scheduler entry on the micro-operations stored in other scheduler entries. The early wake circuit and delayed wake circuit use the dependency matrix for operations described above to speculatively identify child micro-operations as being ready to be picked for issue to an execution unit. For example, in some embodiments, when generating a delayed ready signal, the delayed wake circuit identifies a ready parent micro-operation by searching the dependency record for a parent micro-operation whose dependency is satisfied by the issued grandparent micro-operation using an identifier of the grandparent micro-operation that was issued in the previous cycle of the clock. As another example, in some embodiments, when generating an early ready signal, the early wake circuitry identifies a ready child micro-operation by using the identifier of the ready parent micro-operation to search the dependency records for child micro-operations whose dependencies are satisfied by the ready parent micro-operation.

[0013] In some embodiments, the scheduler includes a broadcast circuit that determines an identifier of an issued micro-operation (i.e., a picked micro-operation issued to an execution unit) and broadcasts it to other circuitry in the scheduler. For example, in some embodiments, the broadcast circuit is connected to a dedicated signal line of each scheduler entry and asserts the signal line of each scheduler entry in which a picked micro-operation was issued. In these embodiments, the broadcast circuit determines an identifier of the issued micro-operation and communicates the identifier to a delayed wake circuit. The delayed wake circuit then uses the identifier of the issued micro-operation and the dependency matrix to generate a delayed ready signal that identifies a ready child micro-operation of the issued micro-operation. The delayed wake circuit forwards the delayed ready signal to the early wake circuit and the blocking circuit, and the delayed ready signal is used as described above. In some embodiments, the issued signal, the delayed ready signal and / or the early ready signal remain asserted until deasserted, which allows recovery from misspeculations and the like, as described above. That is, individual identifiers within the issued signal, the delayed ready signal, and / or the early ready signal are continuously asserted until a change is made.

[0014] In some embodiments, the picker circuit picks ready micro operations for issue to the execution units in order of age. In other words, the picker circuit picks ready micro operations stored in the scheduler entries in an order based on the length of time each micro operation has been stored in a given scheduler entry. For example, assuming there are N execution units, and thus a maximum of N ready micro operations can be picked in each cycle, the picker circuit may pick the oldest ready micro operation, then the second oldest ready micro operation, then the third oldest ready micro operation, and so on, until a maximum of N ready micro operations have been picked. In some of these embodiments, the scheduler (or another entity) keeps a record of the relative ages of the micro operations in the scheduler entries in an age matrix, which is a dynamically updated data structure that contains information to identify the ages of the micro operations stored in the scheduler entries. Continuing with the above example, when picking a child micro-operation from among those speculatively identified as ready for issue to an execution unit, the picker circuit picks the child micro-operations in age order.

[0015] By pipelining the scheduler operations, i.e., by spreading the scheduler operations over two clock cycles, the described embodiments provide more time for individual scheduler operations without unacceptably reducing the throughput of the scheduler. For example, operating the picker in the second cycle of the clock enables age-based picking, an operation that is difficult to perform in existing single-cycle schedulers. The pipelined scheduler design also allows the circuitry within the scheduler (e.g., dependency matrix, scheduler entries, etc.) to be scaled up / increased in size or capacity, which allows the scheduler to better handle a larger number of micro-operations and / or execution units, which is a significant issue for existing single-cycle schedulers. By speculatively marking micro-operations as ready to be picked for issue and then blocking picked micro-operations that were not ready, the described embodiments enable a two-cycle pipelined scheduler to issue micro-operations that have single-cycle dependencies in successive cycles, which is not possible with other proposed multi-cycle scheduler designs. By improving the operation of the scheduler, which is a bottleneck in existing processor designs, the described embodiments can increase the throughput of the processor in which the scheduler is included. Increasing the throughput of a processor improves the performance of the processor, which increases user satisfaction with the processor.

[0016] FIG. 1 illustrates a block diagram of an electronic device 100, according to some embodiments. As can be seen in FIG. 1, the electronic device 100 includes a processor 102 and a memory 104. Generally, the processor 102, the memory 104 are implemented in hardware, i.e., using corresponding integrated circuits, discrete circuits, and / or devices. For example, in some embodiments, the processor 102, the memory 104 are implemented in an integrated circuit on one or more semiconductor chips, in a combination of an integrated circuit on one or more semiconductor chips in combination with discrete circuits and / or devices, or in discrete circuits and / or devices. In some embodiments, the processor 102 and / or the memory 104 perform operations for or associated with a two-cycle pipelined scheduler that speculatively sets micro-operations as ready to be picked for issue to an execution unit, as described herein.

[0017] The processor 102 is a functional block that performs calculations, memory access, control, and / or other operations. For example, the processor 102 may be a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit, a system-on-chip, a field programmable gate array (FPGA), etc.

[0018] Memory 104 is a functional block that stores data for processor 102 (and possibly other functional blocks (not shown) in electronic device 100). For example, in some embodiments, memory 104 is a larger integrated circuit memory (e.g., a “main” memory, etc.) in which copies of data retrieved from a storage device (not shown) (e.g., 4 kB pages of data) are stored for access by processor 102. As another example, in some embodiments, memory 104 is a high-bandwidth memory that is a larger integrated circuit memory in which copies of data are stored for access by processor 102. Memory 104 includes memory circuitry, such as fourth generation double data rate synchronous dynamic random access memory (DDR4 SDRAM) and / or other types of memory circuitry, as well as control circuitry for handling access of data stored in the memory circuitry.

[0019] Although electronic device 100 is illustrated in FIG. 1 with a particular number and arrangement of elements, in some embodiments electronic device 100 includes a different number and / or arrangement of elements. For example, in some embodiments electronic device 100 includes a different number of processors 102. Also, electronic device 100 is simplified for illustrative purposes. However, in some embodiments electronic device 100 includes additional and / or different elements. For example, electronic device 100 may include a human interface subsystem (e.g., a display, a speaker, a keyboard, etc.), a power subsystem, an input / output (I / O) subsystem, etc. Generally, in the described embodiments electronic device 100 includes a number and / or arrangement of elements sufficient to perform the operations described herein.

[0020] Electronic device 100 may be or be included in any device that performs the operations described herein. For example, electronic device 100 may be or be included in a desktop computer, a laptop computer, a wearable electronic device, a tablet computer, a virtual or augmented reality device, a smartphone, an artificial intelligence (AI) or machine learning device, a server, a networking device, a toy, an audiovisual device, a home appliance, a vehicle, and / or combinations thereof. In some embodiments, electronic device 100 is included on one or more semiconductor chips. For example, in some embodiments, electronic device 100 is included entirely on a single "system on a chip" (SOC) semiconductor chip, included in one or more ASICs, and the like.

[0021] In the described embodiment, the electronic device includes a processor that performs operations for or associated with a two-cycle pipelined scheduler that speculatively sets micro-operations as ready to be picked for issue as described herein. Figure 2 shows a block diagram of a processor 200, according to some embodiments. In some embodiments, the processor 102 includes elements similar to those shown in the processor 200, i.e., is arranged internally in a similar manner to the processor 200.

[0022] As can be seen in FIG. 2, processor 200 includes execution (EXEC) units 202-204, each of which is a functional block including circuitry for executing micro-operations. For example, each of execution units 202-204 may include an execution pipeline, a computation unit, an FPGA, and / or other micro-operation execution circuitry that executes micro-operations that cause the circuitry to perform the corresponding operation. Processor 200 also includes address generation unit (AGU) 206, which is a functional block that executes operations for calculating addresses for load and store micro-operations. In some embodiments, some or all of execution units 202-204 and address generation unit 206 are arranged, and in some cases dedicated, to execute a particular type of micro-operation. For example, in some embodiments, execution unit 202 is a simpler integer execution unit that includes circuitry arranged to perform simpler micro-operations (e.g., simpler logical micro-operations, simpler mathematical micro-operations, micro-operations that can be executed in only a few cycles of a control clock, etc.) from among the set of micro-operations supported by processor 200, and execution unit 204 is a more complex integer execution unit that includes circuitry arranged to perform more complex micro-operations (e.g., more complex logical micro-operations, more complex mathematical micro-operations, micro-operations that require more than a few cycles of a control clock to execute, etc.) from among the set of micro-operations supported by processor 200. As another example, in some embodiments, execution unit 202 is an integer execution unit that includes circuitry arranged to perform integer micro-operations, and execution unit 204 is a floating-point execution unit that includes circuitry arranged to perform floating-point micro-operations.

[0023] Processor 200 also includes a register file 208, which is a functional block that contains circuitry for a set of physical registers. Register file 208 includes storage elements (i.e., a number of register file cells, write and read lines / ports, etc.) and access circuitry used to store operands for executing micro-operations in the storage elements and results for executing the micro-operations. The physical registers in register file 208 are referred to as "physical" registers to distinguish them from "architectural" registers, which are logical registers included in the instruction set architecture for processor 200.

[0024] Processor 200 further includes load / store unit (LOAD / STORE) 210, which is a functional block including circuitry for handling the loading and storing of data for processor 200. In some embodiments, to load data, load / store unit 210 retrieves data from L1 data cache 212, or, as appropriate, from L2 cache 214, L3 cache (not shown), memory (e.g., memory 104), or a mass storage device (not shown), and loads / stores the data to a physical register in register file 208. In some embodiments, to store data, load / store unit 210 retrieves data from execution units 202-204, physical registers in register file 208, and / or other sources, and stores the retrieved data in L1 data cache 212 and / or elsewhere (e.g., L2 cache 214, L3 cache, memory, mass storage device).

[0025] The processor 200 further includes a fetch / decode unit (FETCH / DECODE) 216. The fetch / decode unit 216 is a functional block that includes circuitry for fetching a program code instruction (or a group thereof) from an L1 instruction cache 218 (or elsewhere) and decoding the fetched instruction into a micro-operation. In other words, the fetch / decode unit 216 decodes macro-instructions in the program code into micro-operations. After decoding a micro-operation, the fetch / decode unit 216 sends the micro-operation to a dispatch 220. The dispatch 220 is a functional block that includes circuitry for selecting a scheduler among the schedulers 226-228 to which the micro-operation is forwarded to be scheduled for execution and for dispatching (i.e., forwarding, sending, etc.) the micro-operation to the selected scheduler. As explained above, in some embodiments, some or all of the execution units 202-204 and the address generation unit 206 are arranged and possibly dedicated to process a particular type of instruction. In some of these embodiments, schedulers 226-228 only process instructions of the type that are normally processed by the respective execution unit. For example, assuming that address generation unit 206 calculates addresses for load and store instructions, scheduler 228 servicing execution unit address generation unit 206 typically processes only load and store micro-operations. Thus, in some embodiments, the selection operation described above involves dispatch 220 selecting a scheduler to process each micro-operation based on the type of that micro-operation.

[0026] Processor 200 further includes a rename unit (RENAME) 222, which is a functional block that includes circuitry for allocating physical registers in register file 208 to store operands for executing a micro-operation and / or results from the execution of a micro-operation. Generally, a micro-operation first references an architectural register, which again is a set of registers in the instruction set architecture for processor 200. However, the architectural registers referenced by a micro-operation are abstract / logical and are typically not directly used to address physical registers in processor 200. Instead, the architectural registers referenced by a micro-operation are mapped by rename unit 222 to a set of physical registers in register file 208. Thus, when a micro-operation references a given architectural register (e.g., to store a result), rename unit 222 selects an acceptable and available physical register in register file 208 to be used for the micro-operation and redirects the micro-operation to use that physical register. In some embodiments, renaming unit 222 includes circuitry for determining dependencies between micro-operations and communicating information regarding the dependencies to other functional blocks within processor 200 (eg, schedulers 226-228, etc.).

[0027] Processor 200 further includes a reorder buffer (ROB) 224, which is a functional block that contains circuitry used to manage out-of-order execution of micro-operations. In general, processor 200 can execute micro-operations "out-of-order", i.e., in an order different from the order in which they are encountered in the program code, so long as the micro-operations are allowed to be executed out-of-order (i.e., have no dependencies on each other, are retired in a specified order, etc.). Reorder buffer 224 includes circuitry that is used, among other things, to keep track of in-flight micro-operations to ensure that they are retired in the correct order, and thus to update the operational / architectural state of processor 200 (i.e., L1 data cache 212, flags, settings, control values, etc.) in the proper order.

[0028] Processor 200 further includes schedulers (SCH) 226-228, which are functional blocks including circuitry for scheduling micro-operations for execution in one or more respective execution units. In general, scheduling micro-operations includes ensuring that there is an available / free execution unit to execute each of the micro-operations, that previous micro-operations on which a micro-operation depends have or will have the results required by the micro-operation for execution, etc. In some embodiments, scheduler 226 handles the scheduling of micro-operations for execution in execution units 202 and 204, and scheduler 226 handles the scheduling of micro-operations for execution in address generation unit 206. Each of schedulers 226-228 includes scheduler entry circuitry for storing micro-operations awaiting execution (possibly along with other data such as immediate values). In some embodiments, schedulers 226-228 include wake circuitry that determines which micro-operations stored in scheduler entries are ready to be picked for issue to an execution unit for execution (i.e., dependencies have been resolved), and picker circuitry that picks ready micro-operations from the scheduler entries for issue to the execution units. In some embodiments, one or both of schedulers 226-228 perform operations to speculatively identify micro-operations as ready to be picked for issue to execution units 202-204 or 206, respectively, as described herein. A more detailed example of a scheduler is shown in FIG. 3 and described below.

[0029] Processor 200 further includes a retire unit (RETIRE) 230, which is a functional block that includes circuitry for receiving information about micro-operations that have completed execution, e.g., from schedulers 226-228 and / or other functional blocks, and committing the micro-operations to the architectural state of processor 200. For example, in some implementations, retire unit 230 interacts with reorder buffer 224 to ensure that completed instructions can be safely and correctly retired, allows instruction results to be committed / written to L1 data cache 212 and / or other locations in the memory subsystem, allows processor flags and control values ​​to be set / updated, etc.

[0030] Processor 200 is illustrated in FIG. 2 with various functional blocks to provide an example of a processor for certain functional blocks and operations performed by them in the described embodiments. However, processor 200 is simplified for illustrative purposes and for clarity and brevity in describing some embodiments. In some embodiments, processor 200 includes functional blocks and / or arrangements of functional blocks that differ from those shown in FIG. 2. For example, in some embodiments, processor 200 includes a different number of execution units and schedulers. As another example, in some embodiments, processor 200 includes circuitry such as a program counter and branch prediction unit that controls the flow of instruction fetches. Generally, in the described embodiments, processor 200 includes sufficient functional blocks to perform the operations described herein.

[0031] In the described embodiment, the processor includes a two-cycle pipelined scheduler that performs operations to speculatively identify or associated with micro-operations as being ready to be picked for issue to an execution unit. FIG. 3 illustrates a block diagram of a scheduler 300 according to some embodiments. In some embodiments, one or both of scheduler 226 and scheduler 228 include elements similar to those shown in scheduler 300, i.e., are arranged internally similarly to scheduler 300. In some embodiments, some or all of the elements shown in FIG. 3 are implemented in hardware, i.e., using circuitry (e.g., logic gates, storage elements and / or other integrated circuits, discrete circuits, and / or devices) configured to perform the described operations. For example, blocking circuit (BLOCK) 316 includes circuitry configured to block certain micro-operations from being issued to an execution unit while allowing other micro-operations to be issued to an execution unit based on a delayed ready signal 324.

[0032] In the example of Fig. 3, two clock cycles, a first cycle 302 and a second cycle 304, are shown at the bottom of Fig. 3. These clock cycles represent a sequence of two consecutive clock cycles of the clock 306 during which the circuits / functional blocks in the scheduler execute their respective operations. Each of the dependency dispatch flip-flop (DEP DISP FF) 308, the early ready flip-flop (EARLY READY FF) 310, and the issued flip-flop (ISSUED FF) 312 is a rising edge flip-flop that captures data provided by an upstream circuit on the rising edge of the clock 306. For example, the early ready flip-flop 310 captures data output by the early wake circuit (EARLY WAKE) 314 on the rising edge of the clock 306 at the end of the first cycle 302. In this manner, some or all of the operations of the circuitry shown "between" the flip-flops, such as early wake circuit 314, which performs operations between the rising edge of clock 306 at the beginning of first cycle 302 and the rising edge of clock 306 at the end of first cycle 302, are performed within a single cycle of clock 306. Thus, scheduler 300 is "pipelined" in that the complete operations of scheduler 300 to schedule micro-operations are divided and performed over two successive cycles of clock 306.

[0033] 3, scheduler 300 includes scheduler entry 318, which is a functional block containing circuitry for M scheduler entries (M=96, 125, or another number). Each scheduler entry includes memory circuitry for storing micro-operations awaiting issue to an execution unit for execution, and access circuitry for accessing the micro-operations stored in that scheduler entry. In some embodiments, a scheduler entry includes memory circuitry for storing other data, such as immediate values, metadata, etc. for the micro-operation. Micro-operations are received from upstream circuitry, such as rename unit 222 (not shown), and are stored in the scheduler entry until the micro-operation is "ready," i.e., the micro-operation has been executed, the processor state is ready to execute the micro-operation, and all input operands for the micro-operation are available and / or are available. When a micro operation is prepared and / or the execution unit (e.g., execution unit 202) on which the micro operation is prepared is ready to execute the micro operation, the micro operation may be picked (i.e., retrieved, obtained, etc.) from the scheduler entry and issued to the execution unit for execution.

[0034] During operation, at or before the start of a first clock cycle, a set of micro-operations (not shown) are transferred from a rename unit (e.g., rename unit 222) and stored in scheduler entry 318. In addition, dependency dispatch flip-flop 308 captures (i.e., stores, holds, etc.) dependency information for the micro-operations transferred from the rename unit. The dependency information is provided to dependency matrix 320 via dependency dispatch flip-flop 308 and is added to existing dependency information in dependency matrix 320. Generally, the dependency information identifies dependencies between the micro-operations stored in scheduler entry 318. The dependency information received from the rename unit is arranged in a format that allows the information to be used to update dependency records in the dependency matrix, such as by including dedicated signal lines for all dependency combinations for the micro-operations stored in scheduler entry 318. For example, if there are 96 scheduler entries and the set of micro operations includes 6 micro operations, the dependency information can be transmitted over 96 x 6 signal lines (i.e., 576 signal lines, each signal line indicating a dependency on a respective scheduler entry).

[0035] FIG. 4 illustrates a block diagram of a dependency matrix 400, according to some embodiments. In some embodiments, dependency matrix 320 is internally organized similarly to dependency matrix 400. As seen in FIG. 4, dependency matrix 400 includes several rows of storage elements 402, each of which is illustrated via a box, only some of which are illustrated (and labeled) for clarity. Each row is associated with a respective scheduler entry and includes sufficient storage elements to identify the dependency of the micro-operation stored in that scheduler entry on each other micro-operation stored in the respective scheduler entry within scheduler entry 318. For example, if scheduler entry 318 includes 96 scheduler entries, dependency matrix 400 includes a 96×96 array of storage elements with 96 rows with 96 storage elements, each storage element storing a value indicating whether the micro-operation stored in the respective scheduler entry has a dependency on the micro-operation stored in the corresponding other scheduler entry. Elements for updating the dependency information are omitted from Figure 4 for clarity, but include circuitry for receiving the dependency information and updating the storage elements 402 to indicate whether a micro-operation stored in a given scheduler entry has a dependency on a micro-operation stored in another scheduler entry. Each storage element 402 is associated with a logic element 404 that contains circuitry (e.g., logic gates, etc.) used to determine whether a micro-operation stored in the respective scheduler entry is ready to be picked for issue to an execution unit. For clarity, only some of the logic elements 404 are labeled in Figure 4.The completed micro-operation signal line (COMPLETED MICRO-OPERATIONS) 406 is an input signal line to the dependency matrix 400 that identifies scheduler entries in which a micro-operation has completed execution and therefore has results available (or at least has been issued and therefore will be available by the time the micro-operations stored in other scheduler entries are issued). In some embodiments, upon completing execution of a micro-operation, the corresponding completed micro-operation signal line 406 is asserted (e.g., by the picker circuit via the blocking circuit 316 and the issued flip-flop 312) and remains asserted until all dependent micro-operations have been removed from the dependency matrix 400. The ready micro-operation signal line (READY) 408 is an output signal line from the dependency matrix 400 that identifies scheduler entries that store ready micro-operations for which all dependencies have been resolved (by the completion of one or more other micro-operations) and therefore the stored micro-operation may be picked for issue to an execution unit.

[0036] Returning to FIG. 3, in the first cycle 302 of the clock 306, the delayed wake circuit 322 generates a delayed ready signal (LATE READY) 324. The delayed ready signal 324 is a signal that identifies a ready micro-operation to be picked for issuance to an execution unit based on a micro-operation issued in a previous cycle of the clock (i.e., the 0th cycle of the clock). The delayed wake circuit 322 generates the delayed ready signal 324 by forwarding an issued signal (ISSUED) 326 to a dependency matrix 320, which outputs a ready signal (READY) 328. More specifically, the dependency matrix 320 generates the ready signal 328 by providing the issued signal 326 to a logic element (e.g., logic element 404), which generates the ready signal 328 to identify a scheduler entry that stores the ready micro-operation for issuance to an execution unit. The delayed wake circuit 322 then forwards the ready signal 328 to the early wake circuit 314 as a delayed ready signal 324. The early wake circuit 314 then generates an early ready signal (EARLY READY) 330 based on the delayed ready signal 324. The early wake circuit 314 generates the early ready signal 330 by forwarding the delayed ready signal 324 as a delayed ready signal (LATE READY) 332 to the dependency matrix 320, which outputs a ready signal (READY) 334. More specifically, the dependency matrix 320 generates the ready signal 334 by providing the delayed ready signal 332 to a logic element (e.g., logic element 404), which generates the ready signal 334. The ready signal 334 identifies a scheduler entry for which the micro operation will become ready if all of the micro operations stored in the scheduler entries identified as ready in the delayed ready signal 332 are picked for execution.Because more scheduler entries may be identified as ready in the delayed ready signal 332 than there are execution units, some of the micro-operations stored in scheduler entries identified as ready in the delayed ready signal 332 may not be picked. Thus, the identification of a scheduler entry for which a micro-operation will be ready in the ready signal 334 is speculative (i.e., not guaranteed to occur). In other words, the early ready signal 330 speculatively identifies a child micro-operation as ready for picking based on a parent micro-operation that is ready but it is not yet known whether / which parent micro-operation will be picked. At the end of the first cycle 302 of the clock 306, the early ready signal 330 is captured into the early ready flip-flop 310.

[0037] In the second cycle 304 of the clock 306, an early ready signal 330 is provided by the early ready flip-flop 310 to the picker circuit 336. In other words, the micro-operations speculatively identified as ready for execution (i.e., the scheduler entry in which these micro-operations are stored) are provided to the picker circuit 336 so that the picker circuit 336 can pick from among the micro-operations speculatively identified as ready for issuance to the execution units. The picker circuit 336 then picks from among the micro-operations speculatively identified as ready for issuance to the execution units. In some embodiments, for this operation, the picker circuit 336 picks the ready micro-operations in order of age, such that the oldest ready micro-operation is picked first and subsequent ready micro-operations are picked in order of age. The picker circuit 336 then transfers the picked micro-operations (PICKED UOPS) 338 to the blocking circuit 316. The blocking circuit 316 receives the picked micro operation 338 and a delayed ready signal 324, which identifies ready micro operations to be picked for issue to the execution units based on micro operations issued in a previous cycle of the clock (i.e., in the first cycle of the clock; recall that these operations will occur in the second cycle of the clock). Thus, the delayed ready signal 324 reliably identifies which of the parent, i.e., child, micro operations of the picked micro operation speculatively identified as ready will be picked for issue to the execution units. This resolves the speculation from the first cycle 302 by identifying the ready parent micro operation that was picked for issue (recall that not all ready parent micro operations are guaranteed to be picked for issue). The blocking circuit 316 then blocks issue of the picked micro operations that were speculatively identified as ready but were not ready, which resolves the misspeculation.However, the blocking circuit 316 allows the remaining picked micro-operations to be issued to the execution circuitry. Once issued, the remaining micro-operations proceed to downstream circuitry (i.e., "register read / execute") for processing and execution. At the end of the second cycle 304 of the clock 306, the picked micro-operation 338 (e.g., an identifier of the scheduler entry for the issued micro-operation) is captured in the issued flip-flop 312. From the issued flip-flop 312, the issued signal 326 is forwarded to the delayed wake circuit 322 for generating the next delayed ready signal 324, as described above.

[0038] In some embodiments, the picker circuit (e.g., picker circuit 336) picks micro operations for issuance to the execution units in age order. For example, in some embodiments, the picker circuit picks micro operations for issuance to the execution units in age order from the oldest ready micro operation to the newest micro operation. In some of these embodiments, the picker circuit uses an age matrix to pick the micro operations in age order. In general, an age matrix is ​​a data structure that contains information used to identify the relative age of items stored in scheduler entries. FIG. 5 shows a block diagram illustrating an age matrix 500, according to some embodiments. FIG. 6 shows a block diagram illustrating a reduced form of an age matrix 600, according to some embodiments. In the examples of FIGS. 5-6, Ms and Ks are used as value placeholders within the elements of age matrices 500 and 600 for illustrative purposes, but have no particular meaning. The values ​​of the bits in age matrices 500 and 600 and the interpretation of the relative age information are described in more detail below.

[0039] As can be seen in FIG. 5, elapsed time matrix 500 includes several elements 502 arranged in rows 504 and columns 506 (for clarity, only some of them are marked in FIG. 5). The elements in each row and column are associated with different scheduler entries and are used to store elapsed time information for the associated scheduler entries (i.e., for the micro-operations stored in the associated entries). For example, the bottom row and left-most column of elapsed time matrix 500 is associated with scheduler entry "entry_0". Thus, the bottom row and left-most column of elapsed time matrix 500 store elapsed time information for the micro-operations stored in entry_0. Note that the diagonal rows of elapsed time matrix 500 that hold values ​​representing the relative elapsed times of micro-operations stored in the same scheduler entry are not practical and are therefore shown in black. In some embodiments, the elapsed time information is stored in each element using a specified number of bits. For example, in some embodiments, age information is stored for each element in age matrix 500 using two bits, with 00 representing a younger item, 11 representing an older item, and 10 or 01 representing an unset or invalid element (or an invalid value). In these embodiments, the scheduler entry containing the oldest micro operation is determined based on the column that does not contain an 11 (possibly all 00).

[0040] Although the elapsed time matrix 500 shown in FIG. 5 is an example of a particular arrangement of data for an elapsed time matrix, in some embodiments, the elapsed time matrix stores data in one or more different arrangements, including arrangements that are not easily read (e.g., lists, tables, etc.), but that are otherwise representative of what is shown in FIG. 5. An elapsed time matrix 600, which is a reduced form of the elapsed time matrix 500, is shown in FIG. 6, according to some embodiments. Similar to the elapsed time matrix 500, the elapsed time matrix 600 includes elements 602 arranged in rows 604 and columns 606 (only some of which are marked in FIG. 6 for clarity). However, unlike the elapsed time matrix 500, the elapsed time matrix 600 lacks elements in rows and columns above a reflection (REF) line 608. This is because the values ​​stored in such elements of the elapsed time matrix 600 can be determined by swapping the values ​​of elements present in the elapsed time matrix 600 with the reflecting (in this example, M is a swap of K, and vice versa). 6 using dotted lines and italicized text (which are similar to the values ​​of the corresponding elements of elapsed time matrix 500). In other words, given information of the elements on one side of the reflected line 608, the values ​​stored in the elements on the other side of the reflected line can be calculated. For this reason, in some embodiments, a reduced elapsed time matrix 600 is used instead of elapsed time matrix 500. In general, in the described embodiments, any arrangement of values ​​can be stored in an elapsed time matrix having a respective set of rows and columns (or equivalent) and used to determine the relative elapsed times of scheduler entries.

[0041] In a described embodiment, the multi-cycle scheduler performs operations to speculatively identify a micro-operation as ready to be picked for issue to an execution unit. FIG. 7 illustrates a flow chart illustrating a process for speculatively identifying a ready micro-operation to be picked for issue to an execution unit, according to some embodiments. FIG. 7 is presented as a general example of operations that may be performed in some embodiments. However, in other embodiments, different operations may be performed and / or operations may be performed in a different order. Additionally, although certain elements (e.g., early wake circuitry, etc.) are used in describing the process, in some embodiments, other elements may perform the operations.

[0042] As seen in FIG. 7, the process begins when an early wake circuit (e.g., early wake circuit 314) speculatively identifies a child micro operation as being ready whose dependencies are satisfied by a set of ready parent micro operations (step 700). For this operation, the early wake circuit determines the set of ready parent micro operations, such as by receiving a delayed ready signal (e.g., delayed ready signal 324) that identifies the ready parent micro operation based on a previously issued micro operation (i.e., a grandparent micro operation). The early wake circuit then identifies the child micro operation as ready to be issued that has a dependency that is satisfied by the ready parent micro operation. As explained above, in some embodiments, this includes the early wake circuit using a dependency matrix to determine the ready child micro operation based on the ready parent micro operation. Note that the ready parent micro operation that has been or will be picked for issue is not known at this point (the ready parent micro operation itself is picked later in the first cycle). Thus, assuming all of the ready parent micro operations are picked and issued for execution, the child micro operation is identified as speculatively executable. As described below, a misspeculation in step 700, i.e., an identification of a child micro operation as ready that turns out to be erroneous if one or more ready parent micro operations were not picked, is then corrected.

[0043] In step 700, the dependencies of each of the child micro operations are "satisfied" by the ready parent micro operation in that, when each ready parent micro operation is executed, it causes the execution unit to produce a result (or otherwise update the processor state) required as an input (or otherwise) by one or more of the child micro operations. In some cases, some or all of the child micro operations have dependencies on one or more previously issued micro operations in addition to one or more of the ready parent micro operations, but the one or more ready parent micro operations generate the final result (or other processor state update) required by those child micro operations in order for the child micro operations to be ready for execution and therefore the parent micro operation to "satisfy" the child micro operation's dependency.

[0044] Next, a picker circuit (e.g., picker circuit 336) picks some or all of the child micro operations speculatively identified as ready for issue to the execution circuit (step 702). For this operation, the early wake circuit communicates identities (e.g., scheduler entry identifiers, etc.) of the child micro operations speculatively identified as ready to the picker circuit, which picks from among the ready child micro operations for issue to the execution units. In some embodiments, the picker circuit picks ready child micro operations by age (e.g., the picker circuit uses an age matrix or other identifier for relative micro operation ages to determine the relative ages of the micro operations), with older child micro operations being picked first. Note that for this operation, because there may be more ready child micro operations than there are execution units, the picker circuit may pick less than all of the ready child micro operations. In some cases, a child micro operation speculatively identified as ready is included with other ready micro operations (i.e., a ready micro operation that is / was ready in a previous cycle but was not picked due to an overabundance of ready micro operations in the previous cycle, etc.). In these embodiments, due to age-based picking, an older ready micro operation may end up being picked before a ready child micro operation, and none of the ready child micro operations may be picked. However, in the example of FIG. 7, assume that there are no other / previous ready micro operations waiting to be picked, and therefore some or all of the ready child micro operations may be picked.

[0045] A delayed wake circuit (e.g., delayed wake circuit 322) then determines a parent micro operation from among the set of ready parent micro operations that were not issued to an execution unit, and thus a child micro operation speculatively identified as ready that was not ready (step 704). For this operation, the delayed wake circuit receives the identity of a ready parent micro operation that was issued in the previous cycle of the clock (e.g., issued signal 326). The delayed wake circuit then uses the dependency matrix to determine child micro operations speculatively identified as ready in step 700 that were found to be not ready because their respective parent applications were not picked for issue. In this manner, as explained above, the delayed wake circuit determines a speculation miss regarding the readiness of each child micro operation.

[0046] The delayed wake circuit then blocks issuance of picked child micro-operations that were speculatively identified as ready but were not yet ready, but allows the remaining picked child micro-operations that were speculatively identified as ready to be issued to the execution circuit (step 706). For this operation, the delayed wake circuit communicates the identity of the ready child micro-operations (e.g., delayed ready signal 324) to a blocking circuit (e.g., blocking circuit 316), which prevents the picked but not yet ready micro-operations from being issued to the execution unit. This may include discarding the picked but not yet ready micro-operations or performing more complex operations to process the picked but not yet ready micro-operations. The blocking circuit allows picked micro-operations that are ready to be issued to the execution unit based on the identity communicated from the delayed wake circuit, thereby allowing these micro-operations to proceed in execution. Although the blocked micro-operations are blocked, the blocked micro-operations are eventually picked for execution after issuing the parent application to the execution unit for execution.

[0047] In some embodiments, at least one electronic device (such as, for example, electronic device 100) or a portion thereof uses code and / or data stored in a non-transitory computer-readable storage medium to perform some or all of the operations described herein. More specifically, at least one electronic device reads the code and / or data from the computer-readable storage medium and executes the code and / or uses the data when performing the described operations. The computer-readable storage medium may be any device, medium, or combination thereof that stores code and / or data used by the electronic device. For example, the computer-readable storage medium may include, but is not limited to, volatile and / or non-volatile memory, such as flash memory, random access memory (e.g., DDR5 DRAM, SRAM, eDRAM, etc.), non-volatile RAM (e.g., phase change memory, ferroelectric random access memory, spin transfer torque random access memory, magnetoresistive random access memory, etc.), read-only memory (ROM), and / or magnetic or optical storage media (e.g., disk drives, magnetic tapes, CDs, DVDs, etc.).

[0048] In some embodiments, one or more hardware modules perform the operations described herein. For example, a hardware module may include, but is not limited to, one or more central processing units (CPUs) / CPU cores, graphics processing units (GPUs) / GPU cores, application-specific integrated circuit (ASIC) chips, field programmable gate arrays (FPGAs), compressors or encoders, computational units, embedded processors, accelerated processing units (APUs), controllers, requesters, completers, network communication links, and / or other functional blocks. When circuitry (e.g., integrated circuit elements, discrete circuit elements, etc.) within such a hardware module is activated, the circuitry performs some or all of the operations. In some embodiments, a hardware module includes general-purpose circuits, such as execution pipelines, computational or processing units, that perform operations upon execution of instructions (e.g., program code, firmware, etc.). In some embodiments, a hardware module includes application-specific or dedicated circuits that perform operations "in hardware" without executing instructions.

[0049] In some embodiments, data structures representing some or all of the functional blocks and circuit elements described herein (e.g., electronic device 100 or some portion thereof) are stored in a non-transitory computer-readable storage medium including a database or other data structure that can be read by the electronic device and used directly or indirectly to fabricate hardware including the functional blocks and circuit elements. For example, the data structure can be a behavioral level description or a register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool that can synthesize the description to generate a netlist including a list of transistors / circuit elements from a synthesis library that represents the functionality of the hardware including the functional blocks and circuit elements described above. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor processing steps to fabricate a semiconductor circuit or circuits (e.g., integrated circuits) corresponding to the functional blocks and circuit elements described above. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0050] In this description, variables or unspecified values ​​(i.e., general descriptions of values ​​without specific examples of values) are represented by letters such as N, T, X, etc. As used herein, despite the possible use of similar letters in different places in this description, the variables and unspecified values ​​in each instance are not necessarily the same, i.e., there may be variables and values ​​intended for some or all of the general variables and unspecified values. In other words, the examples of specific values ​​of N, and any other letters used to represent variables and unspecified values ​​in this description, are not necessarily related to each other.

[0051] As used herein, the phrase "et al." or "etc." is intended to present one and / or instance, i.e., the equivalent of "at least one of" the elements in the list with which the "et al." is associated. For example, in a statement that "the electronic device performs a first operation, a second operation, etc.", the electronic device performs at least one of the first operation, the second operation, and the other operation. In addition, the elements in the list with which the "et al." are merely examples from a set of examples, and at least some of the examples may not appear in some embodiments.

[0052] The foregoing descriptions of the embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Accordingly, many modifications and variations will be apparent to those skilled in the art. Further, the above disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. 1. A scheduler for a processor, comprising: The early wake circuit, a delayed wake circuit; a picker circuit; In the first cycle of the clock: the early wake circuit speculatively identifies a child micro-operation as being ready whose dependencies are satisfied by a set of ready parent micro-operations; In a second cycle of the clock, said picker circuitry picks at least one of said child micro-operations speculatively identified as ready for issue to an execution circuitry; the delayed wake circuit blocks issuance of at least one picked child micro-operation speculatively identified as ready upon determining that a respective parent micro-operation has not been issued to an execution circuit; Scheduler.

2. a scheduler entry circuit including a set of scheduler entries for storing micro-operations picked by said picker circuit for issuance to an execution circuit; a dependency matrix circuit including a dependency record for each scheduler entry, each dependency record including a storage element for storing information identifying dependencies of micro-operations stored in that scheduler entry on micro-operations in other scheduler entries; The early wake circuitry speculatively identifies the child micro-operation as ready by: receiving a delayed ready signal generated by the delayed wake circuit, the delayed ready signal identifying a ready parent micro-operation based on a micro-operation issued for execution in a previous cycle of the clock; searching the dependency matrix based on the delayed ready signal to find the child micro-operation whose dependency is satisfied by the set of ready parent micro-operations; providing an early ready signal to said picker circuitry identifying said child micro-operation; The scheduler of claim 1.

3. A blocking circuit is provided. During the second cycle of the clock, the delayed wake circuit generating an updated delayed ready signal that identifies a ready child micro-operation based on a parent micro-operation issued for execution in the first cycle of the clock; forwarding the updated delayed ready signal to the blocking circuitry, which blocks issuance of the at least one picked child micro operation speculatively identified as ready upon determining based on the updated delayed ready signal that the at least one picked child micro operation was not ready due to a respective parent micro operation not being issued to an execution circuitry. The scheduler of claim 2.

4. the delayed wake circuit is used to forward the updated delayed ready signal to the early wake circuit for speculatively identifying as ready grandchild micro-operations whose dependencies are satisfied by the ready child micro-operation. The scheduler of claim 3.

5. a broadcast circuit including a respective signal line associated with each scheduler entry, the broadcast circuit asserting a signal on the respective signal line for the scheduler entry in which each micro-operation is issued for execution; the broadcast circuitry asserts a signal on a respective signal line associated with a scheduler entry for each parent micro-operation issued for execution during the first cycle of the clock; the delayed wake circuit generates the updated delayed ready signal by searching the dependency matrix based on each asserted signal line to find a ready child micro-operation whose dependency is satisfied by a parent micro-operation issued for execution in the first cycle of the clock. The scheduler of claim 3.

6. any picked child micro-operations that are speculatively identified as ready and blocked from issue are picked again for execution in subsequent cycles of the clock and allowed to issue to an execution unit when their parent micro-operations are issued; The scheduler of claim 1.

7. and upon determining that each parent micro-operation has been issued to the execution circuitry, the delayed wake circuitry enables picked child micro-operations that have been speculatively identified as being ready to be issued to the execution circuitry. The scheduler of claim 1.

8. When picking for issue said at least one of said child micro operations identified as speculatively ready, the picker logic picks the child micro operations in chronological order, with the oldest child micro operations being picked first; The scheduler of claim 1.

9. an elapsed time matrix circuit including an elapsed time matrix having information regarding relative elapsed times of micro-operations stored in scheduler entries; said picker logic circuitry determines a chronological order of said child micro-operations based on information in said elapsed time matrix. The scheduler of claim 8.

10. a specified number of execution units for executing micro-operations; when the picker circuitry picks the at least one of the child micro operations speculatively identified as ready for issue to an execution circuit, the picker circuitry picks a maximum of the specified number of the child micro operations speculatively identified as ready and no other of the child micro operations speculatively identified as ready. The scheduler of claim 1.

11. A micro-operation is ready when all scheduler entries on which the micro-operation depends have been picked and issued to the execution circuitry. The scheduler of claim 1.

12. 1. A method for processing micro-operations in a scheduler within a processor, comprising: In the first cycle of the clock: speculatively identifying a child micro-operation as being ready whose dependencies are satisfied by a set of ready parent micro-operations; In a second cycle of the clock, picking at least one of said child micro-operations speculatively identified as ready for issue to execution circuitry; and blocking issuance of at least one picked child micro-operation speculatively identified as ready upon determining that the respective parent micro-operation has not been issued to the execution circuitry. method.

13. Speculatively identifying the child micro-operation as ready comprises: receiving a delayed ready signal, said delayed ready signal identifying a ready parent micro-operation based on a micro-operation issued for execution in a previous cycle of said clock; searching a dependency matrix based on said delayed ready signal to find said child micro-operations whose dependencies are satisfied by said set of ready parent micro-operations; providing an early ready signal identifying the child micro-operation.

13. The method of claim 12.

14. In the second cycle of the clock, generating an updated delayed ready signal that identifies a ready child micro-operation based on a parent micro-operation issued for execution in the first cycle of the clock; and upon determining based on the updated delayed ready signal that the at least one picked child micro operation was not ready due to its respective parent micro operation not being issued to execution circuitry, blocking issuance of the at least one picked child micro operation speculatively identified as ready.

14. The method of claim 13.

15. using said updated delayed ready signal to speculatively identify a grandchild micro-operation as being ready to have its dependency satisfied by said ready child micro-operation.

15. The method of claim 14.

16. asserting a signal on a respective signal line associated with a scheduler entry for each parent micro-operation issued for execution during the first cycle of the clock; generating the updated delayed ready signal by searching the dependency matrix based on each asserted signal line to find a ready child micro-operation whose dependency is satisfied by a parent micro-operation issued for execution in the first cycle of the clock.

15. The method of claim 14.

17. re-picking for execution, in a subsequent cycle of the clock, a picked child micro-operation that was speculatively identified as ready and blocked from issue, and allowing the child micro-operation to be issued to an execution unit when a parent micro-operation of the child micro-operation is issued.

13. The method of claim 12.

18. Picking for issue the at least one of the child micro-operations speculatively identified as ready includes: picking the child micro actions in order of age, with the oldest child micro action being picked first; 13. The method of claim 12.

19. determining an elapsed time order for said child micro-operations based on information in an elapsed time matrix; 20. The method of claim 18.

20. when picking for issue to an execution circuit said at least one of said child micro-operations speculatively identified as ready, picking a maximum of said specified number of child micro-operations among said child micro-operations speculatively identified as ready, said specified number being equal to a number of execution units; and not picking any other of the child micro-operations speculatively identified as ready.

13. The method of claim 12.

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