Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the abrupt current rise during turn-on of the semiconductor device without significantly compromising the effective area of the semiconductor device.SOLUTION: A planar layout on a semiconductor substrate SB has a distribution of threshold voltages for switching. When a histogram is defined by multiple classes with a class width of 100 mV and multiple frequencies corresponding to an area of the planar layout belonging to each of the multiple classes for the threshold voltage, the planar layout includes multiple regions RG1 to RGn belonging to different classes among the multiple classes. The multiple regions RG1 to RGn include first to third regions RG1 to RG3. The histogram has a distribution PFL with a tail thereof extending, based on a normal distribution PNM, on a lower voltage side continuously from the normal distribution PNM.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices, and more particularly to insulated gate bipolar transistors or reverse conducting insulated gate bipolar transistors. [Background technology]

[0002] According to International Publication No. 2012 / 141121 (Patent Document 1), in a semiconductor device having a power system active element with an insulated gate such as a power MOSFET, a sub active cell region is provided in the active cell region, which has a lower threshold voltage than other regions and occupies a relatively small area. This document claims that the occurrence of a jump voltage can be reduced because the sub active cell region turns on first when the device is turned on.

[0003] According to JP 2016-154218 A (Patent Document 2), a semiconductor device includes a transistor cell and an enhancement cell. Each transistor cell includes a body region that forms a first pn junction with a drift structure. The transistor cell forms an inversion channel in the body region when a first control signal exceeds a first threshold. The delay unit generates a second control signal whose trailing edge is delayed with respect to the trailing edge of the first control signal. The enhancement cell forms an inversion layer in the drift structure when the second control signal falls below a second threshold that is lower than the first threshold. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2012 / 141121 [Patent Document 2] JP 2016-154218 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the technique of WO 2012 / 141121, simply providing a sub active cell region is likely to result in a large deviation from the switching characteristics originally desired by users of the semiconductor device.

[0006] The technology disclosed in the above-mentioned JP 2016-154218 A forms heterogeneous gate electrodes in heterogeneous cells and sends a delayed signal corresponding to the cell. This causes some cells to turn off earlier, facilitating carrier discharge. This reduces turn-off loss. In this way, it is considered that the configuration of providing separate control signals to each cell can be configured to obtain various effects, not limited to reducing turn-off loss. For example, it is considered that it is possible to suppress radiation noise from the semiconductor device by suppressing the sudden rise in current at turn-on. However, in order to receive multiple types of control signals, the semiconductor device needs to have multiple types of control pads (gate pads). As a result, the effective area of ​​the semiconductor device is greatly impaired.

[0007] The present disclosure has been made to solve the above-mentioned problems, and one of its objectives is to provide a semiconductor device that can suppress a sudden rise in current when the semiconductor device is turned on, without significantly compromising the effective area of ​​the semiconductor device. [Means for solving the problem]

[0008] One aspect of the present disclosure is a semiconductor device that is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, comprising a semiconductor substrate including a drift layer having a first conductivity type, and a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device. A planar layout on the semiconductor substrate has a distribution of threshold voltages for the switching. When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to the areas of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, the plurality of regions include first to third regions, and the histogram has a distribution that is based on a normal distribution and has a tail that is continuous from the normal distribution to the low voltage side. Effect of the Invention

[0009] According to one aspect of the present disclosure, the histogram has a continuous distribution that has a tail on the low voltage side compared to a normal distribution. By utilizing this distribution, it is possible to suppress a sudden rise in current when the semiconductor device is turned on without significantly reducing the effective area of ​​the semiconductor device.

[0010] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view for explaining definitions of a plurality of regions in a planar layout on a semiconductor substrate of a semiconductor device; [Diagram 2] 10 is a graph showing a histogram of threshold voltage distribution in a planar layout of the semiconductor device according to the first comparative example. FIG. [Diagram 3] 1 is a plan view showing a configuration of a planar layout on a semiconductor substrate of a semiconductor device according to a first comparative example. [Figure 4]FIG. 11 is a graph showing a histogram of threshold voltage distribution in a planar layout of the semiconductor device according to the second comparative example. [Diagram 5] 4 is a graph showing a histogram of threshold voltage distribution in a planar layout of the semiconductor device according to the first embodiment. FIG. [Figure 6] 1 is a plan view showing a configuration of a planar layout on a semiconductor substrate of a semiconductor device according to a first or second embodiment. [Figure 7] FIG. 7 is a plan view showing a modification of FIG. 6. [Figure 8] 4 is a graph showing an example of transfer characteristics of the semiconductor device according to the first embodiment. [Figure 9] 13 is a graph showing a histogram of threshold voltage distribution in a planar layout of the semiconductor device according to the second embodiment. FIG. [Figure 10] 11 is a graph showing an example of transfer characteristics of the semiconductor device according to the second embodiment. FIG. [Figure 11] FIG. 1 is a cross-sectional view illustrating a schematic configuration of a typical insulated gate bipolar transistor. [Figure 12] 1 is a cross-sectional view showing a configuration of an insulated gate bipolar transistor as a semiconductor device according to a first or second embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a modification of FIG. [Figure 14] FIG. 7 is a plan view showing a modification of FIG. 6. [Figure 15] FIG. 7 is a plan view showing a modification of FIG. 6. [Figure 16] FIG. 7 is a plan view showing a modification of FIG. 6. [Figure 17] FIG. 7 is a plan view showing a modification of FIG. 6. [Figure 18] FIG. 18 is a graph showing a possible example of the distribution of threshold voltages along line XVIII-XVIII in FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0013] In the following, the case where the first conductivity type is n-type and the second conductivity type is p-type will be mainly described, but the first conductivity type may be p-type and the second conductivity type may be n-type. - " indicates a lower concentration than "n", and "n + " indicates that the impurity concentration is higher than "n". Similarly, "p - " indicates that the impurity concentration is lower than "p", and "p + " indicates that the impurity concentration is higher than "p".

[0014] In the following description, only the concentration of impurities that determine the conductivity type is mentioned, but carbon, which is an element of the same group as silicon, the main component of semiconductors, may be contained. In addition, when the MCZ (Magnetic Field Applied Czochralski) method is applied, oxygen, boron, or nitrogen that is introduced in association with the MCZ method may be contained.

[0015] In the following, it will be described that the active cell region has regions RG1 to RGn (first to nth regions) corresponding to the distribution of the threshold voltage of switching of the semiconductor device. The region with the largest area ratio in the active cell region is called region RG1, and the other regions are called region RG2, region RG3, ...region RGn in descending order of area ratio. In addition, a histogram is defined for regions RG1 to RGn, as will be described in detail later. Before describing the embodiment, the definitions of these regions in this specification will be described first. Specifically, the threshold voltage may be defined as a gate voltage required to pass a current amount that is 1 / 10,000 of the rated current density when a rated voltage is applied between the collector and emitter. In that case, for example, when the rated current density of the semiconductor device is 15 A / cm 2 If so, the current density is 1.5mA / cm 2The gate voltage at which this occurs is the threshold voltage.

[0016] First, matters common to the present embodiment and a comparative example described later will be described with reference to FIG. 1. FIG. 1 is a plan view for explaining the definition of a plurality of regions RG1 to RGn included in a planar layout on a semiconductor substrate SB of a semiconductor device 100. The semiconductor device 100 is an insulated gate bipolar transistor (IGBT) or a reverse conducting insulated gate bipolar transistor (RC-IGBT). The planar layout of the semiconductor device 100 includes an active IGBT cell region 10, a termination region 30, and a gate pad region 41. The semiconductor device 100 may have a diode region (not shown) in a region different from the active IGBT cell region 10.

[0017] The planar layout has a distribution of threshold voltages for switching of the semiconductor device 100. A plurality of classes are defined for the threshold voltages with a class width of 100 mV (in other words, a typical value of ±50 mV). The planar layout has a plurality of regions RG1 to RGn that belong to different classes among the plurality of classes. In other words, different regions belong to different classes, and one region belongs to one class. A histogram (see, for example, FIG. 2) is defined by these classes and a plurality of frequencies corresponding to the areas of the planar layout that belong to each of the plurality of classes.

[0018] If the class width is made too small, the number of classes required to express the distribution of the threshold voltages increases without limit, and therefore the number of regions also increases without limit. Conversely, if the class width is made too large, the number of regions will be reduced to one in an extreme case, regardless of the distribution of the threshold voltages. Histograms with these inappropriate class widths cannot properly evaluate the characteristics of the distribution of the threshold voltages in this embodiment, which will be described later. In order to clearly distinguish and evaluate the characteristics from the manufacturing variations that have been naturally assumed in the past, the class width needs to be selected appropriately, and according to the study by the inventor, 100 mV is one of the optimal values. Since the distribution range of the threshold voltages in the same substrate (in other words, the same chip) of a general IGBT that is not intended to have multiple threshold voltages is 100 mV or less, by setting the class width to 100 mV, it is assumed that the histogram of this general IGBT will be contained within two classes or less (in other words, a voltage range of ±100 mV), and even if overestimated, it is considered to be contained within five classes corresponding to the five regions RG1 to RG5.

[0019] FIG. 2 is a graph showing a histogram of the distribution of threshold voltages Vth in the planar layout of the semiconductor device 100P according to the first comparative example. FIG. 3 is a plan view showing the configuration of the planar layout on the semiconductor substrate SB of the semiconductor device 100P according to the first comparative example. The semiconductor device 100P has a threshold voltage distribution represented by five classes corresponding to the five regions RG1 to RG5 as described above. The distribution of the histogram of the semiconductor device 100P is substantially a normal distribution PNM as a whole. The frequency of each class in the histogram of FIG. 2 corresponds to the area of ​​each of the regions RG1 to RG5 in FIG. 3. For example, in FIG. 3, the region RG2 has 10 scattered minute parts, and the total area of ​​these minute parts corresponds to the frequency of the class "5.85-5.94" [V] in FIG. 2. The distribution of threshold voltages containing unintentional manufacturing variations includes, for example, a region having randomly scattered minute parts as shown in FIG. 3. It is appropriate to evaluate the distribution of the characteristics of the semiconductor device in the planar layout by using the unit cell of the semiconductor device as a unit. Therefore, if the area of ​​one unit cell is defined as a unit area, when the above-mentioned infinitesimal portion is composed of one unit cell, the area of ​​the infinitesimal portion corresponds to the unit area. Also, when the infinitesimal portions are gathered to form an island-like portion that spans multiple unit cells, the area of ​​the infinitesimal portion is the unit area multiplied by the number of multiple unit cells.

[0020] FIG. 4 is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device 100Q according to the second comparative example. This is considered to correspond to an example of a case where the technology of the above-mentioned International Publication No. 2012 / 141121 is simply applied. Thus, the semiconductor device 100Q is an example of a semiconductor device in which a plurality of regions having different threshold voltages are intentionally formed. Specifically, as shown in the figure, large regions A and B are provided corresponding to each intended threshold voltage. Each of the large regions A and B has a substantially normal distribution due to manufacturing variations and the like. On the other hand, the distribution of the large region A and the distribution of the large region B are not continuous. In other words, the distribution of the large region A and the distribution of the large region B do not overlap. Here, not continuous (or not overlapping) means that a class with a frequency of zero is interposed between the large region A and the large region B.

[0021] As described above, if an evaluation were performed using a histogram having an excessively wide class width, the distribution of large region A and the distribution of large region B would be continuous. However, a configuration in which large region A and large region B are separated by a class with a frequency of zero to the extent shown in the histogram of Fig. 4 is due to the designer's intention in this technical field rather than manufacturing variation, and in order to be able to appropriately evaluate such characteristics, evaluation is performed in this specification using a class width of 100 mV.

[0022] Fig. 5 is a graph showing a histogram of threshold voltage distribution in the planar layout of the semiconductor device 101 according to the embodiment 1. Fig. 6 is a plan view showing the configuration of the planar layout of the semiconductor device 101 on the semiconductor substrate SB.

[0023] The histogram of the semiconductor device 101 (FIG. 5) includes a substantially normal distribution PMN (a region with sparse hatching in FIG. 5) similar to the histogram of the semiconductor device 100P (FIG. 2), but has a distribution that is continuously biased toward the low-voltage side compared to the normal distribution PMN. Specifically, the histogram of the semiconductor device 101 has, in addition to the normal distribution PMN, a tailing distribution PFL (a region with dense hatching in FIG. 5) that is a distribution that tails toward the low-voltage side. In other words, the histogram has a tailing distribution PFL that tails toward the low-voltage side continuously from the normal distribution PMN, based on the normal distribution PMN. The histogram of the semiconductor device 101 (FIG. 5) is different from the histogram of the semiconductor device 100Q (FIG. 4) in that there is no class with a frequency of zero between classes with non-zero frequencies. In FIG. 5, the distribution of the histogram is formed by overlapping the tailing distribution PFL on the low-voltage side of the normal distribution PMN. Therefore, the histogram is continuous.

[0024] The planar layout (FIG. 6) has eight regions RG1 to RG8 that belong to different classes among the classes shown in FIG. The regions RG1 to RGn in the planar layout are not limited to the eight regions RG1 to RG8, but may include at least the regions RG1 to RG3, and preferably include the regions RG1 to RG6. This also applies to the second embodiment described later.

[0025] The frequency of each class in the histogram of FIG. 5 (and FIG. 9 (of embodiment 2 described below)) corresponds to the area of ​​each of regions RG1 to RG8 in FIG. 6. In semiconductor device 101 of embodiment 1 shown in FIG. 6, for example, region RG2 has 16 scattered infinitesimal parts, and the total area of ​​these infinitesimal parts corresponds to the frequency of class "5.85-5.94" [V] in FIG. 5. In addition, as in semiconductor device 101M of a modified example shown in FIG. 7, the infinitesimal parts may be gathered together to form an island-like portion spanning multiple unit cells.

[0026] In the example shown in Fig. 5, the region RG8, which is the lowest voltage part of the tail distribution PFL, does not overlap with the normal distribution PMN. Therefore, the lowest voltage part of the histogram distribution is composed only of the tail distribution PFL. On the other hand, the region RG4, which is the lowest voltage part of the normal distribution PMN, overlaps with the tail distribution PFL.

[0027] With reference to FIG. 8, the solid line in the graph indicates an example of the transfer characteristic of the semiconductor device 101 (FIG. 5), and the dashed line in the graph indicates an example of the transfer characteristic of the semiconductor device 100P (FIG. 2). The semiconductor device 101 (FIG. 5) has a tail distribution PFL on the low voltage side, and the cells in the corresponding region are turned on in advance in the on operation. Therefore, compared with the semiconductor device 100P of the comparative example, the current starts to flow from a lower voltage. As the gate voltage is increased, with reference to FIG. 5, the current gradually increases as the regions RG8, RG6, RG5, RG4, and RG2 are turned on in this order, then increases sharply as the largest region RG1 is turned on, and then increases slightly as the regions RG3 and RG7 are turned on in this order, until it reaches a saturated state. Note that FIG. 8 is only an example, and depending on the design, the threshold voltage of the tail distribution PFL may differ from the threshold voltage of the region RG1 by only 100 mV. In that case, although it is difficult to observe a clear inflection point as in FIG. 8, the effect of the tail distribution PFL can be obtained.

[0028] According to the first embodiment, the histogram (FIG. 5) has a continuous distribution that tails on the low voltage side compared to a normal distribution. This suppresses a sudden rise in current when the semiconductor device 101 is turned on. In other words, di / dt (time derivative of current) can be reduced. Thus, radiation noise from the semiconductor device 101 can be suppressed. Meanwhile, by making the proportion of the region RG1, which has the largest occupied area in the active IGBT cell region 10 (FIG. 1), sufficiently large, it is possible to prevent the conduction loss from becoming significantly large due to the tailing distribution PFL. In FIG. 5, the ratio of the total occupied area of ​​the regions other than the region RG1 to the occupied area of ​​the region RG1 is, for example, 1:10 to 1:10. 7The ratio of the total area occupied by the other regions other than the region RG1 may be in the range of 1 / 10 7 Even if the value is suppressed to a very small value, by applying the tailing PFL, the saturation current of a typical IGBT with a saturation current of several A can be reduced by 10 -7 Since a current of the order of A (100 nA) flows, it is possible to easily determine the presence of a tail distribution PFL from the waveform of the transfer characteristics.

[0029] FIG. 9 is a graph diagram showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device 102 according to the second embodiment. The histogram of the semiconductor device 102 (FIG. 9) includes a substantially normal distribution PMN (a region with sparse hatching in FIG. 9) similar to the histogram of the semiconductor device 100P (FIG. 2), but has a distribution that is continuously biased toward the high voltage side compared to the normal distribution PMN. Specifically, the histogram of the semiconductor device 102 includes, in addition to the normal distribution PMN, a tailing distribution PFH (a region with dense hatching in FIG. 5) that is a distribution that tails toward the high voltage side. In other words, the histogram has a tailing distribution PFH that is continuous from the normal distribution PMN to the high voltage side, based on the normal distribution PMN. The histogram of the semiconductor device 102 (FIG. 9) is different from the histogram of the semiconductor device 100Q (FIG. 4) in that no class with a frequency of zero is interposed between classes with non-zero frequencies. In Fig. 9, the histogram distribution is formed by overlapping the normal distribution PMN with the tailing distribution PFH on the high voltage side. Therefore, the histogram is continuous.

[0030] In the example shown in Fig. 9, the region RG8, which is the highest voltage part of the tail distribution PFH, does not overlap with the normal distribution PMN. Therefore, the highest voltage part of the distribution of the histogram is composed only of the tail distribution PFH. On the other hand, the region RG4, which is the highest voltage part of the normal distribution PMN, overlaps with the tail distribution PFH.

[0031] 10, the solid line in the graph shows an example of the transfer characteristic of the semiconductor device 102 (FIG. 9), and the dashed line in the graph shows an example of the transfer characteristic of the semiconductor device 100P (FIG. 2). The semiconductor device 102 (FIG. 9) has a tailing distribution PFH on the high voltage side, which causes a waveform different from the dashed line (comparative semiconductor device 100P) to appear near the saturation current. The cells in the corresponding region are turned off in advance during the off operation. This promotes the sweeping out of carriers compared to the comparative semiconductor device 100P.

[0032] According to the second embodiment, the histogram (FIG. 9) has a continuous distribution that tails toward the high voltage side as compared with a normal distribution. This promotes the discharge of minority carriers when the semiconductor device 102 is turned off. Therefore, the turn-off loss of the semiconductor device 102 can be reduced. In addition, when the histogram of threshold voltages changes continuously as shown in FIG. 9, a sudden turn-off operation is unlikely to occur in the entire chip (in other words, one semiconductor substrate) constituting the semiconductor device 102, and therefore an effect of suppressing a voltage surge can be obtained.

[0033] In FIG. 9, the ratio of the total area occupied by the tail distribution PFH to the total area occupied by the normal distribution PMN is, for example, 1:10 to 1:10. 7 The ratio of the total area occupied by the tail distribution PFH may be in the range of 1 / 10 7 When the threshold voltage is suppressed to a very small value, it may be difficult to determine the presence or absence of a tailing distribution PFH from the transfer characteristics (see Figure 10). Even in such cases, the presence or absence of a tailing distribution PFH can be determined from heat generation analysis. Specifically, when the gate voltage is increased in steps of, for example, several mV, if there is an area with a high threshold voltage inside the chip, the current flow will be low only in that area, suppressing heat generation. In other words, the results of the heat generation analysis will result in a distribution inside the chip. Generally, heat generation analysis is a technology that can analyze defective locations at the unit cell level, so it is possible to determine the presence or absence of a tailing distribution PFH from 1 / 10 of the original amount. 7Even if the ratio of the threshold voltages is only a small area, it is possible to distinguish between areas with different threshold voltages. Therefore, the heat generation analysis is a useful means for determining whether or not the configuration of the second embodiment is applied. Similarly, the light emission analysis is also a useful means. It is also possible to determine whether or not the configuration of the first embodiment is applied by a similar method.

[0034] 11 is a cross-sectional view showing a specific configuration of an active IGBT cell region 10 (see FIG. 1) of a semiconductor device corresponding to a typical trench-gate type IGBT. This semiconductor device differs from the first or second embodiment in that each cell CM has a substantially similar configuration in terms of design. Taking into account manufacturing variations and the like, the histogram of this semiconductor device has a normal distribution PNM similar to that of the semiconductor device 100P (FIG. 2).

[0035] In the active IGBT cell region 10 (see FIG. 1) of the semiconductor device (FIG. 11), the semiconductor substrate SB has an upper surface (first main surface) and a lower surface (second main surface). + The p-type source layer 53 and + The p-type collector layer 55 forms at least a part of the lower surface of the semiconductor substrate SB. - A drift layer 52 is included. - Between the drift layer 52 and the p-type collector layer 55, + A buffer layer 58 is included. - Between the drift layer 52 and the upper surface, n - A charge storage layer (CS layer) 56 is included on the drift layer 52. The CS layer 56 has a higher impurity concentration than the drift layer 52. A p-type base layer 54 is included between the CS layer 56 and the upper surface. A n-type base layer 54 is included between the p-type base layer 54 and the upper surface. + Each of the p-type source layer 53 and the p+ contact layer 57 .

[0036] The semiconductor substrate SB is provided with a gate structure 51 for switching the semiconductor device, penetrating the p-type base layer 54 and the CS layer 56 from the upper surface. The gate structure 51 has a gate electrode 51a and a gate insulating film 51b that are in contact with each other. The gate insulating film 51b is formed in a trench in which the gate structure 51 is buried, and has an n - A drift layer 52 and n + 11 , the gate electrode 51a is in contact with the p-type source layer 53, the p-type base layer 54, and the CS layer 56. The gate insulating film 51b is, for example, an oxide film. An interlayer insulating film 60 is provided on the upper surface of the semiconductor substrate SB to insulate the gate electrode 51a from an emitter electrode (not shown in FIG. 11 ) provided on the upper surface of the semiconductor substrate SB. A collector electrode (not shown) is provided on the lower surface of the semiconductor substrate SB.

[0037] By appropriately replacing a part of the multiple cells CM of the semiconductor device with at least one type of cell having a different threshold voltage, the above-mentioned semiconductor device 101 or 102 can be obtained. The structure of the cell for this purpose will be described below with reference to FIG. 12 or FIG. 13.

[0038] 12, compared with cell CM (FIG. 11), cells CL1 to CL3 have lower threshold voltages, and cells CH1 to CH3 have higher threshold voltages.

[0039] The p-type base layer 54a of the cell CL1 has a lower impurity concentration than the p-type base layer 54 of the cell CM (FIG. 11). Conversely, the p-type base layer 54c of the cell CH1 has a higher impurity concentration than the p-type base layer 54 of the cell CM (FIG. 11). By applying at least one of the cell CL1 and the cell CH1, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the p-type base layer may have an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage required for the semiconductor device.

[0040] The p-type base layer 54b of the cell CL2 is smaller in depth from the upper surface of the semiconductor substrate SB than the p-type base layer 54 of the cell CM (FIG. 11). The p-type base layer 54d of the cell CH2 is larger in depth from the upper surface of the semiconductor substrate SB than the p-type base layer 54 of the cell CM (FIG. 11). By applying at least one of the cell CL2 and the cell CH2, it is possible to control the distribution of the threshold voltage of the semiconductor device. In other words, the p-type base layer may have a depth distribution in the planar layout corresponding to the distribution of the threshold voltage required for the semiconductor device.

[0041] n in cell CL3 + The n-type source layer 53a is the n-type source layer of the cell CM (FIG. 11). + The n-type source layer 53 has a larger depth from the upper surface of the semiconductor substrate SB than the n-type source layer 53. + The n-type source layer 53b is the n-type source layer of the cell CM (FIG. 11). + The depth from the upper surface of the semiconductor substrate SB is smaller than that of the n-type source layer 53. By applying at least one of the cell CL3 and the cell CH3, it is possible to control the distribution of the threshold voltage of the semiconductor device. + The type source layer may have a depth distribution in a planar layout corresponding to the distribution of threshold voltages required for the semiconductor device.

[0042] Moreover, the threshold voltage of the cell can be made lower by decreasing the thickness of the gate insulating film 51b, and can be made higher by increasing the thickness of the gate insulating film 51b. By applying such a cell, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the gate insulating film 51b may have a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0043] The threshold voltage of the cell can also be controlled by the plane orientation of the channel of the gate structure 51. This will be described below. The p-type base layer 54 of the semiconductor substrate SB has a portion facing the gate structure 51 on the inner wall of the trench as a channel region. The threshold voltage depends on the plane orientation of this portion (crystallographic plane orientation of Si when the semiconductor substrate SB is a Si substrate). Therefore, by applying a cell whose plane orientation of this portion is different from that of the cell CM (FIG. 11), it is possible to control the distribution of the threshold voltage of the semiconductor device. In other words, the portion of the p-type base layer 54 facing the gate structure 51 may have a plane orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0044] The threshold voltage of the cell can also be controlled by the internal stress of the semiconductor substrate SB. In other words, the semiconductor substrate SB may have an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage. In general, it is known that the internal stress inherent in the channel region of a semiconductor is related to the interatomic distance, and when the interatomic distance changes, the band gap changes, and thus the threshold voltage easily changes. Methods for controlling the internal stress include heat treatment for mitigating ion implantation damage, formation conditions of the gate oxide film, the film type or formation conditions of the interlayer insulating film, formation conditions of the emitter electrode, formation conditions of the glass coat film, or formation conditions of the polyimide coat film. Here, the formation conditions of each element are, for example, the temperature during formation, the formation speed, the formation film thickness, or the heat treatment after formation.

[0045] FIG. 13 is a cross-sectional view showing cells CL11 to CL13 and cells CH11 to CH13 which are modifications of the cells CL1 to CL3 and cells CH1 to CH3 in FIG.

[0046] 13, the drift layer 52 of the semiconductor substrate SB includes a lifetime control layer 59 in the cells CH11-CH13. Therefore, in a semiconductor device to which the cells CH11-CH13 are applied, the multiple regions RG1-RGn can include a region in which the lifetime control layer 59 is arranged and a region in which the lifetime control layer 59 is not arranged. By appropriately providing the lifetime control layer 59, the discharge of minority carriers becomes smoother and the turn-off loss is further reduced.

[0047] In the example shown in Fig. 13, the charge storage layer 56 (Fig. 12) of the semiconductor substrate SB is selectively adjusted. Specifically, the charge storage layer 56a of the cells CL11-CL13 has a different impurity concentration from the charge storage layer 56 of the cell CM (Fig. 11). Therefore, in a semiconductor device to which the cells CL11-CL13 are applied, the regions RG1-RGn may have different impurity concentrations in the charge storage layer. By adjusting the impurity concentration distribution of the charge storage layer in this manner, minority carriers are discharged more smoothly and turn-off loss is reduced.

[0048] As described above, by applying at least one of the above-mentioned various types of cells having a threshold voltage different from that of the cell CM (FIG. 11), the above-mentioned semiconductor device 101 or semiconductor device 102 can be obtained. Also, a cell having characteristics of two or more types of cells among these multiple types of cells may be applied.

[0049] Fig. 14 is a plan view showing a configuration of a planar layout on a semiconductor substrate SB of a semiconductor device 111 according to a modification of Fig. 6. In the semiconductor device 111, the largest region RG1 among a plurality of regions RG1 to RGn (regions RG1 and RG2 in the illustrated example) in the planar layout includes the center of the semiconductor substrate SB. Region RG2 roughly surrounds region RG1. In the illustrated example, region RG2 and gate pad region 41 surround region RG1.

[0050] The advantages of the semiconductor device 111 will be described below separately for the case where the threshold voltage of the region RG1 is higher than that of the region RG2 and the case where it is lower.

[0051] First, when the threshold voltage in the region RG1 is set relatively high, the turn-off loss at the center of the semiconductor substrate SB can be reduced. In IGBTs during steady-state operation, heat is generally accumulated most at the center of the chip, so by reducing the turn-off loss at the center, the heat distribution in the semiconductor device 111 can be made uniform. This uniform effect is particularly noticeable during high-speed switching. The uniform heat distribution improves the wear life of the semiconductor device 111.

[0052] Secondly, when the threshold voltage in region RG1 is set relatively low, it is possible to speed up switching in the center, which tends to be far from the gate wiring 42 (see FIG. 15). In general, the gate signal of an IGBT tends to be delayed before it reaches the center of the semiconductor substrate SB. Therefore, by designing the threshold voltage of region RG1 located at the center of the semiconductor substrate SB to be low, it is possible to offset this delay. This enables uniform switching across the entire chip. This is expected to increase the short-circuit resistance.

[0053] Therefore, according to the semiconductor device 111, one of the above two effects can be obtained regardless of whether the threshold voltage of the region RG1 is higher or lower than the threshold voltage of the region RG2.

[0054] 15 is a plan view showing a configuration of a planar layout on a semiconductor substrate SB of a semiconductor device 112 according to a modification of FIG. 6. The semiconductor device 112 has a gate wiring 42 provided on the semiconductor substrate SB. The gate wiring 42 is for applying a potential applied to the gate pad region 41 for switching to a gate electrode 51a (see FIG. 11). The gate wiring 42 includes a portion extending along one direction (the vertical direction in FIG. 15). The boundaries between adjacent regions among the multiple regions RG1 to RG3 in the planar layout, in other words, the boundary between the region RG1 and the region RG2 and the boundary between the region RG2 and the region RG3, include portions extending along the one direction (the vertical direction in FIG. 15).

[0055] According to this modification, when the boundary between adjacent regions among the regions RG1 to RG3 in the planar layout includes a portion extending in one direction, the arrangement of the regions RG1 to RG3 is determined according to the distance from the portion of the gate wiring extending in one direction. In this case, if the threshold voltage is distributed so that it is higher the farther away from the portion of the gate wiring, the switching of the region farther from the portion of the gate wiring is delayed more, thereby making it possible to further reduce the turn-off loss. If the threshold voltage is distributed so that it is lower the farther away from the portion of the gate wiring, the switching timing within the chip can be made more uniform.

[0056] Specifically, the semiconductor substrate SB has a roughly rectangular shape, and at least a part of the boundary extends along its long or short side (short side in the example of FIG. 15). The gate wiring 42 is generally arranged parallel to the long or short side of the chip. A gate signal sent from the gate wiring 42 generally has a characteristic that it arrives early near the gate wiring 42 and late away from the gate wiring 42. This characteristic leads to the effect of suppressing turn-off loss. Therefore, if the distribution of the threshold voltage is set so that the threshold voltage becomes higher as the distance from the gate wiring 42 increases, the above effect can be further enhanced. Conversely, if the distribution of the threshold voltage is set so that the threshold voltage becomes lower as the distance from the gate wiring 42 increases, it is possible to perform uniform switching within the chip by offsetting the delay in signal transmission depending on the distance from the gate wiring 42.

[0057] The semiconductor device 112 aims to obtain the above effect by providing a distribution of threshold voltages according to the distance from the main portion of the gate wiring 42 (the portion extending vertically in FIG. 15). The boundary is approximately aligned with the long side or short side (more generally, the one direction) to an extent that this effect can be sufficiently obtained. The one direction is not necessarily limited to the direction along which the long side or short side of the semiconductor substrate SB is aligned. For example, the one direction may be the extension direction of the termination electrode pattern on the semiconductor substrate SB.

[0058] FIG. 16 is a plan view showing the configuration of a planar layout on a semiconductor substrate SB of a semiconductor device 113 according to the modified example of FIG. 6. Note that only the edge of the emitter electrode 50 provided on the semiconductor substrate SB is indicated by a two-dot chain line. The multiple regions RG1 to RGn in the planar layout include the largest region RG1 among them and a region RG2 (more generally, at least one region) having a higher threshold voltage than the region RG1. In the planar layout, at least a part of the edge of the emitter electrode 50 is disposed in the region RG2. As shown in the figure, approximately the entire edge of the emitter electrode 50 may be disposed in the region RG2. Moreover, the region RG2 (more generally, at least one region other than the region RG1) may extend so as to follow the edge of the emitter electrode 50.

[0059] According to this modification, it is possible to increase the short circuit resistance. In general, short circuit breakdown tends to occur easily at the edge of the emitter electrode 50 where current concentrates. Therefore, by forming the region RG2 having a high threshold voltage along the edge of the emitter electrode 50, it is possible to suppress current concentration during a short circuit.

[0060] 17 is a plan view showing a configuration of a planar layout on a semiconductor substrate SB of a semiconductor device 114 according to a modification of FIG. 6. In the planar layout, the semiconductor substrate SB has a rectangular shape having long sides and short sides. In the planar layout, the boundaries between adjacent regions among the multiple regions RG1 to RGn extend along at least a part of an ellipse. The long axis of the ellipse is along the short side of the rectangular shape (the vertical direction in FIG. 17). Therefore, the ellipse has a pair of focal points (not shown) that face each other in the direction along the short sides.

[0061] In addition, the boundary between adjacent regions among the multiple regions RG1 to RGn only needs to extend substantially along at least a part of an ellipse, and does not necessarily need to completely follow a geometrically strict ellipse. The ellipse is a closed curve shape that is line-symmetrical in each of the X direction and the Y direction in the XY coordinate system in the planar layout. Therefore, the boundary is also substantially line-symmetrical in each of the X direction and the Y direction. The axis of line symmetry may pass through approximately the center of the semiconductor substrate SB.

[0062] The regions RG1 to RGn as shown in FIG. 17 can be obtained by warping of the substrate. FIG. 18 is a graph showing an assumed example of the distribution of threshold voltages Vth along the line XVIII-XVIII in FIG. 17. The solid line in the graph is a line obtained by assuming the measurement result of the amount of warping of the semiconductor substrate SB and converting it into Vth. The range NA is different for the region other than the active cell in the semiconductor substrate SB. Also, the assumed measurement variation DM is shown. The dashed line in the graph is an approximation line when the influence of the range NA and the measurement variation DM is excluded. According to this approximation line, the distribution of threshold voltages along the longitudinal direction of the chip has an axis of symmetry approximately at the center of the semiconductor substrate SB. Although not shown, the distribution of threshold voltages along the lateral direction of the chip also has an axis of symmetry approximately at the center of the semiconductor substrate SB.

[0063] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0064] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0065] (Appendix 1) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; A semiconductor device, wherein when a histogram is defined by a plurality of classes for the threshold voltages with a class width of 100 mV and a plurality of frequencies corresponding to areas of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include first to third regions, and the histogram has a distribution that is based on a normal distribution and has a tail that is continuous with the normal distribution on the low voltage side.

[0066] (Appendix 2) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; A semiconductor device, wherein when a histogram is defined by a plurality of classes for the threshold voltages with a class width of 100 mV and a plurality of frequencies corresponding to areas of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include first to third regions, and the histogram has a distribution that is based on a normal distribution and has a tail that continues from the normal distribution to the high voltage side.

[0067] (Appendix 3) 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type; the base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0068] (Appendix 4) 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type; The base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0069] (Appendix 5) 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a source layer having the first conductivity type; the source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0070] (Appendix 6) 3. The semiconductor device according to claim 1, the gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0071] (Appendix 7) 3. The semiconductor device according to claim 1, the semiconductor substrate is provided with a trench in which the gate structure is embedded; the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and having a portion facing the gate structure, the portion facing the gate structure having a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltages.

[0072] (Appendix 8) A semiconductor device according to any one of claims 1 to 7, A semiconductor device, wherein the largest area among the plurality of areas in the planar layout includes a center of the semiconductor substrate.

[0073] (Appendix 9) A semiconductor device according to any one of claims 1 to 7, a gate wiring provided on the semiconductor substrate and including a portion extending in one direction, for applying a potential for the switching to the gate electrode; a boundary between adjacent ones of the plurality of regions in the planar layout includes a portion extending along the one direction.

[0074] (Appendix 10) A semiconductor device according to any one of claims 1 to 7, The semiconductor device further includes an emitter electrode having an edge on the semiconductor substrate. the plurality of regions includes a first region that is the largest among the plurality of regions, and at least one region that has a higher threshold voltage than the first region; In the planar layout, at least a portion of the edge of the emitter electrode is disposed in the at least one region.

[0075] (Appendix 11) A semiconductor device according to any one of claims 1 to 7, In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between adjacent ones of the plurality of regions extends along at least a part of an ellipse having a major axis along the minor side of the rectangular shape.

[0076] (Appendix 12) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, A semiconductor device, wherein the largest area among the plurality of areas in the planar layout includes a center of the semiconductor substrate.

[0077] (Appendix 13) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; a gate wiring provided on the semiconductor substrate and including a portion extending in one direction, for applying a potential for the switching to the gate electrode; a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, a boundary between adjacent ones of the plurality of regions in the planar layout includes a portion extending along the one direction.

[0078] (Appendix 14) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with an emitter electrode having an edge on the semiconductor substrate; a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, the plurality of regions includes a first region that is the largest among the plurality of regions, and at least one region that has a higher threshold voltage than the first region; In the planar layout, at least a portion of the edge of the emitter electrode is disposed in the at least one region.

[0079] (Appendix 15) A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, The semiconductor device further includes an emitter electrode having an edge on the semiconductor substrate. The plurality of regions includes a largest region among the plurality of regions and at least one region, In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between adjacent ones of the plurality of regions extends along at least a part of an ellipse having a major axis along the minor side of the rectangular shape.

[0080] (Appendix 16) A semiconductor device according to any one of appendices 1, 2, and 12 to 15, The semiconductor device, wherein the semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltages.

[0081] (Appendix 17) 17. The semiconductor device according to claim 1, the semiconductor substrate further includes a charge storage layer on the drift layer, the charge storage layer having the first conductivity type and a higher impurity concentration than the drift layer; The plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

[0082] (Appendix 18) 17. The semiconductor device according to claim 1, the drift layer of the semiconductor substrate includes a lifetime control layer, The plurality of regions include a region in which the lifetime control layer is disposed and a region in which the lifetime control layer is not disposed. [Explanation of symbols]

[0083] 10 active IGBT cell area, 41 gate pad area, 42 gate wiring, 50 emitter electrode, 51 gate structure, 51a gate electrode, 51b gate insulating film, 52 n - Drift layer, 53, 53a, 53b n + The p-type source layers 53, 54, 54a to 54d are p-type base layers, 56, 56a are charge storage layers, 59 is a lifetime control layer, 101, 101M, 102, 111 to 114 are semiconductor devices, RG1 to RGn are first to n-th regions, and SB is a semiconductor substrate.

Claims

1. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; a semiconductor device, wherein when a histogram is defined by a plurality of classes for the threshold voltage with a class width of 100 mV and a plurality of frequencies corresponding to areas of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions including first to third regions, and the histogram has a distribution that is based on a normal distribution and has a tail that is continuous with the normal distribution on the low voltage side.

2. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; a semiconductor device, wherein when a histogram is defined by a plurality of classes for the threshold voltage with a class width of 100 mV and a plurality of frequencies corresponding to areas of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include first to third regions, and the histogram has a distribution that is based on a normal distribution and has a continuous tail on the high voltage side from the normal distribution.

3. 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type; the base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

4. 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type; The base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

5. 3. The semiconductor device according to claim 1, the semiconductor substrate further includes a source layer having the first conductivity type; the source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

6. 3. The semiconductor device according to claim 1, the gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

7. 3. The semiconductor device according to claim 1, the semiconductor substrate is provided with a trench in which the gate structure is embedded; the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and having a portion facing the gate structure, the portion facing the gate structure having a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltages.

8. 3. The semiconductor device according to claim 1, A semiconductor device, wherein the largest area among the plurality of areas in the planar layout includes a center of the semiconductor substrate.

9. 3. The semiconductor device according to claim 1, a gate wiring provided on the semiconductor substrate and including a portion extending in one direction, for applying a potential for the switching to the gate electrode; a boundary between adjacent ones of the plurality of regions in the planar layout includes a portion extending along the one direction.

10. 3. The semiconductor device according to claim 1, The semiconductor device further includes an emitter electrode having an edge on the semiconductor substrate. the plurality of regions includes a first region that is the largest among the plurality of regions, and at least one region that has a higher threshold voltage than the first region; In the planar layout, at least a portion of the edge of the emitter electrode is disposed in the at least one region.

11. 3. The semiconductor device according to claim 1, In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between adjacent ones of the plurality of regions extends along at least a part of an ellipse having a major axis along the minor side of the rectangular shape.

12. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, A semiconductor device, wherein the largest area among the plurality of areas in the planar layout includes a center of the semiconductor substrate.

13. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; a gate wiring provided on the semiconductor substrate and including a portion extending in one direction, for applying a potential for the switching to the gate electrode; a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, a boundary between adjacent ones of the plurality of regions in the planar layout includes a portion extending along the one direction.

14. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with an emitter electrode having an edge on the semiconductor substrate; a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, the plurality of regions includes a first region that is the largest among the plurality of regions, and at least one region that has a higher threshold voltage than the first region; In the planar layout, at least a portion of the edge of the emitter electrode is disposed in the at least one region.

15. A semiconductor device which is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, a semiconductor substrate including a drift layer having a first conductivity type; a gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; Equipped with a planar layout on the semiconductor substrate having a distribution of threshold voltages for the switching; When a plurality of classes with a class width of 100 mV are defined for the threshold voltage, the planar layout has a plurality of regions that belong to different classes among the plurality of classes, The semiconductor device further includes an emitter electrode having an edge on the semiconductor substrate. The plurality of regions includes a largest region among the plurality of regions and at least one region, In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between adjacent ones of the plurality of regions extends along at least a part of an ellipse having a major axis along the minor side of the rectangular shape.

16. 16. A semiconductor device according to claim 1, 2, or 12 to 15, The semiconductor device, wherein the semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltages.

17. 16. A semiconductor device according to claim 1, 2, or 12 to 15, the semiconductor substrate further includes a charge storage layer on the drift layer, the charge storage layer having the first conductivity type and a higher impurity concentration than the drift layer; The plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

18. 16. A semiconductor device according to claim 1, 2, or 12 to 15, the drift layer of the semiconductor substrate includes a lifetime control layer, The plurality of regions include a region in which the lifetime control layer is disposed and a region in which the lifetime control layer is not disposed.

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