Semiconductor light emitting device and semiconductor light-emitting module

Abstract

To suppress an increase in a forward voltage of a semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting device includes: a semiconductor substrate 20 including a substrate surface 21 and a substrate back surface 22 on an opposite side to the substrate surface 21; a surface wiring layer 40 formed on the substrate surface 21; a semiconductor light-emitting element 30 bonded to the surface wiring layer 40; and a bonding layer 80 that bonds the surface wiring layer 40 and the semiconductor light-emitting element 30 to each other. The surface wiring layer 40 includes a first metal layer 41 in contact with the substrate surface 21, a first oxide film 43 present on the first metal layer 41, and a second metal layer 42 interposed between the first oxide film 43 and the bonding layer 80. A thickness T2 of the second metal layer 42 is 1000 Å or more.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor light emitting device and a semiconductor light emitting module. [Background technology]

[0002] A semiconductor laser device is known that includes a submount and a semiconductor laser element bonded onto the submount with a conductive adhesive layer (see, for example, Patent Document 1). The submount of Patent Document 1 includes a base material, an insulating layer formed on a main surface of the base material, a conductive layer formed on the insulating layer, and a conductive adhesive layer formed on the conductive layer. The semiconductor laser element is disposed on the conductive adhesive layer. This electrically connects the semiconductor laser element and the conductive layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 116981 Summary of the Invention [Problem to be solved by the invention]

[0004] However, due to a resistance component in the conductive path between the submount and the semiconductor laser element, the forward voltage when a predetermined optical output is output from the semiconductor laser element or the forward voltage at the threshold current may become high. Note that such a problem is not limited to semiconductor laser elements, but may also occur in semiconductor light-emitting elements such as light-emitting diodes (LEDs). [Means for solving the problem]

[0005] A semiconductor light-emitting device according to one embodiment of the present disclosure comprises a substrate having a substrate surface, a surface wiring layer formed on the substrate surface, a semiconductor light-emitting element bonded to the surface wiring layer, and a bonding layer bonding the surface wiring layer to the semiconductor light-emitting element, wherein the surface wiring layer includes a first metal layer formed on the substrate surface, an oxide film present on the first metal layer, and a second metal layer interposed between the oxide film and the bonding layer, and the second metal layer has a thickness of 1000 Å or more. Effect of the Invention

[0006] According to the semiconductor light emitting device and the semiconductor light emitting module according to an aspect of the present disclosure, it is possible to prevent the forward voltage of the semiconductor light emitting element from increasing. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary semiconductor light emitting module according to one embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the semiconductor light emitting module taken along line F2-F2 in FIG. [Diagram 3] FIG. 3 is a plan view of a substrate in the semiconductor light emitting module of FIG. [Figure 4] FIG. 4 is a schematic plan view of the semiconductor light emitting device in the semiconductor light emitting module of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the semiconductor light emitting device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor light emitting device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the semiconductor light emitting device taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic perspective view of the semiconductor light emitting device of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor light emitting device taken along line F9-F9 in FIG. [Figure 10]10A to 10C are schematic cross-sectional views illustrating an exemplary manufacturing process for the semiconductor light emitting device of one embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 13] FIG. 13 is a schematic plan view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the wire wiring layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of the detection wiring layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view of the wire wiring layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of the detection wiring layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Diagram 23] FIG. 23 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view of the first metal layer and its periphery, showing a manufacturing step subsequent to that shown in FIG. [Diagram 25]FIG. 25 is a schematic cross-sectional view of a surface wiring layer and its periphery in a semiconductor light emitting device of a first comparative example. [Figure 26] FIG. 26 is a schematic cross-sectional view of a surface wiring layer and its periphery in a semiconductor light emitting device of a second comparative example. [Figure 27] FIG. 27 is a schematic cross-sectional view of a surface wiring layer and its periphery in a semiconductor light emitting device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the semiconductor light emitting device and the semiconductor light emitting module according to the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] <Embodiment> [Overall configuration of semiconductor light emitting module] The overall configuration of semiconductor light emitting module 100 will be described with reference to Figures 1 and 2. Figure 1 shows a perspective view of semiconductor light emitting module 100, and Figure 2 shows a cross-sectional view of semiconductor light emitting module 100 taken along line F2-F2 in Figure 1. In Figure 1, in order to facilitate understanding of the drawing, a cap 120, which will be described later, is shown by a two-dot chain line, and the configuration of semiconductor light emitting module 100 inside cap 120 is shown by a solid line.

[0011] As shown in FIG. 1, the semiconductor light emitting module 100 includes a semiconductor light emitting device 10, a stem 110, a cap 120, and a terminal pin . The semiconductor light emitting device 10 constitutes a light source of the semiconductor light emitting module 100. The semiconductor light emitting device 10 includes a substrate 20 and a semiconductor light emitting element 30. The semiconductor light emitting element 30 is, for example, a semiconductor laser chip. The semiconductor light emitting element 30 is, for example, an edge emitting semiconductor laser element. For example, a Fabry-Perot type laser diode element is adopted as the edge emitting semiconductor laser element. The substrate 20 supports the semiconductor light emitting element 30. For example, a semiconductor substrate may be used as the substrate 20. In one example, the substrate 20 is formed of a material including, for example, Si (silicon). In one example, the substrate 20 is a Si substrate. Note that the substrate 20 is not limited to a semiconductor substrate, and may be formed of aluminum nitride (AlN). Here, the substrate 20 can also be called a "submount" or a "submount substrate".

[0012] The semiconductor light emitting device 10 is attached to the stem 110. In this way, the stem 110 supports the semiconductor light emitting device 10. The stem 110 has a base 111 and a heat sink 112. In one example, the base 111 and the heat sink 112 are integrally formed. The material from which the stem 110 is formed is not particularly limited, but it is formed, for example, from iron (Fe) or an Fe alloy.

[0013] The base 111 is formed in a flat plate shape. When viewed in the thickness direction of the base 111, the base 111 is formed in a substantially circular shape. As an example of the size of the base 111, the diameter is about 5.6 mm and the thickness is about 1.2 mm. The base 111 has a front surface 111A and a back surface 111B facing opposite each other in the thickness direction.

[0014] Two through holes 113 and 114 are formed in the base 111, penetrating the base 111 in its thickness direction. The through holes 113 and 114 are substantially circular when viewed in the thickness direction of the base 111. In one example, the diameter of the through holes 113 and 114 is about 1.0 mm.

[0015] A recess 115 is formed in the base 111 at a position different from the through holes 113, 114. When viewed from the thickness direction of the base 111, the recess 115 is formed at a position adjacent to the heat sink 112. The recess 115 is recessed from the surface 111A of the base 111 in the thickness direction of the base 111. The bottom surface of the recess 115 is formed so as to become deeper with increasing distance from the heat sink 112. For example, a light receiving element (not shown) that receives light from outside the semiconductor light emitting module 100 may be disposed in the recess 115.

[0016] The heat sink 112 is provided on the surface 111A of the base 111. The heat sink 112 protrudes from the surface 111A of the base 111 in the thickness direction of the base 111. The heat sink 112 has a support surface 116 for mounting the semiconductor light emitting device 10. The support surface 116 is formed as a flat surface along the thickness direction of the base 111. The substrate 20 of the semiconductor light emitting device 10 is attached to the support surface 116. The heat sink 112 is electrically connected to the semiconductor light emitting device 10.

[0017] The cap 120 is formed, for example, in a cylindrical shape with one end open. The cap 120 includes a disk-shaped end wall 121, a cylindrical peripheral wall 122 extending from the outer periphery of the end wall 121 in the thickness direction of the end wall 121, and a flange 123 extending outward from the open end of the peripheral wall 122.

[0018] The cap 120 is attached to the stem 110. More specifically, the flange 123 of the cap 120 is attached to the surface 111A of the base 111. The cap 120 covers the semiconductor light emitting device 10 when attached to the stem 110. That is, the semiconductor light emitting device 10 is housed by the stem 110 and the cap 120. The cap 120 also covers the heat sink 112 when attached to the base 111. Therefore, the heat sink 112 is housed by the base 111 and the cap 120. In this way, the cap 120, together with the base 111, forms an accommodation space SP (see FIG. 2) that accommodates the semiconductor light emitting device 10 and the heat sink 112.

[0019] The cap 120 is made of a material having a light-shielding property. For example, Fe or an Fe alloy is used as the material having a light-shielding property. The cap 120 has an opening 124 through which the laser light emitted by the semiconductor light-emitting device 10 passes. The opening 124 is formed so as to penetrate the end wall 121 in the thickness direction. A light-transmitting plate 125 (see FIG. 2) that closes the opening 124 is attached to the end wall 121. The cap 120 and the light-transmitting plate 125, together with the base 111, form a hollow sealing structure by making the accommodation space SP airtight in a hollow state. The light-transmitting plate 125 may be omitted.

[0020] The terminal pin 130 is electrically connected to the semiconductor light emitting device 10. The terminal pin 130 constitutes an external terminal of the semiconductor light emitting module 100. In one example, when the semiconductor light emitting module 100 is mounted on a mounting substrate, the terminal pin 130 is inserted into a through hole of the mounting substrate and then bonded to the through hole by, for example, a solder paste. The terminal pin 130 is formed of, for example, an Fe-Ni alloy.

[0021] The terminal pins 130 include two individual pins 131 and 132 and one common pin 133 . The individual pins 131, 132 and the common pin 133 are provided to fix the semiconductor light emitting module 100 to a mounting board or the like, and form a power supply path to the semiconductor light emitting device 10. The individual pins 131, 132 and the common pin 133 each have, for example, the same diameter. The individual pins 131, 132 and the common pin 133 each are rod-shaped members with a diameter of, for example, about 0.45 mm. Note that the diameter of at least one of the individual pins 131, 132 and the common pin 133 may be different from the diameter of the other pins.

[0022] The individual pins 131, 132 are individually inserted into through holes 113, 114 of the base 111. Insulating materials 117, 118 are filled between the individual pins 131, 132 and the through holes 113, 114, respectively. The insulating materials 117, 118 are made of a material having electrical insulation properties. For example, glass is used as this material. The individual pins 131, 132 are supported by the base 111 in a state in which they are electrically insulated from the base 111 by the insulating materials 117, 118.

[0023] As shown in FIG. 2, the individual pin 131 has a connection portion 131A and a terminal portion 131B. The connection portion 131A is a portion that protrudes from the front surface 111A of the base 111. The connection portion 131A includes a portion that is connected to the semiconductor light emitting device 10 via the first wire WA. The terminal portion 131B is a portion that protrudes from the rear surface 111B of the base 111. The terminal portion 131B is used when mounting the semiconductor light emitting module 100 on a mounting board or the like. The length of the individual pin 131 is, for example, about 9.0 mm. The length of the connection portion 131A is about 1.5 mm. The length of the terminal portion 131B is about 6.5 mm.

[0024] The individual pin 132 has a connection portion 132A and a terminal portion 132B. The connection portion 132A is a portion that protrudes from the surface 111A of the base 111. The length of the connection portion 132A is shorter than the length of the connection portion 131A of the individual pin 131. The connection portion 132A is a portion that is connected to a light receiving element via a wire when, for example, a light receiving element is mounted. The terminal portion 132B is used when mounting the semiconductor light emitting device 10 on a mounting board or the like. The length of the individual pin 132 is about 8.0 mm. The length of the connection portion 132A is 0 mm or more and about 0.2 mm. The length of the terminal portion 132B is about 6.5 mm.

[0025] The common pin 133 is electrically connected to the base 111. The common pin 133 protrudes from the rear surface 111B of the base 111. In one example, when viewed from the thickness direction of the base 111, the common pin 133 is disposed at a position overlapping with the heat sink 112. The common pin 133 is joined to the base 111 by, for example, silver brazing, resistance welding, or the like.

[0026] The common pin 133 is electrically connected to the semiconductor light emitting device 10 via the base 111 and the heat sink 112. Moreover, the individual pin 131 is electrically connected to the semiconductor light emitting device 10 via the first wire WA. Therefore, a conductive path that supplies a current to the semiconductor light emitting element 30 is formed by the common pin 133, the semiconductor light emitting device 10, and the individual pin 131.

[0027] [Configuration of semiconductor light-emitting device] An example of the configuration of the semiconductor light emitting device 10 will be described with reference to Figs. 3 to 7. Fig. 3 shows the planar structure of the substrate 20 of the semiconductor light emitting device 10. Fig. 4 shows the planar structure of the semiconductor light emitting device 10. Fig. 5 is a cross-sectional structure taken along line F5-F5 in Fig. 4, showing the cross-sectional structure of the semiconductor light emitting element 30 and its periphery. Fig. 6 is a cross-sectional structure taken along line F6-F6 in Fig. 4, showing the cross-sectional structure of a wire wiring layer 50 (described later) and its periphery. Fig. 7 is a cross-sectional structure taken along line F7-F7 in Fig. 4, showing the cross-sectional structure of a detection wiring layer 60 (described later) and its periphery.

[0028] As shown in Fig. 3, the substrate 20 is formed in a rectangular flat plate shape. When viewed in the thickness direction of the substrate 20, the substrate 20 has a rectangular shape having a long side direction and a short side direction. The substrate 20 is attached to the heat sink 112 (see Fig. 2) so that the long side direction coincides with the extension direction of the heat sink 112.

[0029] The substrate 20 has a substrate front surface 21 and a substrate back surface 22 (see FIG. 5) facing opposite to each other in the thickness direction, and first to fourth substrate side surfaces 23 to 26 connecting the substrate front surface 21 and the substrate back surface 22. The first substrate side surface 23 and the second substrate side surface 24 constitute both end surfaces in the longitudinal direction of the substrate 20, and the third substrate side surface 25 and the fourth substrate side surface 26 constitute both end surfaces in the lateral direction of the substrate 20. In this embodiment, the substrate 20 is a semiconductor substrate containing p-type impurities, and the p-type impurity concentration is, for example, 1×10 19 cm -3 More than 1×10 20 cm -3 The p-type impurity is, for example, boron (B). The p-type impurity concentration can be changed as desired.

[0030] A surface oxide film 27 is formed on the substrate surface 21 of the substrate 20. The surface oxide film 27 is formed of a material containing SiO2, for example. The surface oxide film 27 is formed over the entire substrate surface 21. The surface oxide film 27 has a first opening 27A and a second opening 27B that expose a portion of the substrate surface 21.

[0031] The first opening 27A is formed at an end of the substrate surface 21 closer to the first substrate side surface 23 in the longitudinal direction of the substrate 20. The first opening 27A is formed at the center of the substrate surface 21 in the lateral direction. When viewed from the thickness direction of the substrate 20, the first opening 27A is formed in a rectangular shape. In one example, when viewed from the thickness direction of the substrate 20, the first opening 27A is formed in a rectangular shape having a longitudinal direction and a lateral direction. The first opening 27A is formed so that its longitudinal direction coincides with the longitudinal direction of the substrate 20 and its lateral direction coincides with the lateral direction of the substrate 20.

[0032] The second opening 27B is formed at a position closer to the second substrate side surface 24 than the first opening 27A on the substrate surface 21 in the longitudinal direction of the substrate 20. The second opening 27B is formed at a position closer to the fourth substrate side surface 26 than the first opening 27A on the substrate surface 21 in the lateral direction of the substrate 20. In one example, the second opening 27B is formed in a rectangular shape when viewed from the thickness direction of the substrate 20. In one example, the second opening 27B is formed in a square shape when viewed from the thickness direction of the substrate 20. The shapes of the first opening 27A and the second opening 27B can be changed arbitrarily. The positions of the first opening 27A and the second opening 27B can be changed arbitrarily.

[0033] A surface wiring layer 40 is formed on the substrate surface 21 of the substrate 20. In other words, it can be said that the semiconductor light emitting device 10 includes the surface wiring layer 40 formed on the substrate surface 21. The surface wiring layer 40 is disposed within the first opening 27A. For this reason, it can be said that the surface wiring layer 40 is disposed at an end of the substrate surface 21 closer to the first substrate side surface 23 in the longitudinal direction of the substrate 20. It can be said that the surface wiring layer 40 is disposed in the center of the substrate surface 21 in the lateral direction.

[0034] 5, the surface wiring layer 40 is in contact with the substrate surface 21. Therefore, the surface wiring layer 40 is electrically connected to the substrate 20. In one example, the surface wiring layer 40 and the substrate 20 form an ohmic contact.

[0035] As shown in FIG. 3, the surface wiring layer 40 is formed in a rectangular shape when viewed from the thickness direction of the substrate 20. In one example, the surface wiring layer 40 is a rectangular shape having a long side direction and a short side direction. The surface wiring layer 40 is formed so that its long side direction coincides with the long side direction of the substrate 20 and its short side direction coincides with the short side direction of the substrate 20. In one example, the surface wiring layer 40 is slightly smaller than the first opening 27A when viewed from the thickness direction of the substrate 20. The surface wiring layer 40 is formed of a material containing any one of Al (aluminum), Cu (copper), Au (gold), and Pt (platinum). A detailed configuration of the surface wiring layer 40 will be described later.

[0036] The position of the surface wiring layer 40 can be arbitrarily changed. Therefore, the first opening 27A is formed according to the arrangement position of the surface wiring layer 40. Also, the shape of the surface wiring layer 40 as viewed from the thickness direction of the substrate 20 can be arbitrarily changed.

[0037] In addition, a wire wiring layer 50 is formed on the substrate surface 21 of the substrate 20. In other words, it can be said that the semiconductor light emitting device 10 includes the wire wiring layer 50. The wire wiring layer 50 is formed at a position different from the first opening 27A and the second opening 27B of the surface oxide film 27.

[0038] 6, the wire wiring layer 50 is formed on the surface oxide film 27. Therefore, it can be said that the wire wiring layer 50 is formed on the substrate surface 21. Since the surface oxide film 27 is interposed between the wire wiring layer 50 and the substrate 20, the wire wiring layer 50 is electrically insulated from the substrate 20. The wire wiring layer 50 is formed of a material containing, for example, any one of Al, Cu, Au, and Pt. In one example, the wire wiring layer 50 contains Al.

[0039] 3, the wire wiring layer 50 is formed in an L-shape when viewed from the thickness direction of the substrate 20. The wire wiring layer 50 can be divided into a first wire bonding region 51 and a second wire bonding region 52.

[0040] The first wire bonding region 51 is disposed closer to the second substrate side surface 24 than the center in the longitudinal direction of the substrate 20. The first wire bonding region 51 is formed over most of the region between the center in the longitudinal direction of the substrate 20 and the second substrate side surface 24. The first wire bonding region 51 is disposed closer to the second substrate side surface 24 than the surface wiring layer 40. When viewed from the thickness direction of the substrate 20, the first wire bonding region 51 is formed in a substantially rectangular shape. In one example, when viewed from the thickness direction of the substrate 20, the first wire bonding region 51 is formed in a rectangular shape whose long side is the short side direction of the substrate 20 and whose short side is the long side direction of the substrate 20.

[0041] The second wire bonding region 52 extends from an end of the first wire bonding region 51 that is closer to the first substrate side surface 23 and the third substrate side surface 25 toward the first substrate side surface 23. Therefore, the second wire bonding region 52 is formed at a position closer to the third substrate side surface 25 than the surface wiring layer 40. When viewed from the short side direction of the substrate 20, the tip portion of the second wire bonding region 52 is formed at a position overlapping with the surface wiring layer 40.

[0042] When viewed from the thickness direction of the substrate 20, the second wire bonding region 52 is formed in a rectangular shape whose longitudinal direction coincides with the longitudinal direction of the substrate 20 and whose lateral direction coincides with the lateral direction of the substrate 20. In one example, the width dimension of the second wire bonding region 52 (the lateral dimension of the second wire bonding region 52) is larger than the width dimension of the surface wiring layer 40 (the lateral dimension of the surface wiring layer 40). Note that the shape of the wire wiring layer 50 when viewed from the thickness direction of the substrate 20 can be changed arbitrarily.

[0043] Further, a detection wiring layer 60 is formed on the substrate surface 21 of the substrate 20. That is, it can be said that the semiconductor light emitting device 10 includes the detection wiring layer 60 formed on the substrate surface 21. The detection wiring layer 60 is a wiring layer for detecting the electrical characteristics of the semiconductor light emitting device 10. The detection wiring layer 60 is disposed in the second opening 27B. Therefore, it can be said that the detection wiring layer 60 is formed at a position on the substrate surface 21 closer to the second substrate side surface 24 than the surface wiring layer 40 in the longitudinal direction of the substrate 20. In one example, it can be said that the detection wiring layer 60 is formed at a position on the substrate surface 21 closer to the fourth substrate side surface 26 than the surface wiring layer 40 in the lateral direction of the substrate 20. In one example, the detection wiring layer 60 is formed at a position overlapping the second wire bonding region 52 when viewed from the lateral direction of the substrate 20.

[0044] When viewed from the thickness direction of the substrate 20, the detection wiring layer 60 is formed in a rectangular shape. In one example, when viewed from the thickness direction of the substrate 20, the detection wiring layer 60 is a square. When viewed from the thickness direction of the substrate 20, the detection wiring layer 60 is slightly smaller than the second opening 27B of the surface oxide film 27. The position of the detection wiring layer 60 can be changed arbitrarily. Therefore, the second opening 27B is formed according to the position of the detection wiring layer 60.

[0045] As shown in FIG. 7, the detection wiring layer 60 is in contact with the substrate surface 21. Therefore, the surface wiring layer 40 is electrically connected to the substrate 20. In one example, the surface wiring layer 40 and the substrate 20 form an ohmic contact. The detection wiring layer 60 is formed of a material containing, for example, any one of Al, Cu, Au, and Pt. In one example, the detection wiring layer 60 is formed of the same material as the wire wiring layer 50. In one example, the detection wiring layer 60 contains Al. The detailed configuration of the detection wiring layer 60 will be described later. In addition, the detection wiring layer 60 may be formed of a material different from that of the wire wiring layer 50.

[0046] 5, a back surface wiring layer 70 is formed on the back surface 22 of the substrate 20. In other words, it can be said that the semiconductor light emitting device 10 includes the back surface wiring layer 70 formed on the back surface 22 of the substrate. The back surface wiring layer 70 is formed, for example, over the entire back surface 22 of the substrate. Note that the back surface wiring layer 70 may be formed partially on the back surface 22 of the substrate.

[0047] The back wiring layer 70 is in contact with the back surface 22 of the substrate. Therefore, the back wiring layer 70 is electrically connected to the substrate 20. In one example, the back wiring layer 70 and the substrate 20 form an ohmic contact. The back wiring layer 70 is formed of, for example, a material different from that of the front wiring layer 40. In one example, the back wiring layer 70 is formed of a material containing Au. It can be said that the back wiring layer 70 is electrically connected to the front wiring layer 40 via the substrate 20.

[0048] The semiconductor light emitting element 30 is bonded to the surface wiring layer 40. In other words, it can be said that the semiconductor light emitting device 10 includes the semiconductor light emitting element 30 bonded to the surface wiring layer 40. The semiconductor light emitting element 30 is electrically connected to the surface wiring layer 40.

[0049] 4, the semiconductor light emitting element 30 is electrically connected to the wire wiring layer 50 by a second wire WB. The second wire WB is bonded to a second wire bonding region 52 of the wire wiring layer 50. More specifically, the second wire WB is bonded to a region of the second wire bonding region 52 near the semiconductor light emitting element 30. Here, the second wire WB corresponds to "wire."

[0050] The first wire WA is bonded to a first wire bonding region 51 of the wire wiring layer 50. More specifically, the first wire WA is bonded to a region of the first wire bonding region 51 closer to the fourth substrate side surface 26.

[0051] [Configuration of semiconductor light-emitting element] An example of the configuration of the semiconductor light emitting device 30 will be described with reference to Fig. 8 and Fig. 9. Fig. 8 shows a perspective structure of the semiconductor light emitting device 30. Fig. 9 shows a cross-sectional structure of the semiconductor light emitting device 30 taken along line F9-F9 in Fig. 8.

[0052] 8, the semiconductor light emitting element 30 has an element front surface 31 and an element back surface 32 facing opposite to each other in the thickness direction. In a state in which the semiconductor light emitting element 30 is bonded to the front wiring layer 40 (see FIG. 4), the element front surface 31 faces the same side as the substrate front surface 21 of the substrate 20 (see FIG. 5), and the element back surface 32 faces the same side as the substrate back surface 22 (see FIG. 5). The semiconductor light emitting element 30 also has an element substrate 33, a light emitting portion 34, an insulating film 35, an element front surface electrode 36, and an element back surface electrode 37.

[0053] The element substrate 33 is formed, for example, in the shape of a rectangular plate. The element substrate 33 is composed of an n-type semiconductor substrate (n-GaAs substrate) containing, for example, GaAs (gallium arsenide). The element substrate 33 contains, for example, at least one of Si, Te (tellurium), and Se (selenium) as an n-type impurity. The element substrate 33 has a substrate front surface 33A and a substrate back surface 33B facing in opposite directions in the thickness direction. The substrate front surface 33A faces the same side as the substrate front surface 21 (see FIG. 5) of the substrate 20, and the substrate back surface 33B faces the same side as the substrate back surface 22 (see FIG. 5) of the substrate 20.

[0054] The light emitting portion 34 is provided on the substrate front surface 33A of the element substrate 33. The light emitting portion 34 protrudes from the substrate front surface 33A toward the side opposite to the substrate back surface 33B. The light emitting portion 34 has a mesa structure, and is formed in a trapezoidal shape (ridge shape) protruding from the substrate front surface 33A when viewed in the longitudinal direction of the element substrate 33.

[0055] As shown in FIG. 8, the light-emitting portion 34 has an electrode connecting surface 34A, a substrate connecting surface 34B, light-emitting portion end surfaces 34C and 34D, and light-emitting portion side surfaces 34E and 34F. The electrode connection surface 34A faces the same side as the substrate surface 33A. The electrode connection surface 34A constitutes the upper base of the trapezoidal light-emitting portion 34. The electrode connection surface 34A is disposed apart from the substrate surface 33A in the thickness direction of the element substrate 33. The substrate connection surface 34B faces the element substrate 33 side and is connected to the substrate surface 33A. The substrate connection surface 34B constitutes the lower base of the trapezoidal light-emitting portion 34. For this reason, the width dimension of the electrode connection surface 34A is smaller than the width dimension of the substrate connection surface 34B.

[0056] The light-emitting section end faces 34C, 34D and the light-emitting section side faces 34E, 34F form faces connecting the electrode connection face 34A and the substrate connection face 34B. The light-emitting section side faces 34E, 34F form inclined side faces of the trapezoidal light-emitting section 34. The light-emitting section end faces 34C, 34D form both end faces in the longitudinal direction of the light-emitting section 34. When viewed from the longitudinal direction of the light-emitting section 34, the light-emitting section end faces 34C, 34D are formed in a trapezoidal shape (ridge shape). The light-emitting section end faces 34C, 34D form resonator end faces. In one example, the light-emitting section 34 is configured to emit laser light LX from the light-emitting section end face 34C. The laser light LX passes through a light-transmitting plate 125 shown in FIG. 2.

[0057] As shown in Fig. 9, the light-emitting section 34 includes light-emitting units 38 stacked on the substrate surface 33A of the element substrate 33. The light-emitting units 38 generate light by recombination of holes and electrons. In one example, the light-emitting section 34 has three light-emitting units 38. Note that the light-emitting section 34 may have at least one light-emitting unit 38. That is, the number of light-emitting units 38 may be one, two, or four or more.

[0058] The light-emitting section 34 includes a tunnel layer 39 disposed between adjacent light-emitting units 38. The tunnel layer 39 generates a tunnel current due to a tunnel effect and supplies the tunnel current to the light-emitting units 38. In one example, the light-emitting section 34 includes two tunnel layers 39. The tunnel layer 39 is disposed between two adjacent light-emitting units 38. The number of tunnel layers 39 may be changed depending on the number of light-emitting units 38.

[0059] The insulating film 35 is formed so as to cover a part of the substrate surface 33A of the element substrate 33. The insulating film 35 is also formed so as to cover the light emitting portion 34. In one example, the insulating film 35 is formed so as to cover the electrode connecting surface 34A and the light emitting portion side surfaces 34E and 34F of the light emitting portion 34. The insulating film 35 has substrate covering portions 35A and 35B that cover the substrate surface 33A of the element substrate 33, and a light emitting portion covering portion 35C that covers the light emitting portion 34. The insulating film 35 is formed of, for example, SiN (silicon nitride), SiO2, or the like.

[0060] The element surface electrode 36 is provided on an upper surface 35D of the insulating film 35 covering the electrode connection surface 34A. The insulating film 35 covering the electrode connection surface 34A has a first opening 35E exposing a part of the electrode connection surface 34A. The element surface electrode 36 includes a first electrode layer and a second electrode layer. The first electrode layer and the second electrode layer are laminated in this order from the electrode connection surface 34A side. The first electrode layer is made of, for example, Ti (titanium) / Au. The second electrode layer is, for example, a plating layer containing Au. The upper surface 35D of the insulating film 35 and the upper surface of the element surface electrode 36 constitute the element surface 31 of the semiconductor light emitting element 30.

[0061] The element back surface electrode 37 is provided on the substrate back surface 33B of the element substrate 33. In one example, the element back surface electrode 37 covers the entire substrate back surface 33B. The element back surface electrode 37 is electrically connected to the element substrate 33. The element back surface electrode 37 constitutes the element back surface 32 of the semiconductor light emitting element 30.

[0062] The element back electrode 37 may be composed of a plurality of electrode layers. In one example, the element back electrode 37 may include at least one of a Ni (nickel) layer, an AuGe (gold-germanium alloy) layer, a Ti layer, and an Au layer. In one example, the element back electrode 37 may include a Ni layer, an AuGe layer, a Ti layer, and an Au layer stacked in this order from the substrate back surface 33B.

[0063] The configuration of the semiconductor light emitting element 30 is not limited to the configuration of the semiconductor light emitting element 30 shown in Fig. 8 and Fig. 9. The configuration of the semiconductor light emitting element 30 can be changed as desired. In one example, the light emitting portion 34 of the semiconductor light emitting element 30 is not limited to a trapezoidal shape when viewed from the longitudinal direction of the element substrate 33, and may be rectangular. Furthermore, the semiconductor light emitting element 30 may be rectangular when viewed from the longitudinal direction of the element substrate 33.

[0064] [Detailed cross-sectional structure of the surface wiring layer] The detailed configuration of the surface wiring layer 40 will be described with reference to FIG. 5, the surface wiring layer 40 includes a first metal layer 41, a first oxide film 43, and a second metal layer 42. The first metal layer 41, the first oxide film 43, and the second metal layer 42 are laminated in this order. Here, the first oxide film 43 is an example of an "oxide film present on the first metal layer."

[0065] The first metal layer 41 is in contact with the substrate surface 21 of the substrate 20. More specifically, the first metal layer 41 forms an ohmic contact with the substrate 20. The first metal layer 41 is formed of a material containing any one of Al, Cu, Au, and Pt. In one example, the first metal layer 41 contains Al. The first metal layer 41 has first side surfaces 41A, 41B that constitute both end faces in the short direction of the surface wiring layer 40.

[0066] The thickness T1 of the first metal layer 41 is thicker than the thickness T6 of the surface oxide film 27. In one example, the thickness T1 of the first metal layer 41 is about 26000 Å. The width dimension W1 of the first metal layer 41 is larger than the width dimension W6 of the semiconductor light emitting element 30. Here, the width dimension W1 of the first metal layer 41 can be defined by the size of the first metal layer 41 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the width dimension W1 of the first metal layer 41 can be defined by the size of the first metal layer 41 in the short-side direction of the surface wiring layer 40. In addition, the width dimension W6 of the semiconductor light emitting element 30 can be defined by the size of the semiconductor light emitting element 30 in the short-side direction, for example, the size of the semiconductor light emitting element 30 in the short-side direction of the element substrate 33.

[0067] The first oxide film 43 exists on the first metal layer 41. The first oxide film 43 is in contact with the first metal layer 41 on the first metal layer 41. The first oxide film 43 is a film (natural oxide film) formed by natural oxidation of the first metal layer 41. Therefore, the thickness T3 of the first oxide film 43 is thinner than the thickness T1 of the first metal layer 41. Also, the thickness T3 of the first oxide film 43 is thinner than the thickness T6 of the surface oxide film 27. In one example, the thickness T3 of the first oxide film 43 is 1 nm or more and 7 nm or less. In one example, the thickness T3 of the first oxide film 43 may be 2 nm or more and 6 nm or less. In one example, the thickness T3 of the first oxide film 43 may be 2.5 nm or more and 5.5 nm or less. In this case, the thickness T3 of the first oxide film 43 is set to 4.5 nm in design. Due to manufacturing errors and the like, the thickness T3 of the first oxide film 43 is allowed to vary by ±1.5 nm from 4.5 nm. The width dimension W3 of the first oxide film 43 is larger than the width dimension W6 of the semiconductor light emitting element 30. The width dimension W3 of the first oxide film 43 is equal to the width dimension W1 of the first metal layer 41. Here, if the difference between the width dimension W3 of the first oxide film 43 and the width dimension W1 of the first metal layer 41 is, for example, 10% or less of the width dimension W1 of the first metal layer 41, it can be said that the width dimension W3 of the first oxide film 43 is equal to the width dimension W1 of the first metal layer 41. Here, the width dimension W3 of the first oxide film 43 can be defined by the size of the first oxide film 43 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the width dimension W3 of the first oxide film 43 can be defined by the size of the first oxide film 43 in the short-side direction of the surface wiring layer 40.

[0068] The first oxide film 43 is formed of a material containing an oxide of the material contained in the first metal layer 41. When the first metal layer 41 contains Al, the first oxide film 43 is formed of a material containing Al2O3 (alumina), for example. Note that the first oxide film 43 is not limited to alumina and may be formed of a material containing AlO. Furthermore, the first oxide film 43 is changed depending on the material of the first metal layer 41.

[0069] The second metal layer 42 is interposed between the first oxide film 43 and a bonding layer 80 described later. In one example, the second metal layer 42 is on the first oxide film 43 and in contact with the first oxide film 43. The second metal layer 42 is formed of a material containing any one of Al, Cu, Au, and Pt. In one example, the second metal layer 42 is formed of the same material as the first metal layer 41. In one example, both the first metal layer 41 and the second metal layer 42 contain Al. Note that the first metal layer 41 and the second metal layer 42 may be formed of different materials.

[0070] The second metal layer 42 has second side surfaces 42A, 42B that constitute both end faces in the short direction of the surface wiring layer 40. The second side surface 42A faces the same side as the first side surface 41A of the first metal layer 41, and the second side surface 42B faces the same side as the first side surface 41B of the first metal layer 41.

[0071] The thickness T2 of the second metal layer 42 is thinner than the thickness T1 of the first metal layer 41. The thickness T2 of the second metal layer 42 is thicker than the thickness T3 of the first oxide film 43. In other words, the thickness T3 of the first oxide film 43 is thinner than the thickness T2 of the second metal layer 42. In other words, the thickness T3 of the first oxide film 43 is thinner than both the thickness T1 of the first metal layer 41 and the thickness T2 of the second metal layer 42. The thickness T2 of the second metal layer 42 is 1000 Å or more. In one example, the thickness T2 of the second metal layer 42 may be 7000 Å or less. In one example, the thickness T2 of the second metal layer 42 may be 2000 Å or more. In one example, the thickness T2 of the second metal layer 42 may be 3000 Å or more. In one example, the thickness T2 of the second metal layer 42 may be 4000 Å or more. In one example, the thickness T2 of the second metal layer 42 may be 5000 Å or greater.

[0072] The width dimension W2 of the second metal layer 42 is smaller than the width dimension W1 of the first metal layer 41. In other words, the width dimension W2 of the second metal layer 42 is smaller than the width dimension W3 of the first oxide film 43. Here, the width dimension W2 of the second metal layer 42 can be defined by the size of the second metal layer 42 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the width dimension W2 of the second metal layer 42 can be defined by the size of the second metal layer 42 in the short side direction of the surface wiring layer 40.

[0073] In this way, the surface wiring layer 40 includes a step portion 90 formed by the first metal layer 41 and the second metal layer 42. More specifically, the second side surface 42A of the second metal layer 42 is located closer to the center of the first metal layer 41 than the first side surface 41A of the first metal layer 41 in the short-side direction of the surface wiring layer 40. The second side surface 42B of the second metal layer 42 is located closer to the center of the first metal layer 41 than the first side surface 41B of the first metal layer 41 in the short-side direction of the surface wiring layer 40. For this reason, the step portion 90 is provided on both sides of the surface wiring layer 40 in the short-side direction.

[0074] Although not shown, the length dimension of the second metal layer 42 is smaller than the length dimension of the first metal layer 41. That is, the length dimension of the second metal layer 42 is smaller than the length dimension of the first oxide film 43. Here, the length dimension of the second metal layer 42 can be defined by the size of the second metal layer 42 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the length dimension of the second metal layer 42 can be defined by the size of the second metal layer 42 in the longitudinal direction of the surface wiring layer 40. In addition, the length dimension of the first metal layer 41 can be defined by the size of the first metal layer 41 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the length dimension of the first metal layer 41 can be defined by the size of the first metal layer 41 in the longitudinal direction of the surface wiring layer 40. In this way, the step portion 90 is formed over the entire periphery of the surface wiring layer 40.

[0075] The length of each of the first metal layer 41 and the second metal layer 42 can be changed as desired. In one example, the length of the second metal layer 42 may be equal to the length of the first metal layer 41. In this case, the step portion 90 is provided on both sides of the surface wiring layer 40 in the short side direction.

[0076] [Detailed cross-sectional structure of the wire wiring layer] 6, the thickness T8 of the wire wiring layer 50 is thicker than the thickness T6 of the surface oxide film 27. The thickness T8 of the wire wiring layer 50 is equal to the thickness T1 of the first metal layer 41. The wire wiring layer 50 may be formed of the same material as the first metal layer 41. The wire wiring layer 50 may be formed of the same material as the second metal layer 42. The wire wiring layer 50 may be formed of a material different from the first metal layer 41. The wire wiring layer 50 may be formed of a material different from the second metal layer 42.

[0077] A second oxide film 53 is formed on the wire wiring layer 50 so as to be in contact with the wire wiring layer 50. More specifically, the wire wiring layer 50 includes a layer surface 54 facing the same side as the substrate surface 21 of the substrate 20. A second oxide film 53 is formed on the layer surface 54. The second oxide film 53 is a film (natural oxide film) formed by natural oxidation of the wire wiring layer 50. Therefore, the thickness T7 of the second oxide film 53 is thinner than the thickness T8 of the wire wiring layer 50. The thickness T7 of the second oxide film 53 is thinner than the thickness T6 of the surface oxide film 27. In one example, the thickness T7 of the second oxide film 53 is 1 nm or more and 7 nm or less. In one example, the thickness T7 of the second oxide film 53 is equal to the thickness T3 of the first oxide film 43 (see FIG. 5). Here, if the difference between the thickness T7 of the second oxide film 53 and the thickness T3 of the first oxide film 43 is, for example, within 10% of the thickness T3 of the first oxide film 43, it can be said that the thickness T7 of the second oxide film 53 is equal to the thickness T3 of the first oxide film 43.

[0078] If the first metal layer 41 and the wire wiring layer 50 are made of the same material, the second oxide film 53 is made of the same material as the first oxide film 43. If the first metal layer 41 and the wire wiring layer 50 are made of different materials, the second oxide film 53 is made of a different material from the first oxide film 43.

[0079] As shown in Fig. 3, a first wire WA and a second wire WB are bonded to the wire wiring layer 50. The first wire WA and the second wire WB are bonding wires bonded to the wire wiring layer 50 by a wire bonding device. As shown in Fig. 6, the second wire WB penetrates the second oxide film 53 by the pressure when bonding to the wire wiring layer 50 and is bonded to the layer surface 54 of the wire wiring layer 50. Although not shown in Fig. 6, the first wire WA also penetrates the second oxide film 53 and is bonded to the layer surface 54 of the wire wiring layer 50.

[0080] [Detailed cross-sectional structure of the detection wiring layer] 7, the thickness T9 of the detection wiring layer 60 is thicker than the thickness T6 of the surface oxide film 27. The thickness T9 of the detection wiring layer 60 is equal to the thickness T1 of the first metal layer 41. The detection wiring layer 60 may be formed of the same material as the first metal layer 41. The detection wiring layer 60 may be formed of the same material as the second metal layer 42. The detection wiring layer 60 may be formed of a material different from the first metal layer 41. The detection wiring layer 60 may be formed of a material different from the second metal layer 42.

[0081] A third oxide film 61 is formed on the detection wiring layer 60 so as to be in contact with the detection wiring layer 60. The third oxide film 61 is a film (natural oxide film) formed by natural oxidation of the detection wiring layer 60. Therefore, a thickness T10 of the third oxide film 61 is thinner than a thickness T9 of the detection wiring layer 60. The thickness T10 of the third oxide film 61 is thinner than a thickness T6 of the surface oxide film 27. In one example, the thickness T10 of the third oxide film 61 is 1 nm or more and 7 nm or less. In one example, the thickness T10 of the third oxide film 61 is equal to the thickness T3 of the first oxide film 43. Here, if the difference between the thickness T10 of the third oxide film 61 and the thickness T3 of the first oxide film 43 is, for example, within 10% of the thickness T3 of the first oxide film 43, it can be said that the thickness T10 of the third oxide film 61 is equal to the thickness T3 of the first oxide film 43.

[0082] The third oxide film 61 is formed of the same material as the first oxide film 43 if the first metal layer 41 (see FIG. 5) and the detection wiring layer 60 are made of the same material. The third oxide film 61 is formed of a material different from the first oxide film 43 if the first metal layer 41 and the detection wiring layer 60 are made of different materials. The third oxide film 61 is formed of the same material as the second oxide film 53 if the wire wiring layer 50 (see FIG. 6) and the detection wiring layer 60 are made of the same material. The third oxide film 61 is formed of a material different from the second oxide film 53 if the wire wiring layer 50 and the detection wiring layer 60 are made of different materials.

[0083] [Joint structure between surface wiring layer and semiconductor light emitting element] The bonding structure between the surface wiring layer 40 and the semiconductor light emitting element 30 will now be described in detail. 5, the surface wiring layer 40 and the semiconductor light emitting element 30 are bonded by a bonding layer 80. In one example, the surface wiring layer 40 and the semiconductor light emitting element 30 are bonded by eutectic bonding. In other words, it can be said that the semiconductor light emitting device 10 includes a bonding layer 80 that bonds the surface wiring layer 40 and the semiconductor light emitting element 30. The bonding layer 80 is formed on the surface wiring layer 40.

[0084] The bonding layer 80 includes a first bonding layer 81 and a second bonding layer 82. The first bonding layer 81 and the second bonding layer 82 are laminated in this order. In one example, the bonding layer 80 is composed of the first bonding layer 81 and the second bonding layer 82.

[0085] The first bonding layer 81 is in contact with the second metal layer 42 on the second metal layer 42 of the surface wiring layer 40. In other words, no oxide film (natural oxide film) is interposed between the first bonding layer 81 and the second metal layer 42. The second metal layer 42 is in contact with the bonding layer 80. The first bonding layer 81 is a diffusion prevention layer (barrier metal) that prevents the second bonding layer 82 from diffusing into the surface wiring layer 40. The first bonding layer 81 is formed of a material containing, for example, Ti, Mo (molybdenum), or the like. In one example, the first bonding layer 81 contains Ti.

[0086] The thickness T4 of the first bonding layer 81 is thicker than the thickness T3 of the first oxide film 43. In other words, the thickness T3 of the first oxide film 43 is thinner than the thickness T4 of the first bonding layer 81. The thickness T4 of the first bonding layer 81 is thinner than the thickness T1 of the first metal layer 41. In one example, the thickness T4 of the first bonding layer 81 is thinner than the thickness T2 of the second metal layer 42. In other words, the thickness T2 of the second metal layer 42 is thicker than the thickness T4 of the first bonding layer 81. The thickness T4 of the first bonding layer 81 is, for example, not less than 500 Å and not more than 2500 Å. The thickness T4 of the first bonding layer 81 can be changed arbitrarily.

[0087] The width dimension W4 of the first bonding layer 81 is smaller than the width dimension W1 of the first metal layer 41. That is, the width dimension W4 of the first bonding layer 81 is smaller than the width dimension W3 of the first oxide film 43. The width dimension W4 of the first bonding layer 81 is equal to the width dimension W2 of the second metal layer 42. Here, the width dimension W4 of the first bonding layer 81 can be defined by the size of the first bonding layer 81 in the short-side direction of the surface wiring layer 40. Also, if the difference between the width dimension W4 of the first bonding layer 81 and the width dimension W2 of the second metal layer 42 is, for example, 10% or less of the width dimension W2 of the second metal layer 42, it can be said that the width dimension W4 of the first bonding layer 81 is equal to the width dimension W2 of the second metal layer 42. The width dimension W4 of the first bonding layer 81 can be defined by the size of the first bonding layer 81 in the direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the width dimension W4 of the first bonding layer 81 can be defined by the size of the first bonding layer 81 in the short-side direction of the surface wiring layer 40.

[0088] The second bonding layer 82 is on the first bonding layer 81 and is in contact with the first bonding layer 81. The second bonding layer 82 is made of a material containing AuSn (gold-tin). In one example, the second bonding layer 82 is made of AuSn.

[0089] The thickness T5 of the second bonding layer 82 is thicker than the thickness T3 of the first oxide film 43. In other words, the thickness T3 of the first oxide film 43 is thinner than the thickness T5 of the second bonding layer 82. The thickness T5 of the second bonding layer 82 is thicker than the thickness T4 of the first bonding layer 81. In one example, the thickness T5 of the second bonding layer 82 is thicker than the thickness T2 of the second metal layer 42. In other words, the thickness T2 of the second metal layer 42 is thinner than the thickness T5 of the second bonding layer 82. The thickness T5 of the second bonding layer 82 is thinner than the thickness T1 of the first metal layer 41.

[0090] The width dimension W5 of the second bonding layer 82 is smaller than the width dimension W1 of the first metal layer 41. That is, the width dimension W5 of the second bonding layer 82 is smaller than the width dimension W3 of the first oxide film 43. In one example, the width dimension W5 of the second bonding layer 82 is equal to the width dimension W4 of the first bonding layer 81. Here, the width dimension W5 of the second bonding layer 82 can be defined by the size of the second bonding layer 82 in a direction perpendicular to the thickness direction of the surface wiring layer 40. In one example, the width dimension W5 of the second bonding layer 82 can be defined by the size of the second bonding layer 82 in the short direction of the surface wiring layer 40. In addition, if the difference between the width dimension W5 of the second bonding layer 82 and the width dimension W4 of the first bonding layer 81 is, for example, 10% or less of the width dimension W4 of the first bonding layer 81, it can be said that the width dimension W5 of the second bonding layer 82 is equal to the width dimension W4 of the first bonding layer 81.

[0091] The semiconductor light emitting element 30 is disposed on the second bonding layer 82. In one example, the element substrate 33 of the semiconductor light emitting element 30 is disposed on the second bonding layer 82. The element back surface electrode 37 formed on the substrate back surface 33B of the element substrate 33 is disposed on the second bonding layer 82 so as to be in contact with the second bonding layer 82. As a result, the element back surface electrode 37 is electrically connected to the front wiring layer 40 via the bonding layer 80.

[0092] In one example, the width dimension W6 of the semiconductor light emitting element 30 is equal to the width dimension W4 of the first bonding layer 81. Here, if the difference between the width dimension W6 of the semiconductor light emitting element 30 and the width dimension W4 of the first bonding layer 81 is, for example, 10% or less of the width dimension W6 of the semiconductor light emitting element 30, it can be said that the width dimension W6 of the semiconductor light emitting element 30 is equal to the width dimension W4 of the first bonding layer 81.

[0093] In one example, the width dimension W6 of the semiconductor light emitting element 30 is equal to the width dimension W5 of the second bonding layer 82. Here, if the difference between the width dimension W6 of the semiconductor light emitting element 30 and the width dimension W5 of the second bonding layer 82 is, for example, 10% or less of the width dimension W6 of the semiconductor light emitting element 30, it can be said that the width dimension W6 of the semiconductor light emitting element 30 is equal to the width dimension W5 of the second bonding layer 82.

[0094] [Method of manufacturing semiconductor light-emitting device] 10 to 24, an example of a method for manufacturing the semiconductor light emitting device 10 will be described. For ease of explanation, the same components as those in the semiconductor light emitting device 10 will be denoted by the same reference numerals in the following description.

[0095] The manufacturing method of the semiconductor light emitting device 10 mainly includes a step of preparing a substrate 20, a step of depositing a surface wiring layer 40 on a substrate surface 21 of the substrate 20, a step of depositing a bonding layer 80 on the surface wiring layer 40, and a step of bonding the semiconductor light emitting element 30 to the surface wiring layer 40 by the bonding layer 80. The manufacturing method of the semiconductor light emitting device 10 also includes a step of depositing a back surface wiring layer 70 on a substrate back surface 22 of the substrate 20, a step of depositing a wire wiring layer 50 on the substrate surface 21, and a step of depositing a detection wiring layer 60 on the substrate surface 21.

[0096] FIG. 10 shows a process of preparing a substrate 20. FIG. 10 shows a cross-sectional structure of a portion of the substrate 20. The substrate 20 has a substrate front surface 21 and a substrate back surface 22 opposite to the substrate front surface 21. The substrate 20 is, for example, a semiconductor substrate. For example, a Si substrate is used as the semiconductor substrate. The substrate 20 as a semiconductor substrate contains p-type impurities. For example, B is used as the p-type impurity. The p-type impurity concentration is, for example, 1×10 19 cm -3 More than 1×10 20 cm -3 The following is the result.

[0097] As shown in FIG. 10, in the step of preparing the substrate 20, a surface oxide film 27 is formed on the substrate surface 21 of the substrate 20. The surface oxide film 27 is formed over the entire surface of the substrate surface 21. The surface oxide film 27 is made of SiO2. The surface oxide film 27 is formed, for example, by heat treatment of the substrate 20. Then, a first opening 27A and a second opening 27B (see FIG. 13) are formed in the surface oxide film 27, for example, by etching. The substrate surface 21 is exposed by the first opening 27A and the second opening 27B. Note that the first opening 27A is shown in FIG. 10.

[0098] Figures 11 to 13 show one of the steps of depositing a surface wiring layer 40 on a substrate surface 21 in the step following that of Figure 10. Figures 11 and 12 show a cross-sectional structure of a portion of the substrate 20, the same as that of Figure 10. Figure 13 shows the planar structure of the substrate 20.

[0099] 11 , the method for manufacturing the semiconductor light emitting device 10 includes a step of depositing a metal layer 800 on the substrate surface 21. That is, the step of forming the surface wiring layer 40 on the substrate surface 21 includes a step of depositing the metal layer 800 on the substrate surface 21.

[0100] The step of depositing the metal layer 800 on the substrate surface 21 is a step of forming the metal layer 800 on the substrate surface 21 by depositing a first metal material on the substrate surface 21. In one example, in the step of depositing the metal layer 800 on the substrate surface 21, the metal layer 800 is deposited on the substrate surface 21 while the substrate 20 is placed in a vacuum chamber (not shown). In this step, the metal layer 800 is deposited on the substrate surface 21 by physical vapor deposition (PVD). In one example, the metal layer 800 is deposited on the substrate surface 21 by vacuum deposition. The first metal material constituting the metal layer 800 is formed of a material containing any one of Al, Cu, Au, and Pt, for example. In one example, the metal layer 800 (first metal material) contains Al. Note that the metal layer 800 may be deposited on the substrate surface 21 by sputtering instead of vacuum deposition.

[0101] The metal layer 800 is formed over the entire substrate surface 21. More specifically, the metal layer 800 is formed on the surface oxide film 27 so as to be in contact with the surface oxide film 27. Meanwhile, the metal layer 800 enters the first opening 27A and the second opening 27B (see FIG. 13) of the surface oxide film 27. The metal layer 800 that enters each of the first opening 27A and the second opening 27B is in contact with the substrate surface 21. In this manner, the metal layer 800 is a metal layer that constitutes the first metal layer 41 of the surface wiring layer 40, the wire wiring layer 50, and the detection wiring layer 60 (all see FIG. 13).

[0102] 12, the method for manufacturing the semiconductor light emitting device 10 includes a step of patterning the metal layer 800. That is, the step of forming the surface wiring layer 40 on the substrate surface 21 includes a step of patterning the metal layer 800. FIG. 12 shows a step of forming the first metal layer 41 by patterning the metal layer 800.

[0103] In one example, a mask (not shown) covering the region corresponding to the first metal layer 41, the region corresponding to the wire wiring layer 50, and the region corresponding to the detection wiring layer 60 is formed on the metal layer 800. Then, the metal layer 800 exposed from the mask is removed by, for example, etching. As a result, the first metal layer 41, the wire wiring layer 50, and the detection wiring layer 60 are formed on the metal layer 800, as shown in Fig. 13. In this way, the first metal layer 41, the wire wiring layer 50, and the detection wiring layer 60 are formed simultaneously.

[0104] 12, the first metal layer 41 is formed by removing the surrounding portion of the metal layer 800 that has entered the first opening 27A of the surface oxide film 27. The first metal layer 41 is in contact with the substrate surface 21 within the first opening 27A. In this manner, the step of depositing the surface wiring layer 40 on the substrate surface 21 includes a step of forming the first metal layer 41 by depositing a first metal material on the substrate surface 21. In one example, the step of forming the first metal layer 41 by depositing the first metal material on the substrate surface 21 includes a step of depositing the metal layer 800 on the substrate surface 21 and a step of patterning the metal layer 800.

[0105] Fig. 14 shows the step of depositing a wire wiring layer 50 on the substrate surface 21 in the next step of Fig. 10. As described above, the step of depositing a wire wiring layer 50 on the substrate surface 21 includes the step of depositing a metal layer 800 on the substrate surface 21 and the step of patterning the metal layer 800. The step of depositing a wire wiring layer 50 on the substrate surface 21 starts at the same timing as the start of the step of depositing a surface wiring layer 40 on the substrate surface 21, and ends halfway through the step of depositing the surface wiring layer 40 on the substrate surface 21 (i.e., the same timing as the end of the step of forming the first metal layer 41).

[0106] The wire wiring layer 50 is formed of a metal layer 800 deposited on the surface oxide film 27 on the substrate surface 21. Since the wire wiring layer 50 and the first metal layer 41 are both formed of the metal layer 800, the wire wiring layer 50 is formed of the same first metal material as the first metal layer 41 (for example, a material containing Al).

[0107] Fig. 15 shows the step of depositing the detection wiring layer 60 on the substrate surface 21 in the next step of Fig. 10. As described above, the step of depositing the detection wiring layer 60 on the substrate surface 21 includes the step of depositing the metal layer 800 on the substrate surface 21 and the step of patterning the metal layer 800. The step of depositing the detection wiring layer 60 on the substrate surface 21 starts at the same timing as the start of the step of depositing the surface wiring layer 40 on the substrate surface 21, and ends halfway through the step of depositing the surface wiring layer 40 on the substrate surface 21 (i.e., the same timing as the end of the step of forming the first metal layer 41).

[0108] The detection wiring layer 60 is formed by removing the surrounding portion of the metal layer 800 that has entered the second opening 27B of the surface oxide film 27. The detection wiring layer 60 is in contact with the substrate surface 21 within the second opening 27B. Since the detection wiring layer 60 and the first metal layer 41 are both formed of the metal layer 800, the detection wiring layer 60 is formed of the same first metal material as the first metal layer 41. For this reason, it can also be said that the detection wiring layer 60 is formed of the same first metal material as the wire wiring layer 50.

[0109] 16 shows a process of depositing a back surface wiring layer 70 on the back surface 22 of the substrate in the process next to those in Fig. 11 to Fig. 15. That is, the process of depositing the back surface wiring layer 70 on the back surface 22 of the substrate is performed after the process of depositing the first metal layer 41 on the front surface 21 of the substrate, the process of depositing the wire wiring layer 50 on the front surface 21 of the substrate, and the process of depositing the detection wiring layer 60 on the front surface 21 of the substrate.

[0110] In the process of depositing the back wiring layer 70 on the back surface 22 of the substrate, the back wiring layer 70 is deposited on the back surface 22 of the substrate with the substrate 20 placed in a vacuum chamber, for example. In this process, the back wiring layer 70 is deposited on the back surface 22 of the substrate by PVD. In one example, the back wiring layer 70 is deposited on the back surface 22 of the substrate by vacuum deposition. The back wiring layer 70 is formed of a material containing Au, for example. Instead of vacuum deposition, the back wiring layer 70 may be deposited on the back surface 22 of the substrate by sputtering.

[0111] Fig. 17 shows a process of forming an ohmic contact between the first metal layer 41 and the substrate 20 by heat treatment in the process next to Fig. 16. In other words, the process of depositing the back surface wiring layer 70 on the back surface 22 of the substrate is performed before the process of forming an ohmic contact between the first metal layer 41 and the substrate 20.

[0112] In one example, the substrate 20 is heated at a preset heat treatment temperature in a heat treatment furnace (not shown). As a result, the first metal layer 41 and the substrate 20 react with each other to be silicided. As a result, the first metal layer 41 and the substrate 20 form an ohmic contact. Also, the back surface wiring layer 70 and the substrate 20 react with each other to be silicided. As a result, the back surface wiring layer 70 and the substrate 20 form an ohmic contact. That is, this process also includes a process in which the back surface wiring layer 70 and the substrate 20 form an ohmic contact. Therefore, it can be said that the back surface wiring layer 70 and the substrate 20 form an ohmic contact by the heat treatment in the process in which the first metal layer 41 and the substrate 20 form an ohmic contact.

[0113] 17, both the detection wiring layer 60 and the substrate 20 are silicided, so that ohmic contact is formed between the detection wiring layer 60 and the substrate 20. That is, this process also includes a process of forming ohmic contact between the detection wiring layer 60 and the substrate 20. Therefore, it can be said that ohmic contact is formed between the detection wiring layer 60 and the substrate 20 by the heat treatment in the process of forming ohmic contact between the first metal layer 41 and the substrate 20.

[0114] Furthermore, by heating the substrate 20, a surface oxide film 810 is formed on the first metal layer 41, the wire wiring layer 50 (see FIG. 15), and the detection wiring layer 60. On the other hand, since the back wiring layer 70 is made of a material containing Au, no oxide film is formed on it.

[0115] After that, although not shown, the method for manufacturing the semiconductor light emitting device 10 includes a step of cleaning the substrate 20. In this step, the surface oxide film 810 formed on the first metal layer 41 shown in Fig. 17 and the surface oxide films 810 formed on both the wire wiring layer 50 and the detection wiring layer 60 not shown in Fig. 17 are each removed.

[0116] 18 to 20 show a cross-sectional structure of a part of the substrate 20 after the substrate 20 has been cleaned. After the substrate 20 has been cleaned, the substrate 20 is exposed to the air for a period of time during the process of transporting the substrate 20 to an apparatus for carrying out the next process. As a result, as shown in FIG. 18, a first oxide film 43 is present on the first metal layer 41. As shown in FIG. 19, a second oxide film 53 is present on the wire wiring layer 50. As shown in FIG. 20, a third oxide film 61 is present on the detection wiring layer 60. The thicknesses of the first to third oxide films 43, 53, and 61 are thinner than the thickness of the surface oxide film 810 shown in FIG. 17. The thicknesses of the first to third oxide films 43, 53, and 61 are, for example, 1 nm or more and 7 nm or less.

[0117] Fig. 21 shows a step of vapor-depositing a second metal layer 42 in the step of forming a surface wiring layer 40 on the substrate surface 21 in the step following Figs. 18 to 20. The method for manufacturing the semiconductor light-emitting device 10 includes a step of forming the second metal layer 42 by vapor-depositing a second metal material on the first oxide film 43. In other words, the step of vapor-depositing the surface wiring layer 40 on the substrate surface 21 includes a step of forming the second metal layer 42 by vapor-depositing a second metal material on the first oxide film 43. Through the above steps, the surface wiring layer 40 is manufactured.

[0118] In one example, the step of forming the second metal layer 42 on the first oxide film 43 is performed after the step of forming ohmic contact between the first metal layer 41 and the substrate 20 by heat treatment. In other words, the step of forming ohmic contact between the first metal layer 41 and the substrate 20 is performed between the step of forming the first metal layer 41 and the step of forming the second metal layer 42.

[0119] In the step of forming the second metal layer 42 by depositing the second metal material on the first oxide film 43, for example, in a state where the substrate 20 is placed in a vacuum chamber (not shown), the second metal layer 42 is formed by depositing a material containing, for example, any one of Al, Cu, Au, and Pt as the second metal material on the first oxide film 43 formed on the first metal layer 41. In this step, the second metal layer 42 is deposited on the first oxide film 43 by PVD. In one example, the second metal layer 42 is deposited on the first oxide film 43 by vacuum deposition. In this manner, the second metal layer 42 is formed of a material containing any one of Al, Cu, Au, and Pt. In one example, the second metal layer 42 is formed of the same metal material as the first metal layer 41. In this embodiment, the second metal layer 42 contains Al. Note that the second metal layer 42 may be deposited on the first oxide film 43 by a sputtering method instead of vacuum deposition.

[0120] Here, when the second metal layer 42 is vapor-deposited, a region where the second metal layer 42 is vapor-deposited is set using, for example, a mask (not shown). This mask is formed so as to cover the outer periphery of the upper surface of the first oxide film 43. Therefore, as shown in FIG. 21, the width dimension W2 of the second metal layer 42 is smaller than the width dimension W1 of the first metal layer 41. Also, the second metal layer 42 is vapor-deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 1000 Å or more. In one example, the thickness T2 of the second metal layer 42 is thinner than the thickness T1 of the first metal layer 41. The thickness T3 of the first oxide film 43 is thinner than the thickness T2 of the second metal layer 42. The second metal layer 42 may be vapor-deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 2000 Å or more. Also, the second metal layer 42 may be vapor-deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 3000 Å or more. Alternatively, the second metal layer 42 may be deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 4000 Å or more. Alternatively, the second metal layer 42 may be deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 5000 Å or more. Alternatively, the second metal layer 42 may be deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 7000 Å or less.

[0121] Since the step of depositing the second metal layer 42 on the first oxide film 43 is performed after the step of forming an ohmic contact between the first metal layer 41 and the substrate 20, the step of forming an ohmic contact between the first metal layer 41 and the substrate 20 is performed between the step of forming the first metal layer 41 on the substrate surface 21 and the step of forming the second metal layer 42 on the first oxide film 43.

[0122] Figures 22 and 23 show a step of forming a bonding layer 80 on the surface wiring layer 40 in the step next to Figure 21. The step of forming the bonding layer 80 on the surface wiring layer 40 includes a step of depositing a first bonding layer 81 on the second metal layer 42 shown in Figure 22 so as to be in contact with the second metal layer 42, and a step of depositing a second bonding layer 82 on the first bonding layer 81 so as to be in contact with the first bonding layer 81 shown in Figure 23.

[0123] 22, in the step of vapor-depositing first bonding layer 81, first bonding layer 81 is formed by vapor-depositing a material containing Ti, Mo, etc. on second metal layer 42. That is, first bonding layer 81 is formed of a material containing Ti, Mo, etc. In one example, first bonding layer 81 contains Ti. First bonding layer 81 is formed, for example, over the entire upper surface of second metal layer 42.

[0124] In one example, the first bonding layer 81 is formed on the second metal layer 42 while the substrate 20 is placed in the same vacuum chamber as the step of depositing the second metal layer 42 on the first oxide film 43. That is, the state in which the substrate 20 is placed in the vacuum chamber is maintained during the period from the end of the step of depositing the second metal layer 42 on the first oxide film 43 until the start of the step of depositing the first bonding layer 81, so that the second metal layer 42 is prevented from being exposed to the air. This prevents a natural oxide film from being formed on the second metal layer 42, that is, prevents an oxide film from being interposed between the second metal layer 42 and the first bonding layer 81.

[0125] 23, in the step of depositing the second bonding layer 82, the second bonding layer 82 is formed by depositing a material containing AuSn on the first bonding layer 81. That is, the second bonding layer 82 is formed of a material containing AuSn. In one example, the second bonding layer 82 is an AuSn layer. The second bonding layer 82 is formed, for example, over the entire upper surface of the first bonding layer 81.

[0126] In one example, the second bonding layer 82 is formed on the first bonding layer 81 while the substrate 20 is placed in the same vacuum chamber as the step of depositing the first bonding layer 81. That is, the state in which the substrate 20 is placed in the vacuum chamber is maintained during the period from the end of the step of depositing the first bonding layer 81 until the start of the step of depositing the second bonding layer 82. In this manner, the step of depositing the second metal layer 42, the step of depositing the first bonding layer 81, and the step of depositing the second bonding layer 82 are performed successively in a vacuum environment. Through the above steps, the bonding layer 80 is formed.

[0127] FIG. 24 shows a step of bonding the semiconductor light emitting element 30 to the front wiring layer 40 by a bonding layer 80 in the step next to that of FIG. In one example, first, the semiconductor light emitting element 30 is placed on the bonding layer 80. More specifically, the semiconductor light emitting element 30 is placed on the bonding layer 80 so that the element back electrode 37 of the semiconductor light emitting element 30 is in contact with the second bonding layer 82. Next, the second bonding layer 82 is melted and solidified by a reflow process, thereby bonding the element back electrode 37 and the second bonding layer 82. As a result, the semiconductor light emitting element 30 is bonded to the front wiring layer 40 by the bonding layer 80. Through the above steps, the semiconductor light emitting device 10 is manufactured.

[0128] [Effect] The operation of this embodiment will be described with reference to FIGS. 5, 25 and 26. Fig. 25 shows a cross-sectional structure of a portion of the surface wiring layer 40X in the semiconductor light emitting device 10X of the first comparative example. Fig. 26 shows a cross-sectional structure of a portion of the surface wiring layer 40Y in the semiconductor light emitting device 10Y of the second comparative example. The semiconductor light emitting device 10X of the first comparative example and the semiconductor light emitting device 10Y of the second comparative example differ mainly from the semiconductor light emitting device 10 of this embodiment in the configurations of the surface wiring layers 40X, 40Y. For this reason, in the description of the semiconductor light emitting device 10X of the first comparative example and the semiconductor light emitting device 10Y of the second comparative example, the same reference numerals are used for components common to the semiconductor light emitting device 10 of this embodiment.

[0129] 25, the surface wiring layer 40X includes a first metal layer 41 but does not include a second metal layer 42 (see FIG. 5). A first oxide film 43 is formed on the first metal layer 41. In the semiconductor light emitting device 10X of the first comparative example, the bonding layer 80 is deposited on the first oxide film 43 so as to be in contact with the first oxide film 43. That is, the first bonding layer 81 is in contact with the first oxide film 43.

[0130] The inventors of the present application conducted experiments on the relationship between current and voltage (IV characteristics) for multiple semiconductor light emitting devices 10X of the first comparative example, and confirmed the following first to third phenomena related to the following three IV characteristics. That is, the inventors of the present application confirmed that in the semiconductor light emitting device 10X of the first comparative example, the increase in forward voltage with respect to an increase in current is greater than a preset increase in forward voltage (first phenomenon). That is, in the semiconductor light emitting device 10X of the first comparative example, the forward voltage of the semiconductor light emitting element 30, for example, the forward voltage (threshold voltage) at a threshold current and the forward voltage (operating voltage) when a predetermined light output is output, becomes high. The inventors of the present application also confirmed that in the semiconductor light emitting device 10X of the first comparative example, when the current is increased, the forward voltage becomes unstable, changing suddenly in the middle (second phenomenon). The inventors of the present application also confirmed that the semiconductor light emitting element 30 of the first comparative example does not start emitting light at the threshold current, but suddenly emits light at a forward current greater than the threshold current (third phenomenon).

[0131] Therefore, the semiconductor light emitting device 10Y of the second comparative example includes a configuration in which a second metal layer 42Y is formed on a first oxide film 43 that exists on a first metal layer 41 as a surface wiring layer 40Y. In other words, the first oxide film 43 is sandwiched between the first metal layer 41 and the second metal layer 42Y. Here, the thickness TY2 of the second metal layer 42Y is less than 1000 Å.

[0132] The inventors of the present application conducted experiments on the relationship between current and voltage (IV characteristics) for a number of semiconductor light emitting devices 10Y of the second comparative example, similarly to the semiconductor light emitting device 10X of the first comparative example. As a result, although the frequency at which the above-mentioned first to third phenomena were observed was lower than that of the semiconductor light emitting device 10X of the first comparative example, the first to third phenomena were still observed. In addition, the inventors of the present application conducted experiments on the IV characteristics for two cases in which the thickness TY2 of the second metal layer 42Y was 100 Å and 500 Å. As a result, when the thickness TY2 of the second metal layer 42Y was 100 Å, the frequency at which the first to third phenomena were observed was generally the same as that of the semiconductor light emitting device 10X of the first comparative example. When the thickness TY2 of the second metal layer 42Y was 500 Å, the frequency at which the first to third phenomena were observed was lower than when the thickness TY2 was 100 Å.

[0133] In the semiconductor light emitting device 10Y of the second comparative example, the surface wiring layer 40Y has a configuration in which the first oxide film 43 is sandwiched between the first metal layer 41 and the second metal layer 42Y, so that a current easily flows from the first metal layer 41 to the second metal layer 42Y due to the tunnel effect. That is, although the first oxide film 43 exists as a resistance component in the conductive path through which the current flows from the substrate 20 to the semiconductor light emitting element 30, the first oxide film 43 is sandwiched between the first metal layer 41 and the second metal layer 42Y, so that a conductive path penetrating the first oxide film 43 is formed. Therefore, the conductive path between the substrate 20 and the semiconductor light emitting element 30 has a lower resistance than the conductive path between the substrate 20 and the semiconductor light emitting element 30 in the semiconductor light emitting device 10X of the first comparative example. Therefore, in the semiconductor light emitting device 10Y of the second comparative example, the frequency with which the above first to third phenomena occur is reduced.

[0134] On the other hand, when the distance in the Z direction between the first bonding layer 81 and the first oxide film 43 is short, the metal (e.g., Ti or Mo) contained in the first bonding layer 81 penetrates the second metal layer 42Y during the manufacture of the surface wiring layer 40Y and reacts with the oxygen in the first oxide film 43 to form an oxide. For example, when the first bonding layer 81 contains Ti, Ti reacts with the oxygen in the first oxide film 43 to form TiO (titanium oxide) during the formation of the first bonding layer 81. This TiO can have a variety of composition ratios, such as TiO3 or Ti2O3, so the state of the layer containing TiO becomes unstable. As a result, it is considered that the first to third phenomena occur.

[0135] That is, in a configuration in which the first bonding layer 81 and the first oxide film 43 are in contact with each other, such as in semiconductor light emitting device 10X of the first comparative example, a layer containing TiO is likely to be formed. Also, in a case in which the second metal layer 42Y interposed between the first bonding layer 81 and the first oxide film 43 is thin, such as in semiconductor light emitting device 10Y of the second comparative example, Ti that penetrates into the second metal layer 42Y reacts with oxygen in the first oxide film 43, and a layer containing TiO is likely to be formed. In this way, it is considered that the frequency with which the first to third phenomena occur changes depending on the degree to which the layer containing TiO is formed.

[0136] For this reason, the inventors of the present application conducted an experiment on the IV characteristics after increasing the thickness T2 of the second metal layer 42 from the viewpoint of suppressing the formation of a layer containing TiO by increasing the distance between the first bonding layer 81 and the first oxide film 43 in the Z direction. As a result, it was found that if the thickness T2 of the second metal layer 42 is 1000 Å or more, the above-mentioned first to third phenomena do not occur. In other words, if the thickness T2 of the second metal layer 42 is 1000 Å or more, the distance between the first bonding layer 81 and the first oxide film 43 in the Z direction becomes large, so that Ti of the first bonding layer 81 is less likely to reach the first oxide film 43. As a result, it becomes more difficult for a layer containing TiO to be formed, so that the first to third phenomena do not occur.

[0137] [effect] According to this embodiment, the following effects can be obtained. (1) The semiconductor light emitting device 10 includes a substrate 20 having a substrate surface 21, a surface wiring layer 40 formed on the substrate surface 21, a semiconductor light emitting element 30 bonded to the surface wiring layer 40, and a bonding layer 80 bonding the surface wiring layer 40 and the semiconductor light emitting element 30. The surface wiring layer 40 includes a first metal layer 41 formed on the substrate surface 21, a first oxide film 43 present on the first metal layer 41, and a second metal layer 42 interposed between the first oxide film 43 and the bonding layer 80. The second metal layer 42 has a thickness T2 of 1000 Å or more.

[0138] According to this configuration, since the first oxide film 43 is sandwiched between the first metal layer 41 and the second metal layer 42, a conductive path penetrating the first oxide film 43 is formed in the surface wiring layer 40. This reduces the resistance component in the surface wiring layer 40, making it possible to suppress an increase in the operating voltage of the semiconductor light emitting element 30. In addition, since the thickness T2 of the second metal layer 42 is 1000 Å or more, a reaction between the metal material of the bonding layer 80 penetrating the second metal layer 42 and oxygen of the first oxide film 43 is suppressed. This makes it possible to suppress the behavior of the forward voltage in the IV characteristics and the light emission from becoming unstable.

[0139] (2) The thickness T2 of the second metal layer 42 is less than or equal to 7000 Å. According to this configuration, it is possible to form a conductive path penetrating the first oxide film 43 in the surface wiring layer 40, and to shorten the distance between the substrate 20 and the semiconductor light emitting element 30. Therefore, it is possible to achieve both a low resistance of the conductive path between the substrate 20 and the semiconductor light emitting element 30 and a low height of the semiconductor light emitting device 10.

[0140] (3) The thickness T2 of the second metal layer 42 is 3000 Å or greater. With this configuration, even if the thickness T2 of the second metal layer 42 varies due to manufacturing errors, the thickness T2 is likely to be 1000 Å or more. Therefore, it is possible to reliably prevent the behavior of the forward voltage in the IV characteristics and the light emission from becoming unstable.

[0141] (4) The thickness T2 of the second metal layer 42 is 5000 Å or greater. With this configuration, even if the thickness T2 of the second metal layer 42 varies due to manufacturing errors, the thickness T2 is likely to be 1000 Å or more. Therefore, it is possible to reliably prevent the behavior of the forward voltage in the IV characteristics and the light emission from becoming unstable.

[0142] (5) The thickness T2 of the second metal layer 42 is smaller than the thickness T1 of the first metal layer 41. According to this configuration, it is possible to form a conductive path penetrating the first oxide film 43 in the surface wiring layer 40, and to shorten the distance between the substrate 20 and the semiconductor light emitting element 30. Therefore, it is possible to achieve both a low resistance of the conductive path between the substrate 20 and the semiconductor light emitting element 30 and a low height of the semiconductor light emitting device 10.

[0143] (6) The thickness T3 of the first oxide film 43 is smaller than both the thickness T1 of the first metal layer 41 and the thickness T2 of the second metal layer . According to this configuration, a conductive path penetrating the first oxide film 43 in the surface wiring layer 40 is easily formed.

[0144] (7) The thickness T3 of the first oxide film 43 is not less than 1 nm and not more than 7 nm. According to this configuration, a conductive path penetrating the first oxide film 43 in the surface wiring layer 40 is easily formed.

[0145] (8) In a direction perpendicular to the thickness direction of the surface wiring layer 40, the second metal layer 42 is smaller than the first metal layer 41. The surface wiring layer 40 includes a step portion 90 formed by the first metal layer 41 and the second metal layer 42.

[0146] According to this configuration, in a direction perpendicular to the thickness direction of the surface wiring layer 40, the second metal layer 42 is smaller than the first metal layer 41, and therefore, in a direction perpendicular to the thickness direction of the surface wiring layer 40, the semiconductor light emitting element 30 can be accurately positioned at a predetermined position relative to the surface wiring layer 40.

[0147] (9) Bonding layer 80 is composed of a first bonding layer 81 containing Ti and contacting second metal layer 42 on second metal layer 42, and a second bonding layer 82 containing AuSn and contacting first bonding layer 81 on first bonding layer 81.

[0148] According to this configuration, by interposing the first bonding layer 81 containing Ti between the second metal layer 42 and the second bonding layer 82, the adhesion between the second metal layer 42 and the second bonding layer 82 can be improved.

[0149] (10) The semiconductor light emitting element 30 has an element front surface 31 facing the same side as the substrate front surface 21, an element back surface 32 opposite to the element front surface 31, and an element back surface electrode 37 formed on the element back surface 32. The element back surface electrode 37 is electrically connected to the surface wiring layer 40 by a bonding layer 80.

[0150] According to this configuration, the conductive path between the semiconductor light emitting element 30 and the surface wiring layer 40 can be made shorter than in a configuration in which the semiconductor light emitting element 30 and the surface wiring layer 40 are electrically connected by a wire, for example.

[0151] (11) The first metal layer 41 and the substrate 20 form an ohmic contact. According to this configuration, the resistance component between the first metal layer 41 and the substrate 20 is reduced, so that it is possible to prevent the forward voltage (operating voltage) from increasing when the semiconductor light emitting element 30 emits light.

[0152] (12) The semiconductor light emitting device 10 includes a back surface wiring layer 70 formed on the back surface 22 of the substrate. The back surface wiring layer 70 is electrically connected to the front surface wiring layer 40 via the substrate 20. According to this configuration, the back surface wiring layer 70, the substrate 20, the front surface wiring layer 40, the bonding layer 80, and the semiconductor light emitting element 30 can form a conductive path.

[0153] (13) The semiconductor light emitting device 10 includes a wire wiring layer 50 formed on a surface oxide film 27 formed on the substrate surface 21 and electrically connected to the semiconductor light emitting element 30 by a second wire WB. The wire wiring layer 50 has a layer surface 54 facing the same side as the substrate surface 21. A second oxide film 53 is formed on the layer surface 54. The second wire WB is bonded to the layer surface 54 through the second oxide film 53. The thickness T7 of the second oxide film 53 is equal to the thickness T3 of the first oxide film 43.

[0154] According to this configuration, when the second wire WB is formed, the second wire WB penetrates the second oxide film 53. Therefore, the second wire WB and the wire interconnection layer 50 can be easily electrically connected to each other.

[0155] (14) The rear wiring layer 70 and the substrate 20 form an ohmic contact. According to this configuration, the resistance component between the back surface wiring layer 70 and the substrate 20 is reduced, so that the forward voltage (operating voltage) when the semiconductor light emitting element 30 emits light can be prevented from increasing.

[0156] (15) A method for manufacturing a semiconductor light emitting device 10 includes the steps of preparing a substrate 20 having a substrate surface 21 and a substrate back surface 22 opposite to the substrate surface 21, depositing a surface wiring layer 40 on the substrate surface 21, depositing a bonding layer 80 on the surface wiring layer 40, and bonding a semiconductor light emitting element 30 to the surface wiring layer 40 by the bonding layer 80. The step of depositing the surface wiring layer 40 on the substrate surface 21 includes the steps of forming a first metal layer 41 by depositing a first metal material on the substrate surface 21, and forming a second metal layer 42 by depositing a second metal material on a first oxide film 43 formed on the first metal layer 41, and in the step of forming the second metal layer 42, the second metal material is deposited on the first oxide film 43 so that the thickness T2 of the second metal layer 42 is 1000 Å or more.

[0157] According to this configuration, since the first oxide film 43 is sandwiched between the first metal layer 41 and the second metal layer 42, a conductive path penetrating the first oxide film 43 is formed in the surface wiring layer 40. This reduces the resistance component in the surface wiring layer 40, making it possible to suppress an increase in the forward voltage (operating voltage) when the semiconductor light emitting element 30 emits light. In addition, since the thickness T2 of the second metal layer 42 is 1000 Å or more, a reaction between the metal material of the bonding layer 80 penetrating the second metal layer 42 and oxygen of the first oxide film 43 is suppressed. This makes it possible to suppress the behavior of the forward voltage in the IV characteristics and the light emission from becoming unstable.

[0158] (16) The method for manufacturing semiconductor light emitting device 10 further includes a step of forming ohmic contact between first metal layer 41 and substrate 20 by heat treatment. The step of forming ohmic contact between first metal layer 41 and substrate 20 is performed between the step of forming first metal layer 41 and the step of forming second metal layer 42.

[0159] According to this configuration, the first metal layer 41 and the substrate 20 form ohmic contact, thereby reducing the resistance component between the first metal layer 41 and the substrate 20. Furthermore, since the heat treatment is performed before the step of forming the second metal layer 42, it is possible to suppress the formation of an oxide film on the second metal layer 42 due to the heat treatment.

[0160] (17) The method for manufacturing the semiconductor light emitting device 10 further includes a step of depositing a back surface wiring layer 70 on the substrate back surface 22. The step of depositing the back surface wiring layer 70 on the substrate back surface 22 is performed before a step of forming an ohmic contact between the first metal layer 41 and the substrate 20. The back surface wiring layer 70 and the substrate 20 form an ohmic contact by heat treatment in the step of forming an ohmic contact between the first metal layer 41 and the substrate 20.

[0161] According to this configuration, the back surface wiring layer 70 and the substrate 20 form ohmic contact, thereby making it possible to reduce the resistance component between the back surface wiring layer 70 and the substrate 20. Furthermore, since the ohmic contact between the first metal layer 41 and the substrate 20 and the ohmic contact between the back surface wiring layer 70 and the substrate 20 are simultaneously formed, the manufacturing process of the semiconductor light emitting device 10 can be simplified.

[0162] <Example of change> The above embodiment can be modified as follows: The following modifications can be combined with each other as long as no technical contradiction occurs.

[0163] In the above embodiment, the substrate 20 is configured to contain p-type impurities, but this is not limited to the above. The substrate 20 may be configured to contain n-type impurities. In this case, the n-type impurity concentration is, for example, 1×10 19 cm -3 More than 3×10 19 cm -3 The n-type impurity concentration can be changed as desired.

[0164] The relationship between the thickness T3 of the first oxide film 43 formed on the first metal layer 41 and the thickness T7 of the second oxide film 53 formed on the wire wiring layer 50 can be changed arbitrarily. In one example, the thickness T3 of the first oxide film 43 may be thinner than the thickness T7 of the second oxide film 53. In another example, the thickness T3 of the first oxide film 43 may be thicker than the thickness T7 of the second oxide film 53.

[0165] The relationship between the thickness T3 of the first oxide film 43 and the thickness T10 of the third oxide film 61 formed on the detection wiring layer 60 can be changed arbitrarily. In one example, the thickness T3 of the first oxide film 43 may be thinner than the thickness T10 of the third oxide film 61. In another example, the thickness T3 of the first oxide film 43 may be thicker than the thickness T10 of the third oxide film 61.

[0166] The relationship between the thickness T1 of the first metal layer 41 and the thickness T2 of the second metal layer 42 can be changed arbitrarily. In one example, the thickness T2 of the second metal layer 42 may be equal to the thickness T1 of the first metal layer 41. In another example, the thickness T2 of the second metal layer 42 may be thicker than the thickness T1 of the first metal layer 41. In other words, the thickness T2 of the second metal layer 42 may be equal to or greater than the thickness T1 of the first metal layer 41.

[0167] The shape of the surface wiring layer 40 can be changed arbitrarily. In one example, one of the step portions 90 in the short direction of the surface wiring layer 40 may be omitted. In another example, the step portions 90 on both sides of the short direction of the surface wiring layer 40 may be omitted. In this case, for example, the width dimension W2 of the second metal layer 42 may be made larger than that of the above embodiment. That is, the width dimension W2 of the second metal layer 42 is equal to the width dimension W1 of the first metal layer 41. Also, for example, the width dimension W1 of the first metal layer 41 may be made smaller than that of the above embodiment. That is, the width dimension W1 of the first metal layer 41 is equal to the width dimension W1 of the second metal layer 42. In this case, as the width dimension W1 of the first metal layer 41 is made smaller, the width dimension W3 of the first oxide film 43 is also made smaller.

[0168] The material forming the first metal layer 41 and the material forming the second metal layer 42 can each be changed as desired. In one example, the material forming the first metal layer 41 and the material forming the second metal layer 42 may be different from each other. In one example, the first metal layer 41 is formed of Al, and the second metal layer 42 is formed of Cu.

[0169] The configuration of the second metal layer 42 can be changed arbitrarily. For example, the second metal layer 42 may be formed of a laminated structure of a plurality of metal layers. In one example, as shown in FIG. 27, the second metal layer 42 is formed of a laminated structure of two metal layers 42P and 42Q. The metal layer 42P is formed on the first oxide film 43 so as to be in contact with the first oxide film 43. The metal layer 42Q is laminated on the metal layer 42P. The metal layer 42Q is in contact with the first bonding layer 81. The metal layers 42P and 42Q include, for example, any one of Al, Cu, Au, and Pt. In one example, the materials forming the metal layers 42P and 42Q may be different from each other. The metal layer 42P may be formed of a material including Al, and the metal layer 42Q may be formed of a material including Cu. The second metal layer 42 may be a laminated structure of three or more metal layers.

[0170] The thickness T3 of the first oxide film 43 can be changed arbitrarily. In one example, the first oxide film 43 may be thicker than 7 nm. The first oxide film 43 is thinner than the surface oxide film 810. In other words, the thickness T3 of the first oxide film 43 is in the range of thicknesses generally formed as natural oxide films, and is thinner than the oxide film (surface oxide film 810) formed on the first metal layer 41 by heat treatment.

[0171] In the above embodiment, the width dimension W5 of the second bonding layer 82 is equal to the width dimension W4 of the first bonding layer 81, but this is not limited thereto. The width dimension W5 of the second bonding layer 82 may include a portion that is larger than the width dimension W4 of the first bonding layer 81. In one example, the width dimension of the center portion in the thickness direction of the second bonding layer 82 may be larger than the width dimension W4 of the first bonding layer 81. In this case, it can be said that the second bonding layer 82 is formed in a barrel shape. In another example, the width dimension of the portion of the second bonding layer 82 closer to the element back electrode 37 may be larger than the width dimension W4 of the first bonding layer 81. In this case, the second bonding layer 82 may have a shape in which the width dimension gradually increases from the first bonding layer 81 toward the element back electrode 37.

[0172] In the above embodiment, the bonding layer 80 includes the first bonding layer 81 and the second bonding layer 82, but the present invention is not limited to this. In one example, the bonding layer 80 may be formed of the second bonding layer 82. That is, the bonding layer 80 may be formed of a material including AuSn. In this case, the second bonding layer 82 is formed on the second metal layer 42 so as to be in contact with the second metal layer 42.

[0173] In the above embodiment, the first metal layer 41 and the substrate 20 form an ohmic contact, but this is not limited thereto. It is sufficient that the first metal layer 41 and the substrate 20 are electrically connected.

[0174] The shape of the wire wiring layer 50 as viewed in the thickness direction of the substrate 20 can be changed arbitrarily. In one example, either the first wire bonding region 51 or the second wire bonding region 52 of the wire wiring layer 50 may be omitted. In this case, both the first wire WA and the second wire WB are bonded to the remaining wire bonding region.

[0175] The wire wiring layer 50 may be omitted. In this case, the element surface electrode 36 of the semiconductor light emitting element 30 and the individual pin 131 are connected by a wire. In addition, the size of the substrate 20 may be reduced in accordance with the omission of the wire wiring layer 50.

[0176] The detection wiring layer 60 may be omitted. In the above embodiment, the back surface wiring layer 70 and the substrate 20 form an ohmic contact, but this is not limited thereto. The back surface wiring layer 70 and the substrate 20 may be in electrical contact with each other.

[0177] The material forming the back wiring layer 70 is not limited to Au and can be changed as desired. In one example, the back wiring layer 70 may be a material containing at least one of Cu (copper), Ni, and Al.

[0178] Two mutually orthogonal directions among directions perpendicular to the thickness direction of the surface wiring layer 40 may be defined as the first direction and the second direction. Since the thickness direction of the surface wiring layer 40 coincides with the thickness direction of the substrate 20, the direction perpendicular to the thickness direction of the surface wiring layer 40 can also be said to be the direction perpendicular to the thickness direction of the substrate 20. The first direction is, for example, the short side direction of the surface wiring layer 40. The second direction is, for example, the long side direction of the surface wiring layer 40. Since the short side direction of the surface wiring layer 40 coincides with the short side direction of the substrate 20, the first direction can also be said to be the short side direction of the substrate 20. Since the long side direction of the surface wiring layer 40 coincides with the long side direction of the substrate 20, the second direction can also be said to be the long side direction of the substrate 20. In this case, for example, the width dimension is the size in the first direction, and the length dimension is the size in the second direction.

[0179] The statement "at least one of A and B" in this disclosure should be understood to mean "A only, or B only, or both A and B." One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.

[0180] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be directly disposed on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0181] <Additional Notes> The technical ideas that can be understood from the above-mentioned embodiment and modified examples are described below. Note that the reference numerals of the components of the embodiment corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0182] [Appendix 1] a substrate (20) having a substrate surface (21); a surface wiring layer (40) formed on the substrate surface (21); a semiconductor light emitting element (30) bonded to the surface wiring layer (40); a bonding layer (80) that bonds the surface wiring layer (40) and the semiconductor light emitting element (30); Equipped with The surface wiring layer (40) is a first metal layer (41) formed on the substrate surface (21); an oxide film (43) present on the first metal layer (41); a second metal layer (42) interposed between the oxide film (43) and the bonding layer (80); Including, The thickness (T2) of the second metal layer (42) is 1000 Å or more. A semiconductor light emitting device (10).

[0183] [Appendix 2] The thickness (T2) of the second metal layer (42) is 7000 Å or less. 2. The semiconductor light emitting device of claim 1.

[0184] [Appendix 3] The thickness (T2) of the second metal layer (42) is 3000 Å or more. 3. The semiconductor light emitting device according to claim 1 or 2.

[0185] [Appendix 4] The thickness (T2) of the second metal layer (42) is 5000 Å or more. 3. The semiconductor light emitting device according to claim 1 or 2.

[0186] [Appendix 5] The first metal layer (41) contains any one of Al, Cu, Au, and Pt, The second metal layer (42) contains any one of Al, Cu, Au, and Pt. 5. The semiconductor light emitting device according to claim 1.

[0187] [Appendix 6] The second metal layer (42) contains Al. 6. The semiconductor light emitting device according to claim 5.

[0188] [Appendix 7] The first metal layer (41) contains Al. 6. The semiconductor light emitting device according to claim 5.

[0189] [Appendix 8] The material forming the first metal layer (41) and the material forming the second metal layer (42) are different from each other. 6. The semiconductor light emitting device according to claim 1,

[0190] [Appendix 9] The material forming the first metal layer (41) and the material forming the second metal layer (42) are the same. 6. The semiconductor light emitting device according to claim 1,

[0191] [Appendix 10] The bonding layer is a first bonding layer (81) containing Ti and being on the second metal layer (42) and in contact with the second metal layer (42); a second bonding layer (82) containing AuSn and disposed on the first bonding layer (81) and in contact with the first bonding layer (81); Includes 10. The semiconductor light emitting device according to any one of claims 1 to 9.

[0192] [Appendix 11] The second metal layer has a thickness greater than that of the first bonding layer and less than that of the second bonding layer. 11. The semiconductor light emitting device of claim 10.

[0193] [Appendix 12] The thickness (T2) of the second metal layer (42) is smaller than the thickness (T1) of the first metal layer (41). 12. The semiconductor light emitting device according to claim 1.

[0194] [Appendix 13] The thickness (T2) of the second metal layer (42) is equal to or greater than the thickness (T1) of the first metal layer (41). 12. The semiconductor light emitting device according to claim 1.

[0195] [Appendix 14] The second metal layer (42) is formed of a laminated structure of a plurality of metal layers (42P, 42Q). 14. The semiconductor light emitting device according to claim 1,

[0196] [Appendix 15] The materials forming the plurality of metal layers (42P, 42Q) are different from each other. 15. The semiconductor light emitting device of claim 14.

[0197] [Appendix 16] The thickness (T4) of the first bonding layer (81) is 500 Å or more and 2500 Å or less. 11. The semiconductor light emitting device of claim 10.

[0198] [Appendix 17] The thickness (T3) of the oxide film (43) is 1 nm or more and 7 nm or less. 17. The semiconductor light emitting device according to claim 1.

[0199] [Appendix 18] A semiconductor light emitting device (30) according to any one of appendixes 1 to 17; a stem (110) on which the semiconductor light emitting device (30) is attached; a cap (120) attached to the stem (110), covering the semiconductor light emitting device (30), and having an opening (124) through which light emitted by the semiconductor light emitting device (30) passes; a terminal pin (130) electrically connected to the semiconductor light emitting device (30); A semiconductor light emitting module (100).

[0200] [Appendix 19] The thickness (T3) of the oxide film (43) is smaller than both the thickness (T1) of the first metal layer (41) and the thickness (T2) of the second metal layer (42). 2. The semiconductor light emitting device of claim 1.

[0201] [Appendix 20] In a direction perpendicular to a thickness direction (Z direction) of the surface wiring layer (40), the second metal layer (42) is smaller than the first metal layer (41); The surface wiring layer (40) includes a step portion (90) formed by the first metal layer (41) and the second metal layer (42). 20. The semiconductor light emitting device according to any one of claims 1 to 19.

[0202] [Appendix 21] The semiconductor light emitting element (30) is an element surface (31) facing the same side as the substrate surface (21); a back surface (32) of the element opposite to the front surface (31) of the element; a back surface electrode (37) formed on the back surface (32) of the element; having The element back surface electrode (37) is electrically connected to the front surface wiring layer (40) by the bonding layer (80). 11. The semiconductor light emitting device of claim 10.

[0203] [Appendix 22] The first metal layer (41) and the substrate (20) form an ohmic contact. 22. The semiconductor light emitting device according to any one of claims 1 to 21.

[0204] [Appendix 23] A back wiring layer (70) is formed on the back surface (22) of the substrate, The back wiring layer (70) is electrically connected to the front wiring layer (40) via the substrate (20). 23. The semiconductor light emitting device according to any one of claims 1 to 22.

[0205] [Appendix 24] The back wiring layer (70) and the substrate (20) form an ohmic contact. 24. The semiconductor light emitting device of claim 23.

[0206] [Appendix 25] a wire wiring layer (50) formed on a surface oxide film (27) formed on the substrate surface (21) and electrically connected to the semiconductor light emitting element (30) by a wire (W2); The wire wiring layer (50) has a layer surface (54) facing the same side as the substrate surface (21); A second oxide film (53) is formed on the layer surface (54), The wire (W2) penetrates the second oxide film (53) and is bonded to the layer surface (54). 25. The semiconductor light emitting device according to claim 1.

[0207] [Appendix 26] The thickness (T7) of the second oxide film (53) is equal to the thickness (T3) of the oxide film (43). 26. The semiconductor light emitting device of claim 25.

[0208] [Appendix 27] The substrate (20) is a semiconductor substrate containing p-type impurities. 27. The semiconductor light emitting device according to claim 1.

[0209] [Appendix 28] A step of preparing a substrate (20) having a substrate front surface (21) and a substrate back surface (22) opposite the substrate front surface (21); A step of depositing a surface wiring layer (40) on the substrate surface (21); a step of depositing a bonding layer (80) on the surface wiring layer (40); a step of bonding a semiconductor light emitting element (30) to the surface wiring layer (40) by the bonding layer (80); Equipped with The step of depositing the surface wiring layer (40) on the substrate surface (21) includes: forming a first metal layer (41) by depositing a first metal material on the substrate surface (21); forming a second metal layer (42) by depositing a second metal material on an oxide film (43) present on the first metal layer (41); Including, In the step of forming the second metal layer (42), the second metal material is deposited on the oxide film (43) so that the thickness (T2) of the second metal layer (42) is 1000 Å or more. A method for manufacturing a semiconductor light emitting device.

[0210] [Appendix 29] The method further includes a step of forming an ohmic contact between the first metal layer (41) and the substrate (20) by heat treatment; A step of forming an ohmic contact between the first metal layer (41) and the substrate (20) is carried out between the step of forming the first metal layer (41) and the step of forming the second metal layer (42). 29. A method for manufacturing the semiconductor light emitting device according to claim 28.

[0211] [Appendix 30] The method further includes a step of depositing a back wiring layer (70) on the back surface (22) of the substrate, a step of depositing the back wiring layer (70) on the back surface (22) of the substrate is carried out before a step of forming an ohmic contact between the first metal layer (41) and the substrate (20); The heat treatment in the step of forming an ohmic contact between the first metal layer (41) and the substrate (20) forms an ohmic contact between the back wiring layer (70) and the substrate (20). 30. A method for manufacturing the semiconductor light emitting device according to claim 29.

[0212] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0213] 10...Semiconductor light-emitting device 10X, 10Y: Comparative example semiconductor light emitting device 20...Substrate 21...Substrate surface 22…Back side of board 23~26...1st~4th board side 27...Surface oxide film 27A…1st opening 27B…Second opening 30...Semiconductor light emitting device 31...Element surface 32…Back side of element 33... Element substrate 33A…Substrate surface 33B…Back side of board 34…Light emitting part 34A…Electrode connection surface 34B…Board connection surface 34C, 34D…Light emitting part end surface 34E, 34F…Light-emitting part side 35...Insulating film 35A,35B...Substrate covering part 35C…Light-emitting part covering part 35D…Top surface 35E…1st opening 36: Element surface electrode 37…Back electrode of element 38…Light emitting unit 39…Tunnel layer 40…Surface wiring layer 40X, 40Y: Surface wiring layer of the comparative example 41...first metal layer 41A, 41B…1st side 42…Second metal layer 42A,42B…Second side 42P,42Q…metal layer 43…First oxide film 50…Wire wiring layer 51...first wire bonding area 52...Second wire bonding area 53...Second oxide film 54…Layer surface 60…Detection wiring layer 61...Third oxide film 70…Backside wiring layer 80...Joining layer 81...First bonding layer 82…Second bonding layer 90…Step 100...Semiconductor light emitting module 110…Stem 111…base 111A…Surface 111B…Back side 112…Heat sink 113, 114...Through holes 115…Recess 116...support surface 117,118…Insulation material 120…Cap 121...End wall 122...Peripheral wall 123...Flange 124…Opening 125...Translucent plate 130...Terminal pin 131,132...Individual pins 131A, 132A…Connection 131B,132B…Terminal section 133…Common pin 800…metal layer 810...Surface oxide film WA…First wire WB: Second wire LX: Laser light SP…containment space T1: Thickness of the first metal layer T2: Thickness of the second metal layer T3: Thickness of the first oxide film T4: Thickness of the first bonding layer T5: Thickness of the second bonding layer T6: Thickness of surface oxide film T7: Thickness of the second oxide film T8…Wire layer thickness T9: Thickness of detection wiring layer T10: Thickness of the third oxide film W1: Width of the first metal layer W2: Width of second metal layer W3: Width of first oxide film W4: Width of the first bonding layer W5: Width of second bonding layer W6: Width of semiconductor light emitting element

Claims

1. a substrate having a substrate surface; a surface wiring layer formed on the surface of the substrate; a semiconductor light emitting element bonded to the surface wiring layer; a bonding layer that bonds the surface wiring layer and the semiconductor light emitting element; Equipped with The surface wiring layer is a first metal layer formed on a surface of the substrate; an oxide film present on the first metal layer; a second metal layer interposed between the oxide film and the bonding layer; Including, The second metal layer has a thickness of 1000 Å or more. Semiconductor light emitting device.

2. The second metal layer has a thickness of 7000 Å or less. The semiconductor light emitting device according to claim 1 .

3. The second metal layer has a thickness of 3000 Å or more. The semiconductor light emitting device according to claim 1 .

4. The second metal layer has a thickness of 5000 Å or more. The semiconductor light emitting device according to claim 1 .

5. the first metal layer includes any one of Al, Cu, Au, and Pt; The second metal layer includes any one of Al, Cu, Au, and Pt. The semiconductor light emitting device according to claim 1 .

6. The second metal layer includes Al. The semiconductor light emitting device according to claim 5 .

7. The first metal layer includes Al. The semiconductor light emitting device according to claim 5 .

8. The material forming the first metal layer and the material forming the second metal layer are different from each other. The semiconductor light emitting device according to claim 1 .

9. The material forming the first metal layer and the material forming the second metal layer are the same. The semiconductor light emitting device according to claim 1 .

10. The bonding layer is a first bonding layer including Ti and disposed on the second metal layer and in contact with the second metal layer; a second bonding layer including AuSn and disposed on the first bonding layer and in contact with the first bonding layer; Includes The semiconductor light emitting device according to claim 1 .

11. The second metal layer has a thickness greater than that of the first bonding layer and less than that of the second bonding layer. The semiconductor light emitting device according to claim 10.

12. The thickness of the second metal layer is less than the thickness of the first metal layer. The semiconductor light emitting device according to claim 1 .

13. The thickness of the second metal layer is equal to or greater than the thickness of the first metal layer. The semiconductor light emitting device according to claim 1 .

14. The second metal layer is formed of a laminated structure of a plurality of metal layers. The semiconductor light emitting device according to claim 1 .

15. The materials forming the plurality of metal layers are different from each other. The semiconductor light emitting device according to claim 14.

16. The thickness of the first bonding layer is 500 Å or more and 2500 Å or less. The semiconductor light emitting device according to claim 10.

17. The thickness of the oxide film is 1 nm or more and 7 nm or less. The semiconductor light emitting device according to claim 1 .

18. A semiconductor light emitting device according to any one of claims 1 to 17, a stem having the semiconductor light emitting device attached thereto; a cap attached to the stem, covering the semiconductor light emitting device and having an opening through which light emitted by the semiconductor light emitting device passes; a terminal pin electrically connected to the semiconductor light emitting device; A semiconductor light emitting module comprising:

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