Semiconductor device, control method for semiconductor device, and control program

Abstract

To provide a semiconductor device capable of operating accurately while suppressing the propagation of interference noise, a control method for the semiconductor device, and a control program.SOLUTION: A semiconductor device according to the present disclosure includes: a first AD converter of a charge redistribution type sequential comparison type that includes a redundant comparison operation in a sequential comparison operation and outputs a first input signal of an analog differential using a reference voltage to a digital first output signal; a first variable impedance circuit that is provided on a signal line between a first pin to which the reference voltage is supplied from the outside and the first AD converter, and is capable of changing impedance; and a first control circuit that controls the impedance of the first variable impedance circuit according to an operating condition of the first AD converter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a control method for the semiconductor device, and a control program, and, for example, to a semiconductor device, a control method for the semiconductor device, and a control program capable of operating with high precision while suppressing propagation of interference noise. [Background technology]

[0002] Non-Patent Document 1 discloses a charge redistribution type successive approximation AD converter. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Akira Matsuzawa, “The Future of Analog ADC Development”, [online], March 15, 2013, [Retrieved May 20, 2023], Internet<URL:http: / / www.ssc.pe.titech.ac.jp / publications / 2013 / RFanalog / matsu_open_130315.pdf> Summary of the Invention [Problem to be solved by the invention]

[0004] In a charge redistribution type successive approximation AD converter, the charging and discharging of electric charge caused by the switching of capacitance during successive approximation operation causes disturbances (noise) in the reference voltage in the signal line through which the reference voltage is propagated. In particular, in a comparison operation for determining the value of the upper bit of a digital signal, a large capacitance is switched, so the change in current caused by the charging and discharging of electric charge becomes steep, and the noise generated in the signal line through which the reference voltage is propagated becomes large. This causes a problem in that the noise is propagated to other circuits that share the signal line through which the reference voltage is propagated, preventing the other circuits from operating with high precision.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a first AD converter of a charge redistribution type successive approximation type that includes a redundant comparison operation in a successive approximation operation and converts an analog differential first input signal into a digital first output signal using a reference voltage and outputs the signal; a first variable impedance circuit that is provided on a signal line between the first AD converter and a first pin to which the reference voltage is supplied from an outside and is configured to be able to change the impedance; and a first control circuit that controls the impedance of the first variable impedance circuit depending on the operating status of the first AD converter.

[0007] A control method for a semiconductor device according to one embodiment of the present disclosure includes a first AD converter of a charge redistribution type successive approximation type, which includes a redundant comparison operation in a successive approximation operation and converts an analog differential first input signal into a digital first output signal using a reference voltage and outputs the signal; a first variable impedance circuit provided on a signal line between a first pin to which the reference voltage is supplied from an outside and the first AD converter, and configured to be able to change the impedance; and a first control circuit that controls the impedance of the first variable impedance circuit according to an operating status of the first AD converter, the control method comprising the steps of: controlling an impedance of the first variable impedance circuit to a first impedance; performing, in the first AD converter, a comparison operation for determining a value of a higher-order bit in a first predetermined range among a plurality of bits representing the first output signal; controlling the impedance of the first variable impedance circuit to a second impedance lower than the first impedance; and performing, in the first AD converter, a comparison operation for determining a value of a lower-order bit other than the higher-order bit in the first predetermined range among the plurality of bits representing the first output signal, and a redundant comparison operation.

[0008] A control program according to one embodiment of the present disclosure is a control program that causes a computer to execute control processing in a semiconductor device including: a first AD converter of a charge redistribution type successive approximation type that includes a redundant comparison operation in a successive approximation operation and converts an analog differential first input signal into a digital first output signal using a reference voltage and outputs the signal; a first variable impedance circuit that is provided on a signal line between a first pin to which the reference voltage is supplied from an outside and the first AD converter and is configured to be able to change the impedance; and a first control circuit that controls the impedance of the first variable impedance circuit in accordance with an operating status of the first AD converter. The control program causes the computer to execute a process of controlling the impedance of the first variable impedance circuit to a first impedance; a process of executing a comparison operation in the first AD converter to determine a value of a higher-order bit in a first predetermined range among a plurality of bits representing the first output signal; a process of controlling the impedance of the first variable impedance circuit to a second impedance lower than the first impedance; and a process of executing a comparison operation in the first AD converter to determine a value of a lower-order bit other than the higher-order bit in the first predetermined range among the plurality of bits representing the first output signal, and a redundant comparison operation. Effect of the Invention

[0009] The present disclosure can provide a semiconductor device, a control method for a semiconductor device, and a control program capable of operating with high precision while suppressing propagation of interference noise. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing in more detail an AD converter of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a diagram showing a specific example of the semiconductor device according to the first embodiment. In FIG. [Figure 4]FIG. 4 is a diagram for explaining interference noise generated in the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a waveform diagram for explaining interference noise generated in the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a diagram for explaining the successive approximation operation of each AD converter provided in the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a block diagram showing a configuration example of a semiconductor device according to the second embodiment. As shown in FIG. [Figure 9] FIG. 9 is a diagram showing a specific example of the semiconductor device according to the second embodiment. In FIG. [Figure 10] FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to the third embodiment. As shown in FIG. [Figure 11] FIG. 11 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a block diagram showing another configuration example of the semiconductor device according to the third embodiment. In FIG. [Figure 13] FIG. 13 is a diagram showing a first configuration example of a semiconductor device that has been previously examined. [Figure 14] FIG. 14 is a diagram for explaining a propagation path of an interference noise generated in the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a timing chart showing the operation of each AD converter provided in the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a waveform diagram for explaining noise generated in the semiconductor device shown in FIG. [Figure 17] FIG. 17 is a diagram showing a second configuration example of a semiconductor device that has been previously examined. [Figure 18] FIG. 18 is a diagram for explaining a propagation path of an interference noise generated in the semiconductor device shown in FIG. [Figure 19]FIG. 19 is a waveform diagram for explaining noise generated in the semiconductor device shown in FIG. [Figure 20] FIG. 20 is a diagram showing a third configuration example of a semiconductor device that has been previously examined. [Figure 21] FIG. 21 is a diagram for explaining a propagation path of an interference noise generated in the semiconductor device shown in FIG. [Figure 22] FIG. 22 is a waveform diagram for explaining noise generated in the semiconductor device shown in FIG. [Figure 23] FIG. 23 is a diagram for explaining an ideal successive approximation operation of the AD converter provided in the semiconductor device shown in FIG. [Figure 24] FIG. 24 is a diagram for explaining a problem that occurs in the successive approximation operation of the AD converter provided in the semiconductor device shown in FIG. [Diagram 25] FIG. 25 is a diagram showing a fourth configuration example of a semiconductor device that has been examined in advance. [Figure 26] FIG. 26 is a diagram for explaining an ideal successive approximation operation of the AD converter provided in the semiconductor device shown in FIG. [Figure 27] FIG. 27 is a diagram for explaining a problem that occurs in the successive approximation operation of the AD converter provided in the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0013] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0014] <Preliminary review by inventors, etc.> Before describing the semiconductor device according to the present embodiment, a semiconductor device previously examined by the present inventors will be described.

[0015] Fig. 13 is a diagram showing a configuration example of a semiconductor device 5 that has been examined in advance. The semiconductor device 5 is, for example, an MCU (Micro Controller Unit) and includes a plurality of AD converters. In the example of Fig. 13, the semiconductor device 5 includes two AD converters 51 and 52 on a chip 50. The semiconductor device 5 also includes a plurality of pins that interface the chip 50 with the outside of the semiconductor device 5.

[0016] A high-potential side power supply voltage (hereinafter referred to as power supply voltage AVCC) common to the AD converters 51 and 52 is supplied to the pin AVCC from outside the semiconductor device 5. A low-potential side power supply voltage (hereinafter referred to as power supply voltage AVSS) common to the AD converters 51 and 52 is supplied to the pin AVSS from outside the semiconductor device 5. In other words, the AD converters 51 and 52 share the pins AVCC and AVSS.

[0017] A high-potential side reference voltage (hereinafter referred to as reference voltage VREFH) common to the AD converters 51 and 52 is supplied to the pin VREFH from outside the semiconductor device 5. A low-potential side reference voltage (hereinafter referred to as reference voltage VREFL) common to the AD converters 51 and 52 is supplied to the pin AVSS from outside the semiconductor device 5. In other words, the AD converters 51 and 52 share the pins VREFH and VREFL.

[0018] Here, a parasitic inductor L51 is formed in the signal line connected to the pin AVCC by a board substrate, a lead frame, a bonding wire, etc. (none of which are shown). Similarly, a parasitic inductor L52 is formed in the signal line connected to the pin VREFH. A parasitic inductor L53 is formed in the signal line connected to the pin VREFL. A parasitic inductor L54 is formed in the signal line connected to the pin AVSS.

[0019] The pins INP1 and INN1 are supplied with one and the other of an analog differential input signal IN1 that is to be AD converted by the AD converter 51 from outside the semiconductor device 5. The pins INP2 and INN2 are supplied with one and the other of an analog differential input signal IN2 that is to be AD converted by the AD converter 52 from outside the semiconductor device 5.

[0020] At the pin OUT1, a digital output signal (hereinafter referred to as output signal OUT1) which is the result of AD conversion by the AD converter 51 is output to the outside of the semiconductor device 5. At the pin OUT2, a digital output signal (hereinafter referred to as output signal OUT2) which is the result of AD conversion by the AD converter 52 is output to the outside of the semiconductor device 5.

[0021] The AD converter 51 is a charge redistribution type successive approximation AD converter that converts an analog differential input signal IN1 into a digital output signal OUT1 using a binary search algorithm and outputs it. The AD converter 51 is configured to perform AD conversion on the differential input signal IN1 based on the difference between the reference voltages VREFH and VREFL, and therefore can improve the fluctuation rejection ratio of the power supply voltages AVCC and AVSS.

[0022] The AD converter 51 performs a successive comparison operation on the input signal IN1 while redistributing the charges stored in each of the multiple capacitive elements based on the potential of the input signal IN1 and the reference voltages VREFH and VREFL by switching the connections of the multiple capacitive elements using multiple switches.

[0023] Of the multiple terminals provided in the AD converter 51, a reference voltage VREFH is supplied to a terminal VH1. A power supply voltage AVCC is supplied to a terminal VH2. A reference voltage VREFL is supplied to a terminal VL1. A power supply voltage AVSS is supplied to a terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 51, and the reference voltages VREFH and VREFL are used in the successive approximation operation of the AD converter 51.

[0024] Like AD converter 51, AD converter 52 is a charge redistribution type successive approximation AD converter that uses a binary search algorithm to convert analog differential input signal IN2 into a digital output signal OUT2 and outputs it. AD converter 52 is configured to perform AD conversion on differential input signal IN2 based on the difference between reference voltages VREFH, VREFL, and can therefore improve the fluctuation rejection ratio of power supply voltages AVCC, AVSS.

[0025] The AD converter 52 performs a successive approximation operation on the input signal IN2 while redistributing the charges stored in each of the multiple capacitive elements based on the potential of the input signal IN2 and the reference voltages VREFH and VREFL by switching the connections of the multiple capacitive elements using multiple switches.

[0026] Of the multiple terminals provided in the AD converter 52, a reference voltage VREFH is supplied to a terminal VH1. A power supply voltage AVCC is supplied to a terminal VH2. A reference voltage VREFL is supplied to a terminal VL1. A power supply voltage AVSS is supplied to a terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 52, and the reference voltages VREFH and VREFL are used in the successive approximation operation of the AD converter 52.

[0027] Fig. 14 is a diagram for explaining a propagation path of interference noise generated in the semiconductor device 5. Fig. 15 is a timing chart showing the operation of each AD converter provided in the semiconductor device 5. Fig. 16 is a waveform diagram for explaining noise generated in the semiconductor device 5.

[0028] It is generally known that in inductors such as the parasitic inductors L51 to L54, the impedance changes significantly due to a steep change in current.

[0029] Here, for example, assume that the capacitance of the successive approximation operation is switched in the AD converter 52 asynchronously with the AD converter 51 (see FIG. 15). At this time, the current changes at the terminals VH1 and VL1 (terminals to which the reference voltages VREFH and VREFL are supplied) of the AD converter 52 due to charging and discharging of electric charge caused by the switching of the capacitance. In particular, in the comparison operation for determining the value of the upper bit of the digital output signal OUT2, a large capacitance is switched, so that the change in current due to charging and discharging of electric charge becomes steep. When this steep change in current at the terminals VH1 and VL1 of the AD converter 52 is transmitted to the parasitic inductors L52 and L53, the impedance of the parasitic inductors L52 and L53 changes significantly (see FIG. 16). As a result, the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 51 also change significantly (see FIG. 16). That is, noise generated at the terminals VH1 and VL1 of the AD converter 52, which is the aggressor, is transmitted to the terminals VH1 and VL1 of the AD converter 51, which is the victim. As a result, the AD converter 51 cannot operate with high accuracy.

[0030] Therefore, the inventors next examined the semiconductor device 6. 17 is a diagram showing a configuration example of a semiconductor device 6 that has been previously examined. Compared to the semiconductor device 5, the semiconductor device 6 further includes a bypass capacitor C51 on a chip 50. The bypass capacitor C51 is provided in the chip 50 between a signal line common to the AD converters 51 and 52 through which the reference voltage VREFH propagates and a signal line common to the AD converters 51 and 52 through which the reference voltage VREFL propagates. The capacitance value of the bypass capacitor C51 is, for example, about 100 pF to 1 nF. Other configurations of the semiconductor device 6 are similar to those of the semiconductor device 5, and therefore description thereof will be omitted.

[0031] Fig. 18 is a diagram for explaining a propagation path of interference noise generated in the semiconductor device 6. Fig. 19 is a waveform diagram for explaining noise generated in the semiconductor device 6.

[0032] In the semiconductor device 6, similarly to the case of the semiconductor device 5, the current changes sharply at the terminals VH1 and VL1 of the AD converter 52 due to charging and discharging of electric charges caused by switching of the capacitance of the successive approximation operation. However, in the semiconductor device 6, the bypass capacitor C51 suppresses the change in the current flowing through each of the parasitic inductors L52 and L53, so that the change in the impedance of each of the parasitic inductors L52 and L53 becomes small (see FIG. 19). As a result, the fluctuation of the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 51, respectively, is suppressed (see FIG. 19). In other words, the propagation of the noise generated at each of the terminals VH1 and VL1 of the AD converter 52, which is the aggressor, to the terminals VH1 and VL1 of the AD converter 51, which is the victim, is suppressed. As a result, the AD converter 51 can operate with high accuracy.

[0033] However, in the semiconductor device 6, the bypass capacitor C51 is large in scale, which increases the chip size.

[0034] Therefore, the inventors next examined the semiconductor device 7. 20 is a diagram showing a configuration example of a pre-considered semiconductor device 7. Compared to the semiconductor device 6, the semiconductor device 7 includes, on a chip 50, instead of the bypass capacitor C51, resistor elements R51, R52, R61, and R62 that are smaller in scale than the bypass capacitor C51.

[0035] The resistive element R51 is provided on a signal line between the pin VREFH and the terminal VH1 of the AD converter 51, which is branched from the signal line common to the AD converter 52. The resistive element R52 is provided on a signal line between the pin VREFL and the terminal VL1 of the AD converter 51, which is branched from the signal line common to the AD converter 52. The resistive element R61 is provided on a signal line between the pin VREFH and the terminal VH1 of the AD converter 52, which is branched from the signal line common to the AD converter 51. The resistive element R62 is provided on a signal line between the pin VREFL and the terminal VL1 of the AD converter 52, which is branched from the signal line common to the AD converter 51. The other configurations of the semiconductor device 7 are the same as those of the semiconductor device 6, so the description thereof will be omitted. As a result, the semiconductor device 7 can suppress an increase in circuit size compared to the semiconductor device 6.

[0036] Fig. 21 is a diagram for explaining a propagation path of interference noise generated in the semiconductor device 7. Fig. 22 is a waveform diagram for explaining noise generated in the semiconductor device 7.

[0037] In the semiconductor device 7, similarly to the case of the semiconductor device 5, the current changes sharply at the terminals VH1 and VL1 of the AD converter 52 due to charging and discharging of electric charges caused by switching of the capacitance of the successive approximation operation. However, in the semiconductor device 7, the resistance elements R51, R52, R61, and R62 suppress the change in the current flowing through each of the parasitic inductors L52 and L53, so that the change in the impedance of each of the parasitic inductors L52 and L53 becomes small (see FIG. 22). As a result, the fluctuation of the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 51, respectively, is suppressed (see FIG. 22). In other words, the propagation of the noise generated at each of the terminals VH1 and VL1 of the AD converter 52, which is the aggressor, to the terminals VH1 and VL1 of the AD converter 51, which is the victim, is suppressed. However, due to the IR drop caused by the resistive elements R61 and R62, the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 52, which is the aggressor, fluctuate significantly (see FIG. 22). As a result, the AD converter 52 cannot operate with high accuracy.

[0038] Fig. 23 is a diagram for explaining an ideal successive approximation operation of an AD converter provided in the semiconductor device 7. In the example of Fig. 23, an AD converter 52 converts an analog input signal IN2 into a 4-bit digital output signal OUT2 and outputs it.

[0039] First, the AD converter 52 samples the input signal IN2 and holds the sampled input signal IN2.

[0040] Next, the AD converter 52 performs a successive comparison operation on the input signal IN2 while redistributing the charges stored in each of the multiple capacitive elements based on the potential of the input signal IN2 and reference voltages VREFH, VREFL (hereinafter collectively referred to as the reference voltage VREF) by switching the connections of the multiple capacitive elements using multiple switches.

[0041] First, the AD converter 52 performs a comparison operation to determine the value of the most significant bit (MSB) of the 4 bits representing the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1000, in which the most significant bit is set to "1". When the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 23, since the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1".

[0042] Thereafter, the AD converter 52 performs a comparison operation to determine the value of the second most significant bit (the second most significant bit) of the output signal OUT2 by switching the connection of the capacitance element by the switch and redistributing the charge. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1100 in which the second most significant bit is set to "1". When the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the second most significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1100, the second most significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 23, since the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the second most significant bit of the output signal OUT2 is determined to be "1".

[0043] Thereafter, the AD converter 52 performs a comparison operation to determine the value of the third most significant bit (the third bit from the most significant bit) of the output signal OUT2 by switching the connection of the capacitance element by the switch and redistributing the charge. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1110 in which the third most significant bit is set to "1". When the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1110, the third most significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1110, the third most significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 23, since the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1110, the third most significant bit of the output signal OUT2 is determined to be "0".

[0044] Thereafter, the AD converter 52 switches the connection of the capacitance element by the switch to redistribute the charge, thereby performing a comparison operation to determine the value of the fourth most significant bit (least significant bit) of the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1101 in which the least significant bit is set to "1". When the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 23, since the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0".

[0045] As a result, the AD converter 52 ideally performs AD conversion on the analog input signal IN2 and outputs the output signal OUT2 having the digital value 4b'1100.

[0046] Fig. 24 is a diagram for explaining a problem that occurs in the successive approximation operation of the AD converter provided in the semiconductor device 7. In the example of Fig. 24, the AD converter 52 converts an analog input signal IN2 into a 4-bit digital output signal OUT2 and outputs it.

[0047] As shown in FIG. 24, after the most significant bit of the output signal OUT2 is determined, the AD converter 52 performs a comparison operation to determine the value of the second most significant bit of the output signal OUT2 by switching the connection of the capacitance elements with a switch and redistributing the charge. Here, the reference voltages VREFH and VREFL supplied to the AD converter 52 fluctuate greatly due to an IR drop caused by the resistance elements R61 and R62 accompanying the switching of the connection of the capacitance elements. This may cause the AD converter 52 to make a comparison error due to a settling error. In the example of FIG. 24, although the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the potential of the input signal IN2 is determined to be less than the DA-converted value of the digital value 4b'1100. Therefore, the second most significant bit of the output signal OUT2 is erroneously determined to be "0".

[0048] As a result, the AD converter 52 erroneously performs AD conversion on the analog input signal IN2 and outputs the output signal OUT2 having the digital value 4b'1011.

[0049] Therefore, the inventors next examined the semiconductor device 8. 25 is a diagram showing a configuration example of a semiconductor device 8 that has been examined in advance. Compared to the semiconductor device 7, the semiconductor device 8 includes AD converters 61 and 62 instead of the AD converters 51 and 52. Each of the AD converters 61 and 62 is configured to further include a redundant comparison operation in the successive approximation operation. As a result, even if a comparison error occurs due to fluctuations in the reference voltages VREFH and VREFL caused by IR drops of the resistance elements R51, R52, R61, and R62, each of the AD converters 61 and 62 can recover from the comparison error by redundant comparison.

[0050] Fig. 26 is a diagram for explaining an ideal successive approximation operation of an AD converter provided in the semiconductor device 8. In the example of Fig. 26, an AD converter 62 converts an analog input signal IN2 into a 4-bit digital output signal OUT2 and outputs it.

[0051] As shown in FIG. 26, after the most significant bit of the output signal OUT2 is determined, the AD converter 62 performs a comparison operation to determine the value of the second most significant bit of the output signal OUT2 by switching the connection of the capacitance elements with a switch and redistributing the charge. Here, the reference voltages VREFH and VREFL supplied to the AD converter 52 fluctuate greatly due to an IR drop caused by the resistance elements R61 and R62 accompanying the switching of the connection of the capacitance elements. This may cause the AD converter 62 to make a comparison error due to a settling error. In the example of FIG. 26, although the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the potential of the input signal IN2 is determined to be less than the DA-converted value of the digital value 4b'1100. Therefore, the second most significant bit of the output signal OUT2 is erroneously determined to be "0".

[0052] Here, after the comparison operation for determining the value of the third most significant bit of the output signal OUT2, the AD converter 62 switches the connection of the capacitive element using a switch and redistributes the charge, thereby performing a redundant comparison operation with the same resolution as the comparison operation for determining the value of the third most significant bit, for example.

[0053] Specifically, when the AD converter 62 determines in a comparison operation for determining the value of the third most significant bit of the output signal OUT2 that the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value to be compared, in the next redundant comparison operation, the AD converter 62 compares the potential of the input signal IN2 with the DA-converted value of the digital value to be compared, which is obtained by adding 4'b0010 to the digital value to be compared. Also, when the AD converter 62 determines in a comparison operation for determining the value of the third most significant bit of the output signal OUT2 that the potential of the input signal IN2 is less than the DA-converted value of the digital value to be compared, in the next redundant comparison operation, the AD converter 62 compares the potential of the input signal IN2 with the DA-converted value of the digital value to be compared, which is obtained by subtracting 4'b0010 from the digital value to be compared.

[0054] In the example of Figure 26, in the comparison operation to determine the value of the third most significant bit of the output signal OUT2, the AD converter 62 determines that the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4'b1010, and therefore in the next redundant comparison operation, it compares the potential of the input signal IN2 with the digital value 4'b1100, which is the sum of the digital value 4'b1010 and 4'b0010.

[0055] 26, the potential of the input signal IN2 is determined to be equal to or greater than the DA-converted value of the digital value 4'b1100. Therefore, in a comparison operation for determining the value of the next least significant bit, the AD converter 62 compares the potential of the input signal IN2 with a DA-converted value of a digital value obtained by adding 4'b0001 to the digital value to be compared. Specifically, in a comparison operation for determining the value of the least significant bit, the AD converter 62 compares the potential of the input signal IN2 with a digital value 4'b1101 obtained by adding 4'b0001 to the digital value 4'b1100. The comparison operation for determining the value of the least significant bit by the AD converter 62 is similar to that of the AD converter 52.

[0056] In addition, if it is determined that the potential of the input signal IN2 is less than the DA-converted value of the digital value 4'b1100, the AD converter 62 compares the potential of the input signal IN2 with the DA-converted value of the digital value obtained by subtracting 4'b00001 from the digital value to be compared.

[0057] In this way, ideally, even if a comparison error occurs due to a fluctuation in the reference voltages VREFH and VREFL caused by the IR drop of the resistor elements R61 and R62, the AD converter 62 can recover from the comparison error by redundant comparison. The same applies to the AD converter 61.

[0058] However, in reality, the AD converter 62 is highly likely to make a comparison error even in the redundant comparison operation due to fluctuations in the reference voltages VREFH and VREFL caused by the IR drops of the resistance elements R61 and R62 (see FIG. 27).

[0059] Thus, a semiconductor device 1 has been discovered that is capable of operating with high precision while suppressing the propagation of interference noise.

[0060] <Embodiment 1> 1 is a block diagram showing a configuration example of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, an MCU and includes a plurality of AD converters. In this embodiment, a case will be described in which the semiconductor device 1 includes two AD converters 11 and 12 on a chip 10.

[0061] Specifically, the semiconductor device 1 includes AD converters 11 and 12, control circuits 13 and 14, variable impedance circuits Z11 and Z12, and variable impedance circuits Z21 and Z22 on a chip 10. The semiconductor device 1 also includes a plurality of pins that interface the chip 10 with the outside of the semiconductor device 1.

[0062] A high-potential side power supply voltage (hereinafter referred to as power supply voltage AVCC) common to the AD converters 11 and 12 is supplied to the pin AVCC from outside the semiconductor device 1. A low-potential side power supply voltage (hereinafter referred to as power supply voltage AVSS) common to the AD converters 11 and 12 is supplied to the pin AVSS from outside the semiconductor device 1. In other words, the AD converters 11 and 12 share the pins AVCC and AVSS.

[0063] A high-potential side reference voltage (hereinafter referred to as reference voltage VREFH) common to the AD converters 11 and 12 is supplied to the pin VREFH from outside the semiconductor device 1. A low-potential side reference voltage (hereinafter referred to as reference voltage VREFL) common to the AD converters 11 and 12 is supplied to the pin VREFL from outside the semiconductor device 1. In other words, the AD converters 11 and 12 share the pins VREFH and VREFL.

[0064] Here, a parasitic inductor L1 is formed in the signal line connected to the pin AVCC by a board substrate, a lead frame, a bonding wire, etc. (none of which are shown). Similarly, a parasitic inductor L2 is formed in the signal line connected to the pin VREFH. A parasitic inductor L3 is formed in the signal line connected to the pin VREFL. A parasitic inductor L4 is formed in the signal line connected to the pin AVSS.

[0065] The pins INP1 and INN1 are supplied with one and the other of an analog differential input signal IN1 that is to be AD converted by the AD converter 11 from outside the semiconductor device 1. The pins INP2 and INN2 are supplied with one and the other of an analog differential input signal IN2 that is to be AD converted by the AD converter 12 from outside the semiconductor device 1.

[0066] At the pin OUT1, a digital output signal (hereinafter referred to as output signal OUT1) which is the result of AD conversion by the AD converter 11 is output to the outside of the semiconductor device 1. At the pin OUT2, a digital output signal (hereinafter referred to as output signal OUT2) which is the result of AD conversion by the AD converter 12 is output to the outside of the semiconductor device 1.

[0067] The AD converter 11 is a charge redistribution type successive approximation AD converter, which uses a binary search algorithm to convert an analog differential input signal IN1 into a digital output signal OUT1 based on the difference between reference voltages VREFH and VREFL and outputs the digital output signal OUT1. The AD converter 11 is configured to perform AD conversion on the differential input signal IN1 based on the difference between the reference voltages VREFH and VREFL, thereby improving the fluctuation rejection ratio of the power supply voltages AVCC and AVSS. The AD converter 11 is also configured to further include a redundant comparison operation in the successive approximation operation.

[0068] Of the multiple terminals provided in the AD converter 11, a reference voltage VREFH is supplied to a terminal VH1. A power supply voltage AVCC is supplied to a terminal VH2. A reference voltage VREFL is supplied to a terminal VL1. A power supply voltage AVSS is supplied to a terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 11, and the reference voltages VREFH and VREFL are used as a reference for the successive approximation operation of the AD converter 11.

[0069] 2 is a diagram showing a specific configuration example of the AD converter 11. The AD converter 11 includes a DA converter 111, a comparator 112, and a successive approximation register circuit 113. The DA converter 111 includes a DA converter 111u provided on one input signal INP1 side of the differential input signal IN1, and a DA converter 111d provided on the other input signal INN1 side of the differential input signal IN1. The DA converter 111u includes capacitance elements Cu0 and Cu1 exhibiting a minimum capacitance value 2^0·C, n-1 (n is an integer of 2 or more) capacitance elements Cu2 to Cun binary-weighted with respect to the capacitance value of the capacitance element Cu1, a redundant capacitance element Cur exhibiting the same capacitance value 2^(k-1)·C as the capacitance element Cuk (k is any one of 1 to n), and switches Su0, Su1 to Sun, and Sur provided corresponding to the capacitance elements Cu0, Cu1 to Cun, and Cur, respectively. The DA converter 111d includes capacitance elements Cd0 and Cd1 exhibiting a minimum capacitance value of 2^0·C, n-1 (n is an integer of 2 or more) capacitance elements Cd2 to Cdn binary-weighted with respect to the capacitance value of the capacitance element Cd1, a redundant capacitance element Cdr exhibiting the same capacitance value of 2^(k-1)·C as the capacitance element Cdk (k is any one of 1 to n), and switches Sd0, Sd1 to Sdn, and Sdr provided corresponding to the capacitance elements Cd0, Cd1 to Cdn, and Cdr, respectively. The DA converter 111 also has a function of sampling and holding the potential of the input signal IN1.

[0070] In the DA converter 111, the AD converter 11 performs a successive comparison operation between the output of the DA converter 111 and the potential of the input signal IN1, while redistributing the charges stored in each of a plurality of capacitance elements based on the potential of the input signal IN1 and reference voltages VREFH, VREFL by switching the connections of the plurality of capacitance elements using a plurality of switches, and using a comparator 112 and a successive comparison register circuit 113.

[0071] The variable impedance circuit Z11 is provided on a signal line branched off from a signal line shared with the AD converter 12, among the signal lines between the pin VREFH and the terminal VH1 of the AD converter 11. For example, the variable impedance circuit Z11 has m signal lines Z11_1 to Z11_m having different impedances, and a switch SW11 that selects one of the m signal lines Z11_1 to Z11_m based on a control signal from the control circuit 13. Here, m is an integer equal to or greater than 2.

[0072] The variable impedance circuit Z12 is provided on a signal line branched off from a signal line common to the AD converter 12, among the signal lines between the pin VREFL and the terminal VL1 of the AD converter 11. For example, the variable impedance circuit Z12 has m signal lines Z12_1 to Z12_m having different impedances, and a switch SW12 that selects one of the m signal lines Z12_1 to Z12_m based on a control signal from the control circuit 13.

[0073] The control circuit 13 controls the operation of the AD converter 11 and also controls the impedance of each of the variable impedance circuits Z11 and Z12.

[0074] The AD converter 12 is a charge redistribution type successive approximation AD converter, which uses a binary search algorithm to convert an analog differential input signal IN2 into a digital output signal OUT2 based on the difference between reference voltages VREFH and VREFL and outputs the digital output signal OUT2. The AD converter 12 is configured to perform AD conversion on the differential input signal IN2 based on the difference between the reference voltages VREFH and VREFL, thereby improving the fluctuation rejection ratio of the power supply voltages AVCC and AVSS. The AD converter 12 is also configured to further include a redundant comparison operation in the successive approximation operation.

[0075] Of the multiple terminals provided in the AD converter 12, a reference voltage VREFH is supplied to a terminal VH1. A power supply voltage AVCC is supplied to a terminal VH2. A reference voltage VREFL is supplied to a terminal VL1. A power supply voltage AVSS is supplied to a terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 12, and the reference voltages VREFH and VREFL are used as a reference for the successive approximation operation of the AD converter 12.

[0076] The specific configuration of AD converter 12 is similar to that of AD converter 11, and therefore a description thereof will be omitted.

[0077] The variable impedance circuit Z21 is provided on a signal line branched off from a signal line common to the AD converter 11, among the signal lines between the pin VREFH and the terminal VH1 of the AD converter 12. For example, the variable impedance circuit Z21 has m signal lines Z21_1 to Z21_m having different impedances, and a switch SW21 that selects one of the m signal lines Z21_1 to Z21_m based on a control signal from the control circuit 14.

[0078] The variable impedance circuit Z22 is provided on a signal line branched off from a signal line common to the AD converter 11, among the signal lines between the pin VREFL and the terminal VL1 of the AD converter 12. For example, the variable impedance circuit Z22 has m signal lines Z22_1 to Z22_m having different impedances, and a switch SW22 that selects one of the m signal lines Z22_1 to Z22_m based on a control signal from the control circuit 14.

[0079] The control circuit 14 controls the operation of the AD converter 12 and also controls the impedance of each of the variable impedance circuits Z21 and Z22.

[0080] (Specific example of semiconductor device 1) Fig. 3 is a diagram showing a semiconductor device 1a as a specific example of the semiconductor device 1. As shown in Fig. 3, compared to the semiconductor device 1, the semiconductor device 1a includes variable resistance circuits R11, R12, R21, and R22 as specific examples of the variable impedance circuits Z11, Z12, Z21, and Z22.

[0081] The variable resistance circuit R11 is configured to be able to change the resistance value of a signal line branched off from a signal line shared with the AD converter 12 among signal lines between the pin VREFH and the terminal VH1 of the AD converter 11 in response to a control signal from the control circuit 13. The variable resistance circuit R12 is configured to be able to change the resistance value of a signal line branched off from a signal line shared with the AD converter 12 among signal lines between the pin VREFL and the terminal VL1 of the AD converter 11 in response to a control signal from the control circuit 13. The variable resistance circuit R21 is configured to be able to change the resistance value of a signal line branched off from a signal line shared with the AD converter 11 among signal lines between the pin VREFH and the terminal VH1 of the AD converter 12 in response to a control signal from the control circuit 14. The variable resistance circuit R22 is configured to be able to change the resistance value of a signal line branched off from a signal line shared with the AD converter 11 among signal lines between the pin VREFL and the terminal VL1 of the AD converter 12 in response to a control signal from the control circuit 14.

[0082] The rest of the configuration of the semiconductor device 1a is similar to that of the semiconductor device 1, so a description thereof will be omitted.

[0083] Fig. 4 is a diagram for explaining a propagation path of interference noise generated in the semiconductor device 1a. Fig. 5 is a timing chart showing the operation of the semiconductor device 1a. Fig. 6 is a waveform diagram for explaining noise generated in the semiconductor device 1a.

[0084] It is generally known that in inductors such as the parasitic inductors L1 to L4, the impedance changes significantly due to a steep change in current.

[0085] Here, for example, assume that the AD converter 12 switches the capacitance of the successive approximation operation asynchronously with the AD converter 11. At this time, the current changes due to charging and discharging of electric charges caused by the switching of the capacitance at the terminals VH1 and VL1 of the AD converter 12 (terminals to which the reference voltages VREFH and VREFL are supplied). In particular, in the comparison operation for determining the value of the upper bit of the digital output signal OUT2, a large capacitance is switched, so that the current changes due to the charging and discharging of electric charges become steep. When this steep current change at the terminals VH1 and VL1 of the AD converter 12 is transmitted to the parasitic inductors L2 and L3, the impedance of the parasitic inductors L2 and L3 changes significantly. As a result, the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 11 also change significantly. In other words, the noise generated at the terminals VH1 and VL1 of the AD converter 12, which is the aggressor, is transmitted to the terminals VH1 and VL1 of the AD converter 11, which is the victim. As a result, the AD converter 11 cannot operate with high precision.

[0086] Therefore, in the comparison operation for determining the value of the upper bit of the output signal OUT2, in which the change in current accompanying the switching of the capacitance is steep and the interference noise is likely to be large, the semiconductor device 1a increases the resistance values ​​of the variable resistor circuits R21 and R22. This suppresses the change in the current flowing through the parasitic inductors L2 and L3, and reduces the change in the impedance of the parasitic inductors L2 and L3 (see FIG. 6). This suppresses the fluctuation of the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 11, respectively (see FIG. 6). In other words, the propagation of noise generated at the terminals VH1 and VL1 of the AD converter 12, which is the aggressor, to the terminals VH1 and VL1 of the AD converter 11, which is the victim, is suppressed.

[0087] However, since the resistance values ​​of the variable resistor circuits R21 and R22 are large, the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 12, which is the aggressor, fluctuate significantly due to an IR drop (see FIG. 6). This may cause a comparison error in the AD converter 12 in the comparison operation for determining the value of the upper bit of the output signal OUT2.

[0088] Therefore, in the semiconductor device 1a, in the comparison operation for determining the value of the lower bits (the remaining bits other than the upper bits in a predetermined range) of the output signal OUT2, in which the change in current accompanying the switching of the capacitance is gradual and the interference noise is small, and in the redundant comparison operation for re-determining one of the multiple bits representing the output signal OUT2, the resistance values ​​of the variable resistance circuits R21 and R22 are made lower than those in the comparison operation for determining the value of the upper bits. In the redundant comparison operation, among the comparison operations for determining the values ​​of the upper bits in a predetermined range including the most significant bit, a comparison is performed with a resolution equal to or higher than that of the comparison operation for determining the value of the lowest bit (a binary search weight equal to or lower than that). In other words, in the redundant comparison operation, a comparison is performed with a resolution equal to or higher than that of the comparison operation performed in a state in which the resistance values ​​of the variable resistance circuits R21 and R22 are set high.

[0089] This suppresses the IR drop caused by the variable resistance circuits R21 and R22, thereby suppressing the fluctuation of the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 12, which is the aggressor, respectively (see FIG. 6). This allows the AD converter 12 to accurately perform the comparison operation for determining the value of the lower bit and the redundant comparison operation.

[0090] In this embodiment, the case where AD converter 12 is the aggressor and AD converter 11 is the victim has been described as an example, but the same applies to the case where AD converter 11 is the aggressor and AD converter 12 is the victim.

[0091] That is, in the comparison operation for determining the value of the upper bit of the output signal OUT1, where the change in current accompanying the switching of the capacitance is steep and interference noise is likely to occur, the semiconductor device 1a increases the resistance values ​​of the variable resistor circuits R11 and R12 in order to suppress interference noise. Also, in the comparison operation for determining the value of the lower bit of the output signal OUT1 and the redundant comparison operation, where the change in current accompanying the switching of the capacitance is gradual and interference noise is unlikely to occur, the semiconductor device 1a sets the resistance values ​​of the variable resistor circuits R11 and R12 in the comparison operation for determining the value of the upper bit to be lower than that in the comparison operation for determining the value of the upper bit in order to suppress IR drop.

[0092] As a result, in the semiconductor device 1a, the AD converters 11 and 12 can operate with high precision while suppressing the propagation of interference noise. The control circuits 13 and 14 can appropriately change the resistance values ​​set by the variable resistance circuits R11, R12, R21, and R22, respectively, depending on the operating environment, etc.

[0093] Fig. 7 is a diagram for explaining the successive approximation operation of the AD converter provided in the semiconductor device 1a. In the example of Fig. 7, the AD converter 12 converts an analog input signal IN2 into a 4-bit digital output signal OUT2 and outputs it.

[0094] First, the AD converter 12 samples the input signal IN2 and holds the sampled input signal IN2.

[0095] Next, the AD converter 12 performs a successive comparison operation on the input signal IN2 while redistributing the charges stored in each of the multiple capacitive elements based on the potential of the input signal IN2 and reference voltages VREFH, VREFL (hereinafter collectively referred to as the reference voltage VREF) by switching the connections of the multiple capacitive elements using multiple switches.

[0096] In the initial state, the change in current accompanying the switching of capacitance is steep, and interference noise is likely to occur, so the variable resistor circuits R11, R12, R21, and R22 are set to high resistance values, thereby suppressing interference noise.

[0097] First, the AD converter 12 performs a comparison operation to determine the value of the most significant bit (MSB) of the 4 bits representing the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1000 in which the most significant bit is set to "1". When the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 7, since the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1".

[0098] Thereafter, the AD converter 12 switches the connection of the capacitance element by the switch to redistribute the charge, thereby performing a comparison operation to determine the value of the second most significant bit of the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1100 in which the second most significant bit is set to "1". If the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the second most significant bit of the output signal OUT2 is determined to be "1", and if the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1100, the second most significant bit of the output signal OUT2 is determined to be "0".

[0099] However, because the resistance values ​​of the variable resistor circuits R21 and R22 are high, the reference voltages VREFH and VREFL supplied to the AD converter 12 fluctuate greatly due to an IR drop. This may cause the AD converter 12 to make a comparison error due to a settling error. In the example of Fig. 7, even though the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the potential of the input signal IN2 is determined to be less than the DA-converted value of the digital value 4b'1100. Therefore, the second most significant bit of the output signal OUT2 is erroneously determined to be "0".

[0100] Thereafter, when the change in current accompanying the capacitance switching becomes gentle and interference noise is unlikely to occur, the variable resistance circuits R21 and R22 switch to a low resistance value. This suppresses the IR drop caused by the variable resistance circuits R21 and R22, thereby suppressing fluctuations in the reference voltages VREFH and VREFL supplied to the AD converter 12. This allows the AD converter 12 to accurately perform a comparison operation for determining the value of the lower bit and a redundant comparison operation.

[0101] Thereafter, the AD converter 12 switches the connection of the capacitance element by the switch to redistribute the charge, thereby performing a comparison operation to determine the value of the third most significant bit of the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA-converted value of the digital value 4b'1010 in which the third most significant bit is set to "1".

[0102] Thereafter, the AD converter 12 switches the connection of the capacitance element by a switch and redistributes the charge to perform a redundant comparison operation with the same resolution as the comparison operation for determining the value of the third most significant bit (at least the same or higher resolution (equal or lower binary search weight) as the comparison operation for determining the value of the second most significant bit). Specifically, when the AD converter 12 determines in the comparison operation for determining the value of the third most significant bit that the potential of the input signal IN2 is equal to or higher than the DA-converted value of the digital value to be compared, in the next redundant comparison operation, the AD converter 12 compares the potential of the input signal IN2 with the DA-converted value of the digital value obtained by adding 4'b0010 to the digital value to be compared. Also, when the AD converter 12 determines in the comparison operation for determining the value of the third most significant bit that the potential of the input signal IN2 is lower than the DA-converted value of the digital value to be compared, in the next redundant comparison operation, the AD converter 12 compares the potential of the input signal IN2 with the DA-converted value of the digital value obtained by subtracting 4'b0010 from the digital value to be compared.

[0103] In the example of Figure 7, in the comparison operation to determine the value of the third most significant bit of the output signal OUT2, the AD converter 12 determines that the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4'b1010, and therefore in the next redundant comparison operation, it compares the potential of the input signal IN2 with the digital value 4'b1100, which is the sum of the digital value 4'b1010 and 4'b0010.

[0104] 7, the potential of the input signal IN2 is determined to be equal to or greater than the DA-converted value of the digital value 4'b1100. Therefore, in the comparison operation for determining the value of the next least significant bit, the AD converter 62 compares the potential of the input signal IN2 with the digital value 4'b1101 obtained by adding 4'b0001 to the digital value 4'b1100. For example, when the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "1", and when the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0". In the example of FIG. 7, since the potential of the input signal IN2 is less than the DA-converted value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0".

[0105] As a result, the AD converter 12 performs AD conversion on the analog input signal IN2 and outputs the output signal OUT2 having the digital value 4b'1100.

[0106] In this way, in the comparison operation for determining the value of the upper bit of the output signal OUT1, where the change in current accompanying the switching of the capacitance is steep and interference noise is likely to occur, the semiconductor device 1a increases the resistance values ​​of the variable resistor circuits R11 and R12 in order to suppress interference noise. Also, in the comparison operation for determining the value of the lower bit of the output signal OUT1 and the redundant comparison operation, where the change in current accompanying the switching of the capacitance is gradual and interference noise is unlikely to occur, the semiconductor device 1a sets the resistance values ​​of the variable resistor circuits R11 and R12 in the comparison operation for determining the value of the upper bit to be lower than that in the comparison operation for determining the value of the upper bit in order to suppress IR drop.

[0107] In the comparison operation for determining the value of the upper bit of the output signal OUT2, in which the change in current accompanying the switching of the capacitance is steep and interference noise is likely to occur, the semiconductor device 1a increases the resistance values ​​of the variable resistor circuits R21 and R22 in order to suppress interference noise. In the comparison operation for determining the value of the lower bit of the output signal OUT2 and the redundant comparison operation, in which the change in current accompanying the switching of the capacitance is gradual and interference noise is unlikely to occur, the semiconductor device 1a sets the resistance values ​​of the variable resistor circuits R21 and R22 in the comparison operation for determining the value of the upper bit to be lower than that in the comparison operation for determining the value of the upper bit in order to suppress IR drop.

[0108] As a result, in the semiconductor device 1a, the AD converters 11 and 12 can operate with high precision while suppressing the propagation of interference noise.

[0109] <Embodiment 2> 8 is a block diagram showing a configuration example of a semiconductor device 2 according to embodiment 2. While the semiconductor device 1 includes two AD converters 11 and 12, the semiconductor device 2 includes one AD converter 11.

[0110] Specifically, the semiconductor device 2 includes an AD converter 11, a control circuit 13, and variable impedance circuits Z11 and Z12 on a chip 20. The semiconductor device 2 also includes at least pins AVCC, AVSS, VREFH, VREFL, INP1, INP2, and OUT1 that interface the chip 20 with the outside of the semiconductor device 2.

[0111] The configurations of the AD converter 11, the control circuit 13, and the variable impedance circuits Z11 and Z12 are similar to those of the semiconductor device 1, and therefore the description thereof will be omitted. Also, the connection relationships between the AD converter 11, the control circuit 13, and the variable impedance circuits Z11 and Z12 and each pin are similar to those of the semiconductor device 1, and therefore the description thereof will be omitted.

[0112] Here, a parasitic inductor L1 is formed in the signal line connected to the pin AVCC by a board substrate, a lead frame, a bonding wire, etc. (none of which are shown). Similarly, a parasitic inductor L2 is formed in the signal line connected to the pin VREFH. A parasitic inductor L3 is formed in the signal line connected to the pin VREFL. A parasitic inductor L4 is formed in the signal line connected to the pin AVSS.

[0113] (Specific example of semiconductor device 2) Fig. 9 is a diagram showing a semiconductor device 2a as a specific example of the semiconductor device 2. As shown in Fig. 9, compared to the semiconductor device 2, the semiconductor device 2a includes variable resistance circuits R11 and R12 as specific examples of the variable impedance circuits Z11 and Z12. Other configurations of the semiconductor device 2a are similar to those of the semiconductor device 2, and therefore description thereof will be omitted.

[0114] For example, suppose that the capacitance of the successive approximation operation is switched in the AD converter 11. At this time, the current changes at the terminals VH1 and VL1 of the AD converter 11 due to charging and discharging of electric charge caused by the switching of the capacitance. In particular, in the comparison operation for determining the value of the upper bit of the digital output signal OUT1, a large capacitance is switched, so that the change in current due to charging and discharging of electric charge becomes steep. When the steep change in current at the terminals VH1 and VL1 of the AD converter 11 is transmitted to the parasitic inductors L2 and L3, the impedance of the parasitic inductors L2 and L3 changes significantly. As a result, the noise generated in the signal line through which the reference voltages VREFH and VREFL are propagated becomes large. As a result, the noise is propagated to other circuits (not shown) that share the signal line through which the reference voltages VREFH and VREFL are propagated, and the other circuits cannot operate with high accuracy.

[0115] Therefore, in the semiconductor device 2a, in the comparison operation for determining the value of the upper bit of the output signal OUT1, where the change in current accompanying the switching of the capacitance is steep and interference noise is likely to occur, the resistance values ​​of the variable resistor circuits R11 and R12 are increased in order to suppress interference noise. Also, in the comparison operation for determining the value of the lower bit of the output signal OUT1 and the redundant comparison operation, where the change in current accompanying the switching of the capacitance is gradual and interference noise is unlikely to occur, the resistance values ​​of the variable resistor circuits R11 and R12 are lower in order to suppress IR drop than in the comparison operation for determining the value of the upper bit. As a result, in the semiconductor device 2a, the AD converter 11 can operate with high accuracy while suppressing the propagation of interference noise.

[0116] <Embodiment 3> 10 is a block diagram showing a configuration example of a semiconductor device 3 according to an embodiment 3. Compared to the semiconductor device 2, the semiconductor device 3 includes switches SW31 and SW32 instead of the variable impedance circuits Z11 and Z12.

[0117] The switch SW31 is provided between the pins VREFH and AVCC and the terminal VH1 of the AD converter 11, selects either the pin VREFH or the pin AVCC in response to a control signal from the control circuit 13, and connects it to the terminal VH1 of the AD converter 11. The switch SW32 is provided between the pins VREFL and AVSS and the terminal VL1 of the AD converter 11, selects either the pin VREFL or the pin AVSS in response to a control signal from the control circuit 13, and connects it to the terminal VL1 of the AD converter 11.

[0118] 11 is a timing chart showing the operation of the semiconductor device 3. First, in the comparison operation for determining the value of the upper bit of the output signal OUT1, in which the change in current accompanying the switching of the capacitance is steep and interference noise is likely to occur, the semiconductor device 3 connects the pins AVCC and AVSS to the terminals VH1 and VL1 of the AD converter 11 by the switches SW31 and SW32. Here, since the AD converter 11 is configured to perform AD conversion on the differential input signal IN1 based on the difference between the reference voltages VREFH and VREFL, the fluctuation rejection ratio of the power supply voltages AVCC and AVSS is high. Therefore, the propagation of noise generated in VH1 and VL1 of the AD converter 11 (i.e., interference noise) is suppressed.

[0119] In addition, in the comparison operation for determining the value of the lower bit of the output signal OUT1 and the redundant comparison operation, in which the change in current accompanying the switching of the capacitance is gradual and interference noise is unlikely to occur, the semiconductor device 3 connects the pins VREFH, VREFL to the terminals VH1, VL1 of the AD converter 11 by the switches SW31, SW32. This allows the AD converter 11 in the semiconductor device 3 to operate with high precision while suppressing the propagation of interference noise.

[0120] Similarly, the semiconductor device 1 may include switches SW31 and SW32 instead of the variable impedance circuits Z11 and Z12, and may include switches SW41 and SW42 instead of the variable impedance circuits Z21 and Z22. Fig. 12 is a block diagram showing a configuration example of the semiconductor device 3a. Compared to the semiconductor device 1, the semiconductor device 3a includes switches SW31 and SW32 instead of the variable impedance circuits Z11 and Z12, and switches SW41 and SW42 instead of the variable impedance circuits Z21 and Z22.

[0121] The switch SW41 is provided between the pins VREFH and AVCC and the terminal VH1 of the AD converter 12, selects either the pin VREFH or the pin AVCC in response to a control signal from the control circuit 14, and connects it to the terminal VH1 of the AD converter 12. The switch SW42 is provided between the pins VREFL and AVSS and the terminal VL1 of the AD converter 12, selects either the pin VREFL or the pin AVSS in response to a control signal from the control circuit 14, and connects it to the terminal VL1 of the AD converter 12.

[0122] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention.

[0123] Furthermore, in the present disclosure, a part or all of the processing of the semiconductor devices 1 to 3 can be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0124] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal. [Explanation of symbols]

[0125] 1,1a Semiconductor device 2,2a Semiconductor device 3. Semiconductor Devices 10 Chips 20 Chip 11. A / D Converter 12. A / D Converter 13 Control circuit 14 Control circuit L1~L4 Parasitic inductors R11, R12 variable resistor circuit R21, R22 variable resistor circuit SW11, SW12 Switches SW21, SW22 Switches SW31, SW32 Switches Z11, Z12 variable impedance circuit Z11_1~Z11_m Impedance Z12_1~Z12_m Impedance Z21, Z22 variable impedance circuit Z21_1~Z21_m Impedance Z22_1~Z22_m Impedance

Claims

1. a first AD converter of a successive approximation type of charge redistribution type, which includes a redundant comparison operation in a successive approximation operation, converts an analog differential first input signal into a digital first output signal using a reference voltage, and outputs the digital first output signal; a first variable impedance circuit provided on a signal line between a first pin to which the reference voltage is externally supplied and the first AD converter, the first variable impedance circuit being configured to be able to change impedance; a first control circuit that controls the impedance of the first variable impedance circuit in response to an operating state of the first AD converter; A semiconductor device comprising:

2. the first control circuit controls the impedance of the first variable impedance circuit to a first impedance when the first AD converter executes a comparison operation for determining a value of a higher-order bit in a first predetermined range among the multiple bits representing the first output signal, and controls the impedance of the first variable impedance circuit to a second impedance lower than the first impedance when the first AD converter executes a comparison operation for determining a value of a lower-order bit other than the higher-order bit in the first predetermined range among the multiple bits representing the first output signal and a first redundant comparison operation. The semiconductor device according to claim 1 .

3. the first AD converter is configured to execute the first redundant comparison operation with a resolution equal to or greater than a comparison operation for determining a value of the least significant bit of the most significant bits of the first predetermined range; The semiconductor device according to claim 2 .

4. The first AD converter is a first DA converter having a plurality of first capacitance elements and a plurality of first switches; A first comparator; a first successive approximation register circuit; having the first DA converter is configured to perform successive comparison between the potential of the first input signal and an output of the first DA converter using the first comparator and the first successive approximation register circuit while redistributing the charges stored in the plurality of first capacitance elements based on the potential of the first input signal and the reference voltage by switching connections of the plurality of first capacitance elements using the plurality of first switches; The semiconductor device according to claim 1 .

5. the first variable impedance circuit is a first variable resistance circuit configured to be able to change a resistance value; The semiconductor device according to claim 1 .

6. the first AD converter is driven by a power supply voltage; the first variable impedance circuit is a first selection circuit that selects either the first pin or a second pin to which the power supply voltage is supplied from an external source in accordance with an operating state of the first AD converter, and supplies the selected voltage as the reference voltage to the first AD converter; The semiconductor device according to claim 1 .

7. the first variable impedance circuit is configured to be able to select one of a plurality of paths through which a parasitic inductor is formed; The semiconductor device according to claim 6.

8. a second AD converter of a charge redistribution type successive approximation type, which includes a redundant comparison operation in the successive approximation operation, converts a second analog differential input signal into a second digital output signal using the reference voltage, and outputs the second digital output signal; a second variable impedance circuit provided on a signal line between the first pin to which the reference voltage is externally supplied and the second AD converter, the second variable impedance circuit being configured to be able to change impedance; a second control circuit that controls the impedance of the second variable impedance circuit in response to an operating state of the second AD converter; Further equipped with The semiconductor device according to claim 1 .

9. the first control circuit controls the impedance of the first variable impedance circuit to a first impedance when the first AD converter executes a comparison operation for determining a value of a higher-order bit within a first predetermined range among the multiple bits representing the first output signal, and controls the impedance of the first variable impedance circuit to a second impedance lower than the first impedance when the first AD converter executes a comparison operation for determining a value of a lower-order bit other than the higher-order bit within the first predetermined range among the multiple bits representing the first output signal and a first redundant comparison operation; the second control circuit controls the impedance of the second variable impedance circuit to a third impedance when the second AD converter executes a comparison operation for determining a value of a higher-order bit in a second predetermined range among the multiple bits representing the second output signal, and controls the impedance of the second variable impedance circuit to a fourth impedance lower than the third impedance when the second AD converter executes a comparison operation for determining a value of a lower-order bit other than the higher-order bit in the second predetermined range among the multiple bits representing the second output signal and a second redundant comparison operation. The semiconductor device according to claim 8.

10. the first AD converter is configured to execute the first redundant comparison operation with a resolution equal to or greater than a comparison operation for determining a value of the least significant bit of the most significant bits of the first predetermined range; the second AD converter is configured to execute the second redundant comparison operation with a resolution equal to or greater than a comparison operation for determining a value of the least significant bit of the higher order bits of the second predetermined range; The semiconductor device according to claim 9.

11. The first AD converter is a first DA converter having a plurality of first capacitance elements and a plurality of first switches; A first comparator; a first successive approximation register circuit; having the first DA converter is configured to perform successive comparison between the potential of the first input signal and an output of the first DA converter using the first comparator and the first successive approximation register circuit while redistributing charges stored in the plurality of first capacitance elements based on the potential of the first input signal and the reference voltage by switching connections of the plurality of first capacitance elements using the plurality of first switches; The second AD converter is a second DA converter having a plurality of second capacitive elements and a plurality of second switches; A second comparator; a second successive approximation register circuit; having the second DA converter is configured to perform successive comparison between the potential of the second input signal and an output of the second DA converter using the second comparator and the second successive approximation register circuit while redistributing the charges stored in the second capacitance elements based on the potential of the second input signal and the reference voltage by switching connections of the second capacitance elements using the second switches. The semiconductor device according to claim 8.

12. The first variable impedance circuit is a first variable resistance circuit configured to be able to change a resistance value, the second variable impedance circuit is a second variable resistance circuit configured to be able to change a resistance value; The semiconductor device according to claim 8.

13. the first AD converter is driven by a power supply voltage; the first variable impedance circuit is a first selection circuit that selects either the first pin or a second pin to which the power supply voltage is externally supplied in accordance with an operating state of the first AD converter, and supplies the selected voltage as the reference voltage to the first AD converter; the second AD converter is driven by the power supply voltage; the second variable impedance circuit is a second selection circuit that selects either the first pin or the second pin to which the power supply voltage is externally supplied in accordance with an operating state of the second AD converter, and supplies the selected voltage as the reference voltage to the second AD converter. The semiconductor device according to claim 8.

14. the first variable impedance circuit is configured to be able to select one of a plurality of paths through which a parasitic inductor is formed; the second variable impedance circuit is configured to be able to select one of the paths through which the plurality of parasitic inductors are formed. The semiconductor device according to claim 13.

15. a first AD converter of a successive approximation type of charge redistribution type, which includes a redundant comparison operation in a successive approximation operation, converts an analog differential first input signal into a digital first output signal using a reference voltage, and outputs the digital first output signal; a first variable impedance circuit provided on a signal line between a first pin to which the reference voltage is externally supplied and the first AD converter, the first variable impedance circuit being configured to be able to change impedance; a first control circuit that controls the impedance of the first variable impedance circuit in response to an operating state of the first AD converter; A method for controlling a semiconductor device, comprising: controlling the impedance of the first variable impedance circuit to a first impedance; performing a comparison operation in the first AD converter to determine a value of a first predetermined range of upper bits of a plurality of bits representing the first output signal; controlling the impedance of the first variable impedance circuit to a second impedance lower than the first impedance; a comparison operation for determining a value of lower bits other than the upper bits of the first predetermined range among the plurality of bits representing the first output signal, and a redundant comparison operation are performed in the first AD converter; A method for controlling a semiconductor device.

16. a first AD converter of a successive approximation type of charge redistribution type, which includes a redundant comparison operation in a successive approximation operation, converts an analog differential first input signal into a digital first output signal using a reference voltage, and outputs the digital first output signal; a first variable impedance circuit provided on a signal line between a first pin to which the reference voltage is externally supplied and the first AD converter, the first variable impedance circuit being configured to be able to change impedance; a first control circuit that controls the impedance of the first variable impedance circuit in response to an operating state of the first AD converter; A control program for causing a computer to execute a control process in a semiconductor device, comprising: A process of controlling an impedance of the first variable impedance circuit to a first impedance; a process of performing a comparison operation in the first AD converter to determine a value of a first predetermined range of upper bits of a plurality of bits representing the first output signal; A process of controlling an impedance of the first variable impedance circuit to a second impedance lower than the first impedance; a process of executing, in the first AD converter, a comparison operation for determining a value of lower bits other than the upper bits in the first predetermined range among a plurality of bits representing the first output signal, and a redundant comparison operation; A control program that causes a computer to execute the above.

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