Photodetection device and electronic apparatus

Abstract

To enhance a degree of freedom in arranging pixel transistors in a photoelectric conversion region.SOLUTION: A photodetection device comprises: a semiconductor layer having a first surface portion and a second surface portion that are positioned on mutually opposite sides in a thickness direction; a photoelectric conversion region that is provided on the semiconductor layer in a manner of being divided by a separation region extending in the thickness direction of the semiconductor layer, and that has an upper surface portion positioned on the first surface portion side of the semiconductor layer, and a first side surface portion positioned on the separation region side thereof; a transfer transistor that is provided on the upper surface portion side of the photoelectric conversion region and transfers, to a charge holding unit, a signal charge photoelectrically converted by a photoelectric conversion unit; and a plurality of pixel transistors provided on the upper surface portion of the photoelectric conversion region. At least one of the plurality of pixel transistors has a gate electrode that is provided on the separation region so as to be adjacent to the first side surface portion of the photoelectric conversion region across a gate insulating film.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and electronic device, and in particular to a technology that is effective when applied to a photodetector having pixel transistors provided in a photoelectric conversion region and electronic device including the same. [Background technology]

[0002] Photodetection devices such as solid-state imaging devices and distance measuring devices include a transfer transistor that transfers photoelectrically converted signal charges to a charge storage section, and a pixel circuit that outputs a pixel signal based on the signal charges stored in the charge storage section. Patent Document 1 discloses a solid-state imaging device in which a transfer transistor and a pixel transistor included in a pixel circuit are provided in a photoelectric conversion region of a semiconductor layer. Patent Document 1 also discloses a photoelectric conversion region partitioned by a trench-type isolation region.

[0003] On the other hand, Patent Document 2 discloses an imaging device in which a groove for shallow trench isolation (STI) is formed in a substrate, and a voltage is applied to a buried polysilicon electrode buried in this groove via an insulating film, thereby strengthening the pinning of the STI sidewall during accumulation, and the transfer of signal charges is improved during transfer by applying a voltage to a pixel area P-well and the buried polysilicon electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-101491 A [Patent Document 2] JP 2006-120804 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, in recent years, there has been a demand in the market for high-resolution image sensors, and the development of image sensors with reduced pixel sizes is underway.

[0006] However, as the pixel size is reduced, it becomes difficult to arrange active elements such as transfer transistors and pixel transistors in the photoelectric conversion region, and the degree of freedom in arranging the active elements decreases.

[0007] An object of the present technology is to provide a technology that enables an increase in the degree of freedom in arranging active elements in a photoelectric conversion region. [Means for solving the problem]

[0008] (1) A photodetector according to one aspect of the present disclosure, a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region extending in a thickness direction of the semiconductor layer. The photoelectric conversion region is an upper surface portion located on the first surface side of the semiconductor layer and a first side surface portion located on the separation region side; a transfer transistor provided on the upper surface side of the photoelectric conversion region and configured to transfer the signal charge photoelectrically converted by the photoelectric conversion portion to a charge holding portion; a plurality of pixel transistors provided on the upper surface of the photoelectric conversion region; It is equipped with: At least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

[0009] (2) A photodetector according to another aspect of the present technology, A semiconductor layer; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer; It is equipped with: The photoelectric conversion region is A top surface portion and a side surface portion; a charge holding section provided on the upper surface side and holding signal charges transferred from the photoelectric conversion section via a transfer transistor; A pixel transistor provided on the upper surface side; It is equipped with: In two photoelectric conversion regions adjacent to each other via the isolation region in a planar view, the pixel transistor provided in one of the photoelectric conversion regions has a gate electrode that is provided across the top surface portion and isolation region of one of the photoelectric conversion regions in a planar view, and is connected to the charge retention portion of the other photoelectric conversion region at the side portion of the other photoelectric conversion region.

[0010] (3) An electronic device according to another aspect of the present technology includes: The photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the detection device; a signal processing circuit for processing a signal output from the photodetector; It is equipped with: [Brief description of the drawings]

[0011] [Figure 1] 1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present technology. [Diagram 3] 1 is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to a first embodiment of the present technology. [Figure 4A] 2 is a plan view illustrating a schematic configuration example of four pixels included in the pixel array unit of FIG. 1. [Figure 4B] FIG. 4B is an enlarged plan view of a portion of FIG. 4A. [Figure 5A] 4B is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a4-a4 cutting line in FIG. 4A. [Figure 5B] FIG. 5B is an enlarged schematic longitudinal sectional view of a portion of FIG. 5A. [Figure 6]4B is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the b4-b4 cutting line in FIG. 4A. [Figure 7] 4B is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the c4-c4 cutting line in FIG. 4A. [Figure 8] 4B is a longitudinal sectional view showing a schematic enlarged view of a part of the longitudinal sectional structure taken along the d4-d4 cutting line in FIG. 4A. [Figure 9] 4B is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) that illustrates a process of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. [Figure 10] FIG. 10 is a diagram (a longitudinal sectional view taken along the same line a4-a4 in FIG. 4A) illustrating a step subsequent to the step in FIG. 9; [Figure 11] 11 is a diagram (a longitudinal sectional view taken along the same line a4-a4 in FIG. 4A) showing a step subsequent to the step in FIG. 10; FIG. [Figure 12] 12 is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) showing a process subsequent to FIG. 11. [Figure 13] 13 is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) showing a process subsequent to FIG. 12. [Figure 14] 14 is a diagram (a longitudinal sectional view taken along the same position as the b4-b4 cutting line in FIG. 4A) showing a process subsequent to FIG. 13. FIG. [Figure 15] 15 is a diagram (a longitudinal sectional view taken along the same position as the b4-b4 cutting line in FIG. 4A) showing a process subsequent to FIG. 14. [Figure 16] 16 is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) showing a step subsequent to FIG. 15. [Figure 17A] 17 is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) showing a step subsequent to FIG. 16. FIG. [Figure 17B] 17 is a diagram (a longitudinal sectional view taken along the same position as the b4-b4 cutting line in FIG. 4A) showing a step subsequent to FIG. 16. FIG. [Figure 18A] 17B is a diagram (a longitudinal sectional view taken along the same position as the a4-a4 cutting line in FIG. 4A) showing a process subsequent to FIG. 17A. [Figure 18B] 17B (a longitudinal sectional view taken along the same line b4-b4 in FIG. 4A). FIG. [Figure 19] 11 is a longitudinal sectional view illustrating a schematic view of a portion of a longitudinal sectional structure of a solid-state imaging device according to a second embodiment of the present technology. FIG. [Figure 20] 13 is a plan view illustrating a schematic configuration example of one pixel block in a solid-state imaging device according to a third embodiment of the present technology. FIG. [Figure 21] 21 is a longitudinal sectional view showing a schematic diagram of a part of the longitudinal sectional structure taken along the a20-a20 cutting line in FIG. 20. [Figure 22] 13 is a plan view diagrammatically illustrating a portion of a vertical cross-sectional structure of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. [Figure 23] 13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. [Figure 24] 24 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the a23-a23 cutting line in FIG. 23. [Diagram 25] 13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a sixth embodiment of the present technology. FIG. [Figure 26] 26 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the a25-a25 cutting line in FIG. 25. [Figure 27] 26 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the b25-b25 cutting line in FIG. 25. [Figure 28] 26 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the c25-c25 line in FIG. 25. [Figure 29] 26 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the d25-d25 line in FIG. 25. [Diagram 30] 13 is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit in a solid-state imaging device according to a seventh embodiment of the present technology. FIG. [Diagram 31]13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a seventh embodiment of the present technology. FIG. [Diagram 32] 31 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the a30-a30 cutting line in FIG. 30. [Diagram 33] 13 is an equivalent circuit diagram illustrating a configuration example of a pixel and a pixel circuit in a solid-state imaging device according to an eighth embodiment of the present technology. FIG. [Diagram 34] 13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to an eighth embodiment of the present technology. FIG. [Diagram 35] 34. FIG. 35 is a longitudinal sectional view showing a schematic enlarged view of a portion of the longitudinal sectional structure taken along the a34-a34 cutting line in FIG. [Diagram 36] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-1 according to an eighth embodiment of the present technology. [Figure 37] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-2 according to the eighth embodiment of the present technology. [Figure 38] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-3 according to the eighth embodiment of the present technology. [Figure 39] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-4 according to the eighth embodiment of the present technology. [Diagram 40] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-5 according to the eighth embodiment of the present technology. [Diagram 41] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-6 according to the eighth embodiment of the present technology. [Diagram 42] FIG. 13 is a longitudinal cross-sectional view of a main portion that illustrates a modified example 8-7 according to the eighth embodiment of the present technology. [Diagram 43] 13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a ninth embodiment of the present technology. FIG. [Diagram 44] 43. FIG. 44 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a43-a43 cutting line in FIG. [Diagram 45]16 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a tenth embodiment of the present technology. FIG. [Figure 46] 46 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a45-a45 cutting line in FIG. 45. [Figure 47] FIG. 23 is a diagram showing a configuration example of an electronic device according to an eleventh embodiment of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description.

[0013] In addition, the drawings may of course include parts with different dimensional relationships and ratios. In addition, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] In addition, the following embodiments are merely examples of devices and methods for embodying the technical ideas of the present technology, and are not intended to limit the configurations to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0016] In the following embodiment, among the three mutually orthogonal directions in space, a first direction and a second direction mutually orthogonal in the same plane are defined as an X direction and a Y direction, respectively, and a third direction perpendicular to each of the first direction and the second direction is defined as a Z direction. In the following embodiment, the thickness direction of a semiconductor layer 21 described later is described as the Z direction. In the following description, "planar view" refers to a view from a direction along the thickness direction of the semiconductor layer 21 described later. In addition, "thickness direction of the semiconductor layer" refers to a direction representing the thickness of the semiconductor layer 21.

[0017] [First embodiment] In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. In the first embodiment, a case will be described in which, among a plurality of pixel transistors included in a pixel circuit, the gate electrodes of the selection transistor and the reset transistor are provided in an isolation region.

[0018] <Overall configuration of solid-state imaging device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1, a solid-state imaging device 1A according to a first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig. 47, this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 focused on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0019] As shown in Fig. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a square pixel array section 2A provided in the center in a two-dimensional plane including mutually orthogonal X-direction and Y-direction, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally similar in a wafer state before the semiconductor wafer is diced. That is, the present technology is applicable in a semiconductor chip state and a semiconductor wafer state.

[0020] The pixel array section 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 47. In the pixel array section 2A, a plurality of pixels 3 (sensor pixels) are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other on the two-dimensional plane.

[0021] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0022] <Logic circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0023] The vertical drive circuit 4 shown in Fig. 2 is formed of, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A in the vertical direction row by row, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 11.

[0024] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion for removing fixed pattern noise specific to each pixel.

[0025] 2 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5 to select each of the column signal processing circuits 5 in turn, and causes each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to a horizontal signal line 12.

[0026] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signals. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, and the like.

[0027] 2 generates clock signals and control signals that serve as a reference for the operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0028] <Pixel block> The semiconductor chip 2 includes a pixel block 15 and a pixel circuit (readout circuit) 16 shown in FIG. As shown in Figures 3 and 4A, the pixel block 15 includes a plurality of pixels 3. The pixel block 15 of the first embodiment includes, for example, two pixels 3 (3a, 3b) arranged adjacent to each other in the X direction in a plan view as one unit, although this is not limited thereto. Fig. 3 mainly illustrates one pixel block 15, and Fig. 4A mainly illustrates two pixel blocks 15 arranged adjacent to each other in the Y direction, but the pixel blocks 15 are repeatedly arranged in each of the X direction and the Y direction to form the pixel array unit 2A shown in Fig. 1.

[0029] 3, two pixels 3a and 3b included in one pixel block 15 each have common components. Specifically, each of the two pixels 3a and 3b included in one pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD as a charge holding unit that holds (accumulates) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the two pixels 3a and 3b included in one pixel block 15 further includes a photoelectric conversion region 22 of the semiconductor layer 21 shown in Fig. 5A. Each of the photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR is provided in the photoelectric conversion region 22, as shown in Fig. 5A.

[0030] (Photoelectric conversion section) 3 is configured by, for example, a pn junction type photodiode (PD) and generates a signal charge according to the amount of received light. In addition, the photoelectric conversion unit 25 temporarily holds (accumulates) the generated signal charge.

[0031] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (eg, ground).

[0032] (transfer transistor) 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor driving line of the pixel driving line 10 shown in FIG.

[0033] (Floating diffusion region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0034] <Pixel circuit> As shown in FIG. 3, although not limited thereto, the pixel circuit 16 is provided for each pixel 3, and the input side thereof is electrically connected to the floating diffusion region FD.

[0035] Here, in the first embodiment, as an example, a circuit configuration is shown in which a pixel circuit 16 is assigned to each pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two pixels 3 (3a, 3b), or a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two or more pixels 3. A circuit configuration may also be used in which one pixel circuit 16 is assigned to multiple pixel blocks 15, each unit of which includes multiple pixels 3.

[0036] 4A, in the first embodiment, the pixel block 15 is configured such that two pixels 3a and 3b arranged adjacent to each other in the X direction form one unit, but the number of pixels 3 and the arrangement direction of the pixels 3 are not limited to those in the first embodiment. For example, the pixel block 15 may be configured such that four pixels 3 arranged two by two in each of the X and Y directions form one unit.

[0037] 3 has an input stage electrically connected to the floating diffusion region FD of the pixel 3. The pixel circuit 16 reads out the signal charge held in the floating diffusion region FD of the pixel 3, and outputs a pixel signal based on the read-out signal charge. In other words, the pixel circuit 16 converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charge, and outputs the pixel signal.

[0038] 3, the pixel circuit 16 includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as the pixel transistor Q. That is, the pixel circuit 16 of the first embodiment has a three-transistor configuration.

[0039] The pixel transistor Q (AMP, RST, SEL) and the transfer transistor TR described above are configured as insulated gate type field effect transistors, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) whose gate insulating film is made of silicon oxide (SiO2) film. In addition, these pixel transistors and transfer transistors TR may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of silicon nitride (Si3N4) film or a laminated film of silicon nitride film and silicon oxide film.

[0040] Of the pixel transistors Q (AMP, RST, SEL) included in the pixel circuit 16, the selection transistor SEL and the reset transistor RST mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0041] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD of the pixel 3 (photoelectric conversion region 22) and the source region of the reset transistor RST.

[0042] 3, the source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor driving line of the pixel driving line 10 shown in FIG.

[0043] 3, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the floating diffusion region FD of the pixel 3, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0044] The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0045] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0046] 3 resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd when the reset transistor RST is turned on. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 16.

[0047] The amplification transistor AMP shown in Fig. 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD, and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0048] During operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 25 of the pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charge held in the floating diffusion region FD is read out by the pixel circuit 16 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 16. A selection control signal for a horizontal line is provided to the gate electrode of the selection transistor SEL of the pixel circuit 16 from the vertical shift register. By setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. By setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.

[0049] Each of the photoelectric conversion unit 25, the transfer transistor TR, and the floating diffusion region FD shown in Fig. 3 is mounted on a semiconductor layer 21 (see Fig. 5A) described later. In addition, although not limited thereto, the pixel transistor Q (AMP, RST, SEL) included in the pixel circuit 16 in Fig. 3 is also mounted on, for example, the semiconductor layer 21.

[0050] As will be described in detail later, in this first embodiment, one reset transistor RST is shared by two pixels 3 (3a, 3b) included in one pixel block 15. Also, in this first embodiment, one selection transistor SEL is shared by two pixel blocks 15 aligned in the X direction.

[0051] <<Specific configuration of solid-state imaging device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4A to 8. FIG.

[0052] In order to make the drawing easier to see, a multilayer wiring layer 55, which will be described later, is omitted in Fig. 4A, and layers above a first wiring layer 57 included in the multilayer wiring layer 55 are omitted in Fig. 5A. In addition, while Fig. 1 illustrates the light incident surface side of the semiconductor chip 2, Fig. 4A is a plan view seen from the opposite side to the light incident surface side of the semiconductor chip 2 (the multilayer wiring layer side).

[0053] As shown in Figure 5A, the semiconductor chip 2 includes a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in the thickness direction (Z direction), an inter-pixel isolation region 31 as an isolation region extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 31.

[0054] As shown in FIG. 5A, the semiconductor chip 2 further includes a multi-layer wiring layer 55 provided on the first surface S1 side of the semiconductor layer 21. Moreover, the semiconductor chip 2 further includes, on the second surface S2 side of the semiconductor layer 21, a planarization film 61, an optical filter 63, and a microlens (on-chip lens) 64, which are provided in this order from the second surface S2 side.

[0055] Here, the first surface S1 of the semiconductor layer 21 may be referred to as a main surface or an element forming surface, and the second surface S2 may be referred to as a back surface. In the solid-state imaging device 1A according to the first embodiment, incident light incident from the second surface S2 side of the semiconductor layer 21 is photoelectrically converted by a photoelectric conversion section 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 may be referred to as a light incident surface.

[0056] In the first embodiment, the inter-pixel isolation region 31 corresponds to a specific but not limitative example of "isolation region" of the present technology.

[0057] As shown in Fig. 4A, two pixels 3 (3a, 3b) included in one pixel block 15 are arranged adjacent to each other in the X direction in a plan view. That is, in the pixel array section 2A shown in Fig. 1, pixel blocks 15, each of which has two pixels 3 (3a, 3b) as one unit, are repeatedly arranged in each of the X and Y directions.

[0058] <Planarization films, optical filters and microlenses> The planarization film 61 shown in FIG. 5A is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21 and planarize the second surface S2 side of the semiconductor layer 21.

[0059] 5A is provided for each pixel 3. The optical filter 63 separates the color of the incident light incident from the light incident surface side (the second surface portion S2 side) of the semiconductor chip 2. The microlens 64 collects the irradiated light and allows the collected light to efficiently enter the pixel 3.

[0060] <Semiconductor layer> 5A, the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, although not limited thereto, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21.

[0061] <Separation area> (Plane shape) 4A, the inter-pixel isolation region 31 includes a first planar portion 31x extending in the X direction in a plan view and a second planar portion 31y extending in the Y direction. The inter-pixel isolation region 31 further includes an intersection portion (intersection portion) where the first planar portion 31x and the second planar portion 31y intersect with each other on the same plane. In the first embodiment, the first planar portion 31x and the second planar portion 31y are, for example, perpendicular to each other.

[0062] The first planar portions 31x are repeatedly arranged at a predetermined interval in the Y direction. The second planar portions 31y are repeatedly arranged at a predetermined interval in the X direction. That is, the inter-pixel isolation region 31 has a lattice-like planar pattern in plan view.

[0063] 4A, the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. The inter-pixel isolation region 31 corresponding to one pixel block 15 has a composite planar pattern including a rectangular annular planar pattern surrounding the outer peripheries of two pixels 3a and 3b, and a planar pattern of a second planar portion 31y disposed between the two pixels 3a and 3b.

[0064] (Cross-sectional shape) 5A, the inter-pixel isolation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a plan view. The inter-pixel isolation region 31 is, for example, a carved type, a so-called trench type, in which a carved portion 33 is formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22.

[0065] The inter-pixel isolation region 31 includes, for example, but not limited to, a recessed portion 33 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, and an isolation insulating film 34 provided in the recessed portion 33. That is, the inter-pixel isolation region 31 extends across the first surface S1 and the second surface S2 of the semiconductor layer 21. The isolation insulating film 34 may be, for example, a silicon oxide film. In the first embodiment, the recessed portion 33 is filled with, for example, the isolation insulating film 34.

[0066] <Photoelectric conversion area> 4A and 4B, the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view, and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first planar portions 31x extending in the X direction and spaced apart in the Y direction, and two second planar portions 31y extending in the Y direction and spaced apart in the X direction, in the inter-pixel isolation region 31. The photoelectric conversion region 22 is partitioned by the first planar portion 31x and the second planar portion 31y, and is separated from other photoelectric conversion regions 22.

[0067] As shown in Figures 5A and 5B, the photoelectric conversion region 22 has an upper surface portion 22a located on the first surface portion S1 side of the semiconductor layer 21, and a first side surface portion (outer wall surface portion) 22b located on the inter-pixel isolation region 31 side. Moreover, the photoelectric conversion region 22 further includes the above-mentioned photoelectric conversion portion 25, a floating diffusion region FD, and a transfer transistor TR. Furthermore, as shown in Figures 4A to 5B, the photoelectric conversion region 22 further has an inter-element isolation region (field isolation region) 41 provided on the upper surface portion 22a side, and an island-shaped element formation region (active region) 43 partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31 and provided on the upper surface portion 22a side (the first surface portion S1 side of the semiconductor layer 21). Moreover, the photoelectric conversion region 22 further includes, as the pixel transistor Q included in the pixel circuit 16 described above, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The photoelectric conversion region 22 further includes a second side surface portion 22c that is located on the opposite side to the first side surface portion 22b in a plan view and that is adjacent to the element isolation region 41. Moreover, the photoelectric conversion region 22 further includes a p-type semiconductor region (well region) 23, an n-type semiconductor region 24, and a p-type power supply contact region WC (see FIG. 4B).

[0068] (p-type semiconductor region and n-type semiconductor region) 5A and 5B, the p-type semiconductor region 23 is provided over a wide area in the photoelectric conversion region 22, extending across the first face portion S1 side and the second face portion S2 side of the semiconductor layer 21. The p-type semiconductor region 23 contacts the inter-pixel isolation region 31 along the depth direction (Z direction) of the semiconductor layer 21.

[0069] 5A and 5B, the n-type semiconductor region 24 is provided in the p-type semiconductor region 23 in the photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type semiconductor region 23. The n-type semiconductor region 24 is separated from the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0070] (Photoelectric conversion section) 5A and 5B includes a p-type semiconductor region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a pn junction type photodiode (PD) including a pn junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0071] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface portion S2 side of the semiconductor layer 21 into a signal charge in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charge at the pn junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0072] (Floating diffusion region) 7, the floating diffusion region FD is provided in the p-type semiconductor region 23 on the first surface portion S1 side of the semiconductor layer 21 (the upper surface portion 22a side of the photoelectric conversion region 22). The floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view, and is separated from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type semiconductor region 23 is provided between the floating diffusion region FD and the n-type semiconductor region 24. The floating diffusion region FD also serves as a main electrode region 52r of the reset transistor RST described later, and is composed of an n-type semiconductor region.

[0073] (Isolation region and element formation region) 5A to 7, the element isolation region 41 is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The element isolation region 41 has, for example, but is not limited to, an STI (Shallow Trench Isolation) structure in which an isolation insulating film 42b is embedded inside a shallow groove portion 42a recessed from the first surface portion S1 to the second surface portion S2 side of the semiconductor layer 21.

[0074] As shown in FIG. 4B, the inter-element isolation region 41 has an island-like planar pattern separated from the inter-pixel isolation region 31 except for a part in a plan view, and defines an element formation region 43 together with the inter-pixel isolation region 31.

[0075] 5A to 7, the element formation region 43 is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. Then, as shown in Fig. 4B, the element formation region 43 is partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31, and has a planar pattern extending in a ribbon shape along the four sides of the photoelectric conversion region 22 in a planar view.

[0076] The planar patterns of the element formation region 43 are different between the two pixels 3a and 3b included in the pixel block 15. That is, as shown in Fig. 4B, in the two pixels 3a and 3b included in the pixel block 15, the planar pattern of the element formation region 43 in one pixel 3a and the planar pattern of the element formation region 43 in the other pixel 3b are inverted about the boundary between the pixels 3a and 3b arranged in the X direction.

[0077] (p-type power supply contact area) As shown in FIG. 4B, the p-type power supply contact region WC is provided on a corner side between two sides of the photoelectric conversion region 22 in a plan view. Although not shown in detail, the p-type power supply contact region WC is provided on a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, that is, on a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The p-type power supply contact region WC is provided in an island-shaped power supply region partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31 on the upper surface portion 22a side of the photoelectric conversion region 22. The p-type power supply contact region WC is composed of a p-type semiconductor region having a higher impurity concentration than the p-type semiconductor region 23. The p-type power supply contact region WC is connected to the p-type semiconductor region 23 and is electrically conductive.

[0078] A first reference potential of, for example, 0V is applied to this p-type power supply contact region WC as a reference potential within the semiconductor chip 2 (within the solid-state imaging device 1A) during operation, and the potential is fixed to this first reference potential.

[0079] (transfer transistor) As shown in Fig. 4B and Fig. 5B, the transfer transistor TR is provided on the first surface portion S1 side of the semiconductor layer 21, that is, on the upper surface portion 22a side of the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 47t provided on the upper surface portion 22a side of the photoelectric conversion region 22 across the inside and outside of the photoelectric conversion region 22, and a gate insulating film 46 provided between the gate electrode 47t and the semiconductor layer 21. The transfer transistor TR further has an n-type semiconductor region 24 functioning as a source region, an n-type floating diffusion region FD functioning as a drain region, and a p-type semiconductor region 23 functioning as a channel formation portion. The transfer transistor TR is, for example, configured as a vertical type, but is not limited thereto.

[0080] 5B, the gate electrode 47t of the transfer transistor TR has a head 47t1 provided on the outside of the first surface portion S1 of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween, and a leg portion 47r2 protruding from the head 47t1 into the semiconductor layer 21 and adjacent to the semiconductor layer 21 with the gate insulating film 46 interposed therebetween. The gate electrode 47t of the first embodiment is configured, for example, to have a T-shaped cross-sectional shape in which the width of the leg portion 47t2 is narrower than the width of the head portion 47t1, although this is not limited thereto.

[0081] A leg portion 47t2 of the gate electrode 47t is provided in the recessed portion 45a of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween, and the tip of the leg portion 47t2 extends into the n-type semiconductor region 24 with being insulated and isolated.

[0082] <Pixel transistor> 4B and 5B, a plurality of pixel transistors Q (AMP, SEL, RST) included in the pixel circuit 16 are provided in the element formation region 43. At least one pixel transistor Q of the plurality of pixel transistors Q has a gate electrode provided in the inter-pixel isolation region 31. In this first embodiment, of the three pixel transistors Q (AMP, SEL, RST), the gate electrodes 47s and 47r of the selection transistor SEL and the reset transistor RST are provided in the inter-pixel isolation region 31.

[0083] (Amplification transistor) As shown in FIG. 4B and FIG. 7, the amplifier transistor AMP has a gate electrode 47a provided on the upper surface portion 22a side of the photoelectric conversion region 22 (the first surface portion S1 side of the semiconductor layer 21) so as to overlap with the element formation region 43 (semiconductor layer 21) in a planar view, and a gate insulating film 46 interposed between the gate electrode 47a and the element formation region 43. The amplifier transistor AMP further has a pair of main electrode regions 52as and 52ar provided in the element formation region 43 on both sides in the gate length direction of the gate electrode 47a and functioning as a source region and a drain region. The amplifier transistor AMP further has a channel formation portion 53a (see FIG. 7) provided in the element formation region 43 so as to overlap with the gate electrode 47a in a planar view. The pair of main electrode regions 52as and 52ar are spaced apart from each other via the channel formation portion 53a. The pair of main electrode regions 52as and 52ar are formed of n-type semiconductor regions provided in the element formation region 43, and the channel formation portion 53a is formed of a p-type semiconductor region 23 provided in the element formation region 43.

[0084] (Reset transistor RST) As shown in FIG. 4B, FIG. 5B, FIG. 6, and FIG. 8, the reset transistor RST is provided on the inter-pixel isolation region 31 side between two photoelectric conversion regions 22 included in the pixel block 15. The reset transistor RST has a gate electrode 47r provided in the inter-pixel isolation region 31 adjacent to each other with the first side surface portion 22b of the photoelectric conversion region 22 and the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52r and 52ar provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47r in a plan view, and functioning as a source region and a drain region. The reset transistor RST further has a channel formation portion 53r provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47r in a plan view. The pair of main electrode regions 52as and 52ar are formed of n-type semiconductor regions, and the channel formation portion 53r is formed of a p-type semiconductor region 23.

[0085] The gate electrode 47r of the reset transistor RST is selectively provided in the inter-pixel isolation region 31 and is embedded in the inter-pixel isolation region 31, for example, although this is not limited to the first embodiment.

[0086] 4B and 5B, the reset transistor RST and the amplifying transistor AMP share a main electrode region 52as of the reset transistor RST and a main electrode region 52as of the amplifying transistor AMP, and are provided in series connection in the element formation region 43. And, as shown in Fig. 4B, 5B, and 8, in the reset transistor RST, one main electrode region 52r of a pair of main electrode regions 52r and 52ar is also used as a floating diffusion region FD.

[0087] 4B and 5B, the reset transistor RST is shared by two pixels 3a and 3b (two photoelectric conversion regions 22) included in the pixel block 15. The gate electrode 47r of the reset transistor RST is adjacent to each of the first side surface portions 22b of the two photoelectric conversion regions 22 adjacent to each other in a planar view, with the gate insulating film 46 interposed between them. That is, the reset transistor RST of the first embodiment has a gate electrode 47r provided in an inter-pixel isolation region 31 between the two photoelectric conversion regions 22 adjacent to each other in a planar view, and a pair of main electrode regions 52r, 52ar and a channel formation portion 53r provided in each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0088] (selection transistor SEL) As shown in Fig. 4B, Fig. 5B and Fig. 8, the selection transistor SEL is provided on the opposite side of the photoelectric conversion region 22 from the reset transistor TST side in a plan view. The selection transistor SEL has a gate electrode 47s provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52s and 52as provided on the upper surface portion 22a side of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47s in a plan view and functioning as a source region and a drain region. The selection transistor SEL further has a channel formation portion 53s provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47s in a plan view. The pair of main electrode regions 52s and 52as are formed of n-type semiconductor regions, and the channel formation portion 53s is formed of a p-type semiconductor region 23.

[0089] The gate electrode 47s of the selection transistor SEL is selectively provided in the inter-pixel isolation region 31 and is embedded in the inter-pixel isolation region 31, for example, although this is not limited to the first embodiment.

[0090] As shown in FIGS. 4B and 5B, the selection transistor SEL and the amplification transistor AMP share a main electrode region 52as of the selection transistor SEL and a main electrode region 52as of the amplification transistor AMP, and are provided in the element formation region 43 in series connection.

[0091] 4B and 5B, in two pixel blocks 15 aligned in the X direction, the selection transistor SEL is shared by the pixel 3a of one pixel block 15 and the pixel 3b of the other pixel block 15. In other words, in the two pixel blocks 15 aligned in the X direction, the selection transistor SEL is shared by the pixel circuit 16a assigned to the pixel 3a of one pixel block 15 and the pixel circuit 16b assigned to the pixel 3b of the other pixel block 15. The select transistor SEL has a gate electrode 47s adjacent to each of the first side surface portions 22b of the two photoelectric conversion regions 22 adjacent to each other in a planar view, with the gate insulating film 46 interposed therebetween. That is, the select transistor SEL of the first embodiment has a gate electrode 47s provided in an inter-pixel isolation region 31 between the two photoelectric conversion regions 22 adjacent to each other in a planar view, and a pair of main electrode regions 52s, 52as and a channel formation portion 53s provided in each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0092] (Channel forming part) As shown in FIG. 4B and FIG. 5B, the channel forming portions 53r, 53s of the reset transistor RST and the select transistor SEL are formed in the semiconductor layer 21 between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. That is, the reset transistor TRS and the select transistor SEL have the channel forming portions 53r, 53s between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. In other words, the reset transistor RST and the select transistor SEL have the channel forming portions 53r, 53s in the semiconductor layer 21 between the inter-pixel isolation region 31 and the inter-element isolation region 41. The thickness of the channel forming portions 53r, 53s in a plan view can be reduced by reducing the distance between the inter-pixel isolation region 31 and the inter-element isolation region 41. The thickness of the channel forming portions 53r, 53s is preferably less than 100 nm.

[0093] (Gate electrode material) The gate electrodes 47a, 47s, 47r, and 47t of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the transfer transistor TR are each made of, for example, a polycrystalline silicon film (doped polysilicon film) doped with an impurity that reduces the resistance value.

[0094] (Enhancement type) Each of the reset transistor RST and the selection transistor SEL can be configured as an enhancement type (normally off type) in which a drain current flows by applying a gate voltage equal to or higher than a threshold voltage to the gate electrodes 47r and 47s. Also, each of the reset transistor RST and the selection transistor SEL can be configured as a depletion type (normally on type) in which a drain current flows even if no voltage is applied to the gate electrodes 47r and 47s. In this first embodiment, the transistors are configured as, for example, enhancement types, although not limited thereto. In the case of the enhancement type, in each of the reset transistor RST and the selection transistor SEL, a channel (inversion layer) electrically connecting a pair of main electrode regions 52r (52s) and 52ar (52as) is formed (induced) in the channel formation portions 53r and 53s by a voltage applied to the gate electrodes 47r and 47s, and a current (drain current) flows from the drain region side (e.g., the main electrode region 52r, 52s side) through the channel of the channel formation portions 53r and 53s to the source region side (e.g., the main electrode region 52ar, 52as side). Similarly to the reset transistor RST and the selection transistor SEL, the amplification transistor AMP is also configured as, for example, an enhancement type.

[0095] ≪Multilayer wiring layer≫ As shown in FIG. 5A to FIG. 7, the multi-layer wiring layer 55 is provided on the first surface S1 side of the semiconductor layer 21. The multi-layer wiring layer 55 includes an interlayer insulating film 56 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the inter-element isolation region 41 and the element formation region 43, contact electrodes 57a, 57f, 57r, 57s, and 57t provided in the interlayer insulating film 56, and a first-layer wiring layer 58 provided on the opposite side of the interlayer insulating film 56 to the semiconductor layer 21 side. The first-layer wiring layer 58 includes wirings 58a, 58r, 58s, and 58t. The contact electrodes 57a, 57f, 57r, 57s, and 57t can be made of, for example, tungsten (W), a high-melting point metal. The first-layer wiring layer 58 can be made of, for example, a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly composed of Al or Cu. For example, a silicon oxide film can be used as the interlayer insulating film 56. The gate electrode 47t of the transfer transistor TR and the gate electrodes (47a, 47s, 47r) of each of the multiple pixel transistors Q (AMP, SEL, RST) are covered with the interlayer insulating film 56.

[0096] <Contact electrodes and wiring> As shown in Figures 5B and 7, the gate electrode 47t of the transfer transistor TR is electrically connected to a wiring 58t provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57t provided in the interlayer insulating film 56.

[0097] As shown in FIG. 5B, the gate electrode 47r of the reset transistor RST is electrically connected to a wiring 58r provided in the wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57r provided in the interlayer insulating film 56.

[0098] As shown in FIG. 5B, the gate electrode 47s of the selection transistor SEL is electrically connected to a wiring 58s provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57s provided in the interlayer insulating film 56.

[0099] As shown in FIG. 7, in two pixels 3a and 3a arranged in the Y direction, the gate electrode 47a of the amplification transistor AMP provided in the photoelectric conversion region 22 of one pixel 3a is electrically connected to a wiring 58a provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57a provided in the interlayer insulating film 56. The wiring 58a is electrically connected to a floating diffusion region FD (main electrode region 52r) provided in the photoelectric conversion region 22 of the other pixel 3a via a contact electrode 57f provided in the interlayer insulating film 56. That is, in two pixels 3a and 3a arranged in the Y direction, the gate electrode 47a of the amplification transistor AMP provided in one photoelectric conversion region 3a and the floating diffusion region FD (main electrode region 52r) provided in the other photoelectric conversion region 22 are electrically connected to each other via the contact electrode 57a, the wiring 58a, and the contact electrode 57f.

[0100] <Method for manufacturing solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described with reference to FIGS. In this first embodiment, the description will be focused on the manufacture of pixel transistors, which is included in the manufacturing method of the solid-state imaging device 1A.

[0101] 9 to 13, 16, 17A, and 18A are longitudinal sectional views each showing a schematic view of a part of the longitudinal sectional structure taken along the same position as the a4-a4 cutting line in FIG. 4A.

[0102] 14, 15, 17B, and 18B are longitudinal sectional views each showing a schematic view of a part of the longitudinal sectional structure taken along the same position as the b4-b4-cutting line in FIG. 4A.

[0103] First, as shown in Figure 9, a photoelectric conversion region 22 partitioned by an inter-pixel isolation region 31 is formed in a semiconductor layer 21, and an element formation region 43 partitioned by an inter-element isolation region 41 is formed on the upper surface portion 22a side of the photoelectric conversion region 22, which is the first surface portion S1 side of the semiconductor layer 21.

[0104] The photoelectric conversion region 22 has an upper surface portion 22a located on the first surface portion S1 side of the semiconductor layer 21, a first side surface portion 22b located on the inter-pixel isolation region 31 side, and a second side surface portion 22c located on the opposite side to the first side surface portion 22b in a planar view and adjacent to the inter-element isolation region 41.

[0105] The inter-pixel isolation region 31 can be formed by forming a recessed portion 33 extending in the thickness direction (Z direction) of the semiconductor layer 21 in the semiconductor layer 21, and then selectively filling the recessed portion 33 with an isolation insulating film 34. The inter-element isolation region 41 can be formed by forming a shallow groove portion 42a on the first surface portion S1 side of the semiconductor layer 21, and then selectively filling the shallow groove portion 42a with an isolation insulating film 42b. By forming the inter-pixel isolation region 31 and the inter-element isolation region 41, a photoelectric conversion region 22 is formed that is partitioned by the inter-pixel isolation region 31 and the inter-element isolation region 41 and has an upper surface portion 22a, a first side surface portion 22b and a second side surface portion 22c.

[0106] 10, dug portion 45a and dug portion 45b are formed to extend in the thickness direction (Z direction) of semiconductor layer 21. Dug portion 45a is for forming gate electrode 47t of transfer transistor TR, and is formed in the center of photoelectric conversion region 22 away from inter-pixel isolation region 31 in plan view. Dug portion 45b is for forming gate electrode of pixel transistor Q, and is formed in inter-pixel isolation region 31. In this first embodiment, dug portion 45b is formed in inter-pixel isolation region 31 in a first gate electrode formation portion where gate electrode 47r of reset transistor RST is formed, and in a second gate electrode formation portion where gate electrode 47s of select transistor SEL is formed. The dug portion 45a can be formed by selectively etching the semiconductor layer 21 using well-known photolithography and anisotropic dry etching techniques. The dug portion 45a can be formed by selectively etching the pixel isolation region 31 using well-known photolithography and anisotropic dry etching techniques. The dug portion 45a and the dug portion 45b are basically formed in separate steps, but either one may be formed first.

[0107] In this step, the dug portion 45a is formed so that the semiconductor layer 21 is exposed from the inner wall surface portion including the side wall surface portion and the bottom wall surface portion of the dug portion 45a. In this step, the dug portion 45b is formed so that the first side surface portion 22b of the photoelectric conversion region 22 is exposed from the side wall surface portion of the dug portion 45b.

[0108] In this step, since the depth of the dug portion 45a determines the length of the leg portion 42t2 of the gate electrode 42t in the transfer transistor TR, the dug portion 45a is preferably formed to a depth that allows its tip to penetrate into the n-type semiconductor region 24.

[0109] In this step, since the depth of the dug portion 45b defines the gate width of the gate electrodes 42r, 42s of the reset transistor RST and the select transistor SEL, the dug portion 45b is preferably formed to a depth of about 0.1 μm to 1 μm.

[0110] Next, the native oxide film and excess insulating film on the first surface portion S1 side of the semiconductor layer 21 and on the upper surface portion 22a side of the photoelectric conversion region 22 are removed by, for example, wet etching to expose the first surface portion S1 (upper surface portion 22a of the photoelectric conversion region 22) of the semiconductor layer 21, and then a gate insulating film 46 is formed as shown in Fig. 11. The gate insulating film 46 is formed on the upper surface portion 22a of the photoelectric conversion region 22 and the inner wall surface portion of the dug portion 45a, and is also formed on the first side surface portion 22b of the photoelectric conversion region 22 exposed inside the dug portion 45b. For example, a silicon oxide film can be used as the gate insulating film 46. The silicon oxide film can be formed by a thermal oxidation method or a deposition method, but in this first embodiment, a silicon oxide film by the thermal oxidation method is formed as the gate insulating film 46. The thermal oxidation method can form a silicon oxide film with better film quality than the deposition method.

[0111] 12, a gate electrode film 47 is formed. The gate electrode film 47 is formed on the first surface S1 side of the semiconductor layer 21 so as to fill the insides of the recesses 45a and 45b. The gate electrode film 47 may be a polycrystalline silicon film that can be formed by a CVD method.

[0112] Next, the gate electrode film 47 is patterned to form the gate electrodes 47t, 47r and 47s as shown in FIG. 13, and also form the gate electrode 47a (see FIG. 4B) although not shown.

[0113] In this process, the gate electrode 47t is formed in a T-shaped cross-sectional shape having a head 47t1 provided on the outside of the first surface portion S1 of the semiconductor layer 21 (outside the upper surface portion 22a of the photoelectric conversion region 22) with the gate insulating film 46 interposed therebetween, and a leg portion 47t2 protruding from the head 47a1 into the recessed portion 45a of the semiconductor layer 21 and adjacent to the semiconductor layer 21 with the gate insulating film 46 interposed therebetween.

[0114] Also, in this process, each of the gate electrodes 47r and 47s is formed to have a T-shaped cross-sectional shape having a head 47r1, 47s1 provided outside the first surface portion S1 of the semiconductor layer 21 (outside the upper surface portion 22a of the photoelectric conversion region 22) with the gate insulating film 46 interposed therebetween, and leg portions 47r2, 47s2 protruding from the head 47r1, 47s1 into the recessed portion 45b of the semiconductor layer 21 and provided in the inter-pixel isolation region 31 adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. In this step, the gate electrode 47a is formed on the element formation region 43 with the gate insulating film 46 therebetween.

[0115] 14, a dug portion 51 is formed in the inter-pixel isolation region 31. Although not shown in detail, the dug portion 51 is formed along the periphery of the photoelectric conversion region 22 except for the regions of the gate electrodes 47r and 47s in a plan view.

[0116] In this step, the depth of the recessed portion 51 defines the depth of the pair of main electrode regions of the pixel transistor Q (AMP, SEL, RST), and therefore is preferably formed to a depth of about 0.1 μm to 1 μm.

[0117] Furthermore, in this process, it is preferable that the recess 51 is formed so that the isolation insulating film 34 remains with a thin film thickness on the first side portion 22b of the photoelectric conversion region 22, in other words, so that the first side portion 22b of the photoelectric conversion region 22 is covered with the isolation insulating film 34 with a thin film thickness.

[0118] Next, referring to Figures 15 and 4B, as shown in Figures 15 and 4B, main electrode regions 52as, 52ar, 52r and 52s made of n-type semiconductor regions are formed in the element formation region 43 of the photoelectric conversion region 22. Specifically, each of the main electrode regions 52as, 52ar, 52r, and 52s is formed by injecting impurity ions into the element formation region 43 from the upper surface portion 22a of the photoelectric conversion region 22 shown in FIG. 15 and from the first side surface portion 22b of the photoelectric conversion region 22 through the recessed portion 51 shown in FIG. 15, and then performing a heat treatment to activate the injected impurity ions. The impurity ions are injected using the inter-pixel isolation region 31, the inter-element isolation region 41, and the gate electrodes 47a, 47r, and 47s as masks. The impurity ions are injected in a state in which the injection direction is inclined with respect to the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22. The impurity ions may be, for example, phosphorus (P + ) and arsenic (As + ) can be used.

[0119] 4B and 7, this process forms a channel formation portion 53a in the semiconductor layer 21 between the main electrode regions 52as and 52ar and overlapping with the gate electrode 47a in a plan view. Then, an amplification transistor AMP is formed having the gate insulating film 46, the gate electrode 47a, the pair of main electrode regions 52as, 52ar, and the channel formation portion 53a.

[0120] 4B, 5B and 8, this process forms a channel formation portion 53r adjacent to the gate electrode 47r with the gate insulating film 46 interposed therebetween in the semiconductor layer 21 between the main electrode regions 52r and 52ar and between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. Then, a reset transistor RST is formed, which has the gate insulating film 46, the gate electrode 47r, the pair of main electrode regions 52r, 52ar, and the channel formation portion 53r.

[0121] 4B and 5B, a channel formation portion 53r adjacent to the gate electrode 47r with the gate insulating film 46 interposed therebetween is formed in the semiconductor layer 21 between the main electrode regions 52s and 52as and between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22 by this process. Then, a reset transistor RST is formed, which has the gate insulating film 46, the gate electrode 47r, the pair of main electrode regions 52r and 52ar, and the channel formation portion 53r.

[0122] Next, the head portions 47r1, 47s1 of the gate electrodes 47r and 47s are selectively removed to form the gate electrodes 47r and 47s buried in the inter-pixel isolation region 31 as shown in FIG.

[0123] 17A and 17B, an interlayer insulating film 56 is formed on the first surface S1 side of the semiconductor layer 21. The interlayer insulating film 56 is formed to cover the inter-element isolation region 41 and the element formation region 43, as well as to cover the gate electrode 47t of the transfer transistor TR and the gate electrodes 47a, 47s, and 47r of each of the pixel transistors Q (AMP, SEL, and RST), and to fill the recessed portion 51. A silicon oxide film that can be formed by a CVD method can be used as the interlayer insulating film 56.

[0124] Next, as shown in Figures 18A and 18B, contact electrodes 57t, 57a, 57r, and 57s are formed in the interlayer insulating film 56, and also a contact electrode 57f (not shown) is formed. Thereafter, wirings 58t, 58a, 58s, and 58r are formed on the interlayer insulating film 56, thereby resulting in the state shown in Figures 5A to 7.

[0125] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. As shown in FIG. 4A and FIG. 5B, in the solid-state imaging device 1A according to the first embodiment, among the pixel transistors Q (AMP, RST, SEL) included in the pixel circuit, the reset transistor RSE and the selection transistor SEL each have a gate electrode 47r, 47s provided in the inter-pixel isolation region 31 adjacent to each other with the first side portion 22b of the photoelectric conversion region 22 and the gate insulating film 46 interposed therebetween. Therefore, compared with the case where the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL are arranged in the photoelectric conversion region 22, the area occupied by each of the reset transistor RST and the selection transistor SEL in the photoelectric conversion region 22 can be reduced, and the degree of freedom (layout freedom) of arranging the active elements including the pixel transistors Q (AMP, RST, SEL) and the transfer transistor TR in the photoelectric conversion region 22 can be increased. Therefore, according to the solid-state imaging device 1A according to the first embodiment, the degree of freedom of arranging the active elements in the photoelectric conversion region 22 can be increased.

[0126] Furthermore, since the area occupied by each of the reset transistor RST and the selection transistor SEL in the photoelectric conversion region 22 can be reduced, the photoelectric conversion region 22 can be miniaturized without miniaturizing the pixel transistor Q provided in the photoelectric conversion region 22. This makes it possible to miniaturize the photoelectric conversion region 22 while suppressing characteristic deterioration associated with miniaturization of the pixel transistor Q provided in the photoelectric conversion region 22.

[0127] Furthermore, the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL are provided in the inter-pixel isolation region 31 adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. This makes it possible to widen the gate width Wg of the gate electrodes 47r, 47s in the thickness direction (Z direction) of the semiconductor layer 21, thereby improving the mutual conductance (gm) without expanding the planar size of each of the reset transistor RST and the selection transistor SEL.

[0128] Moreover, the pair of main electrode regions 52r and 52ar of the reset transistor RST and the pair of main electrode regions 52s and 52as of the select transistor SEL are provided on the upper surface portion 22a side (the first surface portion S1 side of the semiconductor layer 21) of the photoelectric conversion region 22, spaced apart from each other along the sides (edges) of the photoelectric conversion region 22 in a plan view. This makes it possible to easily electrically connect the pair of main electrode regions 52r, 52ar of the reset transistor RST to the wiring of the multilayer wiring layer 55, and also to easily electrically connect the pair of main electrode regions 52s, 52as of the select transistor SEL to the wiring of the multilayer wiring layer 55, thereby increasing the degree of freedom in routing the wiring in the multilayer wiring layer 55.

[0129] In addition, the main electrode region 52ra of the reset transistor RST and the main electrode region 52ar of the amplifier transistor AMP are shared. In addition, the main electrode region 52as of the selection transistor SEL and the main electrode region 52as of the amplifier transistor AMP are shared. In addition, the floating diffusion region FD is also used as the main electrode region 52r of the transfer transistor TR. Therefore, the planar size of the photoelectric conversion region 22 can be reduced, and the number of pixels in the pixel array section 1A can be increased without increasing the planar size of the pixel array section 1A. In recent years, image sensors capable of high resolution have been in demand in the market, and this can contribute to increasing the resolution of image sensors.

[0130] The photoelectric conversion region 22 has a first side portion 22b on the inter-pixel isolation region 31 side and a second side portion 22c located on the opposite side to the first side portion 22b and adjacent to the inter-element isolation region 41. The reset transistor RST and the select transistor SEL each have a channel forming portion 53r, 53s between the first side portion 22b and the second side portion 22c of the photoelectric conversion region 22. This makes it possible to easily adjust the thickness of the channel forming portion 53r, 53s in the planar direction by the distance between the inter-pixel isolation region 31 and the inter-element isolation region 41, and to make the channel forming portion 53r, 53s thinner (thinner). This makes it possible to prevent the depletion layer from almost extending from the main electrode regions 52r, 52ar, 52s, 52as that function as the source region and the drain region, so that the short channel effect can be reduced in each of the reset transistor RST and the select transistor SEL, and the back bias effect from the semiconductor layer 21 can also be reduced. As a result, the transistor characteristics of each of the reset transistor RST and the selection transistor SEL can be improved.

[0131] In addition, in two photoelectric conversion regions 22 (pixels 3) arranged side by side in the Y direction in plan view, the floating diffusion region FD of one photoelectric conversion region 22 and the amplification transistor AMP of the other photoelectric conversion region 22 are arranged adjacent to each other, thereby shortening the conductive path electrically connecting the floating diffusion region FD of one photoelectric conversion region 22 and the gate electrode 47a of the amplification transistor AMP of the other photoelectric conversion region 22, and reducing the wiring capacitance added to the floating diffusion region FD. As a result, the conversion efficiency can be increased and the random noise characteristics can be improved.

[0132] Here, in the amplification transistor AMP, defects at the interface of the gate insulating film 46 affect random noise. Since there are fewer defects at the interface of the gate insulating film 46 on the upper surface portion 22a side than on the second side surface portion 22c side of the photoelectric conversion region 22, it is preferable to provide the gate insulating film 46 on the upper surface portion side of the photoelectric conversion region in the amplification transistor AMP.

[0133] <Modification of the First Embodiment> In the above-described first embodiment, the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL are provided in the inter-pixel isolation region 31. However, the present technology is not limited to the above-described first embodiment.

[0134] For example, the gate electrode 47a of the amplification transistor AMP may be provided in the inter-pixel isolation region 31. That is, in the present technology, the gate electrode of at least one of the multiple pixel transistors Q included in the pixel circuit 16 is provided in the inter-pixel isolation region 31.

[0135] In the above-described first embodiment, the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL are embedded in the inter-pixel isolation region 31, but the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL may be configured so that a portion of each of them overlaps with the inter-pixel isolation region 31 and the other portion is embedded in the inter-pixel isolation region 31. In other words, the gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL may be configured to extend from the inside to the outside of the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21.

[0136] Second Embodiment As shown in FIG. 19, the solid-state imaging device 1B according to the second embodiment of the present technology is basically configured similarly to the solid-state imaging device 1A according to the first embodiment described above, except for the configuration of the inter-pixel isolation region.

[0137] That is, as shown in Figures 5A and 5B, the inter-pixel isolation region 31 of the first embodiment described above is composed of one vertical portion extending linearly across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21.

[0138] In contrast, as shown in FIG. 19, the inter-pixel isolation region 31B of the second embodiment has a stepped structure including a first vertical portion 31b1 provided on the first surface portion S1 side of the semiconductor layer 21, a second vertical portion 31b2 extending from this first vertical portion 31b1 toward the second surface portion S2 side of the semiconductor layer 21 and having a width narrower than that of the first vertical portion 31b1, and a step portion 31bz formed by the difference between the width of the first vertical portion 31b1 and the width of the second vertical portion 31b2.

[0139] The gate electrodes 47r, 47s of the reset transistor RST and the selection transistor SEL are embedded in the first vertical portion 31b1 of the inter-pixel isolation region 31B. The gate electrodes 47r and 47s are adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0140] This inter-pixel isolation region 31B can be formed, for example, by forming a shallow groove portion on the first surface S1 side of the semiconductor layer 21, then forming a recessed portion extending from the bottom surface of the shallow groove portion toward the second surface S2 side of the semiconductor layer 21, and then selectively embedding an isolation insulating film 34 in the recessed portion and the shallow groove portion.

[0141] In addition, this inter-pixel isolation region 31B can be formed, for example, by forming a recessed portion extending from the first face portion S1 side of the semiconductor layer 21 toward the second face portion S2 side, selectively embedding the isolation insulating film 34 in this recessed portion, selectively etching the semiconductor layer 21 in the area overlapping the recessed portion in which the isolation insulating film 34 is embedded on the first face portion S1 side of the semiconductor layer 21 and its surrounding area to form a shallow groove portion, and then selectively embedding the isolation insulating film in this shallow groove portion.

[0142] The present technology can also be applied to the inter-pixel isolation region 31B of the second embodiment. Moreover, by applying the present technology, the solid-state imaging device 1B according to the second embodiment can also obtain the same effects as the solid-state imaging device 1A according to the above-described first embodiment. Furthermore, in the case of the inter-pixel isolation region 31B of the second embodiment, the volume of the n-type semiconductor region 24 can be increased compared to the inter-pixel isolation region 31 of the first embodiment described above, and therefore the saturation signal amount Qs can be further improved.

[0143] Third Embodiment As shown in Figures 20 and 21, the solid-state imaging device 1C of the third embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, except for the configurations of the gate electrodes of the reset transistor RST and the selection transistor SEL.

[0144] That is, as shown in Figures 20 and 21, the reset transistor RST and the selection transistor SEL of the third embodiment include gate electrodes 71r and 71s instead of the gate electrodes 47r and 47s of the first embodiment shown in Figures 4B and 5B. The other configurations are generally similar to those of the first embodiment.

[0145] As shown in FIGS. 20 and 21, the gate electrode 71r of the reset transistor RST is provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0146] Specifically, the gate electrode 71r has a head 71r1 extending across the photoelectric conversion region 22 and the inter-pixel isolation region 31 outside the first surface portion S1 of the semiconductor layer 21 in a plan view, and a leg portion 71r2 protruding from the head 71r1 toward the inter-pixel isolation region 31 and adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. The gate insulating film 46 is provided between the head 71r1 and an upper surface portion 22a of the photoelectric conversion region 22.

[0147] 20 and 21, similar to the gate electrode 71r, the gate electrode 71s of the selection transistor SEL is also provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with a gate insulating film 46 interposed therebetween.

[0148] Specifically, like the gate electrode 71r, the gate electrode 71s has a head 71s1 extending across the photoelectric conversion region 22 and the inter-pixel isolation region 31 in a plan view outside the first surface portion S1 of the semiconductor layer 21, and a leg portion 71s2 protruding from the head 71s1 toward the inter-pixel isolation region 31 and adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. The gate insulating film 46 is also provided between the head 71s1 and an upper surface portion 22a of the photoelectric conversion region 22.

[0149] In the third embodiment, the gate electrodes 71r, 71s of the reset transistor RST and the select transistor SEL are, like the gate electrode 47r of the transfer transistor TR, such that the width of the heads 71r1, 71s1 is wider than the width of the leg portions 71r2, 71r2, and the cross-sectional shape is T-shaped.

[0150] The solid-state imaging device 1C according to the third embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0151] Furthermore, the gate electrodes 71r, 71s of the reset transistor RST and the select transistor SEL in this third embodiment are provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, so that the gate width Wg of the gate electrodes 71r, 71s can be made wider than in the first embodiment.

[0152] In the third embodiment, a case has been described in which the present technology is applied to each of the reset transistor RST and the selection transistor SEL, but the present technology can also be applied to the amplification transistor AMP.

[0153] [Fourth embodiment] As shown in FIG. 22, the solid-state imaging device 1D according to the fourth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A according to the first embodiment described above, except for the configurations of the gate electrodes of the reset transistor RST and the selection transistor SEL.

[0154] That is, as shown in Fig. 22, the reset transistor RST and the selection transistor SEL of the fourth embodiment include gate electrodes 72r and 72s instead of the gate electrodes 47r and 47s of the first embodiment shown in Fig. 4B and Fig. 5B. The other configurations are generally similar to those of the first embodiment.

[0155] As shown in FIG. 22, the gate electrode 72r of the reset transistor RST is provided across the upper surface portion 22a, the first side surface portion 22b, and the second side surface portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0156] Specifically, the gate electrode 72r has a head 72r1 located outside the first surface portion S1 of the semiconductor layer 21 and extending across the inter-pixel isolation region 31 and the inter-element isolation region 41 across the upper surface portion 22a (element formation region 43) of the photoelectric conversion region 22 in a plan view, a first leg portion 72r2 protruding from the head 72r1 toward the inter-pixel isolation region 31 and adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a second leg portion 72r3 protruding from the head 72r1 toward the inter-element isolation region 41 and adjacent to the second side surface portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. The gate insulating film 46 is provided between the head 72r1 and the upper surface portion 22a of the photoelectric conversion region 22. Also in the fourth embodiment, the reset transistor RST is shared by two pixels 3a and 3b arranged adjacent to each other in the X direction, and therefore the gate electrode 72r has two second leg portions 72r3 for one head portion 72r1.

[0157] As shown in FIG. 22, the gate electrode 72s of the select transistor SEL, like the gate electrode 72r of the reset transistor RST, is provided across the upper surface portion 22a, the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22, with a gate insulating film 46 interposed therebetween.

[0158] Specifically, the gate electrode 72s has a head 72s1 that is provided outside the first surface portion S1 of the semiconductor layer 21 and extends across the inter-pixel isolation region 31 and the inter-element isolation region 41 across the upper surface portion 22a of the photoelectric conversion region 22 in a plan view, a first leg portion 72s2 that protrudes from the head 72s1 toward the inter-pixel isolation region 31 and is adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a second leg portion 72r3 that protrudes from the head 72sr1 toward the inter-element isolation region 41 and is adjacent to the second side surface portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. The gate insulating film 46 is provided between the head 72r1 and the upper surface portion 22a of the photoelectric conversion region 22. Also in this fourth embodiment, in two pixel blocks 15 arranged adjacent to each other in the X-direction, the select transistor SEL is shared between the pixel 3b of one pixel block 15 and the pixel 3a of the other pixel block 15, and therefore the gate electrode 72s also has two second leg portions 72s3 for one head portion 72s1.

[0159] The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0160] Furthermore, the gate electrodes 72r, 72s of the reset transistor RST and the select transistor SEL in this fourth embodiment are provided across the upper surface portion 22a, the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, so that the gate width Wg of the gate electrodes 72r, 72s can be made wider than in the third embodiment.

[0161] In the fourth embodiment, a case has been described in which the present technology is applied to each of the reset transistor RST and the selection transistor SEL, but the present technology can also be applied to the amplification transistor AMP.

[0162] Fifth embodiment As shown in Figures 23 and 24, the solid-state imaging device 1E according to the fifth embodiment of the present technology is basically configured similarly to the solid-state imaging device 1A according to the first embodiment described above, except for the configuration of the amplification transistor AMP.

[0163] That is, as shown in FIGS. 23 and 24, in the amplification transistor AMP of the fifth embodiment, a gate electrode 47a is provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 adjacent to each other in the Y direction in plan view.

[0164] Specifically, the amplification transistor AMP of the fifth embodiment has a gate electrode 47a provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52as and 52ar provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47a in a plan view and functioning as a source region and a drain region. The amplification transistor AMP further has a channel formation portion 53a provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47a in a plan view. The pair of main electrode regions 52as and 52ar are formed of n-type semiconductor regions, and the channel formation portion 53r is formed of a p-type semiconductor region 23.

[0165] The amplification transistor AMP of this fifth embodiment has a gate electrode 47a that is connected to the floating diffusion region FD of one of the photoelectric conversion regions 22 adjacent to each other in two photoelectric conversion regions 22 arranged in the Y direction with the inter-pixel isolation region 31 in a planar view, and is adjacent to the first side portion 22b of the other photoelectric conversion region 22 with a gate insulating film 46 interposed therebetween and provided in the inter-pixel isolation region 31.

[0166] The solid-state imaging device 1E according to the fifth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0167] In addition, in the amplification transistor AMP of the fifth embodiment, the gate electrode 47a is connected to the floating diffusion region FD so as to be adjacent to each other in a plan view. Therefore, the gate electrode 47a and the floating diffusion region FD can be electrically connected at the shortest distance, and the wiring capacitance added to the floating diffusion region FD can be reduced compared to the case where the gate electrode 47a and the floating diffusion region FD are electrically connected via the wiring of the multi-layer wiring layer 55. This can increase the conversion efficiency and reduce random noise.

[0168] Sixth Embodiment 25 to 29, the solid-state imaging device 1F according to the sixth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the amplifying transistor AMP. In addition, the solid-state imaging device 1F according to the sixth embodiment of the present technology further includes relay conductors 74a and 74b provided in the inter-pixel isolation region 31.

[0169] <Gate electrode> 25 and 26, the amplification transistor AMP of the sixth embodiment includes a gate electrode 73a instead of the gate electrode 47a of the first embodiment shown in Fig. 4A and 7. The other configurations are generally similar to those of the first embodiment.

[0170] As shown in Figures 25 and 26, in two photoelectric conversion regions 22 that are adjacent to each other and lined up in the Y direction with an inter-pixel isolation region 31 interposed therebetween in a planar view, the amplification transistor AMP provided in one of the photoelectric conversion regions 22 has a gate electrode 73a that is provided across the upper surface portion 22a of one of the photoelectric conversion regions 22 and the inter-pixel isolation region 31 in a planar view, and is electrically and mechanically connected to a floating diffusion region FD provided in the other photoelectric conversion region 22 at a first side portion 22b of the other photoelectric conversion region 22.

[0171] 25 and 26, the gate electrode 73a of the amplification transistor AMP according to the sixth embodiment has a head 73a1 extending from the first surface portion S1 of the semiconductor layer 21 to one of the photoelectric conversion regions 22 and the inter-pixel isolation region 31 in a plan view, and a relay protrusion 73a3 protruding from the head 73a1 toward the inter-pixel isolation region 31 and electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. A gate insulating film 46 is interposed between the head 73a1 and the upper surface portion 22a of the one photoelectric conversion region 22. The relay protrusion 73a3 is embedded in the inter-pixel isolation region 31.

[0172] <Relay conductor section> 25, 27, and 29, the relay conductor 74a is provided in the inter-pixel separation region 31 between two photoelectric conversion regions 22 included in one pixel block 15. The relay conductor 74a is electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in one of the two photoelectric conversion regions 22 included in one pixel block 15 at the first side surface portion 22b of one of the photoelectric conversion regions 22, and is also electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. That is, the relay conductor 74a is electrically and mechanically connected to the main electrode region 52ar of each of the two amplifier transistors AMP adjacent to each other across the inter-pixel separation region 31 at the first side surface portion 22b of each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0173] 27 and 29, the relay conductor 74a is embedded in the inter-pixel isolation region 31, penetrates the inter-pixel isolation region 31 in the X direction, and is connected to the first side surface portions 22b of each of the two photoelectric conversion regions 22 included in one pixel block 15. The relay conductor 74a is electrically connected to a wiring 58ar provided in the wiring layer 58 on the inter-layer insulating film 56 via a contact electrode 57ar provided in the inter-layer insulating film 56.

[0174] As shown in Fig. 25 and Fig. 28, the relay conductor 74b is provided in the inter-pixel separation region 31 between two pixel blocks 15 arranged adjacent to each other in the Y direction. Although not shown in detail, the relay conductor 74b is electrically and mechanically connected to the power supply contact region WC of one photoelectric conversion region 22 at the first side surface portion 22b of one photoelectric conversion region 22 in two adjacent photoelectric conversion regions 22 in the two pixel blocks 15 arranged in the Y direction, and is also electrically and mechanically connected to the power supply contact region WC of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. That is, the relay conductor 74b is electrically and mechanically connected to two power supply contact regions WC adjacent to each other across the inter-pixel separation region 31 at each first side surface portion 22b of two photoelectric conversion regions 22 adjacent to each other in a plan view.

[0175] 28, the relay conductor 74b is embedded in the inter-pixel isolation region 31, penetrates the inter-pixel isolation region 31 in the X direction, and is connected to the first side surface portions 22b of two adjacent photoelectric conversion regions 22 sandwiching the inter-pixel isolation region 31. Similarly to the relay conductor 74a, the relay conductor 74b is electrically connected to a wiring 58wc provided in the wiring layer 58 on the inter-layer insulating film 56 via a contact electrode 57wc provided in the inter-layer insulating film 56. A reference potential of, for example, 0V is supplied from the wiring 58wc through the contact electrode 57wc to the relay conductor 74b.

[0176] Each of the relay conductors 74a and 74b is made of, for example, a polycrystalline silicon film doped with an impurity that reduces the resistance value. Although a metal film may be used for each of the relay conductors 74a and 74b, it is preferable to use a polycrystalline silicon film in consideration of the difference in thermal expansion coefficient between the inter-pixel isolation region 31 and the semiconductor layer 21.

[0177] <<Main Effects of the Sixth Embodiment>> As described above, the amplification transistor AMP of the sixth embodiment has a gate electrode 73a that is provided across the upper surface portion 22a and the inter-pixel isolation region 31 of one of the two photoelectric conversion regions 22 arranged in the Y direction via the inter-pixel isolation region 31 in a plan view, and is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22 at the first side portion 22b of the other photoelectric conversion region 22. Therefore, it is not necessary to electrically connect the gate electrode 73a of the amplification transistor AMP to the floating diffusion region FD by wiring of the multi-layer wiring layer 55, and the wiring density of the multi-layer wiring layer 55 that overlaps with the photoelectric conversion region 22 in a plan view can be reduced. This increases the degree of freedom in routing the wiring that connects to the pixel transistor Q of the photoelectric conversion region 22, and reduces the constraint on the arrangement of the pixel transistor Q caused by the wiring. Therefore, according to the solid-state imaging device 1F of the sixth embodiment, the degree of freedom in the arrangement of the pixel transistor Q in the photoelectric conversion region 22 can be increased.

[0178] The solid-state imaging device 1F according to the sixth embodiment also includes a relay conductor 74a provided in an inter-pixel separation region 31 between two photoelectric conversion regions 22 arranged in the X direction in one pixel block 15. The relay conductor 74a is electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in one photoelectric conversion region 22 at the first side surface portion 22b of one photoelectric conversion region 22 in the two photoelectric conversion regions 22 included in one pixel block 15, and is also electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. Therefore, in the connection between the relay conductor 74a and the contact electrode 57ar, it is possible to suppress connection failures due to an impurity concentration sufficient for connection, etching damage, silicide abnormality, etc., and also to suppress the generation of dark current due to leakage current.

[0179] The solid-state imaging device 1F according to the sixth embodiment also includes a relay conductor 74b provided in the pixel separation region 31 between two pixel blocks 15 arranged adjacent to each other in the Y direction. Similarly to the relay conductor 74a, the relay conductor 74b is electrically and mechanically connected to the power supply contact region WC of one photoelectric conversion region 22 at the first side portion 22b of one photoelectric conversion region 22 in two adjacent photoelectric conversion regions 22 in the two pixel blocks 15 arranged in the Y direction, and is electrically and mechanically connected to the power supply contact region WC of the other photoelectric conversion region 22 at the first side portion 22b of the other photoelectric conversion region 22. Therefore, in the connection between the relay conductor 74b and the contact electrode 57wc, it is possible to suppress connection failure due to an impurity concentration sufficient for connection, etching damage, silicide abnormality, etc., and also to suppress the generation of dark current due to leakage current.

[0180] Seventh embodiment As shown in Figures 30 to 32, the solid-state imaging device 1G according to the seventh embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A according to the first embodiment described above, with the following differences.

[0181] That is, the solid-state imaging device 1G of the seventh embodiment includes a pixel circuit 16G shown in Fig. 30 instead of the pixel circuit 16 of the first embodiment shown in Fig. 3. In the seventh embodiment, the transistor layout of the photoelectric conversion region 22 is slightly different from that of the first embodiment. The other configurations are generally similar to those of the first embodiment.

[0182] 30, the pixel circuit 16G has a circuit configuration in which a switching transistor FDG is newly added to the configuration of the above-mentioned pixel circuit 16. That is, the pixel circuit 16G includes, as the pixel transistor Q, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG.

[0183] As shown in Fig. 30, the switching transistor FDG has a source region electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP, and a drain region electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to the switching transistor drive line of the pixel drive line 10 shown in Fig. 2. This switching transistor FDG controls charge retention by the floating diffusion region FD, and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor AMP.

[0184] As shown in FIGS. 31 and 32, the switching transistor FDG has a gate electrode 47f provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 adjacent to each other in the Y direction in plan view. Specifically, the switching transistor FDG has a gate electrode 47f provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52f and 52r provided on the upper surface portion 22a side of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view and functioning as a source region and a drain region. The switching transistor FDG further has a channel formation portion 53f provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52r are formed of n-type semiconductor regions, and the channel formation portion 53f is formed of a p-type semiconductor region 23.

[0185] The switching transistor FDG is used when switching the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, if the FD capacitance C (floating diffusion capacitance C) of the floating diffusion region FD is large when performing charge-voltage conversion, the voltage V when converted to a voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C of the floating diffusion region FD is not large, the floating diffusion region FD cannot receive the charge of the photoelectric conversion unit 25 (photodiode PD). Furthermore, the FD capacitance C of the floating diffusion region FD needs to be large so that the voltage V when converted to a voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of these, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, so that the overall FD capacitance C becomes large. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor FDG on / off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0186] In the seventh embodiment, the floating diffusion region FD is also used as the main electrode region 52f of the switching transistor FDG. The reset transistor RST and the switching transistor FDG share the main electrode region 52r of the reset transistor RST and the main electrode region 52r of the switching transistor FDG, and are connected in series.

[0187] The solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0188] In the seventh embodiment, the gate electrodes 47f, 47r, and 47s of the switching transistor FDG, reset transistor RST, and selection transistor SEL are provided in the inter-pixel isolation region 31 as the pixel transistors Q included in the pixel circuit 16G. However, the gate electrode of at least any one of the multiple pixel transistors Q included in the pixel circuit 16G may be provided in the inter-pixel isolation region 31.

[0189] Eighth embodiment As shown in Figures 33 to 35, the solid-state imaging device 1H according to the eighth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A according to the first embodiment described above, with the following differences.

[0190] That is, the solid-state imaging device 1H of the eighth embodiment includes a pixel circuit 16H shown in Fig. 33 instead of the pixel circuit 16 of the first embodiment shown in Fig. 3. In the eighth embodiment, the planar layout of the pixel transistors Q included in the pixel circuit 16H is slightly different from that of the first embodiment. All the gate electrodes of the pixel transistors Q included in the pixel circuit 16H are provided in the element formation region 43 of the photoelectric conversion region 22. The other configurations are generally similar to those of the first embodiment.

[0191] As shown in Fig. 33, the pixel circuit 16H has a circuit configuration in which two switching transistors FDG, FCG are newly added to the configuration of the pixel circuit 16 shown in Fig. 3 described above. That is, the pixel circuit 16H includes an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and two switching transistors FCG, FDG as pixel transistors Q that constitute the circuit. The pixel circuit 16G (see Fig. 30) of the seventh embodiment described above includes one switching transistor FDG, but the pixel circuit 16H of the eighth embodiment includes two switching transistors FCG and FDG.

[0192] 33, the source region of the switching transistor FCG is electrically connected to the drain region of the switching transistor FDG, and the drain region is electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FCG is electrically connected to the first switching transistor driving line of the pixel driving line 10 shown in FIG.

[0193] 33, the switching transistor FDG has a source region electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD, and a drain region electrically connected to the source region of the switching transistor FCG. The gate electrode of the switching transistor FDG is electrically connected to the second switching transistor driving line of the pixel driving line 10 shown in FIG.

[0194] 33, like the switching transistor FDG of the seventh embodiment described above, controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor AMP. Then, by switching on / off each of the two switching transistors FCG and FDG, like the pixel circuit 16G of the seventh embodiment described above, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0195] Although not shown in detail, referring to Fig. 34, the switching transistor FCG has a gate electrode 47fc provided in the element formation region 43 (first side surface portion 22b of the photoelectric conversion region 22) of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52fc and 52r provided in the element formation region 43 (upper surface portion 22a) of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47fc in a plan view and functioning as a source region and a drain region. The switching transistor FCG further has a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47fc in a plan view. The pair of main electrode regions 52fc and 52r are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0196] Although not shown in detail, referring to FIG. 34, the switching transistor FDG has a gate electrode 47f provided in the element formation region 43 (first side surface portion 22b of the photoelectric conversion region 22) of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52f and 52fc provided in the element formation region 43 (upper surface portion 22a) of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view and functioning as a source region and a drain region. The switching transistor FDG further has a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52fc are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0197] In the eighth embodiment, the floating diffusion region FD is also used as the main electrode region 52f of the switching transistor FDG. The reset transistor RST and the switching transistor FCG share the main electrode region 52r of the reset transistor RST and the main electrode region 52r of the switching transistor FCG, and are connected in series. The switching transistor FCG and the switching transistor FDG share the main electrode region 52fc of the switching transistor FCG and the main electrode region 52fc of the switching transistor FDG, and are connected in series. That is, the reset transistor RST and the two switching transistors FCG and FDG are provided in the element formation region 43 of the photoelectric conversion region 22 in a state of being directly connected to each other.

[0198] As shown in FIGS. 34 and 35, the amplifier transistor AMP of the eighth embodiment has a configuration basically similar to that of the amplifier transistor AMP of the above-described first embodiment, but has a different gate electrode configuration.

[0199] That is, in two photoelectric conversion regions 22 (22X1 and 22X2) adjacent to each other in the Y direction via the inter-pixel isolation region 31 in a planar view, the amplification transistor AMP provided in one of the photoelectric conversion regions 22X1 has a gate electrode 75a that is provided across the upper surface portion 22a (element formation region 43) of one of the photoelectric conversion regions 22X1 and the inter-pixel isolation region 31 in a planar view, and is connected to the floating diffusion region FD of the other photoelectric conversion region 22X2 at the first side portion 22b of the other photoelectric conversion region 22X2.

[0200] 35, the gate electrode 75a includes a head 75a1 provided across one photoelectric conversion region 22X1 and the inter-pixel isolation region 31 in a plan view, and a relay connection portion 75a3 protruding from the head 75a1 toward the inter-pixel isolation region 31 and connected to the floating diffusion region FD at the first side surface portion 22b of the other photoelectric conversion region 22X2. In other words, the gate electrode 75a extends outside the first surface portion S1 of the semiconductor layer 21 across one photoelectric conversion region 22X1 and the inter-pixel isolation region 31, protruding from the head 75a1 into the inter-pixel isolation region 31, and electrically and mechanically connected to the floating diffusion region FD at the first side surface portion 22b of the other photoelectric conversion region 22X2. The gate electrode 75a of the eighth embodiment is made of, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces resistance is introduced, similar to the gate electrode 47a of the amplification transistor AMP according to the above-mentioned first embodiment. The gate electrode 75a of the eighth embodiment has substantially the same impurity concentration distribution on the side of one photoelectric conversion region 22X1 and the side of the other photoelectric conversion region 22X2. In the eighth embodiment, the first side surface portion 22b of the photoelectric conversion region 22 corresponds to a specific but not limitative example of "side surface portion of a photoelectric conversion region" of the present technology.

[0201] <<Main Effects of the Eighth Embodiment>> As described above, the amplification transistor AMP of the eighth embodiment has a gate electrode 75a that is provided across the upper surface portion 22a of one photoelectric conversion region 22X1 and the inter-pixel isolation region 31 in two photoelectric conversion regions 22 (22X1, 22X2) arranged in the Y direction via the inter-pixel isolation region 31 in a plan view, and is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22X2. Therefore, it is not necessary to electrically connect the gate electrode 75a of the amplification transistor AMP to the floating diffusion region FD by wiring of the multilayer wiring layer 55, and it is possible to reduce the wiring density of the multilayer wiring layer 55 that overlaps with the photoelectric conversion region 22 in a plan view. This makes it possible to increase the degree of freedom in routing the wiring that connects to the pixel transistors Q (AMP, SEL, RST, FCG, FDG) of the photoelectric conversion region 22, and to alleviate the constraints on the arrangement of the pixel transistors Q caused by the routing of the wiring. Therefore, in the solid-state imaging device 1H according to the eighth embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, the degree of freedom in arranging the pixel transistors Q in the photoelectric conversion region 22 can be increased.

[0202] In addition, the gate electrode 75a and the floating diffusion region FD can be electrically connected over the shortest distance, and the wiring capacitance added to the floating diffusion region FD can be reduced compared to the case where the gate electrode 47a and the floating diffusion region FD are electrically connected via the wiring of the multi-layer wiring layer 55. This can increase the conversion efficiency and reduce random noise.

[0203] In a CMOS image sensor, high conversion efficiency is an effective means of achieving high sensitivity and low noise. In order to increase the conversion efficiency, it is necessary to reduce the FD capacitance and the source-follower gain (SF It is necessary to increase the SF-Gain. However, the SF-Gain is generally about 0.8 to 0.9, and a significant improvement cannot be expected. On the other hand, a significant reduction in the FD capacitance can be expected by a structural approach. The FD capacitance is mainly composed of the sum of the FD diffusion layer capacitance in the floating diffusion region FD, the amplifier gate capacitance in the amplifying transistor AMP, and the FD wiring capacitance in the wiring connected to the floating diffusion region FD. The reduction of the FD diffusion layer capacitance is effective in reducing the area of ​​the floating diffusion region FD and reducing the concentration, but there is a concern that the FD white spots and the FD dark current may worsen. The reduction of the amplifier gate capacitance is effective in reducing the gate electrode size of the amplifying transistor AMP and making the gate insulating film 46 thicker, but there is a concern that the random noise (RN) may worsen. However, the reduction of the FD wiring capacitance does not cause a deterioration of the pixel characteristics, and it is possible to achieve a high conversion efficiency. Therefore, in order to further increase the conversion efficiency, it is effective to reduce the FD capacitance by reducing the FD wiring capacitance as in the eighth embodiment.

[0204] In the eighth embodiment, the wiring capacitance component of the FD capacitance can be almost eliminated, and further, signal coupling via other wiring can be reduced, and fixed pattern noise (FPN) can also be suppressed.

[0205] <Modification of the Eighth Embodiment> Next, a modification of the eighth embodiment will be described. <Variation 8-1> FIG. 36 is a longitudinal cross-sectional view of a main part that is a schematic diagram illustrating a modified example 8-1 according to the eighth embodiment of the present technology. In the above-described eighth embodiment, a case has been described in which the impurity concentration of the gate electrode 75a of the amplification transistor AMP has approximately the same impurity concentration distribution on the one photoelectric conversion region 22X1 side and the other photoelectric conversion region 22X2 side. However, the present technology is not limited to the above-described eighth embodiment.

[0206] For example, the gate electrode 75a may have an impurity concentration distribution in which the impurity concentration on the photoelectric conversion region 22X2 side is lower than the impurity concentration on the other photoelectric conversion region 22X1 side.

[0207] In this case, as shown in FIG. 36, the gate electrode 75a has a first portion 75X1 located on one photoelectric conversion region 22X1 side and a second portion 75X2 located on the other photoelectric conversion region 22X2 side and having a lower impurity concentration than the first portion 75X1. A boundary portion 75Z between the first portion 75X1 and the second portion 75X2 overlaps with the inter-pixel isolation region 31 in a plan view. The first portion 75X1 includes the one photoelectric conversion region 22X1 side of the head portion 75a1 of the gate electrode 75a. The second portion 75X2 includes the other photoelectric conversion region 22X2 side of the head portion 75a1 of the gate electrode 75a and also includes a relay connection portion 75a3. That is, in the gate electrode 75a of this modification 8-1, the impurity concentration of the relay connection portion 75a3 is lower than the impurity concentration on one photoelectric conversion region 22X1 side.

[0208] In the case of this modification example 8-1, the resistance of the channel formation portion side (the portion on the one photoelectric conversion region 22 side) of the gate electrode 75a can be reduced while suppressing impurity diffusion from the relay connection portion 75a3 to the floating diffusion region FD, thereby reducing the FD diffusion layer capacitance.

[0209] <Variation 8-2> FIG. 37 is a longitudinal cross-sectional view of a main part that is a schematic diagram illustrating a modified example 8-2 according to the eighth embodiment of the present technology. In the above-described eighth embodiment, as the inter-pixel isolation region, as shown in Figures 5A and 35, an inter-pixel isolation region 31 was described that includes a recessed portion 33 provided in the semiconductor layer 21 and extending in the thickness direction (Z direction) of the semiconductor layer 21, and an isolation insulating film 34 provided in the recessed portion 33 of the semiconductor layer 21 so as to bury this recessed portion 33.

[0210] 37, the pixel isolation region 31 of the modified example 8-2 includes a recessed portion 33 provided in the semiconductor layer 21 and extending in the thickness direction (Z direction) of the semiconductor layer 21, an isolation insulating film 34 provided in the recessed portion 33 of the semiconductor layer 21 along the inner wall of the recessed portion 33, and a conductor 35 provided in the recessed portion 33 of the semiconductor layer 21 via the isolation insulating film 34. Although not shown, the conductor 35 is electrically connected to a wiring to which a reference potential is applied. That is, the pixel isolation region 31 of the modified example 8-2 includes the conductor 35 to which a reference potential is applied. For example, a negative bias potential is applied as the reference potential.

[0211] 37, the gate electrode 75a of the amplification transistor AMP overlaps with the conductor 35 of the inter-pixel isolation region 31 in a plan view. The conductor 35 of the inter-pixel isolation region 31 extends along the thickness direction (Z direction) of the semiconductor layer 21, and one end side located on the first surface portion S1 side of the semiconductor layer 21 faces (is adjacent to) the gate electrode 75a of the amplification transistor AMP via the isolation insulating film 34.

[0212] Here, if the parasitic capacitance of the floating diffusion region FD is too small, the FD potential fluctuates due to coupling from other signal lines, and RN (on-resistance) is likely to deteriorate. Therefore, by applying a constant potential to the conductor 35 of the inter-pixel isolation region 31 and stabilizing the potential of the capacitively coupled floating diffusion region FD, it is possible to reduce or eliminate the potential fluctuation due to coupling with other signal lines, thereby achieving low noise. Therefore, in this modification 8-2, the same effect as the above-mentioned eighth embodiment can be obtained, and low noise can be achieved.

[0213] <Variation 8-3> FIG. 38 is a longitudinal cross-sectional view of a main part that is a schematic diagram illustrating a modified example 8-3 according to the eighth embodiment of the present technology.

[0214] In the above-described eighth embodiment, the gate electrode 75a including the head portion 75a1 and the relay connection portion 75a3 has been described as the gate electrode of the amplification transistor AMP. However, the present technology is not limited to the gate electrode 75a of the above-described eighth embodiment.

[0215] 38, the gate electrode 75a may include a head 75a1 and a relay connection portion 75a3, and may further include a leg portion 75a2 protruding from the head 75a1 toward one of the photoelectric conversion regions 22X1. The leg portion 75a2 protrudes from the head 75a1 into the semiconductor layer 21 in the element formation region 43 of one of the photoelectric conversion regions 22X1, and is adjacent to the channel formation portion 53a of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween. Although one leg portion 75a2 is illustrated in FIG. 38, two or more legs 75a2 may be provided.

[0216] By using the amplification transistor AMP of the modified example 8-3, flicker noise and thermal noise can be reduced, and a low on-resistance can be achieved.

[0217] <Variation 8-4> FIG. 39 is a longitudinal cross-sectional view of a main part that illustrates a modified example 8-4 according to the eighth embodiment of the present technology.

[0218] In the above-described eighth embodiment, the gate electrode 75a of the amplifier transistor AMP provided in one photoelectric conversion region 22X1 is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22X2 at the first side portion 22b of the other photoelectric conversion region 22X2. However, the present technology is not limited to the above-described eighth embodiment.

[0219] For example, as shown in FIG. 39, the gate electrode 75a of the amplification transistor AMP provided in one photoelectric conversion region 22X1 may be electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22X2 at the upper surface portion 22a and first side surface portion 22b of the other photoelectric conversion region 22X2.

[0220] In the case of this modification 8-4, the contact area between the gate electrode 75a and the floating diffusion region FD can be increased, thereby achieving a reduction in resistance.

[0221] <Variation 8-5> FIG. 40 is a longitudinal cross-sectional view of a main part that illustrates a modified example 8-5 according to the eighth embodiment of the present technology. This modification is a combination of the impurity concentration distribution technique of the modification 8-1 shown in Fig. 36 and the parasitic capacitance addition technique of the modification 8-2 shown in Fig. 37. This modification 8-5 can obtain the respective effects of the above-mentioned modifications 8-1 and 8-2.

[0222] <Variation 8-6> FIG. 41 is a longitudinal cross-sectional view of a main part that is schematic of a modified example 8-6 according to the eighth embodiment of the present technology. This modification is a combination of the impurity concentration distribution technique of the modification 8-1 shown in Fig. 36 and the channel width expansion technique of the modification 8-3 shown in Fig. 38. This modification 8-6 can obtain the respective effects of the above-mentioned modifications 8-1 and 8-3.

[0223] <Variation 8-7> FIG. 42 is a longitudinal cross-sectional view of a main part that is a schematic diagram illustrating a modified example 8-7 according to the eighth embodiment of the present technology. This modified example 8-7 is a combination of the impurity concentration distribution technique of modified example 8-1 shown in Fig. 36 and the floating diffusion region connection technique of modified example 8-4 shown in Fig. 39. This modified example 8-7 can obtain the respective effects of modified examples 8-1 and 8-4 described above.

[0224] <Other Modifications> Although not shown, the parasitic capacitance adding technique of variant example 8-2 shown in FIG. 37 can be combined with the channel width widening technique of variant example 8-3 shown in FIG. 38 and the floating diffusion region connection technique of variant example 8-4 shown in FIG. 39.

[0225] Although not shown, the channel width widening technique of Modification 8-3 shown in FIG. 38 and the floating diffusion region connection technique of Modification 8-4 shown in FIG. 39 can be combined.

[0226] Ninth embodiment Next, a solid-state imaging device 1I according to a ninth embodiment of the present technology will be described with reference to FIGS. FIG. 43 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 44 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a43-a43 cutting line in FIG.

[0227] A solid-state imaging device 1I according to a ninth embodiment of the present technology includes a pixel block 15I shown in Fig. 43. The pixel block 15I of the ninth embodiment mainly includes two pixels 3 (3a1, 3b1) arranged adjacent to each other in the Y direction as one unit.

[0228] Each of the two pixels 3 (3a1, 3b1) included in one pixel block 15I includes a photoelectric conversion region 22 (22X3, 22X4) partitioned by an inter-pixel isolation region 31. The photoelectric conversion region 22 (22X3, 22X4) of the ninth embodiment is basically configured similarly to the photoelectric conversion region 22 of the eighth embodiment described above, with the following differences.

[0229] That is, the photoelectric conversion regions 22 (22X3, 22X4) of the ninth embodiment are different from the photoelectric conversion region 22 of the eighth embodiment described above in the transistor layout and the planar shape of the element formation region 43. In two photoelectric conversion regions 22 (22X3, 22X4) included in one pixel block 15I, the planar pattern of the element formation region 43 in one photoelectric conversion region 22X3 and the planar pattern of the element formation region 43 in the other image photoelectric conversion region 22X4 are inverted with respect to the boundary between pixels 3a1 and 3b1 arranged in the Y direction.

[0230] In the photoelectric conversion region 22 (22X3, 22X4) of the ninth embodiment, the element formation region 43 is provided with an amplification transistor AMP, a selection transistor SEL, and a switching transistor FDG as pixel transistors, but does not include the switching transistor FCG shown in Fig. 34 of the eighth embodiment. In the ninth embodiment, the configuration of the amplification transistor AMP is slightly different from that of the eighth embodiment.

[0231] Specifically, the amplification transistor AMP of the ninth embodiment is shared by two photoelectric conversion regions 22 (22X3, 22X4) included in one pixel block 15I, in other words, shared by two pixels 3 (3a1, 3b1) included in one pixel block 15I.

[0232] As shown in FIG. 44, the amplification transistor AMP of the ninth embodiment has a gate electrode 75a that is electrically and mechanically connected to the floating diffusion region FD of one of the photoelectric conversion regions 22X3 at the first side portion 22b of the one photoelectric conversion region 22X3, and is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22X4 at the side portion 22b of the other photoelectric conversion region 22X4, in two photoelectric conversion regions 22 (22X3, 22X4) included in one pixel block 15I. That is, the gate electrode 75a of the amplification transistor AMP of the ninth embodiment has a head portion 75a1 extending outside the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31, and a relay connection portion 75a3 protruding from this head portion 75a1 into the inter-pixel isolation region 31 and electrically and mechanically connected to each of the first side portions 22b of two adjacent photoelectric conversion regions 22 (22X3, 22X4) that are positioned across the inter-pixel isolation region 31 in a planar view.

[0233] The solid-state imaging device 1I according to the ninth embodiment also provides the same effects as the solid-state imaging device 1H according to the eighth embodiment.

[0234] Tenth embodiment Next, a solid-state imaging device 1I according to a tenth embodiment of the present technology will be described with reference to FIGS. FIG. 45 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to the tenth embodiment of the present technology. FIG. 46 is a longitudinal sectional view that typically shows a longitudinal sectional structure taken along the a45-a45 cutting line in FIG.

[0235] A solid-state imaging device 1J according to a tenth embodiment of the present technology includes a pixel block 15J shown in Fig. 45. The pixel block 15J according to the tenth embodiment mainly includes two pixels 3 (3a2, 3b2) arranged adjacent to each other in the Y direction as one unit.

[0236] Each of the two pixels 3 (3a2, 3b2) included in one pixel block 15J includes a photoelectric conversion region 22 (22X5, 22X6) partitioned by an inter-pixel isolation region 31. The photoelectric conversion region 22 (22X5, 22X6) of the tenth embodiment basically has the same configuration as the photoelectric conversion region 22 of the eighth embodiment described above, with the following differences.

[0237] That is, the photoelectric conversion regions 22 (22X5, 22X6) of the tenth embodiment are different from the photoelectric conversion region 22 of the eighth embodiment described above in the transistor layout and the planar shape of the element formation region 43. In the two photoelectric conversion regions 22 (22X5, 22X6) included in one pixel block 15J, the planar pattern of the element formation region 43 in one photoelectric conversion region 22X5 and the planar pattern of the element formation region 43 in the other photoelectric conversion region 22X6 are inverted with respect to the boundary between the pixels 3a2 and 3b2 aligned in the Y direction.

[0238] In the photoelectric conversion region 22 (22X3, 22X4) of the tenth embodiment, the element formation region 43 is provided with an amplification transistor AMP, a selection transistor SEL, and a switching transistor FDG as pixel transistors, but does not include the switching transistor FCG shown in Fig. 34 of the eighth embodiment. In the ninth embodiment, the configuration of the amplification transistor AMP is slightly different from that of the eighth embodiment.

[0239] Specifically, the amplification transistor AMP of the tenth embodiment is shared by two photoelectric conversion regions 22 (22X5, 22X6) included in one pixel block 15J, in other words, shared by two pixels 3 (3a2, 3b2) included in one pixel block 15J.

[0240] As shown in FIG. 46, the amplification transistor AMP of the tenth embodiment has a gate electrode 75a that is electrically and mechanically connected to the floating diffusion region FD of one photoelectric conversion region 22X5 at the top surface portion 22a and first side surface portion 22b of one photoelectric conversion region 22X5 in two photoelectric conversion regions 22 (22X5, 22X6) included in one pixel block 15J, and is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22X6 at the top surface portion 22a and first side surface portion 22b of the other photoelectric conversion region 22X5. That is, the gate electrode 75a of the amplification transistor AMP of the tenth embodiment has a head portion 75a1 extending outside the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31, and a relay connection portion 75a3 protruding from this head portion 75a1 into the inter-pixel isolation region 31 and electrically and mechanically connected to each of the upper surface portion 22a and the first side surface portion 22b of two adjacent photoelectric conversion regions 22 (22X5, 22X6) that are positioned across the inter-pixel isolation region 31 in a planar view.

[0241] In the solid-state imaging device 1J according to the tenth embodiment, the same effects as those of the solid-state imaging device 1H according to the eighth embodiment can be obtained, and the resistance can be reduced as in the above-mentioned modification 8-4.

[0242] Eleventh Embodiment <Applications to electronic devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0243] FIG. 47 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0244] 47, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging device 1A according to the first embodiment of the present technology is used as the solid-state imaging device 101 in an electronic device (e.g., a camera).

[0245] The optical lens 102 focuses image light (incident light 106) from a subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 transfer charges in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The video signals that have undergone signal processing are stored in a storage medium such as a memory, or output to a monitor.

[0246] With this configuration, the mutual conductance (gm) of the transfer transistor TR is improved in the solid-state imaging device 101, and therefore the image quality performance of the electronic device 100 of the eleventh embodiment can be improved.

[0247] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0248] In addition, the present technology can be applied to light detection devices in general, including distance measuring sensors that measure distance, called ToF (Time of Flight) sensors, in addition to the solid-state imaging devices as image sensors described above. Distance measuring sensors emit light toward an object, detect the light reflected back from the surface of the object, and calculate the distance to the object based on the flight time from when the light is emitted to when the reflected light is received. The pixel transistor described above can also be used in such distance measuring sensors.

[0249] The present technology may be configured as follows. (1) a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer; Equipped with The photoelectric conversion region is an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the separation region side; a transfer transistor provided on the upper surface side and configured to transfer the signal charge photoelectrically converted by the photoelectric conversion unit to a charge storage unit; A plurality of pixel transistors provided on the upper surface portion; Equipped with At least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween. (2) The photodetection device according to claim 1, wherein at least one of the plurality of pixel transistors further has a pair of main electrode regions spaced apart from each other in a gate length direction of the gate electrode in a planar view and provided on the upper surface side of the photoelectric conversion region. (3) The photodetector according to (1) or (2) above, wherein the gate electrode is selectively provided in the isolation region. (4) The photodetector according to any one of (1) to (3) above, wherein the gate electrode is provided across the top and side surfaces of the photoelectric conversion region with the gate insulating film interposed therebetween. (5) The gate electrode is a head portion extending across the photoelectric conversion region and the separation region in a plan view outside the first surface portion of the semiconductor layer; a leg portion protruding from the head portion toward the isolation region and adjacent to the first side surface portion of the photoelectric conversion region with the gate insulating film interposed therebetween; The optical detection device according to (4) above, (6) the photoelectric conversion region further includes an inter-element isolation region provided on the upper surface portion side, and a second side surface portion located on the opposite side to the first side surface portion in a plan view and adjacent to the inter-element isolation region, The photodetector according to (1) above, wherein the gate electrode is provided across the top surface portion, the first side surface portion, and the second side surface portion with the gate insulating film interposed therebetween. (7) The gate electrode is a head portion extending across the isolation region and the inter-element isolation region in a plan view on an outer side of the first surface portion of the semiconductor layer; a first leg portion that protrudes from the head portion toward the isolation region and is adjacent to the first side portion of the photoelectric conversion region with the gate insulating film interposed therebetween; a second leg portion that protrudes from the head portion toward the element isolation region and is adjacent to the second side portion of the photoelectric conversion region with the gate insulating film interposed therebetween; The optical detection device according to (6) above, (8) The photodetector device according to claim 6, wherein at least one of the plurality of pixel transistors has a channel forming portion between the first side portion and the second side portion of the photoelectric conversion region. (9) the separation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than a width of the first vertical portion; The photodetector according to (1) above, wherein the gate electrode is entirely provided in the first vertical portion. (10) the separation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than a width of the first vertical portion; The photodetector according to (1) above, wherein a portion of the gate electrode is provided in the first vertical portion. (11) The photodetector according to (1) above, wherein the gate electrodes are adjacent to each other with the gate insulating film interposed between them and the first side portions of two of the photoelectric conversion regions adjacent to each other in a planar view. (12) The photodetector according to (2) above, wherein one of the pair of main electrode regions also serves as the charge retaining portion. (13) The photodetection device described in (1) above, wherein in two of the photoelectric conversion regions adjacent to each other via the isolation region in a planar view, the gate electrode is adjacent to the first side portion of one of the photoelectric conversion regions via the gate insulating film, and is connected adjacent to the charge retention portion of the other photoelectric conversion region. (14) Further, a relay conductor portion is provided in the separation region between two of the photoelectric conversion regions adjacent to each other in a plan view, The photodetector device described in (1) above, wherein the relay conductor portion is connected to a semiconductor region provided in each of the two photoelectric conversion regions that are adjacent to each other in a planar view at the first side portion of each of the two photoelectric conversion regions. (15) A semiconductor layer; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer; Equipped with The photoelectric conversion region is A top surface portion and a side surface portion; a charge holding section provided on the upper surface side and holding signal charges transferred from the photoelectric conversion section via a transfer transistor; A pixel transistor provided on the upper surface side; Equipped with A photodetection device, wherein the pixel transistor provided in one of the two photoelectric conversion regions, which are adjacent to each other in a planar view with the isolation region interposed therebetween, has a gate electrode that is provided across the top surface portion and the isolation region of one of the photoelectric conversion regions in a planar view, and is connected to the charge retention portion of the other photoelectric conversion region at the side portion of the other photoelectric conversion region. (16) The photodetector device described in 815) above, wherein the gate electrode includes a head portion provided across one of the photoelectric conversion regions and the separation region, and a relay connection portion protruding from the head portion toward the separation region and connected to the charge retention portion at the side portion of the other photoelectric conversion region. (17) The photodetector according to claim 15 or 16, wherein the gate electrode has a lower impurity concentration on one of the photoelectric conversion regions than on the other of the photoelectric conversion regions. (18) the gate electrode has a first portion located on one of the photoelectric conversion regions and a second portion located on the other of the photoelectric conversion regions and having a lower impurity concentration than the first portion; The light detection device according to any one of (15) to (17) above, wherein a boundary between the first portion and the second portion overlaps with the separation region in a plan view. (19) The photodetector according to any one of (16) to (18), wherein the gate electrode further includes a leg portion protruding from the head portion toward one of the photoelectric conversion regions. (20) The photodetector according to any one of (15) to (19), wherein the gate electrode is connected to the charge retention portion across the top surface and the side surface of the other of the photoelectric conversion regions. (twenty one) 16. The photodetector according to claim 15, wherein the separation region includes a conductor to which a potential is applied. (twenty two) A photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; Equipped with The light detection device includes: a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer, the photoelectric conversion region having an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the separation region side; a transfer transistor provided on the upper surface side of the photoelectric conversion region and configured to transfer the signal charge photoelectrically converted by the photoelectric conversion portion to a charge storage portion; a plurality of pixel transistors provided on the upper surface of the photoelectric conversion region; Equipped with at least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

[0250] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the intended purpose of the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0251] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J...Solid-state imaging device 2. Semiconductor chip 2A: Pixel array section 2B: Periphery 3,3a,3a1,3a2,3b,3b1,3b2...pixel 4. Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7. Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14…Bonding pad 15,15,15I,15J...Pixel block, 15H 16, 16G, 16H...Pixel circuit (readout circuit) 21...Semiconductor layer 22...Photoelectric conversion area 22a...Top part 22b...first side part 22c…Second side part 23...p-type semiconductor region 24...n-type semiconductor region 25...Photoelectric conversion section 31, 31B...Inter-pixel isolation region (isolation region) 31b1…First vertical section 31b2…Second vertical section 31bz…Step 31x…1st plane part 31y…Second plane part 31z1…First vertical section 31z2…Second vertical section 33…Dug-in section 34...Isolation insulating film 35…Conductor 41...Element isolation region (field isolation region) 42a...Shallow groove part 42b...Isolation insulating film 43...Element formation region (active region) 45a, 45b…Dug-in section 46...Gate insulating film 47...Gate electrode film 47a, 47r, 47s, 47t...gate electrode 47t1…Head 47t2…Leg 51…Dug-in section 52as,52as,52r,52s…Main electrode area 53r, 53s…Channel forming section 55...Multilayer wiring layer 56...Interlayer insulating film 57…First wiring layer 57a, 57f, 57r, 57s, 57t...Contact electrodes 58a, 58r, 58s, 58t...Wiring 61...Planarization film 63...Optical filter 64...Micro lens 71r...gate electrode, 71r1...head, 71r2 leg 71s...gate electrode, 71s1...head, 71s2...leg 72r...gate electrode, 72r1...head, 72r2...first leg, 72r3...second leg 72s...gate electrode, 72s1...head, 72s2...first leg, 72s3...second leg 73a...gate electrode, 73a1...head, 73a2...leg 74a, 74b... relay conductor section 75a...gate electrode, 75a1...head, 75a3...relay connection part 100...Electronic equipment 101...Solid-state imaging device 102...Optical lens (optical system) 103...Shutter device 104...Drive circuit 105...Signal processing circuit AMP: Amplification transistor FD: n-type floating diffusion region FCG, FDG…switching transistor Q: Pixel transistor RST: Reset transistor SEL...Select transistor S1 …1 surface S2: Second surface TR: Transfer transistor WC: Power supply contact area

Claims

1. a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer; Equipped with The photoelectric conversion region is an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the isolation region side; a transfer transistor provided on the upper surface side and configured to transfer the signal charge photoelectrically converted by the photoelectric conversion unit to a charge storage unit; A plurality of pixel transistors provided on the upper surface portion; Equipped with At least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

2. 2. The photodetection device according to claim 1, wherein at least one pixel transistor of the plurality of pixel transistors further includes a pair of main electrode regions spaced apart from each other in a gate length direction of the gate electrode in a plan view and provided on the upper surface side of the photoelectric conversion region.

3. The photodetector according to claim 1 , wherein the gate electrode is selectively provided in the isolation region.

4. The photodetector according to claim 1 , wherein the gate electrode is provided across the top surface and side surface of the photoelectric conversion region with the gate insulating film interposed therebetween.

5. The gate electrode is a head portion extending across the photoelectric conversion region and the separation region in a plan view outside the first surface portion of the semiconductor layer; a leg portion protruding from the head portion toward the isolation region and adjacent to the first side portion of the photoelectric conversion region with the gate insulating film interposed therebetween; The optical detection device of claim 4 .

6. the photoelectric conversion region further includes an inter-element isolation region provided on the upper surface portion side, and a second side surface portion located on the opposite side to the first side surface portion in a plan view and adjacent to the inter-element isolation region, The photodetector according to claim 1 , wherein the gate electrode is provided across the top surface portion, the first side surface portion, and the second side surface portion with the gate insulating film interposed therebetween.

7. The gate electrode is a head portion extending across the isolation region and the inter-element isolation region in a plan view on an outer side of the first surface portion of the semiconductor layer; a first leg portion that protrudes from the head portion toward the isolation region and is adjacent to the first side portion of the photoelectric conversion region with the gate insulating film interposed therebetween; a second leg portion that protrudes from the head portion toward the element isolation region and is adjacent to the second side portion of the photoelectric conversion region with the gate insulating film interposed therebetween; The optical detection device of claim 6 .

8. The photodetector according to claim 6 , wherein at least one of the plurality of pixel transistors has a channel forming portion between the first side portion and the second side portion of the photoelectric conversion region.

9. the separation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than a width of the first vertical portion; The photodetector according to claim 1 , wherein the gate electrode is entirely disposed in the first vertical portion.

10. the separation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than a width of the first vertical portion; The photodetector according to claim 1 , wherein a portion of the gate electrode is provided in the first vertical portion.

11. The photodetector according to claim 1 , wherein the gate electrodes are adjacent to each other with the gate insulating film interposed between the first side portions of two of the photoelectric conversion regions adjacent to each other in a plan view.

12. The photodetector according to claim 2 , wherein one of the pair of main electrode regions also serves as the charge retaining portion.

13. 2. The photodetection device of claim 1, wherein in two photoelectric conversion regions adjacent to each other in a planar view via the isolation region, the gate electrode is adjacent to the first side portion of one of the photoelectric conversion regions via the gate insulating film, and is connected adjacent to the charge retention portion of the other photoelectric conversion region.

14. The photoelectric conversion device further includes a relay conductor portion provided in the separation region between two of the photoelectric conversion regions adjacent to each other in a plan view, The photodetector device according to claim 1 , wherein the relay conductor portion is connected to a semiconductor region provided in each of the two photoelectric conversion regions adjacent to each other in a planar view at the first side portion of each of the two photoelectric conversion regions.

15. A semiconductor layer; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer; Equipped with The photoelectric conversion region is A top surface portion and a side surface portion; a charge holding section provided on the upper surface side and holding signal charges transferred from the photoelectric conversion section via a transfer transistor; A pixel transistor provided on the upper surface side; Equipped with A photodetection device comprising two photoelectric conversion regions adjacent to each other via the isolation region in a planar view, the pixel transistor provided in one of the photoelectric conversion regions having a gate electrode that is provided across the top surface portion and the isolation region of one of the photoelectric conversion regions in a planar view, and is connected to the charge retention portion of the other photoelectric conversion region at the side portion of the other photoelectric conversion region.

16. The photodetection device of claim 15, wherein the gate electrode includes a head portion provided across one of the photoelectric conversion regions and the separation region, and a relay connection portion protruding from the head portion toward the separation region and connected to the charge holding portion at the side portion of the other photoelectric conversion region.

17. 16. The photodetector according to claim 15, wherein the gate electrode has a lower impurity concentration on one of the photoelectric conversion regions than on the other of the photoelectric conversion regions.

18. the gate electrode has a first portion located on one of the photoelectric conversion regions and a second portion located on the other of the photoelectric conversion regions and having a lower impurity concentration than the first portion; The light detection device according to claim 15 , wherein a boundary between the first portion and the second portion overlaps with the separation region in a plan view.

19. The photodetector according to claim 18 , wherein the gate electrode further includes a leg portion protruding from the head portion toward one of the photoelectric conversion regions.

20. The photodetector according to claim 15 , wherein the gate electrode is connected to the charge retaining portion across the top surface portion and the side surface portion of the other of the photoelectric conversion regions.

21. 16. The photodetection device of claim 15, wherein the isolation region comprises a conductor to which an electrical potential can be applied.

22. A photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; Equipped with The light detection device includes: a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer, the photoelectric conversion region having an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the separation region side; a transfer transistor provided on the upper surface side of the photoelectric conversion region and configured to transfer the signal charge photoelectrically converted by the photoelectric conversion portion to a charge storage portion; a plurality of pixel transistors provided on the upper surface of the photoelectric conversion region; Equipped with at least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

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