Multilayer printed wiring board

Abstract

To provide a multilayer printed wiring board which suppresses breakage of via bottom parts of three or more stages of stacked vias.SOLUTION: A multilayer printed wiring board includes a core substrate having a filled via, build-up layers which are laminated on the upper and lower sides of the core substrate, and are composed of an arbitrary layer number of an insulation resin layer having a glass fiber and / or an inorganic filler therein and a conductor layer, and three or more stages of stacked vias for connecting between the conductor layers in a vertical direction in the build-up layers, wherein in the three or more stages of stacked vias, via bottom diameters between at least the via stacked at the first stage from the side of the core substrate and the via positioned at the center or the via positioned at an n-(n / 2)-th stage (n is even stage number) are substantially the same or more than a via top diameter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multilayer printed wiring board having multiple layers and high density, which has filled vias in a core substrate and vias stacked in three or more stages in a build-up layer. [Background technology]

[0002] There is a need to mount high-speed communication systems on semiconductor package components mounted on printed wiring boards for in-vehicle equipment. The semiconductor package components mounted on these printed wiring boards are BGA, LGA, or PGA type processors, and as package component sizes continue to increase while at the same time the number of pins on mounting terminals is increasing and the pitch is becoming narrower, there is a demand for even higher multi-layer structures and higher density wiring even in multi-layer printed wiring boards for in-vehicle use.

[0003] In addition, the circuit design specifications and structure of the printed wiring board are determined according to the semiconductor package parts. In other words, in order to mount multiple high-performance semiconductor package parts with narrower pitches for component terminals, more pins for terminals, and larger sizes, it is essential to have multiple build-up layers for wiring between the land terminals of the printed wiring board on the mounting side, as well as stacked vias between multiple layers for interlayer connections, smaller diameter via lands, and finer circuit wiring technology. In particular, in the case of a multi-stage stacked via structure, as the diameter of the via land becomes smaller, the via diameter must be made smaller while still ensuring connection reliability.

[0004] Multilayer printed wiring boards used in high-performance products such as mobile consumer devices have traditionally been equipped with multiple semiconductor package components with narrow pitches and high pin counts. These multilayer printed wiring boards use a thin insulating layer (thickness 40 μm or less) and a thin conductor layer (thickness 25 μm or less) to achieve high density through a multi-stage structure of fine circuit wiring and small diameter vias. The glass cloth that makes up the thin insulating layer uses a material that uses small diameter filaments (glass cloth thickness 21 μm or less: IPC standard #1027 or less).

[0005] On the other hand, multilayer printed wiring boards for automotive and industrial equipment also need to be equipped with power semiconductors to control actuators and motors. To meet the high current and high voltage specifications, the insulation layer thickness of the build-up layer must be 60 μm or more, so the glass cloth thickness must be 25 μm or more and the conductor thickness must be 35 μm or more. Hereinafter, an example in which three or more stacked vias are formed in a multilayer printed wiring board of such design will be described with reference to FIG.

[0006] In Fig. 11, 500 denotes a multilayer printed wiring board, which includes a core substrate 1 having a filled via 4 formed by filling a bottomed hole processed from above with a laser with copper plating, a build-up layer 5 formed of a laminate of any number of insulating resin layers and conductor layers stacked above and below the core substrate 1, and three or more stacked vias 8 formed directly above and below the filled via 4 to connect the conductor layers in the upper and lower direction in the build-up layer 5. The stacked via 8 is formed in a tapered shape in which the bottom (B) diameter of the via is smaller than the top (T) diameter of the via, taking into consideration the laser processing conditions and the adhesion of copper plating, and the contact area between the bottom of the via and the land (receiving land) below the via 8 and the contact area between the bottom of the via and the lower conductor layer of the via are both smaller than the contact area between the top of the via and the upper conductor layer of the via. Similarly, the filled via 4, which is filled in the core substrate 1 with copper plating, is formed in a tapered shape in which the bottom (Ba) diameter of the via is smaller than the top (Ta) diameter of the via, and the contact area between the bottom of the via and the copper foil (receiving land) on the underside of the core substrate 1, and the contact area between the bottom of the via and the lower conductor layer of the via are both smaller than the contact area between the top of the via and the upper conductor layer of the via.

[0007] However, if the via shape is a taper shape in which the bottom (B, Ba) diameter of the via is smaller than the top (T, Ta) diameter of the via, when performing accelerated tests (reliability tests) assuming use in harsh environments, such as thermal shock tests (high temperature 125°C or higher ⇔ low temperature -55°C or lower, 1000 cycles), cracks develop at the bottom of the via connected to the filled via filled with copper plating on the core board, or at the bottom of the via one level above, causing the via bottom to break. This is thought to be because the insulating layer thickness of the build-up layer becomes thicker (60μm or more, especially 70~80μm or more), which increases the linear expansion in the Z-axis direction, and in the thermal shock test, the material shrinks due to the temperature difference between a high temperature of 125°C or higher and a low temperature of -55°C or lower, causing the smaller diameter via bottom to be unable to withstand the stress concentration. Furthermore, when the thickness of the insulating resin layer of the build-up layer is 40 μm or less, even if the via diameter is small and the via shape is tapered, the thermal expansion coefficient in the Z-axis direction is small, and there is no risk of breakage even if the connection area at the bottom of the via is smaller than the top diameter.

[0008] Patent Document 1 discloses a multilayer resin wiring board in which a core substrate is provided with buried holes and lid plating, and four-stage stacked vias are arranged above and below the lid plating. In this multilayer resin wiring board, the second-stage via hole, counting from the core substrate of the stacked via, is shifted to avoid stress concentration on the via conductor and suppress cracks in the stacked via. However, there is a problem in that shifting a part of the stacked via prevents the stacked via from achieving high density due to the detouring of the wiring circuit. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2008-91737 A Summary of the Invention [Problem to be solved by the invention]

[0010] The inventors have studied how stress is applied to stacked vias, and have found that a large stress is applied to the bottom of the vias in the core substrate, the bottom of the vias stacked in the first layer counting from the core substrate side, and the bottom of the vias in the middle of the stacking number. For example, in the case of vias stacked in three layers, it has been confirmed that stress is applied to the bottom of the filled vias in the core substrate, and the bottom of the vias stacked in the first layer counting from the core substrate side, and the bottom of the vias stacked in the second layer. Similarly, in the case of vias stacked in five layers, it has been confirmed that a large stress is applied to the bottom of the filled vias in the core substrate, the bottom of the vias stacked in the first layer counting from the core substrate side, and the bottom of the vias in the third layer that is in the middle of the stacking number. More specifically, in a multilayer printed wiring board with three or more stacked vias, it goes without saying that a large stress is applied to the bottom of the filled via in the core substrate and the bottom of the via stacked in the first layer, which is the connection part with the core substrate, but even the vias in the middle layer of the stacked vias are subjected to stress similar to that of the bottom of the vias stacked in the first layer. Therefore, depending on the quality of vias stacked in three or more layers, when accelerated tests such as thermal shock tests were conducted, for example, in vias stacked in three layers, cracks sometimes occurred not at the bottom of the filled vias in the core board, or at the bottom of the vias stacked in the first layer counting from the core board, but at the bottom of the vias in the second layer located in the middle. Similarly, in vias stacked in five layers, cracks sometimes occurred at the bottom of the vias in the third layer in the middle. The results showed that the frequency of cracks at the bottom of the first layer of vias stacked on the filled vias of the core board was higher in the vias stacked on the top of the filled vias of the core board, but there was no difference between the top and bottom of the stacked vias in the middle. Similar results were also obtained from structural analysis using thermal stress analysis simulation.

[0011] In particular, it has been confirmed that the connection in this via structure breaks most quickly at the location where the cross-sectional area including the connection part is the smallest, i.e., at the bottom of the via. The via bottom is firmly connected by a metallic bond between the plated copper on the receiving land side and the via-plated copper, but one of the factors that reduces the connection strength is the presence at the joint interface of adsorbates and precipitates of metals different from the plated copper, such as electroless copper plating and palladium catalysts that are necessary in the manufacturing process for electroless copper plating.

[0012] The present invention has been made in consideration of the above-mentioned conventional problems, and has an object to provide a multilayer printed wiring board in which breakage of the bottoms of vias stacked in three or more levels is suppressed. [Means for solving the problem]

[0013] The inventors of the present invention conducted various studies to solve the above problems and found that connection reliability can be improved by using a structure with an enlarged cross-sectional area at the bottom of the via, which disperses the stress applied to the via and does not concentrate the stress at the bottom of the via. As a result of further investigation, the inventors found that extremely good results can be obtained by using an insulating resin layer having glass fiber and / or inorganic filler therein as the interlayer resin insulating layer of the build-up layer and forming the via bottom diameter of a via at a predetermined position among three or more stacked vias to be approximately the same as or larger than the via top diameter, thereby completing the present invention.

[0014] In other words, the present invention solves the above-mentioned problem by providing a multilayer printed wiring board comprising a core substrate having filled vias, build-up layers consisting of any number of laminates of insulating resin layers having glass fibers and / or inorganic filler therein and conductor layers stacked above and below the core substrate, and three or more stages of stacked vias connecting the vertical conductor layers in the build-up layer, wherein the via bottom diameter of at least the via stacked in the first stage from the core substrate side to the via located in the middle or the via located in the n-(n / 2)th stage (n is an even number of stages) is approximately the same as or greater than the via top diameter. Effect of the Invention

[0015] According to the multilayer printed wiring board of the present invention, since an insulating resin layer having glass fiber and / or inorganic filler therein is used as an interlayer resin insulating layer of the build-up layer, strong rigidity and low expansion are ensured, and there is no peeling of the insulating resin layer or the conductor layer. In addition, since the via bottom diameter and the via top diameter of a via at a predetermined position among three or more stacked vias are approximately the same diameter, or the via bottom diameter is larger, for example, when a thermal shock test (high temperature 125°C or more ⇔ low temperature -55°C or less, 1000 cycles) is performed, the bias of the stress applied to the via and the stress applied to the metal bonding part at the via bottom can be alleviated, and the breakage of the via bottom can be suppressed and the connection reliability can be improved. In particular, when the test is performed at a high temperature condition of 130°C or more, especially 150°C, the effect of reliability can be confirmed remarkably. [Brief description of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view showing a first embodiment of a multilayer printed wiring board according to the present invention; [Diagram 2] FIG. 4 is a schematic cross-sectional view showing a second embodiment of a multilayer printed wiring board according to the present invention. [Diagram 3] 3 is an enlarged cross-sectional view of a main portion for explaining the shape of stacked vias in the multilayer printed wiring board of FIG. 2. [Figure 4] 3 is an enlarged cross-sectional view of a main portion for explaining a modified example of stacked vias in the multilayer printed wiring board of FIG. 2. [Diagram 5] FIG. 4 is a schematic cross-sectional view showing a third embodiment of a multilayer printed wiring board according to the present invention. [Figure 6] FIG. 11 is a schematic cross-sectional view showing a fourth embodiment of a multilayer printed wiring board according to the present invention. [Figure 7] FIG. 13 is an explanatory diagram for explaining the positions of stacked vias whose via bottom diameter is equal to or greater than the via top diameter. [Figure 8] This is a schematic cross-sectional diagram illustrating the use of ANSI grade FR-4 base material for the insulating layer of a core board with drum-shaped vias and the insulating resin layer of the build-up layer. [Figure 9] FIG. 5 is a schematic cross-sectional view of an insulating layer 5a in which the ratio of glass cloth to resin is changed and intentionally thin glass cloth is used between the insulating layer of a core substrate having drum-shaped vias and the insulating resin layer of a build-up layer. [Figure 10] FIG. 1 is a schematic cross-sectional view of an insulating resin layer when a low-loss insulating material is sandwiched between an insulating layer of a core substrate having drum-shaped vias and an insulating resin layer of a build-up layer. [Figure 11] FIG. 1 is a schematic cross-sectional view showing a configuration of a multilayer printed wiring board according to a conventional technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0018] First, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 100 denotes a multilayer printed wiring board, which is composed of a core substrate 1 having filled vias 2, a buildup layer 5 consisting of a laminate of any number of insulating resin layers and conductor layers stacked above and below the core substrate 1, and three or more levels of stacked vias 6 connecting the vertical conductor layers in the buildup layer 5. 1, the core substrate 1 is a double-sided substrate, and the cylindrical filled vias 2 are formed, for example, by filling with copper plating a bottomed hole that is machined with a laser from the top of the core substrate 1. The filled vias 2 have approximately the same via bottom (Ba) and via top (Ta) diameters. In the first embodiment, the insulating resin layer of the build-up layer 6 is an insulating resin layer having glass fiber and / or inorganic filler therein. For example, the insulating material forming the insulating resin layer having the glass fiber therein has a Tg(TMA) of less than 150°C, a linear expansion coefficient (TMA) α1 of 23 to 40 ppm / °C, and α2 of 140 to 180 ppm / °C. The glass fiber is IPC standard #1080, has a thickness of 0.055 mm, and a mass of 47 g / m2. The Tg(TMA) is appropriately from 133°C to less than 150°C. The insulating resin layer may contain an inorganic filler as appropriate, which reduces the expansion of the insulating resin layer and suppresses peeling of the insulating resin layer. As the inorganic filler, silica, mica, aluminum borate, aluminum hydroxide, alumina, etc. are appropriately used.

[0019] Moreover, the three or more stacked vias 6 are formed directly above and below the filled vias 2 of the core substrate 1, and all of the vias have a cylindrical shape, with the bottom (B) diameter of the via and the top (T) diameter of the via being substantially the same. As a result, even when the insulating layer thickness of the build-up layer is thick (60 μm or more, particularly 70 to 80 μm or more), for example, when a thermal shock test (high temperature 125°C or more ⇔ low temperature -55°C or less, 1000 cycles) is performed, the bias of the stress applied to the vias and the stress applied to the metal bonding part at the via bottom is mitigated, making it possible to suppress breakage at the via bottom.

[0020] Next, a second embodiment of the present invention will be described with reference to FIGS. 2, 200 denotes a multilayer printed wiring board, which is configured in the same manner as in the first embodiment, except that a drum-shaped filled via 3 in a core substrate and a drum-shaped via 7 are formed as three or more stacked vias. The filled vias 3 and via 7 have approximately the same via bottom (Ba, B) and via top (Ta, T) diameters. 3, the cross-sectional area 9 of the via bottom (contact area between the via bottom and the lower conductor layer of the via) of the filled via 3 and the via 7 is larger than the cross-sectional area 10 of the intermediate portion of the via. This makes it possible to prevent breakage of the via bottoms of the first tier stacked from the core substrate side. Similarly, it makes it possible to prevent breakage of the via bottoms of the middle tier of stacked vias, which are subjected to stress similar to that of the filled vias of the core substrate and the vias stacked in the first tier.

[0021] In this second embodiment, the cross-sectional area 9 of the via bottom (contact area between the via bottom and the lower conductor layer of the via) and the cross-sectional area 11 of the via top (contact area between the via top and the upper conductor layer of the via) are the same, but as shown in Fig. 4, the via may be formed so that the via bottom diameter is larger than the via top diameter, and the cross-sectional area 9 of the via bottom (contact area between the via bottom and the lower conductor layer of the via) may be larger than the cross-sectional area 11 of the via top. In this case, the cross-sectional area 10 of the via middle part and the cross-sectional area 11 of the via top are configured such that the cross-sectional area 11 of the via top is larger than the cross-sectional area 10 of the via middle part.

[0022] Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 5, 300 is a multilayer printed wiring board, which is configured in the same manner as in the first embodiment, except that two types of cylindrical vias 6a and 6b with different via diameters are formed as vias stacked in three or more stages. Here, in FIG. 5, the number of stacked build-up layers is shown as four. The vias 6a, 6 each have approximately the same via bottom diameter and via top diameter, but the via bottom diameters of the vias stacked in the first row from the core substrate side to the vias in the third row, i.e., the via bottom diameters of the vias 6 in the first, second and third rows, are larger than the via bottom diameter of the via 6a located in the fourth row.

[0023] Next, a fourth embodiment of the present invention will be described with reference to FIG. In FIG. 6, 400 is a multilayer printed wiring board, which is configured in the same manner as in the first embodiment except that three types of vias are formed: a drum-shaped filled via 3 in a core substrate, a drum-shaped via 7 as a via stacked in three or more stages, and a cylindrical via 6a. Here again, the number of stacked build-up layers is shown as four in FIG. The via bottom diameters of the vias stacked in the first stage to the third stage counting from the core substrate side, that is, the vias 7 in the first stage, second stage and third stage, are larger than the via top diameters. In the fourth embodiment, the via bottom diameters of the vias stacked in the first stage to the via 7 located in the third stage counting from the core substrate side are larger than the via bottom diameter of the via 6a in the fourth stage.

[0024] In the third and fourth embodiments, examples have been described in which two types of "cylindrical" vias with different via diameters are formed, and two types of vias, a "drum-shaped" via and a "cylindrical" via, are formed. However, the via combinations are not limited to these, and any combination can be selected, such as three types of "cylindrical" vias with different via diameters, or two types of "cylindrical" vias with different via diameters and a "drum-shaped" via. In addition, although the filled vias of the core substrate and the vias stacked in three or more stages have been described as having the same shape, they may have different shapes and can be selected arbitrarily.

[0025] Next, the shape of the vias according to the number of stacked vias will be described with reference to FIG. Figures 1, 2, 5 and 6 show examples in which the via bottom diameter of all stacked vias is formed to be approximately the same as or greater than the via top diameter, but in the present invention, it is sufficient that at least the via bottom diameter of the via from the first stacked via counting from the core substrate side to the via located in the middle of the number of stacked vias, or the via bottom diameter of the via from the first stacked via counting from the core substrate side to the via located in the n-(n / 2)th tier (n is an even number of tiers) is approximately the same as or greater than the via top diameter. Specifically, as shown in Figure 7, when the number of stacked vias is an odd number of stages, at least the via bottom diameter of the vias from the via stacked in the first stage counting from the core substrate side to the via located in the middle of the stacked vias is approximately the same as or greater than the via top diameter. For example, in the case of vias stacked in three tiers, the via bottom diameters of the vias stacked in the first tier to the vias stacked in the second tier, i.e., the via bottom diameters of the vias stacked in the first and second tiers, counting from the core substrate side, are approximately the same as or greater than the via top diameter. In the case of vias stacked in five layers, the via bottom diameters of the vias stacked in the first layer through the vias stacked in the third layer, counting from the core substrate side, i.e., the via bottom diameters of the vias stacked in the first, second and third layers, are approximately the same as or greater than the via top diameter. In the case of vias stacked in seven layers, the via bottom diameters of the vias stacked in the first layer through the vias stacked in the fourth layer counting from the core substrate side, i.e., the via bottom diameters of the vias stacked in the first, second, third and fourth layers, are approximately the same as or greater than the via top diameter. Furthermore, in the case of five-stage stacked vias, it is more preferable to set the via bottom diameter of the via located in the fourth stage counting from the core substrate side to be approximately the same as or greater than the via top diameter, since this improves connection reliability. In the case of seven-stage stacked vias, it is more preferable to set the via bottom diameter of the via located in the fifth stage counting from the core substrate side to be approximately the same as or larger than the via top diameter, since this improves connection reliability. These measures are effective when a thermal shock test of 3,000 cycles is required, or when the high temperature condition of a thermal shock test is required to be 130°C or higher.

[0026] On the other hand, when the number of stacked vias is an even number, the via bottom diameter of at least the via stacked in the first stage counting from the core substrate side to the via located in the middle of the stacked vias or the via located in the n-(n / 2)th stage (n is an even number of stages) is approximately the same as or larger than the via top diameter. When the number of stacked vias is an even number, the via located in the middle of the stacked vias corresponds to two stages. In the present invention, it is sufficient that the via bottom diameter of the via up to one of the two vias located in the middle is approximately the same as or larger than the via top diameter. More preferably, the via bottom diameter of the via closer to the core substrate, i.e., the via located in the n-(n / 2)th stage (n is an even number of stages) is approximately the same as or larger than the via top diameter. For example, in the case of vias stacked in four stages, the via bottom diameters of the vias stacked in the first stage to the via located in the second stage (4-(4 / 2) stage) counting from the core substrate side, i.e., the via bottom diameters of the vias stacked in the first and second stages, are approximately the same as or greater than the via top diameter. In the case of vias stacked in six layers, the via bottom diameters of the vias stacked in the first layer through the via located in the third layer (6-(6 / 2) layer) counting from the core substrate side, i.e., the via bottom diameters of the vias stacked in the first, second and third layers, are approximately the same as or greater than the via top diameter. In the case of vias stacked in eight layers, the via bottom diameters of the vias stacked in the first layer through the via located in the fourth layer (8-(8 / 2) layer) counting from the core substrate side, i.e., the vias stacked in the first, second, third and fourth layers, are approximately the same as or larger than the via top diameter. Furthermore, for six-stacked vias, it is more preferable to make the via bottom diameter of the vias located up to the fifth row counting from the core substrate side approximately the same as or greater than the via top diameter, as this improves connection reliability. For eight-stage stacked vias, it is more preferable to make the via bottom diameter of the vias located in the sixth stage counting from the core substrate side approximately the same as or greater than the via top diameter, since this improves connection reliability. These measures are effective when a thermal shock test of 3,000 cycles is required, or when the high temperature side of a thermal shock test is required to be 130°C or higher. In explaining the present invention, the vias are stacked up to eight levels, but the number of via stacks is not limited to this and can be selected arbitrarily.

[0027] Here, the relationship between the shape of the vias stacked in three or more stages and the build-up layer 5 (insulating resin layer) of the present invention will be described with reference to FIGS.

[0028] As shown in FIG. 8, when a drum-shaped via 7 is formed as a via stacked in three or more stages according to the present invention, a via of this shape can be suitably formed by using an ANSI grade FR-4 base material as the insulating resin layer of the build-up layer 5.

[0029] Furthermore, in order to appropriately form drum-shaped vias, it is possible to use a general insulating material and devise laser processing conditions (output, processing frequency, mask, energy density, number of shots, etc.) and desmear processing conditions (adjustment of the processing times for the swelling and permanganate processes, etc.). In addition, it is also possible to form vias by devising material properties and material composition. For example, as shown in Fig. 9, by changing the ratio of glass cloth to resin in the prepreg used in the buildup layer 5 (resin ratio of 78% or more) and intentionally using a thin glass cloth for the buildup layer 5a, it becomes possible to improve the formability of drum-shaped vias. Also, this is more preferable than normal prepregs because it improves transmission loss and stabilizes characteristic impedance.

[0030] As shown in FIG. 10, the low-loss insulating material 5c (Teflon-based) used in the build-up layer 5 is sandwiched between insulating resins 5d to form the build-up layer 5b, which makes it possible to improve the formability of the via hole-shaped vias. This is also preferable because it improves transmission loss and stabilizes the characteristic impedance. In this case, it is necessary to use an insulating resin whose resin etching rate in the desmear process is 1.3 times or more that of the low-loss material, and the low-loss insulating material 5c that does not contain glass cloth is preferable in terms of electrical properties. The insulating resin 5d contains an inorganic filler. Examples of inorganic fillers include silica, mica, aluminum borate, aluminum hydroxide, and alumina. As explained using Figures 8 to 10, the relationship between the shape of vias stacked in three or more layers and the build-up layers has been explained, but a similar effect can also be expected for the relationship between the drum-shaped filled vias of the core substrate and the core substrate.

[0031] Next, an example of forming vias stacked in three or more stages will be described. The via processing conditions for the following via shapes were examined. Cylindrical: A via with a cylindrical shape (top and bottom diameters are approximate). · Drum shape: Processing to obtain a drum-shaped via shape for the above via diameter. Cylindrical + large bottom diameter: Via processing with the bottom diameter slightly larger than the top diameter. Drum-shaped + large bottom diameter: Processing to obtain a drum-shaped via shape with the above via diameter.

[0032] As for the laser processing conditions, the output, processing frequency, mask, and other settings were adjusted on the laser processing device to adjust the energy density at the processing point, and the number of processing shots was varied to derive the optimal conditions. Laser processing was carried out by varying the following levels from the processing conditions for the general shape (tapered shape). A. Increased energy density B. Increased shot count C. Combination of increasing the number of shots under conditions of lowering the energy per shot

[0033] As a result of laser processing, the desired shape could be obtained under conditions A, B, and C, and at the processing levels of X, Y, and Z below. X: Laser processing conditions that increase energy density by 10 to 30% Y·Number of shots: 1.2 to 2.0 times (minimum to maximum of reference number of shots per structure) Laser conditions For the laser shots after the Z·1 shot, the number of shots is increased by 1.2 to 2.5 (minimum to maximum of the reference number of shots per structure) under the condition that the energy of one shot is reduced by 10 to 20%. That is, by using laser shots with 10 to 20% less energy per shot than normal conditions and 1.2 to 2.5 times the number of shots used in normal processing, it was possible to form vias with the above shape. The normal processing conditions were set because they vary depending on the plate thickness, the type of base material, and the hole diameter.

[0034] Example 1 In an insulating layer with an interlayer thickness of 70 μm, which was made by laminating prepregs with a glass cloth thickness of 55 μm, drum-shaped vias with a diameter of 125 μm at the top and bottom were processed by laser processing. The first shot was performed with energy sufficient to penetrate the copper foil, and from the second shot onwards, the pulse width and energy were reduced by 20% compared to the first shot conditions for three shots, for a total of four shots, resulting in a drum-shaped via with approximately the same diameter at the via bottom and via top. Furthermore, a stable shape can be obtained by performing an additional shot with an energy that is 10% lower than the pulse width in addition to the above four shot conditions.

[0035] Example 2 Under the same conditions as in Example 1, a 70 μm thick insulating layer was laminated with a 55 μm thick glass cloth prepreg, and a via hole with a diameter of 125 μm was formed on the top and bottom of the insulating layer by laser processing. After that, in order to remove the resin smear and the carbide on the bottom copper foil, a desmear process was performed using a horizontal conveying type device or a vertical type device, which is a permanganate desmear process consisting of three steps of swelling, permanganate, and reduction. In the horizontal conveying type device, the normal processing conditions were used twice. In the vertical type device, the swelling and permanganate treatment times were extended by 2.25 times from the treatment conditions of general products. Specifically, the general conditions of swelling for 4 minutes, permanganate treatment for 4 minutes, and reduction treatment for 5 minutes were changed to swelling for 9 minutes, permanganate treatment for 9 minutes, and reduction treatment for 5 minutes.

[0036] Example 3 A 70μm thick insulating layer was laminated with a 55μm thick glass cloth prepreg, and top and bottom drum-shaped vias with a diameter of 125μm were processed using a UV laser processing device with a solid-state laser oscillator. After that, in order to remove the resin smear and carbide on the bottom copper foil, a desmear process was performed using a horizontal conveying device or a vertical device in a permanganate desmear process consisting of three steps: swelling, permanganate, and reduction. [Explanation of symbols]

[0037] 1: Core board 2: Cylindrical filled vias in a core board filled with copper plating 3: A drum-shaped filled via in a core board filled with copper plating 4: Tapered filled vias in a core board filled with copper plating 5: Build-up layer 5a: Build-up layer (thin glass cloth with a resin ratio of 78% or more) 5b: Build-up layer (low-loss insulating material sandwiched between insulating resin) 5c: Low-loss insulating materials 5d: Insulating resin 6: Cylindrical vias in 3 or more stacked build-up layers 6a: Cylindrical vias in 3 or more stacked buildup layers (smaller diameter than 6) 7: Hump-shaped vias in 3 or more stacked build-up layers 8: Tapered vias in 3+ stacked build-up layers 9: Cross-sectional area of ​​the via bottom 10: Cross-sectional area of ​​the middle part of the via 11: Cross-sectional area of ​​via top 12: Receiving land (copper foil on the underside of the core board) B: Via bottom Ba: Via top of core layer T:Beer Top Tb: via bottom of core layer 100, 200, 300, 400, 500: Multilayer printed wiring boards

Claims

1. A multilayer printed wiring board comprising a core substrate having filled vias, build-up layers each consisting of an arbitrary number of laminates of insulating resin layers having glass fibers and / or inorganic fillers therein and conductor layers stacked above and below the core substrate, and three or more stages of stacked vias connecting the vertical conductor layers in the build-up layer, wherein the via bottom diameter of at least the vias stacked in the first stage from the core substrate side to the via located in the middle or the via located in the n-(n / 2)th stage (n is an even number of stages) is approximately the same as or greater than the via top diameter.

2. 2. The multilayer printed wiring board according to claim 1, characterized in that the shapes of the vias from the via stacked in the first row counting from the core substrate side to the via located in the middle or to the via located in the n-(n / 2)th row (n is an even number of rows) are cylindrical or drum-shaped.

3. The multilayer printed wiring board according to claim 2, characterized in that the cross-sectional area of ​​the bottom of a via from the via stacked in the first row counting from the core substrate side to the via located in the middle or the via located in the n-(n / 2)th row (n is an even number of rows) is larger than the cross-sectional area of ​​the middle of the via.

4. The multilayer printed wiring board according to claim 2, characterized in that the cross-sectional area of ​​the bottom of a via from the via stacked in the first row counting from the core substrate side to the via located in the middle or to the via located in the n-(n / 2)th row (n is an even row number) is larger than the cross-sectional area of ​​the middle part of the via and is also larger than the cross-sectional area of ​​the via top.

5. 5. The multilayer printed wiring board according to claim 1, wherein a via bottom diameter of the filled via in the core substrate is substantially the same as or greater than a via top diameter.

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